SiGe^HETEROJUNCTiON BIPOLAR TRANSISTORS: KEY TECHNOLOGIES AND APPLICATIONS IN COMMUNICATION SYSTEMS D. Behammer, A. Gruhle, U. König, A. Schüppen* Daimler-Benz Research Center, Ulm, Germany *TEMIC, Heilbronn, Germany 33'' International Conference on Microelectronics, Devices and Materials, MIDEM '97 September 24. - September 26., 1997, Hotel Špik, Gozd Martuljek, Slovenia INVITED PAPER Keywords: semiconductors, semiconductor devices, SiGe HBT, Silicon-Germanium Heterojunotion Bipolar Transistors, key teci:nologies, practical applications, communication systems, IC, Integrated Circuits, iiigh frecjuencies fmax™ 160 GHz, noise figure <0 5 dB (at f~2GHz) electrical resistors electrical inductors, spiral electrical inductors, electrical capacitors, MMIC, Monolithic Microwave Intergrated Circuits Abstract: The SiGe HBT is attractive for future broadband and wireless communication ICs owing to its outstanding performance and from the fabrication point of view (fabrication costs == 0.25 x GaAs and 1.3 x Si). Most processes of main-stream Si technology can be utilized for integration of the HBT on Si substrates. This is due to the similar chemical and physical behaviors of Si and SiGe with respect to reactive ion etching, low ohmic contact systems, isolation and passivation. Thus, several groups have integrated the SIGe-HBT in standard Bipolar and BiCMOS technologies using differential or selective Si/SiGe/Si-epitaxy. Others use blanl !i\!. pii p j trri 1___ |i % u i ■ I ■[.>!■ ?,!)! eiiüls.ej winffow eoniti.-; inside-spao.;r oD^sid'j-sp.'^cür 05iistde-spncef (bi: iE2) (e.g. IBM /19/, NTT /16/, NEC /25/, Motorola /22/, DBAG/TEMIC /54/, AT&T (Lucent Technology) /53/, Siemens /52/, Philips /54/ and HP /23/). Base contact The three HBT versions Al-A3 have different contacts to the exstrinsic base (Fig. 3). In the differential SiGe-HBT A2 the polycrystalline layer on the field oxide regions acts as a lateral base contact with the smallest contact resistance between the mono- and polycrystalline silicon. The selective SiGe-HBT A3 utilizes the conventional double polysilicon technology with a negligible contact resistance between the monocrystalline extrinsic base and the deposited B-doped polysilicon. A further reduction of the external base resistance can be achieved either by an additional B implantation /17, 45/, a low ohmic salicide /53, 32/ or a selective deposited metal /16/. For the blanket double mesa SiGe-HBT a significant reduction of parasitic resistances and capacitances can be achieved by using additional self-aligning processes like planarization for transistor contacts and outside-spacer-technology for micromasking /55, 56/. The size of the base-collector area depends strongly on the integration concept. For A2 /14,16,17/ the area can be minimized owing to the sidewall contacted base. In A1 and A3 a defined parasitic base contact area remains /10,12,25,26,56/. Sophisticated concepts for self-aligned lateral base contact of Si-BJTs /50,51/ are not useable for the SiGe-HBT. bfan.kin üpilüx) -.i i LE ! ic M [M : . f ä ' 1 r „ni. F ig. 2: The different concep s for the integration of the Si/SiGe/Si-epitaxy and the emitter constructions. / -x a -pcilysilnAin • vkujbk' pi.)lysil(c n c UK -iJcKsiik:! Emitter definition After the low-doped collector (LDC)/SiGe-base/low doped emitter (LDE) epitaxy, the emitter can be definied using inside- or outside-spacer- polysilicon technology (see E1, E2 and E3 in Fig. 2). The outside-spacer structure can be generated by a polysilicon deposition or monocrystalline high-doped emitter (HDE) epitaxy followed by a mesa etching (E3).0n the other hand an oxide hole filled with polysilicon can be planarized (E2). For E1 und E2 the emitter width can even become smaller than the minimum feature size using an oxide inside-spacer. In addition the integration of the SIC (Selective Implanted Collector) can easily be realized by the self-aligned implantation through the emitter window. E1 and E2 dominate in the SiGe-lC technology Fig. 3: Optimization of the base contact and the parasite base-collector-area in correlation with the integration of the SiGe epitaxy. 2. Experimental results (a) SiGe-HBT A non-passivated and non-implanted double mesa HBT can quickly be processed. The zero thermal budget processing prevents any outdiffusion of the boron doping profile and any SiGe layer relaxation. Therefore it is suited best to obtain optimum performance. The process flow for such a test transistor is shown in Fig. 4a. The 300nm thick PtAu metallisation defined in a lift off process masks the wet chemical etching of the emitter in KOH solution, which stops at the SiGe base. The undercut of the emitter mask results in a self-aligned base metallisation also structured in a lift-off process. After the lift-off of the collector contact metal, air bridges are etched in an isotropic SF6/O2 plasma in order to reduce the parasitic elements. Using such a double mesa test transistor a high transit cutoff frequency fr of 116 GHz /57/ has been obtained for a single emitter transistor. A multi emitter finger structure with an optimized vertical doping profile has increased the maximal oscillation frequency fmax up to 160 GHz /44/. Fig. 5 shows the remarkable improvement of the fr and fmax values in the last years. In order to integrate a SiGe-HBT, the device should be passivated and have all elements of a high integrability including contact implantation and self-aligned low oh-mic contacts (see Fig. 4b). The process starts with the implanted buried layer formation into the 5-10 Qcm p (100) 4' substrate. After the blanket epitaxy of the entire LDC/SiGe-base/LDE/ HDE layer structure the emitter mesa is defined by reactive ion etching masked by oxide. / N(,( t 1 II ixule ! 1' I (or p' biu^c utiK basrt ,!it iiiiiljK bnse crtiutci „irsa^ I ol!i 1 Ü11 VVll \l uol lector (a) Fig.4 Process flow of (a) a non-passivated quick test SiGe-tiBT and (b) a passivated doubie mesa SiGe-HBT frequency f f M 5 * nmx - DBAG/rEMlC/ 125 - 100 IBM / ^ J" 75 cf^^ ''''' f ^Siemens 50 / ^ ' / / vONEC ■ ..............1—........-1----------1— PH 25 SiGe-HBTs 1 1 . ..........I.. JL__- 1989 1990 1991 1992 1993 1994 1995 1996 time Fig 5: Deveiopment of the frequencies fr and fmax ofSiGe-HBTs Ib,Ic decade/div [A] mo -1.000 0-000 UR0.1/div[V] Fig.6: i-V characteristic of a passivated Si/SiGe-HBT An outer base contact implantation is necessary to reduce the parasitic resistances. Low temperature passivation (LTO) by CVD SiH4/02 at 300°C follows after etching of the BC-mesa and annealing of the contact implantation. Contact holes are defined and the WTi/Al-metallisation is wet chemically etched. Conventional silicon process technologies use high temperature oxidation and high temperature gettering processes to ensure a high quality surface passivation of the active and passive device areas and a low level of active metal contaminants. That is not acceptable for Si/SiGe-HBTs, because of the strong outdiffusion of the base and the SiGe layer relaxation. The Gummel plot in Fig. 6 shows a low temperature budget SiGe-HBT after a 450°C n2/h2-anneal. The passivation seems to be sufficient for Si/SiGe/Si double mesa transistors, according to the good ideality at low currents. For the production of SiGe-HBTs TEMIC uses their Si-bipolar production line. The process, which was recently described in /58/, starts with a buried layer formation and a channel stop implantation in a 20 11cm substrate. The collector layers are formed by a 700 nm CVD silicon deposition and seperated by a recessed LOCOS process. The collector contact regions are implanted with phosphorus. Subsequently the differential CVD or MBE growth of the SiGe-base and the n-emitter follows. The 24-26% Ge and the 4-5-1 O^^cm"^ boron are kept constant in the SiGe-base. The growth is mono-crystalline in the oxide windows and poly-crystalline on the Si02. The CVD/MBE-poly-silicon, originally n-type, is converted to p by a BF2 implantation. A selectively implanted collector offers the possibility to build transistors with high breakdown voltage and low collector-base capacitance and on the same wafer HBTs with higher current densities and higher fr, but higher capacitance and lower breakdown voltage. In order to reduce the lead and the contact resistances titanium silicide is formed by a salicide process. The fabrication process ends with a two level AI metallization. Fig. 7 shows a top view of the transistor and Fig. 8 presents the transistor parameters. " ', , y ^m •• < f] Ulf ■• i-^m -ä •'• -r^M ' ..... Fig. 7: Top view of SiGe-tiBT fabricated in a production iine (TEMIC) second metallization (100 nm WTi and 4 ^m Al(siCu)). A second polyimide (1.5/jm) covers the second metallization and is opened only in the pad area. Hor a i'aj «i* 1IWS,,;N. SiGt>HBT ^Si ^ hurRxilava r-S; :> ^ifbhiiiili- S sRi;i S äJ-Si Parameter no SIC SIC AH 1.2x2 1.2x2 Nc [cm"^] 3E16 1E17 BVceo [V] 6.0 3.5 [O/ j 1200 1200 hfe [] 150 150 Va [V] 50 40 f. [GHz] 30 50 fmsx [GHz] 50 50 Fn,in(2GHz) [db] 1 1 Rb [Q] 140 140 Cbc [fF] 10 15 Cos m 22 22 Fig. 9a: Schematic cross section of the two ievel met-ailization with the passive RLC-devices Fig. 8: Transistor Parameter (TEMiC) L[ntl] n Da [^m] Da [l^m] W/S=10/10 W/S=10/5 1.25 2 190 175 3 155 140 4 130 3.00 2 330 315 4 210 185 7.50 5 300 265 7 280 240 15.0 6 385 8 350 340 9 305 (b) passive components High performance communication ICs need not only active but also passive devices. Fig. 9 gives an overview of the technological concept for resistors (R), inductors (L) and capacitors (C). After having processed the SiGe-HBT following layers are sputter-deposited: A 100 nm PECVD-oxide, the WSix-layer, the thin insulator INc of the integrated capacitors (Si02, Si3N4, AIN or Ti02), the 50 nm WTi barrier and the 50 nm Al(SiCu) top layer. The MIM-structure for the capacitors is defined by the wet chemical etching of the Al(siCu) and the WTi barrier. An additional 300 nm PECVD-oxide insulates the upper electrode of the MIM-capacitor. After the contact hole etching and the wet chemical etching of the first metallization (WTi/AI(SiCu)) the resistors and the capacitors are processed. A 3 jjm thick polyimide is spun on and forms the IML (Inter Metal Layer) for the isolation to the ' i <'' (' ! i'!- Fig. 9b: Tabie with the geometry of the spiral inductor (n=number of turns, L=inductivity, Da=outer diameter, W= width of the Ai-iines, S=dis-tance between the lines) and a top view of a integrated inductor with polyimide between the to metallizations. Resistors: For high performance analog and digital circuits there is a great interest for integration of thin film resistors (TFRs), because of the poor longterm stability of poiysilicon resistors due to their polycrystalline structure. The materials of integrated TFR are WSix or WSiyNz /59/, FeSix /60/, NiCr and NiCrxOy /61,62/, Ta2N /63/ or Ru02 /64/. In contrast to VLSI integration, for most of these materials the lateral definition is done by lift off techniques or wet chemical etching. However sputtered WSix(Ny) can be structured in F-based plasma or reactive ion etching and has a long term stability against temperature and current stress and has a sufficient resistance for most applications. The conductivity of the WSix(Ny)-TFRs is defined by the DC-power and the Ar/N2 gas flow. Target values are Rs=1000 (WSix: 30sccm Ar, 220W, 0.51 Qcm, d=52nm) and Rs= 10OOQ (WSixNy: SOsccm Ar, 4sccm N2, 220W, 6,OOr2cm, d = 58nm). The homogenity of the sheet resistance Rs across a 4 inch wafer is below 2% for Rs = 100r2 and around 10% for Rs=1000Q, with a high batch to batch reproducibility. Capacitors: The integration concept for the capacitors has already been described above. The main advantage is the planar deposition of the bottom electrode (WSix), of the insulator INc and of the upper WTi/AI(SiCu) electrode e.g. in one multi target PVD machine. We use 20 nm PVD-Si02 and 45 nm AIN and receive capacitances of C* = 6.0 fF//jm2 and 2.3 fF/^m2. In addition other materials with higher dielectric constants have to be tested to reduce the parasitic inductor. Inductors: In monolithic microwave integrated circuits (MMICs) spiral inductors are used. They will be applied as reactive loads, for low-noise coupling purposes and in matching networks. From these applications inductors should have a high imaginary part and a high quality factor Q. The layout optimization of the spiral inductors for applications in the 2 (7.5 nH), 5 (3.0 nH) and 12 GHz (1.25 nH) range is shown in Fig. 9b. The inductivities are calculated using the Greenhouse Algorithmus /65/. Some of the measured inductivities and quality factors are plotted in Fig. 10. The difference between the measured and target inductivity values is due to the Ing contact lines. The quality factors increase with decreasing substrate loss and thicker second metallization and/or a thicker IML. The maximum of the quality factors is near the operating frequency. 3. SiGe-HBT circuits Various HBT-IGs have been reported so far, some with outstanding, some at least with promising performances. Fig. 11 shows a chip with circuits for 5 to 40 GHz operation realized on semiinsulating Si-substrate. More production like are circuits on 20 iicm substrates (one example in Fig. 12), has under development at TEM1C/66/. ECL ring oscillators realized by Siemens, Philips, IBM, NEC, or Temic together with our house (DBAG) exhibit 11 to 20 ps /52^",67-69/. A 12 bit DAC operating at 1 GHz has been demonstrated by IBM together with ADI /70/. NEC has reported on D-type flip-flop for 20 Gbit/s, a selector for 30 Gbit/s and 33 ps, a 2:1 multiplexer for 20 Gbit/s and a preamplifier with 19 GHz and 36 dB /71,72/. Multiplexer and demultiplexer K)' QL.- , L [nH] , 12 . 10 0.1 1 10 100 Frequency (GHz] quality \ 5GHz a[)pUcation~U^ ("^'l factor ; ! 12 lOi ....... 0.1 1 10 100 Frequeiizy [GHz] quality 12GHz application s; r factor L [nH] 101 0 i....... / % :__________ 0.1 1 10 100 Frequejizy [GHz] 6r 4 ; 2: 0 i— 0,1 1 10 100 Frcqucnzy [GHz] li 0.1 1 10 100 Frequcnzy [GHz] 6i- i 4 f 2i oL.. O.I 1 10 100 Frequcnzy [GHz] Fig. 10: Measured inductivity and quaiity factor for different frequency ranges. Fig. 11: SiGe-HBT chip with circuits for 5-40 GHz. Fig.12: SiGe-HBT switches for 2 GHz with spiral inductors (Temic) /66/ Associated 10 Gain [dB] (a) High Bandwidth 18GHz - High Gain 9.5dB G50 I ,o\v Supply Voltage 1.6-3V _I_i_I_I_I_ 0 Frequency 44 [GHz] 43 42 41 40 39 -,-16 Output Power -'-20 [dBm] "i-22 - -24 - -26 - -28 - -30 - -32 (b) 0 12 3 4 Varactor Voltage [VJ 5 10 15 20 25 30 Frequency [GHz] Fig. 13: Low power consumption broad-band amplifier a) and varactor controlied osciiiators with SiGe-f-iBTs /74, 751 noise figure ^ ^ &gain [db] 3.8 4.6 5.4 6.2 7.0 7.8 8.6 Frequency [GHz] Fig. 16: Hybrid active antenna with a SiGe H BT yielding low noise at a receiving frequency of 5.8 GHz (Uni Ulm) Fig. 14: SIGe-HBTpower amplifier and enlarged emitter area 1.5 2 2.5 3 3.5 4 Frequency/GHz Fig. 15 Low-Noise Amplifier using SIGe HBTs for DECT Receivers (Unl Ulm) 1761. with 28 Gbit/s have been realized by the Ruhr University Bochum using samples from DBAG /73/. A wideband amplifier capable of 9.5 dB gain with 18 GHz bandwidth while drawing only 50 mW from a 3 V supply and operating even at 1.6 V was realized (Fig. 13a) /74/. Varactor controlled oscillators for different frequency ranges of 1.8, 11, 26, 28, 40 GHz (e.g. see Fig. 13b) were presented by Nortel together with IBM, by TEMIC, by IBM and by DBAG /75. 76/. Power amplifiers for 0.9 to 2 GHz have been realized by Temic together with DBAG (Fig. 14) and by Philips /54, 77/. LNAs with Fmin of 1.7 to 1.9 dB came from Temic together with DBAG and the University of Ulm (Fig. 15) A frequency devider of 42 Gbit/s was recently realized by Siemens /78/. We have used SIGe HBTs for hybrid intergration, too: A dielectric resonator oscillator (DRO) for 9.6 GHz and a 8-12 GHz VCO were reported by DBAG and Dornier /79/. Very recently an active antenna for receive at 5.8 GHz with the excellent noise Figure of 1.4 dB was reported by the University of Ulm using a device of DBAG (Fig. 16) /80/. 4. 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