Dinamika izhodnega signala pri kaskadni obliki izvedbe nerekurzivnih digitalnih sit
The dinamics of the output signal in the cascade form implementation of FIR digital filters

slovenian

2001

volume 31, issue 3

Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale

Finite impulse response (FIR) digital filters represent an integral part of digital systems in several applications. Since usual multipliers in digital filters represent complex hardware structure which consume power, and execution time, the distributed arithmetic or ROM accumulator structure for practical implementation of the inner product of two vectors is sometimes the way to overcome this problems /7, 10/. The exponential growth in the memory requirements in higher order FIR digital filters is pointed out and the higher order sections cascade structure is proposed as solution to this problem. An important advantage of this structure is that the total memory requirements can be reduced at the same speed of operation as in basic distributed arithmetic structure. In this paper the implementation of FIR digital filters of high order in cascade form with higher order cascade sections using distributed arithmetic is described and dynamic range of the output signal is analized. The proposed structure of cascade form with higher order cascade sectionis a compromise between direct form realization and conventional cascade form with cascade sections of first, second and fourth order /3/. Beside the basic distributed arithmetic structure the modified distributed arithmetic structure is proposed. The modified distributed arithmetic structure is based upon an unipolar presentation of the input signal in the basic distributed arithmetic structure. With this modification the enlargement of dynamic range of the output signal in comparison with the basic distributed structure is obtained, and allows also the hardware complexity reduction due to better normalization of patial sums of products. With additional use of the symmetrical presentation of the partial sums of products the memory for saving the pre-calculated sums of products was halved and required memory for storing the precalculated partial sums of products wasalso reduced. We have shown, that the modified distributed arithmetic structure is applicapable also in the higher order cascade structure of the FIR digital filter implementation, where the enlargement of the pass band gain is very useful. The comparable simulation results for lowpass FIR digital filters with 15,31 and 41 coefficients are shown with emphasis to the passband gain calculation of filters implemented in one, two, and three higher order sections cascade structure and with different quantization steps of hadware complexity. The cascade form realization of FIR digital filter structure has a low passband gain. This is the result of great pass band ripples of the frequency responses of the individual cascade sections, and because of the preventing of the oveflow problem inside the cascade sections. When we deal with distributed arithmetic mechanization the sum of partial products must be scaled down to prevent overflow in the aritmetic logic unit. Because of this property, there is an additional decrease in passband gain, which depend on the number of cascada sections. The values of passband gain (PBG) are given in table 3 for the basic distributed arithmetic structure and in the table 4 for the modified distributed arithmetic structure respectively. The number of cascada sections has a direct influence on the dynamic range of the digital filter structure. In our case of digital filter complexity only two or tree cascade sections can be proposed. The pass band gain then remain in the upper halve of the output signal range or is not smaller than -6 dB. The most degradation of the output range are noticed at 31 tap digital, implemented in three cascade sections. With the proposed modified distributed arithmetic mechanization the (PBG)=0.687, or -3.2 dB is obtained, while with basic distributed arithmetic this value is twenty times lower, (PBG)=0.033 or -29,5 dB. From the presented results we can conclude that the proposed modified distributed arithmetic structure make an improvement to the dynamic range of output signal. It is of great importance, that in restricted hardware solutions, in FPGA realization of such digital systems for example, it is also possible to obtain the ame frequency response performances in cascade form as in the basic distributed arithmetic structure.

18.12.2015