Adaptivna digitalna sita v strukturi porazdeljene aritmetike
Adaptive digital filter implementation with distributed arithmetic structure

slovenian

2001

volume 31, issue 3

Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale

Adaptive digital filters have a wide range of applications in the area of signal processing where only minimum a priori knowledge of signal characteristics is available. In this article the adaptive FIR digital filter implementation based on the distributed arithmetic technique is described. The major problem with conventional adaptive digital filter is the need for fast multipliers. When using a hardware implementation. These multipliers take up the disproportional amount of the overall cost and complexity. The distributed arithmetic filter structure is the way to overcome this problem because no classical multipliers is needed in the designing of the adaptive filtering structure. With FPGA realization of such a structure offers a large increase in hardware efficiency over conventional digital adaptive filter implementation. The basic adaptive digital structure is shown in figure 5 with circuitry of FIR digital filter and with arithmetic- logic unit for the filter weights calculation by an adaptive algorithm towards their optimum values. For partial products calculation in the inner distributed arithmetic structure the simultaneously, or direct principle is used and with this procedure the RAM memory for storing of the partial product is omitted. The computer simulation of the mathematical model of the whole structure in Matlab Simulink environment is used to verify our discussion. For verification purposes of the mathematical model and input signals description the VHDL language is used. Although it is not exactly identical to the real hardware realization, results from the simulation are used to analyse the performance and of the system.

18.12.2015