812 KB36 KB198520252001Babič, RudolfHorvat, BogomirOsebik, Davorinštevilka:3letnik:31str. 160-168ISSN:0352-9045COBISSID:6660118URN:URN:NBN:SI:doc-S68ZH8RAslStrokovno društvo za mikroelektroniko, elektronske sestavne dele in materialeInformacije MIDEMdigitalna obdelava signalovdigitalna sitaelektrična vezjakarakteristikeporazdeljena aritmetikaAdaptivna digitalna sita v strukturi porazdeljene aritmetike| Adaptive digital filter implementation with distributed arithmetic structure|Adaptive digital filters have a wide range of applications in the area of signal processing where only minimum a priori knowledge of signal characteristics is available. In this article the adaptive FIR digital filter implementation based on the distributed arithmetic technique is described. The major problem with conventional adaptive digital filter is the need for fast multipliers. When using a hardware implementation. These multipliers take up the disproportional amount of the overall cost and complexity. The distributed arithmetic filter structure is the way to overcome this problem because no classical multipliers is needed in the designing of the adaptive filtering structure. With FPGA realization of such a structure offers a large increase in hardware efficiency over conventional digital adaptive filter implementation. The basic adaptive digital structure is shown in figure 5 with circuitry of FIR digital filter and with arithmetic- logic unit for the filter weights calculation by an adaptive algorithm towards their optimum values. For partial products calculation in the inner distributed arithmetic structure the simultaneously, or direct principle is used and with this procedure the RAM memory for storing of the partial product is omitted. The computer simulation of the mathematical model of the whole structure in Matlab Simulink environment is used to verify our discussion. For verification purposes of the mathematical model and input signals description the VHDL language is used. Although it is not exactly identical to the real hardware realization, results from the simulation are used to analyse the performance and of the systemV članku je opisana izvedba adaptivnega nerekurzivnega digitalnega sita s programirnimi logičnimi (FPGA) vezji v strukturi porazdeljene aritmetrike. Za načrtovanje smo uporabili programski paket OrCad Express, s programskim paketom XACT pa smo opravili implementacijo celotne strukture vezja v dve programirni vezji firme Xilinx. Adaptivno FIR digitalno sito 15. stopnje, s 16-bitno dolžino registrov za zapis vhodno-izhodnega signala in 16 do 24 bitno aritmetrično logično enoto, smo izvedli vezjema XC4013E in XC4020E. Digitalno FIR sito smo načrtali v strukturi porazdeljene aritmetike s sprotnim izračunom delnih vsot koeficientov. Pri osnovnih urinih impulzih s frekvenco 20MHz, smo dosegli frekvenco vzorčenja vhodnega signala 100kHz. Za verifikacijo delovanja smo adaptivno sito in vhodne signale opisali v VHDL jeziku. Izdelano adaptivno sito je namenjeno izločanju šuma iz koristnega signala. Za testiranje adaptivnega sita smo uporabili koristni harmonični signal s frekvenco 1 kHz, na katerega je bil superponiran pasovno omejen beli šum. Razmerje signal šum smo izboljšali za 18 dBTEXTznanstveno časopisjejournalsSlovenian National E-content AggregatorNational and University Library of SloveniaStrokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale