Professional paper Informacije ^efMIDEM A lonrnal of Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 1 (2014), 69 - 74 Delaying analogue quadrature signals in Sin/ Cos encoders Tomaž Dogša, Mitja Solar, Bojan Jarc University of Maribor, Faculty of Electrical Engineering and Computer Science, Slovenia Abstract: Various measurement and control systems use magnetic or optical encoders that transform linear displacement and other physical quantities to an analogue quadrature signal. In this paper, we study the problem of, how to accurately delay the analogue quadrature signals in the Sin/Cos encoders within the range of ±10° with the circuit that is potentially integrable on a single chip. Such precision is needed for the efficient phase shift compensation. The typical analogue delay circuit comprises a summing amplifier and a digitally controlled variable resistor that is used to set a delay. We propose a new circuit based on the voltage divider with better linearity and a completely symmetrical range. The design procedure for the delay circuit is also presented. Keywords: quadrature encoder signals, phase delay, error analysis, delay circuit, analogue quadrature signals. Zakasnjevanje analognih kvadraturnih signalov v Sin/Cos enkoderjih Izvleček: Razni krmilni in merilni sistemi uporabljajo optične in magnetne enkoderje, ki pretvarjajo linearni pomik in tudi druge fizične veličine v analogni kvadraturni signal. V tem prispevku objavljamo rezultate raziskave, v kateri smo proučevali problem natančnega zakasnjevanja enega izmed kvadraturnih signalov, ki jih generirajo Sin/Cos enkoderji. Natančnost zakasnitve je pomembna za učinkovito korekcijo faze. Rešitev za zakasnjevanje v območju ±10° smo iskali v obliki vezja, ki je integrabilno. Tipično analogno vezje, ki se uporablja za zakasnjevanje, temelji na seštevalniku, ki vsebuje digitalno krmiljen potenciometer. Z novo strukturo zakasnilnega vezja, ki temelji na napetostnem delilniku, smo dosegli boljšo linearnost in popolnoma simetrično območje. Prikazan je tudi načrtovalski postopek. Ključne besede: kvadraturni signali, fazna zakasnitev, analiza pogreška, zakasnilno vezje, enkoder. ' Corresponding Author's e-mail: tdogsa@uni-mb.si 1 Introduction Various measurement and control systems use magnetic or optical encoders that transform linear displacement, the angular position, velocity, and other physical quantities to an analogue quadrature signal. The precision of the system is further improved with the interpolator. The ideal quadrature signals consist of two periodic signals with equal amplitudes and a relative phase shift of 90°. The signals are usually denoted as signal A and signal B or SIN and COS signal (Fig. 1). Imperfections of encoders and quadrature signals are the major cause of the interpolation error. A method for estimating the accuracy of quadrature output sensors is proposed in [1-2]. The reduction of the imperfections can be performed either in software or implemented with the conditional circuit which is inserted between the output sensors and the interpolator [3]. Authors [4-8] proposed various interpolation algorithms that reduce the imperfections of the signals. These approaches generally require high-precision ADCs and a high-speed DSP to compute the angle to the required resolution. A harmonic distortion reduction achieved by adequate design of a reading-plate is also reported in [9]. All proposed methods are aimed toward the compensation of the imperfections. In this paper, we focus on the problem of how to precisely set the small delay 4 j of the analogue quadrature signal within the interval (-10°, 10°). Such precision is needed for the efficient phase shift compensation. The most straightforward way to delay an analogue harmonic signal is to use a circuit with at least one reactance as in the analogue a. b. Figure 1: a. Sin/Cos sensor and b. the quadrature signals phase shifter. Yet these solutions are frequency dependent. The second method is based on a trigonometric identity: adding a fraction of signal A to signal B delays a cosine signal. The typical analog delay circuit, based on this idea, comprises a controlled resistor and a summing amplifier [3, 9, 10] In this paper we propose a new circuit that has better linearity and is based on the voltage divider. This paper is organized as follows. In Section 2, we briefly describe the theoretical aspect of the delaying an analogue orthogonal signal and the structure of the proposed circuit. Example of the design procedure is in Section 3. The experimental version of the proposed circuit was built and the measurements were carried out (Section 4). Finally, the results are summarized in the Conclusion section. 2 Delaying the orthogonal signals The ideal quadrature signals consist of two periodic signals with equal amplitudes and with a relative phase shift of 90°. The actual signals are harmonically distorted, have unequal amplitudes (Vsi^Vc), have DC offset (V0) and a phase shift offset (Aj0). If the harmonic distortion is neglected then signals can be expressed as Va(t) = Vs sin(fflf)+ Vos and Vb (t) = Vc cos{a)t + )+Voc (1) It will be assumed that signal B has to be delayed, and the total shift is smaller than 10° A^max = 10° (2) Given is the required phase shift step k^ and delay interval (±4 j^^^). Let b denote the control signal. Then the characteristic of an ideal delay circuit is specified by Ap(b) = ±kj), b = 0, 1, 2 ^ b (3) The most straightforward way to delay an analogue harmonic signal is to use a circuit with at least one reactance as in the analogue phase shifter. Yet these solutions are frequency dependent. The second method is based on a trigonometric identity: adding a fraction of signal A to signal B (see Fig. 2) delays a cosine signal. Vc cos{(Ot + A^) = Vc cos{(Ot)+ kVs sin{(Ot) (4) where -1 < k < 1. Let kA denote the amplitude imbalance of the signals A and B V k A = V (5) Note that value of the actual amplitude imbalance kA is not known precisely and may vary within known ranges. Figure 2: Positive A j increases the amplitude of signal B. Note, that amplitudes of real signals are not equal By applying the trigonometric formulas and considering (5), the resulting delay is given by A^k, ) = 45°+ arctg '{kAk -1) cos {kAk +1) 1 + sin (6) Note, that delay does not depend solely on k, but also on the phase shift offset Aj^ and amplitude imbalance kA as well. Furthermore, adding the signal B also increases/decreases the amplitude of signal A for AV^ (see Fig. 2) _)2 +{Vc)2 -^kVsVc sinA^o = + AV^ (7) If there is no initial phase shift offset (Ajg=0°) the equations (7) reduces to Vc_out = Vc /cosA^; Aj>0 Vc out = Vc COS A^; Aj<0 (8) To set a required delay digitally, k in (6) has to be controlled by the digital signal b. If Aj^ = 0°, the equation (6) simplifies to = arctg{kAk(b)), b = 0, 1, The relation (9) is approximately linear1, if k is small 180 kAk n The required range of k is (9) (10) k 180 (11) If = ±10° is chosen, then the required range of k is ±0.1745. The biggest change of the amplitude within this range is ±1.5 %. Fig. 3 (a) shows typical implementations of the equation (4) [3, 9, 10]. A small amount of signal A is added to signal B using a summing amplifier. A desired fraction of signal A is set by the value of whereas Rbs is needed for setting the step of the delay. The influence of the wiper's resistance2 Rw (see Fig. 4) and the week linearity are the main disadvantages of this variant. We propose a new circuit based on the voltage divider with better linearity and a completely symmetrical range (Fig. 3(b)). For these reasons we decided to study variant based on the voltage divider. 2.1 Delay circuit A scheme of the implemented circuit shown in Fig. 3(b) is presented in Fig. 5. A delay is set by digital potentiometer RD. The unity gain amplifier A5 eliminates the R3 (a) -sin(rot) cos(rot) B' Vc_out=-COS(rot+Aj) Figure 3: Two possible configurations of the delay circuits Figure 4: Simplified model of a digital potentiometer Rd with N segments and the additional resistor Rbs. Rw is a resistance of the CMOS switch. influence of the wiper's resistance Rw. All control signals for the digital potentiometers are generated with FPGA module. The fraction of the signal A is added to a signal B by a specially designed summing amplifier A2. Unity gain amplifiers (A7, A6) may be neglected if the output resistance of the sensors is low. Out of the many imperfections only the amplitude imbalance kA will be considered in the analysis that follows. Since DC offset affects phase shift, all opams should have low offset voltage. ? arctg(x) = (x - x^/3 + x5/5 -...) 2 For the 128-tap, 100kW digital potentiometer MAX5439 is Rw = 0.9... 2kW sin(wt) 0-» A cos(wt) B -C0s(wt+Aj) 100k I I ±Aj 10^^ 10k M1 A 'bp Ü M2 "J- (Amplitude correction) Figure 5: An implemented delay circuit with simple amplitude correction circuit First, we rewrite the equation (9) into the form ^^{b) = arctg {k^Ai {b)A2) (12) where A2 is a gain of the summing amplifier and A^ib) is the attenuation of the voltage divider. By applying a model of N-bit digital potentiometer (see Fig. 4), we N+b (13) Note that b is in the numerator, which means that A^ is linearly dependent on b. Let Ac denote the gain u2/u6 and A2 the gain u2/u5 Ac = u2l u6 =-R\/R2 The analysis of the circuit gives Ui = AcVc cos (Ot + A^k^A^ (b)Vc sin a>t = = AcVc (cos at + kAAj (b )sin at) (14) (15) This proves the correct implementation of the theoretical model (4). Note, that A^ does not affect the phase shift but the amplitude of the delayed signal. The sign of the delay is controlled by MOS switches M1 and M2. For Aj<0 is M1 OFF and M2 is ON. If the change of amplitude (8) cannot be tolerated, then the amplitude correction is needed. If the amplification of cos signal, that is defined by ratio R1/R2, is greater that one, then oversized output amplitude can be adjusted with a divider RDP2 that is controlled by the amplitude detection circuit. By choosing R2=R3=R4, we obtain A = = - R\ R3 + R 4 (16) To achieve positive delay the summing amplifier is transformed by the switches M1=ON, M2=OFF to the non-inverting type with the same inverted gain. A2 = + R6 R5 + R6 1 + R1(R2 + R3) R2R3 Ac = +-2^ (17) The equal gain (11) is obtained by the appropriate ratio R6/R5: = A + 3 R6 A (18) Note that gains A^, A^ and Ac are well defined since they depend on the ratio of resistors. A^, has to be greater than one to ensure that the amplitude of u^ will always be greater than Vc. This oversized output amplitude of cos signal is reduced to Vc with a divider RDP2 that is controlled by the amplitude detection circuit. The equation (12) can be rewritten now = arctg k, b 2 (^ + bs) (19) If the amplitude imbalance kA is unknown then kA has to be considered as a random variable. In order to reduce the phase error, amplitudes has to be equalized by a special circuit. For small delays is (19) approximately linear 180 kA b n 2 (N + bs) = A^stepb (20) By rearranging (18) and setting Aj^^^^ = k^ we can derive a designing rule for Rbs Rbs - bsRstep - 90kA - N R step (21) 2.2 Reducing the systematic error due to the nonlinearity Let denote the systematic error, which is the difference between a measured Aj(b) and the target value A^err_s (b) = - k^b (22) One reason for the is a nonlinear function arctg in (12). If the argument of the arctg follows tg function, then the nonlinearity is eliminated: Ap(b) = arctg [k^Ai (b )A2 ) = = arctg (tg (/caAi [b )A2 )) = kAA^ (b)A2 (23) The simplest way to implement this idea is to adequately change the value of the signal b. Let bp denote modified control signal A' -sin(wt) u B u A 5 A5 11k sign(Aj) ba b 2 u bp = b + Ab (24) 3 Example of the design procedure From (23) we can derive a modification rule b^bp. bp = floor Db 2 1 0 0.5+ k, delta_bp.vsd kA b 2 (N + bs) (25) 1 1 b = :78 b=113 \ \ \ 20 60 Figure 6: The solution of (25) and (24) 100 From the solution of (24) and (25) a simple modification rule can be constructed (see Fig. 6). If the range of the control signal is b=1^127, then the rule is then b = b p if (78113) then bp = b+2 Note that the modification rule reduces the range bmax = N -Abmax (26) For example, If k^ = 0.1 ° and N = 127, then the biggest error is = -0.15° (Fig. 7(b)). By using the correction of the i^, ttie eaoi^ is ^(^t e^^n^^r^ated yet substantially reduced: -0.06° < < +0.06° (see D(Perr_s 0.0° -0.1° -0.2° / o s nI Xb 2.0° 6.0° 10.0° Dp Figure 7: Systematic (linearity) error (Eq. 11, 23 and 25) for k^ = 0.1 ° and N = 127. Amplitudes are equal (k.=1). a with linearity correction, b without correction Given are: k = 0.1°, < 10°, > -10°, k » 1 j ' T max ' T min ' A 128-tap, 100kQ digital potentiometer MAX5439 was selected for a prototype with discrete components. This means: R = 100 kW, N=127 and R =787Q. If ^ ' step the integrated version were planned then N would be 101. Equation (21) gives b^ = 159 and Rbs=125kW. A.^ was chosen 11/10 and R2=fR3=R4=10kW. Elquations (1'4) and (18) determine the value of R1=11kW and R5/ R6=53kW/11kW. The resulting theoretical characteristics (19) of the delay circuit are: = -arctg ' b " 572 ; b = 0, 1, 2,^ 125 ^jmax = 12.52° , = -12.52° , < 0.06°, l^js.pl = 0.10° 4 Measurement results To estimate a worst-case a SPICE simulator was applied. OPA27 amplifiers and two digital potentiometers (128-Tap MAX5437 and MAX5439) were used in the prototype circuit. The magnetic encoder sensor was replaced by the signal generator that generates almost perfect signals. Each delay was measured 100 times with digital oscilloscope LeCroy LT344. Data for the positive delay3 are shown in Fig. 8. The signal generator had an offset delay (Ajer(b = 0)) which was removed in the analysis. The biggest total error Ajerr = 0.39° was at 10°. Best results were in the range from 0° to 5° where total error was below 0.2°. ▲ Average ♦ +a ■ -a Djerr 0.50° 0.00° -0.50° -1.00° 0.00° —»—^ „M^^ 1 jP^' 4.00° 8.00° Figure 8: Simulation and actual measurement results (f = 1 kHz) 3 The negative delay had even better results b 5 Conclusions In order to achieve a precise delay, low-offset voltage opamps are required and the circuit has to be designed in such a way, that the delay depends only on the ratio of the resistors. The design procedure for the delay circuit was developed: two out of four parameters (N, A, k Aj ) can be chosen, the other two are calculated. If the signals are perfect and frequency is low, then the precision of the delay is limited only by the systematic error Dj and the resistors ratio. In the ideal case ~ en—s the phase step defined by Dj..ep= Djmax/N = 10°/128 = 0.08°. The actual usable Dj^,^^ depends on the quality of the signal and on the tolerances as well. To verify the theoretical results the SPICE simulation was applied and a discrete prototype of the delay circuit was built. The prototype shows that with the discrete elements it is possible to obtain the total error below 0.2° in the range from 0° to 5°, if signals are of good quality. To obtain more reliable yield estimation the additional tolerance analysis is needed. 8. 9. 10. 11. Emura, T., Wang, L. (2000). A high-resolution interpolator for incremental encoders based on the quadrature PLL method. IEEE Trans. Industrial Electronics, 47 (1), 84 - 90. Rozman, J., Pleteršek, A. (2010). Linear optical encoder system with sinusoidal signal distortion below -60 dB. IEEE trans. instrum. meas., 59 (6), 15441549. Yang, C.-J., Kao, C.-F., Chen, Y.-Y., Lin, C.-F., Chen, T.-L. & Ker, M.-D. (2003). ASIC with interpolator for incremental optical encoders. Proc. 7th Int. Conf. Mechatronics Technology. Jung, W. G. (2005). Op Amp Applications Handbook, Elsevier/Newnes, ISBN 0-7506-7844-5. Arrived: 03. 10. 2013 Accepted: 08. 01. 2014 6 References 1. Lin, Q., Li, T., Zhou, Z. (2011). Error Analysis and Compensation of the Orthogonal Magnetic Encoder. 2011 International Conference on Instrumentation, Measurement, Computer, Communication and Control. doi: 10.1109/IMCCC.2011.12. 2. Denk, D. E. (2008). A method for estimating the accuracy of quadrature output sensors. ISSN 8756-6990, Optoelectronics, Instrumentation and Data Processing, 44(2), 105-110. 3. Pleteršek, A. (2001). Integrated optical position microsystem with programmable resolution. Inf. MIDEM, 31(4), 281-286. 4. Hieu Tue Le; Hung Van Hoang; Jae Wook Jeon. (2008). Efficient method for correction and interpolation signal of magnetic encoders. Industrial Informatics, 6th IEEE International Conference on. Daejeon, 1383-1388. 5. Tan, K. K., Zhou, H. X., Lee, T. H. (2002). New interpolation method for quadrature encoder signals. IEEE Trans. On Instrument and Measurement, 51(5), 1073-1079. 6. Balemi, S. (2005). Automatic Calibration of Sinusoidal Encoder Signals. Proceedings of IFAC World Congress, Prague. 7. Hoang, H. V., Jeon, J. W. (2007). Signal Compensation and extraction of High Resolution Position for Sinusoidal Magnetic Encoders. International Conference on Control, Automation and System, 1368-1373.