APA:
Sulaiman, Mohd Shahiman (2006). A methodology for optimum delay, skew, and power performances in an FPGA clock network.
Informacije MIDEM, volume 36, issue 2, str. 85-90.
URN:NBN:SI:DOC-U4EM5DT8 from http://www.dlib.si
MLA:
Sulaiman, Mohd Shahiman. "A methodology for optimum delay, skew, and power performances in an FPGA clock network."
Informacije MIDEM volume 36. issue 2 (2006) str. 85-90.
<http://www.dlib.si/?URN=URN:NBN:SI:DOC-U4EM5DT8>