Exploiting symbolic model checking for sensing stuck-at faults in digital circuits
Uporaba simboličnega preverjanja modelov pri zaznavanju zatičnih napak v digitalnih vezjih

english

2002

volume 32, issue 3

Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale

This paper presents algorithms for automatic test pattern generation for discovering stuck-at faults in sequential digital circuits or proving that there are no stuck-at faults in the given circuit. A circuit is represented as a finite state machine. Properties for stuck-at faults expressed with CTL formulas which are valid in the circuit with stuck-at faults and generally not valid in the good circuit are generated. Validity of the formulas is checked by symbolic model checking, and for invalid formulas counterexamples are constructed which guide the circuit to the states which prove the absence of stuck-at faults. Test patterns guide the circuits exactly as the counterexamples. Experimental results for a set of benchmark circuits togetherwith the time and space complexity analysis of the algorithms are also given.

18.12.2015