APA:
Fajfar, Dušan, Lokar, Matija (1987). Analysis of buffered multistage interconnection network for parrallel processors.
Informatica (Ljubljana), volume 11, issue 4, str. 3-7.
URN:NBN:SI:DOC-0L0YESVA from http://www.dlib.si
MLA:
Fajfar, Dušan, Lokar, Matija. "Analysis of buffered multistage interconnection network for parrallel processors."
Informatica (Ljubljana) volume 11. issue 4 (1987) str. 3-7.
<http://www.dlib.si/?URN=URN:NBN:SI:DOC-0L0YESVA>