ULTRA LOW NOISE PAGO AMPLIFIER FOR MICROSYSTEM SENSOR SIGNAL PROCESSING
Janez Trontelj, Aleksander Sešek University of Ljubljana, Faculty of electrical engineering, Ljubljana, Slovenia
Key words: low noise amplifier, automatic gain control for programmable temperature coefficient (PAGC), microsystems
Abstract: One of the key properties of the microsystems is the quality of the front-end sensor signal processing. Typically a fully differential input and output stages are required for most of the analog signal processing to maintain the best possible rejection of the unwanted signals.
The design of such amplifier is discussed in this article. Special attention is paid to the offset voltage minimization, 1 /f noise and thermal noise minimization. Temperature dependent Programmable Automatic Gain Control (PAGC) is incorporated to allow for sensor temperature coefficient compensation. Amplifier parameters are measured and characterized on the realized ASIC.
Ekstremno malošumni PAGC ojačevalnik za procesiranje senzorskega signala v mikrosistemih
Kjučne besede: malošumni ojačevalnil^, avtomatsl<a regulacija temperaturnega koeficienta (PAGC), mikrosistemi
Izvleček: Ključna lastnost v mikrosistemih je kvaliteta procesiranja vhodnega senzorskega signala. Običajno zahtevamo vhodno stopnjo z diferencialnim vhodom in izhodom. Na ta način zagotovimo najboljše slabljenje neželjenih signalov. V članku je prikazana izvedba takšnega ojačevalnika, kjer sta mini-mizirana šuma 1 /f in termični šum. Temperaturno odvisna avtomatska regulacija ojačenja z možnostjo nastaviWe PAGC omogoča kompenzacijo temperaturnega koeficienta senzorja.
Rezultati simulacij in meritev na izdelanem ojačevalniku so podani v članku.
1. Introduction
The target was the amplifier with minimal input noise, differential input stage and single-ended output. The output signal has to be around the reference level Vret.
The most commonly used answer to a problem is combination of either four input amplifier or combination of two unity gain input amplifier and the output stage. In both cases the input noise contribution is the sum of four input transistors together with resistor noise. A solution where the noise contribution is only the noise of two input transistors and the resistor noise is minimised to a negligible level is presented. The front-end block diagram is shown in figure 1.
^-,,		; DifacmiaJ jfipi;i ^mpi-f«:'	
			
-Sfos-t I	Vm		
		gaifi	
			
			
			
InvE^unieriioi
Vpcoi;
Fig.1: Front-end block diagram
2. Differential input amplifier
Selected topology of the differential amplifier with controlled gain is shown in the figure 2.
Fig. 2: Differentiai ampiifier
It consists of the differential input transistor pair m4 and m5 and load resistors r1 and r2. The bias generator is made of bipolar transistor q1, resistor r3, MOS transistors m1 and m3 and sub circuit si for driving the transistor m3.
The bias generator, its influence and main proprieties is described in section 3. The dimensions of differential pair and bias current are calculated to obtain 26dB gain i.e. 20dB at each output.
The target 1/f noise density of differential amplifier at 1 kHz is less than 7nV/VHz; the target thermal noise density level at 100 kHz is less than 5nV/A/Hz and the gain-band-width product over 100MHz.
2.1 Noise characteristic
Several simulations were made to analyze the influence of the input stage transistor type on noise performance. The amplifier was intended to be used in a magnetic microsystem where the equivalent noise resistance of the sensor was 1 kQ. In all simulations and measurements this equivalent noise resistor was included.
Input noise
8.00e-008 v-7.00e-008 1 ■■ 6.00e-008 f-5.00e-008 f-4,00e-008 i-
3.00e-008 i-2.00e-008 f -1.00e-008 f O.OOE+000 -i -
aat IkHz nat 100kHz
n06
Technology
Fig. 3: Noise density for n-type input transistor stage (n06) for p-type input transistor stage (p06)
Input noise
9.00E-009 .......
8.00E-009 I.......
7.00E-009 4........
^ 6.00E-009 i-
5.OOE-OO9J-
^ 4.00E-009 .......
w ö
c 3.00E-009 f.......
2.00E-009 I.......
1.00E-009 1.......
O.OOE+000 4.......
^ :Bal 1kHz , i 0 at 100kHz
p06 Rsens=1k	p06 Rsens=0.5k
Technology
Fig. 4: Tiie infiuence of equivaient noise resistance of the microsensor
The analyses were made for 0.6)im technology. It was found out, that p-type transistor input stage, using the same transistor sizes, has lower noise than the n-type. Figure 3 presents simulation results for p and n-type input stage. As shown, the noise level for n-type input differential stage is around 68nV/VHz, and for p-type stage 7,9nV/VHz at 1kHz (1/f noise mainly). At 100kHz (thermal noise) the noise density levels are 8.1 nV/^Hz for n-type and 4.6nV/ VHz for p-type. Even with lowest noise level around 24nV/ VHz at 1 kHz for n-type input stage could be achieved.
Figure 4 shows the noise density level at different sensor equivalent noise resistances. As expected, the sensor resistance value has major influence on thermal noise (lOOkHz). The thermal noise level of the system for 1 kß sensor equivalent noise resistance is 4,62nV/VHz and 3,62nV/VHz for 0.5kü sensor equivalent noise resistance.
2.2 Comparing technologies
The basic proprieties of the input differential stage for different technologies have been analysed. Figure 5 shows the noise density level of input differential amplifier in 0,35um, 0,6um and 0,8um CMOS technology. The comparison is done for p-type input stage transistors due to better performance. As expected 1 /f noise (at 1 kHz) level is lower with smaller technology; meanwhile the thermal noise (at 100kHz) doesn't change a lot. The noise level varies from 5,27nV/VHz for 0.35um technology, up to 8,95nV/VHz for 0.8um technology. The thermal noise is around 4.65nV/VHz, for all technologies.
Input noise
a
I 4.00e-009 ■
p035
p06 Technology
Fig. 5: Noise at different technologies
The influence of different technologies on gain has been analysed. For these simulations the dimensions of input differential transistor pair were modified to achieve the same input capacitances, to compensate the gate oxide thickness change with the technology. For example, the thickness of gate oxide for 0,8um technology is 18nm, for 0,6um technology 12nm and for 0,35um around 15nm. In 0,35um technology, the thickness is larger due to the use of tran-
sistorwith mid-gate oxide, operating at 5V. Figure 6 shows the gain for different technologies with p-type input transistors and for comparison the 0,6um n-type input transistor stage is added. As seen, the gain doesn'tvary a lot with technologies. As expected n-type input stage has a higher gain factor.
Ao
n06
p035
p06
Technology
Fig. 6: Gain at different technologies
-3dB frequency margin
1.20E+007 ■ 1.00E+007 , 8.00E+006 I
I
c 6.00E+006 -
O" £
4.00E+006 ■ 2.00Et006 +
O.OOE+000 -h—-
p035	p06
Technology
Fig, 7; -3ciB frequency margin
Variation of-3dB frequency margin is shown in figure 7. As shown, n-type of input stage doesn't have the best performance. The best technology is 0,35um where gain-bandwidth product over 190MHz has been achieved.
2.3 Performance of the selected differential input stage
Due to the best performance the p-type input differential stage in 0,35um technology was chosen for our system. Several analyses with different corners (worst cases of technology parameters) have been performed in the temperature range between -20°C and 100°C.
In figure 8, the results for temperature sweep are presented. The gain variation for technology corners wp (worst power), WS (worst speed), wz (worst n-type transistors) and wo (worst p-type transistors) can be observed.
Ao
20.5 -20 ■
19.5 --------
19 1............
S 18.5 i---------
p
C
M 18 -i---
O)
17.5 17 16,5 -16 ■
-vvp - wz
'WO ■WS
-20
20 40 60 Temperature
100
Fig. 8: Gain variations with temperature and process corners
-3dB corner frequency
1.20E+007 1.00E+007 8.00E+006
N
I
C 6.00E+006
o
3
£
4.00E+006 2.00E+006 O.OOE+000
-20
20 40 60 80 Temperature
Fig. 9:
-3dB corner frequency as a function of temperature and process corners
As shown, in the worst case the gain of the input stage drops to the lowest value around 19,4dB at worse speed parameters and at the highest temperature.
The lowest -3dB corner frequency is 8MHz at worst p-type transistors condition at high temperature. This corresponds to the worst case gain-bandwidth product of 1 SBMHz. The level of input noise density at 1 kHz (1 /f noise) is shown in figure 10.
When changing the corners there are no noticeable influence to the noise density level. However noise density at 1 kHz changes with the temperature from 4,75nV/VHz to 6,12nV/VHz, and from 4.25nV/VHz to 5,25nV/VHz at-
100kHz as seen at figures 10 and 11, in the temperature range of 120 °C.
Input noise at 1kHz
6.00E.009
6.50E-009
V 4.50E-009
4.00E-009
3.00E-009
				
				1
		Sy*» ■ *-		
				
				
				
-WS
. " "WO
■ w. ' - .wp
20 40 60 Temperature
Fig. 10: Input 1/f noise
Input noise at lOOhHz
5,50E-009 V -
5.00E-009
£ 4,50E-009 c
V)
s. r
s 4.00E-009 i-
3,50E-009
-20 0 20 40 60 80 100 Temperature
Fig. 11: Input thermal noise
3. Programmable automatic gain control
The programmable bias generator is used to control the gain of the amplifier and to compensate the temperature dependence of the proposed amplifier and of the micro-sensor.
Special attention was paid to the design of relevant components of the bias generator to minimize its influence to the overall noise. The topology of the bias generator is shown in figure 12.
Minimization of the noise influence is taken care by appropriate sizes of the transistors ml and m2. The temperature coefficient of the bias current is set by the appropriate selection of the reference voltage and the value of resistor r3.
za3
xta
V
'-bi as
Fig. 12: Bias generator
Figure 13 shows the temperature behavior of the bias current for all corners.
When selecting such temperature dependence of the bias current we obtain minimal gain variation of the amplifier as seen in the figure 8. The sensor temperature coefficient can be programmed by the control voltage on the Prog input. The temperature dependence of the bias current is given by the expression:
I^(temp) =
r^itemp)
Bias current
; - - - . woi - -WSi
20 40 Temperature
Fig. 13: Bias current
As both the temperature dependance of the Vbe and ra are known for a given technology the wide range of bias current temeprature dependance can be achieved by changing the programming voltage Vpmg.
The measured results for noise density are shown in figure 14 compared to simulation results. A perfect matching with simulated results has been observed also in other amplifier characteristics.
Noise level
	120.00 J
	100,00 t
	i
X	
tr CT	80.00 --
5	
iS	60,00 --
i S	
I ž	1 40.00 t
i 1	
i z	20,00 -
	0,00
	

Frequency [Hz]
generator. Typical sensitivity variation of the system w/ith temperature is 70ppm/°C. Typical gain-bandwidth product is 190MHz.
5. References
1.	Trontelj J., Pevec A., Microsystem for electrical current sensing. Informacije MIDEM, letnik 33, št. 2 (2003), str 118-121
2.	Pleteršek A., Ratiometric-to-supply voltage output buffer design. Informacije MIDEM, letnik 33, št. 1 (2003), str 63-69
Fig. 14: Measurement results compared to simulation results
4. Conclusion
A minimal noise and offset input amplifier with automatic temperature controlled gain has been introduced. It has been shown, that n-type transistors have larger noise than p-type transistors. When using smaller technology, 1/f noise is decreasing for the same silicon area. Very low 1 /f noise density level of 5,27n\//VHz at 1 kHz typical and 4,65nV/VHz thermal noise density typical with dominant contribution of the sensor equivalent noise resistance has been achieved. The microsystem sensitivity is temperature stabilized by the use of special programmable bias current
prof.dr. Janez Trontelj Univerza i/ Ljubljani, Fal<uiteta za elektrotehniko Tržaška 25, SI-1000 Ljubljana E-mail: janez.tronteijWguest.arnes.si Telefon: +386 1 4768 333
Aleksander Sešek, univ.dipi.inž.el. Univerza i/ Ljubljani, Fakulteta za elektrotehniko Tržaška 25, SI-1000 Ljubljana E-mail: sandi@kalvarija. fe. uni-lj. si Telefon: +386 1 4768 727
Prispelo (Arrived): 15.02.2005 Sprejeto (Accepted): 15.03.2005