Original scientific paper
Informacije
^efMIDEM
A Innrnal of
Journal of Microelectronics, Electronic Components and Materials Vol. 43, No. 3 (2013), 173 - 178
Low-Voltage FGMOS Based Voltage-to-Current Converter
Rishikesh Pandey1, Maneesha Gupta2
^Dept. of Electronics and Comm. Engineering, Thapar University, Patiala, India
2Dept. of Electronics and Comm. Engineering, Netaji Subhas Institute of Technology, New
Delhi, India
Abstract: This paper proposes a novel floating-gate MOSFET (FGMOS) based voltage-to-current (VTC) converter. The proposed VTC converter has rail-to-rail input dynamic range, low THD (total harmonic distortion) and low power dissipation. The VTC converter has been simulated using SPICE in 0.25-mm CMOS technology with the supply voltages of ±0.75V. The simulation results of the VTC converter demonstrate THD of less than 1%, 3-dB frequency of 1.63GHz and maximum power dissipation of 0.84mW.
Keywords: Floating gate MOSFETs, low-voltage, mobility degradation, SPICE, VTC converter.
Nizkonapetostni napetostno-tokovni pretvornik na osnovi FGMOS
Izvleček: Članek predlaga nov napetostno-tokovni pretvornik (VTC) na osnovi MOSFET (FGMOS) s plavajočimi vrati. Predlagan VTC pretvornik ima polni vhodni napetostni obseg, nizko THD (dinamično harmonično distorzijo) in nizko disipacijo moči. VTC pretvornik je bil simuliran s SPICE v 0.25-mm CMOS tehnologiji z napajalno napetostjo ±0.75V. Simulacije VTC pretvornika izkazujejo THD manjši od 1 %, 3 dB pri 1.63 GHz in največjo disipacijo moči 0.84 mW.
Ključne besede: MOSFET s plavajočimi vrati, nizka napetost, degradacija mobilnosti, SPICE, VTC pretvornik
' Corresponding Author's e-mail: riship23@gmail.com
1 Introduction
Low-voltage operation has become a major design issue for the analog signal processing applications. This is because a low-voltage power supply reduces the power dissipation which increases the battery lifetime and the reliability of the portable systems. Some of the low-voltage techniques used to reduce supply voltages are level shifters, self-cascode MOSFETs, sub-threshold MOSFETs, bulk-driven MOSFETs and floating-gate MOSFETs (FGMOS) [1-2]. Out of these, FGMOS presents a unique advantage of programmability of the threshold voltage. The other advantage of FGMOS is its compatibility with standard double-poly CMOS process technology. The FGMOS transistors have found many applications in electronic programming [3], digital-to-analog (D/A) and analog-to-digital converters [4], neural networks [5], voltage-controlled resistors [6]-[9], operational transconductance amplifier [10], multipliers [11], squarers [11]-[12], etc.
The voltage-to-current (VTC) converter is extensively used in the design of mixers/ modulators, voltage-to-frequency converters and interface units between circuits employing voltage-mode signal processing and those using current-mode processing. In addition, VTC converters are used as basic building blocks to perform various computational functions, such as square-rooting, squaring, multiplying, sum of squares and difference of squares, etc. [13]-[14]. The linearity and bandwidth are the usually concerned specifications of VTC converter which dominate whether its performance is adequate. The nonlinear effects of VTC mainly including nonlinear second-order V-I characteristic, body effect, mobility degradation, temperature variation and so on [15-19]. Recently, many researchers have been developed a fixed gain V-I converter input stage with programmable gain current mirrors [20]-[23]. However, these structures increase
complexity and power dissipation. In this paper, we have proposed a wide band linear VTC converter with mobility degradation and channel length modulation compensation.
The paper is organized as follows. The operation of the FGMOS is described in section 2. In section 3, the FGMOS based VTC converter is proposed. The detailed analysis of second-order effects on the performance of the proposed VTC converter is discussed in section 4. In section 5, SPICE simulation results are presented to verify the theoretical analysis and to demonstrate the effectiveness of the proposed circuit. The paper is concluded in section 6.
2 Operation of FGMOS
The basic structure of n-type, N-input FGMOS is shown in Figure 1. The first poly-silicon layer over the channel forms the floating gate and the second poly-silicon layer forms N-input gates that are located over the floating gate. The symbol and equivalent circuit model for an N-input FGMOS are shown in Figures. 2 (a) and (b), respectively. In both the figures, Vj (for i = 1, 2,_, N) are the control input voltages and D, S and B are the drain, source and substrate, respectively.
Fiaure 1: N-input FGMOS
Figure 2: FGMOS (a) Symbol (b) Equivalent circuit
The N-input control gates are capacitively coupled to the floating gate. Hence, the voltage on the floating gate (VFG) can be determined using the charge
/-/^r^cqi-x/oti/^r» Ioia/ oc n/ll-
y Ci (Vi - Vro )+ Cf, (Vcs - Vpo	(Vss - VpQ )+
i=l
+ Cfb(VBS-VFG)+QFG=0
(1)
Where C1, C2, C3, CN are the input capacitances
n
between control gates and floating gate, ^ Cj is the
i=1
sum of N-input capacitances, Cfd is the parasitic capacitance between floating-gate and drain, Cfs is the parasitic capacitance between floating-gate and source, Cfb is the capacitance between floating gate and substrate, Vi is the input voltage of ith input gate, VDS is the drain-to-source voltage, VSS is the source voltage, VBS is the substrate-to-source voltage (usually, the value of VBS is chosen as zero volt to avoid body effect), and Qfg is the residual charge.
The residual charge QFG is trapped in the oxide-silicon interface during the fabrication process. The trapped residual charge gives rise to large variations in the threshold voltage of the FGMOS. The removal of the trapped charge in the FGMOS is possible by using the method suggested in [25-26], in which the first poly-silicon layer is connected to the metal-k (where k represents the top most metal layer, which is deposited and etched last) layer. By this contact, the floating gate is not connected to any other part of the circuit, so it will not affect the operation of the FGMOS. Therefore, Eq. (1) reduces to
+ CfdVns + CfsVss
=

C
(2)
where CT is the total capacitance and is given as
Ct	+ Cfs + Cfb	(3)
i=1
N
If X Ci >> Cfd, Cfs, Eqs. (2) and (3) are modified as:
N
y cv

n

N
C C
(4)
(5^

The current equation of N-input FGMOS has been obtained by modifying the current equation of conventional MOSFET. The current Ip in the saturation region is expressed as follows:
K„
E CiV
n




where Kp = mpCox (W/L) is the transconductance parameter, ^p is the mobility of holes, Cox is the gateoxide capacitance per unit area, (W/L) is the aspect ratio and VTp is the threshold voltage.
3 FGMOS based voltage-to-current
converter
The proposed FGMOS based voltage-to-current (VTC) converter is shown in Figure 3. In this figure, the FGMOS transistors M1, M2, M3 and M4 are used to develop voltage-to-current conversion whereas the conventional MOS transistors M5, M6, M7 and M8 are used to provide proper biasing condition. All these transistors are biased in the saturation region. The transistors M1, M2, M3 and M4 are perfectly matched i.e. Kpi = Kp, VTpi = Vtp and ki1 = ki2 = k1, where i = 1,2,3,4. The applied bias & input gate voltages of transistors M1, M2,
M3 and M4 are Vb &V,N1, Vb V and V &V respectively.
"|N2'
The transistors M and M form the current mirror and
56
transistors M7 and M8 set the bias current. From Figure 3, it is evident that there is no body effect in the proposed circuit. The output current I is given as
lo = II - l2 =(lp1 + Ip2 )-(lp3 + Ip4 )
(7)
Where I , I , I , and I , are the currents of transistors
p1 p2 p3	p4
M1, M2, M3 and M4, respectively.
Using Eq. (6), the currents I 1, I 2, I 3, and I 4 are given as
Ipi = ^^(Vdd -ki (Vb + ViNi )-|Vtpi) Ip2 = ^^ (Vdd - ki (Vb - Vin2 )- Vtp )2
(8)
(9)
Ip3 = ^^r(Vdd -ki (Vb - ViNi)-|Vtp|
K
Ip4 = ^^(Vdd -ki (Vb + Vin2)-|VtpI)
(10)
(11)
Where k1 = C1/CT is capacitive coupling ratio, VIN1 & VIN2 are input voltages, Vb is the bias voltage and VDD is the supply voltage.
Substituting Eqs. (8) - (11) in Eq. (7), the output current Io is given as
lo = A (Vin2 - ViNi)	(12)
where A = 2Kp k^ (v^d -k^Vb -|Vtp|).
Equation (12) gives the linear relationship between the output current (Io) and the differential input voltage (VIN2 - VIN1). Hence, Figure 3 behaves as VTC converter.
4 Second order effects
In this section, the effects of channel length modulation and mobility degradation on the proposed VTC converter are discussed.
4.1 Channel Length Modulation Effect
The current Ip of 2-input FGMOS including channel length modulation effect is given as
Ip = (Vdd - ki (Vb + ViN )-1 VTP |(l + ^VDS ) (13) where 1 is the channel length modulation parameter. Considering this effect, Eqs. (8)- (11) are modified as
Ipi = (Vdd -ki (Vb + ViNi)-|VTPI) (l + ^VDSI)(14) =
K
Figure 3: Proposed FGMOS based VTC converter
■(Vdd -ki (Vb - Vin2)-|Vtp)2 (1 + ^Vds2 )(15) Ip3 = (Vdd - ki (Vb - ViNi)-|VtP ) (1 + ^Vds3 ) (16)
K	\2
Ip4 (Vdd -ki (Vb + Vin2)-|VtP) (1 + ^Vds4)(17)
From Figure 3, it can be seen that VDS1 = VDS2 and VDS3 = VDS4. Substituting the values of I 1, I 2, I 3, and I 4, from Eqs. (14)-(17) and Vds1 = Vds2 & Vdps3 =pVdps4 in Eq. p(7), the output current Io is given as
lo = A (Vin2 - ViN, )+ B + C + D	(18)
where A = 2Kp ki (v^d -kjV^ -|V^p|);
B = XKp (Vdd - kiVb -^ 2
V
Vp|)(Vdsi - Vds3 ); C = ^2k2Kp (v,Ni + V,n2 )(Vdsi - Vds3 ) and D = Xki Kp (Vdd - kiVb -1 Vtp i )(Vdsi + V^sb )(V,n2 - V,ni ).
For smaller values of (V^^, - and (V - V|N1), the effect of channel length modulation in Eq. (18) can be neglected.
4.2 Mobility Degradation Effect
The current Ip of 2-input FGMOS including mobility degradation effect is given as
K„
(Vdd - ki (Vb + ViN )-| VtpI )2
1+e(VDD - ki (Vb + ViN)- |Vtp| )
(19)
In Eq. (19), e(vDD - ki (¥„ + V,«)- |Vtp| ) <<1, where 0 is the mobility degradation parameter. Using Binomial theorem expansion and neglecting the higher order terms, Eq. (19) is approximated as
Ip (Vdd -ki (Vb + Vin)-V^pl(l-e(vDD -k, (V^ + V,n)-|Vtp|))
(20)
Including this effect, Eqs. (8)- (11) are modified as
Ipi ^^(Vdd -ki (Vb +V,Ni)-|Vtpi) (l-e(vDD -ki (Vb + V,ni)-|V-rp]))
(21)
Ip2 (Vdd -ki (Vb -Vin2)-|Vtp|| (l-e(VDD -ki (Vb -V,N2)-|VtpI))
(22)
Ip3 (Vdd -ki (Vb -V,Ni)-|Vtpi) (l-e(VDD -ki (Vb -ViNi)-|Vtpi))
(23)
Ip4 (Vdd -k, (Vb +Vin2)-|Vtp|| (l-e(VDD -k, (Vb +V,N2 )-| VtpI ))
(24)
Using Eqs. (21)-(24) in Eq. (7), the output current Io is given as
I„ =2Kp ki (Vdd -k,Vi -|Vtp|)(V:n2 -V^i)-3ekiKp (Vdd -k,V, -|VTp|;f (V,,^ -V:,,O-0Kpk? (v^^ -V^^ ) (25)
or
Io=A(ViN2 -ViNi)
^f(vDD-kiVb -VTp|)-2k:
e 2 (Vi2n2 +V,2ni +V,n2V,ni )

Vnn -kiVb -
From equation (26), it can be seen that the second and third terms are very smaller than the unity, causes only the gain error. Since output current (Io) is varied with the differential input voltage (
ViN2 — ViNi), mobility degradation effect can be neglected.
5 Results and Discussion
The proposed VTC converter has been simulated using SPICE in 0.25mm CMOS technology. The VTC converter operates with the supply voltages of±0.75V. The various parameters of the designed VTC converter are listed in Table 1.
Table 1: Various circuit parameters
Circuit parameters	Values
CMOS Technology	0.25mm
Vb	0.75V
VTp	-0.55
A	9.6X10-3
e	0.05
Figure 4 shows the I-V characteristic of VTC converter and plots the output current Io versus differential input voltage V |N2 - V|N1. In this figure, blue and red lines denote the current/voltage characteristic for V |N2 while V |N1 = 0 and for V |N1 while V |N2 = 0 respectively. Figure 5 shows the THD obtained in the output waveform as a function of the peak-to-peak differential input voltage. From this figure, it is observed that for differential input voltage swings as large as 1.5V, distortion is still low (< 0.9%).
The total power dissipation of this circuit is .84mW. Figure 6 shows the frequency response ofVTC converter and it is observed that the response remains constant till 1.63GHz.
-800mv -600mv 400mv -200mv
■•«iia)
200mv	400mv	600mv koomv
Figure 4: I-V characteristic of the proposed VTC converter
I
Conclusion
Figure 5: THD vs. differential input voltage amplitude
Figure 6: Transconductance (Io/(V|N2-V|N1)) curve for Figure 3
Table 2 compares the proposed FGMOS based voltage-to-current converter and the voltage-to-current converter reported by Srinivasan et al. in [27]. It is observed that FGMOS based voltage-to-current converter proposed in this manuscript has lower supply voltage requirement, lower power dissipation and wider input voltage range as compared to the existing circuit.
Table 2: Comparison of FGMOS based voltage-to-current converter with the voltage-to-current converter reported in [27]
Circuit parameters
Supply voltage
Voltage-to- Proposed FGMOS current converter based voltage-to-[271	current converter
CMOS technology
Input voltage range
Power dissipation
-3dB frequency
THD
Not available
0.25 um
+ 500 mV
Not available
200 MH7
Mot a\/ailahlp
+ 0.75 V
0.25 um
+ 750 mV
840 uW
1 63 GH7
I ess than 0 Q%
In this paper, a new low-voltage FGMOS based VTC converter operates with the supply voltages of ± 0.75V has been presented. The inherent advantages of this circuit are wide input range, low power dissipation, low THD and wide frequency range which make it suitable for low-voltage signal processing applications. The analysis of the channel length modulation and mobility degradation effects show that they have little influence on the proposed circuit.
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Arrived: 16. 02. 2013 Accepted: 26. 08. 2013