ISSN 0352-9045 Informacije IMIDEM Journal of Microelectronics, Electronic Components and Materials Vol. 49, No. 2(2019), June 2019 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 49, številka 2(2019), Junij 2019 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 2-2019 Journalof Microelectronics, Electronic Components and Materials VOLUME 49, NO. 2(170), LJUBLJANA, JUNE 2019 | LETNIK 49, NO. 2(170), LJUBLJANA, JUNIJ 2019 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2019. All rights reserved. | Revija izhaja trimesečno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale - Društvo MIDEM. Copyright © 2019. Vse pravice pridržane. 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Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madic Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana Informacije (midem Journal of M Journal of Microelectronics, Electronic Components and Materials vol. 49, No. 2(2019) Content | Vsebina Original scientific papers Izvirni znanstveni članki M. T. I. Badal, M. Bin I. Reaz, M. A. S. Bhuiyan, C. A. Dhawale: Nano CMOS Charge Pump for Readerless RFID PLL 53 M. T. I. Badal, M. Bin I. Reaz, M. A. S. Bhuiyan, C. A. Dhawale: Nano CMOS črpalka energije za RFID PLL brez čitalca W. Tangsrirat: Linearly Tunable CMOS Voltage Differencing Transconductance Amplifier (VDTA) 61 W. Tangsrirat: Linearno nastavljiv CMOS napetostni transkonduktančni diferencialni ojačevalnik (VDTA) X. Huang: Simulation on the Interfacial Singular Stress-strain Induced Cracking of Microelectronic Chip Under pPower On-off Cycles 69 X. Huang: Simulacija razpok mikroelektronskega čipa zaradi posameznih mejnih stresov pri ciklih vklapljanja napajanja A. M. Garipcan, E. Erdem: Implementation of a Digital TRNG Using Jitter Based Multiple Entropy Source on FPGA 79 A. M. Garipcan, E. Erdem: Uporaba digitalne TRNG na FPGA z uporabo več entropijskih virov na osnovi tresenja D. Cheng, P. Zhang, F. Zhang, J. Huang: Fault Prediction of Online Power Metering Equipment Based on Hierarchical Bayesian Network 91 D. Cheng, P. Zhang, F. Zhang, J. Huang: Napovedovanje izpada na opremi merjenja moči na osnovi hierarhične Bayesianove mreže M. Možek, B. Pečar, D. Resnik, D. Vrtačnik: Piezoelectric Micropump Driving Module with Programmable Slew-Rate and Dead-Time 101 M. Možek, B. Pečar, D. Resnik, D. Vrtačnik: Krmilni modul piezoelektričnih mikročrpalk z nastavljivo hitrostjo spremembe in mrtvim časom krmilnega signala Doctoral theses on Microelectronics, Electronic Components and Materials in Slovenia in 2018 113 Doktorske disertacije na področju mikroelektron-ike, elektronskih sestavnih delov in materialov v Sloveniji v letu 2018 Front page: Naslovnica: Body teperature load Temperaturna obremenitev (X. Huang) (X. Huang) 51 52 Original scientific paper Informacije ímidem Journal of M https://doi.org/10.33180/InfMIDEM2019.201 Journal of Microelectronics, Electronic Components and Materials Vol. 49, No. 2(2019), 53 - 60 Nano CMOS Charge Pump for Readerless RFID PLL Md Torikul Islam Badal1, Mamun Bin Ibne Reaz2, Mohammad Arif Sobhan Bhuiyan3, Chitra A. Dhawale4 1RMIT University, Department of Electronic and Telecommunication Engineering, Melbourne, Victoria, Australia 2University Kebangsaan Malaysia, Department of Electrical, Electronic and System Engineering, Bangi, Selangor, Malaysia 3Xiamen University Malaysia, Department of Electrical and Electronics Engineering, Sepang, Selangor, Malaysia 4P.R.Pote College of Engineering and Management, Department of MCA, Amravati, Maharashtra, India Abstract: Readerless RFID has become more significant for reliable wireless communication. The Phase Locked Loop (PLL) is among the most crucial functional block in the Readerless RFID where the PLL performance greatly depends on the Charge Pump (CP). Conventional CP circuits suffer from current mismatching characteristics which generate phase offset and spurs in the PLL output signals. To overcome these problems, the CP current mismatch has to be minimized. An enhanced CP circuit with zero current mismatch is presented in this article adopting an ideal current mirror technique and an additional inverter to provide a rail-to-rail voltage. The post-layout simulation shows that the proposed CP maintains the steady current over a wide range of output voltage from 0.1-1.8 V consuming the substantially lower power of 0.178 ^W. The CP circuit is designed in 130 nm CMOS process that operates at 1.8 V, and the core occupies 17 x 59.5 ^m2. The proposed CP will be a good solution for low voltage, high-frequency PLL structure which suffers from poor performance. Keywords: Charge pump; CMOS; Current mismatch; PLL; RFID Nano CMOS črpalka energije za RFID PLL brez čitalca Izvleček: RFID brez čitalca so postali pomembni za zanesljivo brezžično komunikacijo. Eden izmed kritičnih funkcijskih blokov RFID brez čitalca je, od črpalke energije (CP) odvisna, fazno sklenjena zanka (PLL). Konvencionalni CP trpijo z neuravnoteženo tokovno karakteristiko, ki vpliva na izhodni signal PLL. V izogib tem problemom je potrebno minimizirati CP. Članek opisuje izboljšan CP z ničelno tokovno neuravnoteženostjo z uporabo tehnike idealnega zrcaljenja toka in dodatnega inverterja za zagotavljanje napajanja. Simulacije nakazujejo da CP vzdržuje konstantni tok čez široko območje napajalne napetosti od 0.1-1.8 V in porabijo izredno malo moč 0.178 |W. Vezje je zasnovano v 130 nm CMOS tehnologiji pri napajalni napetosti 1.8 V. Velikost jedra je 17.0 x 59.5 ^m2. Predlagana rešitev je dobra za uporabo v nizkonapetostnihvisokofrekvenčnih PLL strukturah z nizkim učinkom. Ključne besede: črpaka energije; CMOS; tokovno neujemanje; PLL; RFID * Corresponding Author's e-mail: torikul.uniten@gmail.com; 1 Introduction At present, Readerless RFID systems are experiencing rapid growth because of the advancement of the wireless communication system. RFID is an identification system, where data is transferred/received via radio frequency among antenna, reader, and transponder. In an RFID system, electronic product code which is also known as the identification code is attached to 53 Md T. I. Badal et all; Informacije Midem, Vol. 49, No. 2(2019), 53 - 60 an object for tracking. A frequency synthesizer (FS) is a feedback system that produces one or more frequencies from a single or several frequency sources. Charge pump based PLL (CPPLL) is broadly used in a wireless communication systems for frequency synthesis; especially in radio, telecommunications and other electronic applications due to its simple feedback system [1, 2]. CPPLL is preferred because of low bias current [3, 4], low static phase offset [5-7] and large system gain [8, 9]. Furthermore, it performs the key role to ensure the stability of frequency synthesis [10, 11]. The PLL is generally composed of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), a voltage-controlled oscillator (VCO) and a frequency divider as depicted in Figure 1. Among all the functional blocks, CP is the most crucial block which significantly contributes to boosting the PLL's overall performance and stability. It changes the digital signal originating from PFD into an analog signal which in turn controls the VCO frequency [12]. The output voltage of the charge pump must be fixed when the PLL goes into a locked state at a specific frequency. Any change of that voltage results in frequency offset. [5, 13, 14]. In this regard, it is imperative to design a charge pump circuit that can generate a steady output current and can produce a superbly matched current with zero error in CPPLL. Figure 1: A Basic Block Diagram of CPPLL [4] Charge pump (CP) is the subsequent stage to the PFD, i.e., the output (UP and DWN) signals of the PFD are fed to the CP circuit. The key principle of a charge pump is to translate the logic states of the PFD into suitable analog signals to control the voltage-controlled oscillator (VCO) through a loop filter. Fundamentally, the charge pump is made up of current sources and switches as shown in Figure 2. The output currents from the CP is usually filtered by a low pass filter (LPF) that converts the charge pump current to an equivalent control voltage for the VCO. The conventional CP circuit consists of a charge and a discharge digital output current source, ICH and IDIS respectively described in Figure 2. A couple of transistor-based switches control both ICH and IDIS of the PFD. The two switches drive the loop filters and convert the output signals of the PFD to an analog voltage signal, Vcntrl, to tune the frequency of the VCO. The basic CP circuit suffers from many disadvantages, and as a consequence, several charge pump architectures have Figure 2: The basic concept of a charge pump circuit. been reported with their pros and cons in the literature [14]. The imperfection of a CP can be estimated by the current mismatch, timing mismatch, power consumption, and charge sharing. But the current mismatch is the most vital parameter which leads the PLL performance. The current mismatch implies the magnitude dissimilarity between charging and discharging current which is a crucial concern for the CP design [8, 15]. Figure 3 represents the charging and discharging time diagram of a charge pump circuit. Figure 3: Charging and discharging time diagram of a charge pump circuit The issues of current mismatch and leakage current introduce the phase error problem and produce PLL's reference spur [16, 17]. The current mismatch and leakage can be characterized as: A0= 2n (A0. + A0 . th + A0 .. ) v timing mismatch leakage' (1) 54 Md T. I. Badal et all; Informacije Midem, Vol. 49, No. 2(2019), 53 - 60 Where, A0, A0timing, A0mismatch, and A0leakage, are the phase error, timing mismatch, current mismatch and leakage current of the CP circuit, respectively. Equation 1 shows that the current mismatch is directly associated with phase error and PLL's reference spur which is otherwise called dynamic jitter [7]. The measure of the reference spurs Pr can be defined by [18] Pr = 20 log ' A0/bw a -20log REF 7 r / \ REF V /PL [dBc (2) and the loop bandwidth, f is given by fw = IcPKvcoR/(2nN) (3) Where, Pr is the PLL reference spur, fREF refer the reference frequency of the phase frequency detector (PFD), fBW stands for the loop bandwidth, A0 is the phase error, and fPL is the Loop filter's pole frequency. ICP stands for the CP current flow, KVCO refers to the VCO gain, R is the loop filter's resistor value where N is the divider value. Equation (2) describes that Pr is proportional to the loop bandwidth (fBW) and phase error (A0). Which means, the reference spurs can be reduced by increasing the reference frequency (fREF) and minimizing the phase error (A0) and loop bandwidth (fBW). Therefore, a CP design is required, which can reduce the current mismatch and maintain the constant current over a wide range of output voltage. By decreasing the current variation and mismatch, the performance of CP can be significantly improved. This reduces the PLL's spurs and static phase offset. Therefore, a CP that can reduce the current mismatch and maintains the currents constant across a wide range of output voltage is the key block for creating an optimum CPPLL system. Based on the literature review the current mismatch issue in CP design can be overcome in many ways [2023]. Low-voltage cascade topology [19, 20] is a conventional approach for minimizing the current mismatch at the cost of high output resistance. With this conventional approach, the current mismatching features in these CPs [19, 20] are scaled down to 2%. Besides, current mismatching is reduced to <1% in [6, 8] by integrating operational amplifiers (Op-amp) technique. This method integrates a negative feedback amplifier along with op-amp where Op-amp controls the voltage node maintaining high amplifier gain and provides the advantage of the large input voltage of charge and discharge currents [21]. The current mismatch in [7] is reduced by executing a differential CP with an active loop filter (LF) and common-mode feedback scheme. This scheme integrated an op-amp, an analog adder, and a reference voltage circuit. Huh et al [22] proposed a replica CP where the current mismatch is compensat- ed down to 1% by utilizing a bias generator. But, it requires a complicated circuit and creates a longer locking time. An unexpected current mismatch occurs in this architecture because of the fabrication mismatch between two CPs. The variables that are responsible for current mismatch are current sharing, charge injection and clock feed. Controlling the switching circuit by the transistor causes charge injection. Charge injection arises when the transistor is utilized to govern the switching circuit and produce limited capacitance to the current sources [20, 23]. Keeping in mind the end goal to diminish current mismatch and current variation, the power consumption and the output voltage dynamic range must also be considered. Besides, the approach with double stage op-amps in three rail-to-rail amplifiers is competent and established for reducing the current mismatch. It adjusts the current mirror gate bias that results in matching the output of the switch current with the drain current. Thus, it reduces the static phase offset significantly and minimizes the current mismatch. This article proposes an improved CP design in 130 nm CMOS process based on the current mirror method employing an inverter at the gates of transistors for providing a rail-to-rail voltage swing to accomplish adequate current matching. 2 Proposed Charge Pump Circuit A modified CP is designed based on current mirror technique integrating an inverter at the gates of the transistor to provide a rail-to-rail voltage swing that reduces the current mismatch and the voltage mismatch problem. The recommended CP circuit with current mirrors technique is presented in figure 4. The two current sources I1 and I2 are implemented as current mirrors. I1 and Up utilize PMOS transistors while I2 and Down use NMOS transistors. To increase the output resistance, the lengths of all transistors have been set to twice the minimal size at 700 nm [8]. To decrease the required amount of VGS the transistors with large widths were chosen so that the circuit could perform near the rail. An inverter is added at the PMOS transistor because its input must be inverted. Two inverters were set at the Dn gate to match the capacitances at the gates. Transistors M5 and M9 are connected to the node "aout" through the mirror transistors M6 and M8. This helps to decrease the impact of charge sharing. Moreover, the current mirror approach ensures that the charge and discharge currents retain a precise value for large voltage and guarantee that the Up and the Dn inputs are matched well. To assure both currents are equivalent, the current mirror is utilized for replicating current Up and current Dn from a single current source. 55 Md T. I. Badal et all; Informacije Midem, Vol. 49, No. 2(2019), 53 - 60 Figure 4: The proposed CP circuit based on current mirrors technique with inverters 3 Results and Discussions The post-layout results of the designed CP circuit are depicted in figure 5-9. From the post-layout simulation, it is shown that the proposed CP can reach maximum output voltage of 1.8 V. Generally, schematic simulation is viewed as an ideal case, while the post-layout simulation is considered the actual case, which incorporates reverse charge sharing or body impact and parasitic capacitance. The post-layout simulation output voltage result is identical in comparison with the schematic simulation. The output results of the designed CP are verified using ELDONET simulators in TSMC 130 nm CMOS process. Usually, the voltage amplitudes of "clka" and "clkb" are equal to the power supply (VDD). The simulation parameters are used at 10 MHz pumping clock frequency along with 0.1 pF pumping capacitor and the input voltage connected to a 1.8V power supply. It is found that the designed CP circuit is successfully pumped up and down for the output voltage range from 0.1V to 1.8V. Figure 5 shows that when the reset transistor is disconnected, "clkb" is set to be delayed by 1.5 ns. As a result, the output waveform is observed to be charged up to Vdd, and the Up signal is wider than the Dn signal. Figure 5: Post layout Result of Proposed CP Circuit: Pumping-Up @ (Vdd = 1.8 V, f = 10MHz) Figure 6 clearly shows the voltage trend at the Vc node moving down, and the Dn pulse is wider than the Up pulse. When the reset transistor is connected, and "clka" signal is delayed by 1.5 ns. Figure 7 is the zoomed plot of the simulation where the Dn and Up signals are perfectly in phase with the pulse widths being 224.6 ps (Dn) and 222.8ps (Up). The voltage of pumping-up and pumping down for the modified CP is in the range between 0.1 V and 1.8V. Figure 6: Post layout of the proposed CP Circuit: Pump-ing-down@ (Vdd = 1.8 V, f = 10MHz). Figure 7: Simulation result of proposed CP Circuit (When both clock sources set are perfectly in-phase) Figure 8 describes the current matching of the designed charge pump circuit, and it is observed that the maximum value for the current mismatch is zero. The curve (Figure 8 results) is taken from the Mentor Graphics EZwave analysis window. In EZwave window, the current mismatch is shown in the form of the graph instead of a percentage. The cyan and Blue, both graphs represent the current (Y-axis) graph with respect to time(X-axis). It can be seen in the figure that, the changes in the current of both graphs with respect to time (X-axis) is almost the same. There is no difference in current fluctuation which represent the Zero current mismatch. The zero current mismatches are achieved because of the low voltage NMOS cascade mirror technique and the addition of the M5 and M9 which are connected to the node "aout" through the mirror 56 Md T. I. Badal et all; Informacije Midem, Vol. 49, No. 2(2019), 53 - 60 transistors M6 and M8. For the PMOS switched mirror, the low-voltage cascade current mirror is connected to Gnd and for the NMOS switched mirror VDD is chosen as these are the values of Up and Dn signals at the lock which results in higher matching. Figure 8 proves that this modified scheme manages to decrease the effects of charge sharing and the current mismatch as well. Figure 8: Current Up and Dn Plots (current matching) Statistical analysis is very important in the absence of measured results. The Monte Carlo analysis of the proposed CP is presented in Figure 9 as a histogram representation. For 50 runs, the actual current mismatch of the proposed CP is zero. But randomly it shows the current mismatch varies from -2 to 2.5% which is very negligible. Besides, according to the netlist analysis of Monte Carlo simulation, the results showed that the current mismatch performance of the CP was stable around zero percentage. The Monte Carlo analysis was performed in the Mentor graphics environment. The performance comparison among proposed CMOS charge pump circuit and recently reported other CMOS CP designs based on different input and output parameters are given in table 1. Figure 9: Monte Carlo simulation of current mismatch of the proposed CP From table 1, it can be noted that the performance of the charge pump can be assessed by the current mismatch and power dissipation. For easy integration on a compact die, the designer tends to choose a simple circuit architecture for the charge pump. It can be observed from table 1 that the proposed CP circuit exhibits a many-fold reduction in both current mismatch and power dissipation compared to others designs. The major advancements have been achieved in the current mismatch of the proposed CP. The maximum current mismatch (<7%) occurs in [6] in table 1. The channel length modulation effect, the mismatch between PMOS and NMOS transistors and CMOS process variations cause this high current mismatch. Park et al. Table 1: Comparison of proposed CMOS CP performance with other CMOS CP architectures. Publication year and Ref. CMOS CP scheme CMOS process (^m) Supply voltage (V) Output voltage (V) Current mismatch Power consumed [23] [2011] Rail-to-rail op-amp 0.18 1.8 0.4-1.7 0.4% 0.9 mW [24] [2013] Basic CP-PLL 0.18 1.8 0.7-1.3 5% 1.6 mW [8] [2013] Digital calibration technique 0.18 1.8 - 1% 6.2 mW [11] [2014] Dickson CP with CTS's 0.18 1.8 1.8-4.2 - 1.2 mW [25] [2015] Feedback Op-amp 0.18 1.8 0.25- 1. <5% 13 mW [26] [2016] Wide-swing current mirror 0.18 1.8 0.3- 1.5 0.32% 0.38 mW [6] [2017] Feedback loop 0.18 1.8 0.3-1.4 <7% 740 nW Proposed CMOS CP Current mirror and chain inverter 0.13 1.8 0.1-1.8 0% 0.178 mW 57 Md T. I. Badal et all; Informacije Midem, Vol. 49, No. 2(2019), 53 - 60 [25] suggested architecture also suffers from a high current mismatch of <5% because of the finite output impedance of the current source and highest power consumption of 13 mW. A high power consumption and current mismatch are achieved at the same time by Zhiqun et al. [6] Implementing a rail-to-rail operational amplifier. The recently reported CP proposed by Lozada et al. [8] managed to achieve a good current mismatch of 0.32% and less power consumption compared to [6, 11]. Therefore, compared to results mentioned in table 1, it can be concluded that the proposed charge pump circuit has the lowest power consumption of 0.178 mW and provides the lowest (zero) current mismatch by using the current mirror and chain inverter technique which leads to a high-performance CPPLL. Moreover, in the case of output voltage, it is clear that the output voltage of the proposed CP is significantly higher than those of all previously designed [24-26] charge pumps. This signifies the notable enhancement in output over those achieved in previous researches. Figure 10 presents the complete layout of the proposed CP using TSMC 130 nm CMOS process. The dimension of the designed CP layout is 17 x 59.5 ^m. Since the CP circuit covers only a small area, it reduces the cost as well. In this design, the triple-well isolated MOSFET structure has been used. Multi-finger structure has also been implemented for transistors with large aspect ratios to keep the conductivity within acceptable limits. The layout is designed for the convenience of cascading an extra pumping stage to the output voltage for additional improvement. Fabrication in CMOS technology makes it a good candidate for integration with other CMOS-based devices or modules in telecommunications and other electronic applications. 21.2 25.5 29.B 34.0 38.2 42.5 46.S 51.0 55.2 59.5 17.0 Figure 10: Layout diagram of proposed CMOS CP using TSMC 130 nm CMOS technology 4 Conclusions The CP output parameters have a large impact on PLL performance. To meet the current demand of low power consumption, zero current mismatch and zero net charges, an enhanced charge pump circuit implementing the current mirror technique along with an inverter is presented in this research. The low voltage NMOS cascade mirror technique and additional transistors that are connected to the output node through the mirror transistors manage to achieve the lowest current mismatch. The post-layout result shows that the proposed charge pump circuit provides zero current mismatch at 1.8 V supply voltage with a pumping capacitor of 0.1 pF and consumes only 0.178 pW. The charge pump circuit is suitable for Readerless RFID applications and can be widely used in various low power wireless electronic devices such as a transceiver; disk read/write channels for high-speed data transmission, clock synthesis, synchronization, jitter reduction, etc. 5 Conflicts of Interest "The authors declare no conflict of interest." 6 Acknowledgment This research is financially supported by University Ke-bangsaan Malaysia. Project code: [AP-2017-008/1]. 7 References 1. Jiang X., Yu X., Moez K., Elliott D. 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Two-stage feedback-looped charge-pump for spur reduction in CMOS PLL, Analog Integrated Circuits and Signal Processing, 2015, 83(2), pp. 143-148. https://doi.org/10.1007/s10470-015-0517-z 59 Md T. I. Badal et all; Informacije Midem, Vol. 49, No. 2(2019), 53 - 60 26. Lozada O, Espinosa G. A charge pump with a 0.32% of current mismatch for a high speed PLL, Analog Integrated Circuits and Signal Processing, 2016, 86(2), pp. 321-326. https://doi.org/10.1007/s10470-015-0676-y mons Attribution (CC BY) License (https://creativecom-mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 18. 11. 2018 Accepted: 14. 05. 2019 © ® Copyright © 2019 by the Authors. This is an open access article distributed under the Creative Com- 60 Informacije imidem https://doi.org/10.33180/InfMIDEM2019.202 Journal of Microelectronics, Electronic Components and Materials Vol. 49, No. 2(2019), 61 - 68 Linearly Tunable CMOS Voltage Differencing Transconductance Amplifier (VDTA) Worapong Tangsrirat Faculty of Engineering, King Mongkut's Institute of Technology Ladkrabang (KMITL), Bangkok, Thailand Abstract: This paper proposes an alternative way to implement a linearly tunable CMOS voltage differencing transconductance amplifier (VDTA). It has been designed by using the floating current source (FCS) and the current squaring circuit. The circuit achieves its linear tunability by squaring the long-tail biasing current of the FCS. In this way, the transconductance gains of the proposed CMOS VDTA can be varied linearly through adjusting the DC bias currents. As an application example, the proposed VDTA is used in the design of an actively tunable voltage-mode multifunction filter. The derived filter possesses the following desirable properties: simultaneous realization of three standard filter functions; employment of only two grounded capacitors; and electronic tunability of the natural angular frequency and the quality factor. The performance of the proposed circuit and its filter design application were examined by PSPICE simulations with TSMC 0.25-mm CMOS real process technology. Keywords: Voltage Differencing Transconductance Amplifier (VDTA); Current Squarer; MOS analog circuits; Low-voltage circuits; Electronically tunable. Linearno nastavljiv CMOS napetostni transkonduktančni diferencialni ojačevalnik (VDTA) Izvleček: Članek predlaga alternativno rešitev uporabe linearno nastavljivega CMOS napetostnega trnskonduktančnega diferencialnega ojačevalnika (VDTS). Načrtovan je z uporabo plavajočega tokovnega vira (FCS) in kvadriranjem toka. Vezje dosega linearno nastavljivost s kvadriranjem počasnega deleža toka FCS. Na ta način se lahko z nastavitvijo napajalnega toka linearno spreminja transkonduktančno ojačenje. Filter ima naslednje lastnosti: sočasna realizacija treh standardnih funkcij filtra, uporaba le dveh ozemljenih kondenzatorjev in elektronska nastaljivost wo in Q. Lastnosti so bile simuliranje v PSPICE okolju v TSMC 0.25-mm CMOS tehnologiji. Ključne besede: napetostni transkonduktančni diferencialni ojačevalnik; (VDTA); tokovni kvadrirnik; analogna MOS vezja; nizkonapetostna vezja; elektronska nastavljivost * Corresponding Author's e-mail: drworapong@gmail.com 1 Introduction A brief review of the recently reported active elements and an introduction to several new controllable elements are given in [1]. Among other things, the voltage differencing transconductance amplifier (VDTA) is one of attractive active devices with two-parameter control [2-6]. This device is a modified version of the previously introduced current differencing transconductance amplifier (CDTA) element, in which the current differencing unit at the input stage is replaced by the voltage differencing unit. Usually, the VDTA solution can be realized by composing two voltage-controlled current sources, which are interconnected internally. Each of them provides two independent transconductance gains (gmF and gmS), which are electronically adjustable by external DC biasing currents [5]. Therefore, the VDTA element is very useful in active circuit synthesis and quite suitable for electronically controllable analog circuits. Another advantageous feature of this element is that it can easily be used for transconductance-mode solutions due to its input signals being voltages while the output signals are current [2]. Several CMOS reali- 61 W. Tangsrirat; Informacije Midem, Vol. 49, No. 2(2019), 61 - 68 zations of the VDTA circuit have been described in the literature [2-4]. Previously, the CMOS implementation of the VDTA employing basic floating current sources (FCSs) and supply voltages of ±0.9 V was introduced in [2]. The improved CMOS VDTA was suggested in [3], in which the ideal current sources are realized with swing cascade current mirrors. This kind of current mirrors is used because it has good accuracy and high-output impedance, and the minimum output voltage swing is approximated to 2VDS(sat) [7]. In [4], the design of the CMOS VDTA was also reported, where both transcon-ductance sections were derived from the structure presented in [5]. In this structure, the well-known configuration of multiple-output second-generation current conveyor (MO-CCII) has been supplemented to obtain the required number of current outputs of the first transconductance section. However, their major disadvantage though is the well-known fact that their performance (namely the gain gm) is directly proportional to the square root function of the external DC biasing current. Due to this the tunability is non-linear, and their linear transconductance ranges are rather limited. The motivation of this paper is to develop the CMOS VDTA with linearly tunable transconductance. To this aim, the proposed CMOS VDTA utilizes the floating current source (FCS) in its voltage-to-current conversion. In the presented work, the CMOS current squaring functional circuit with the output current proportional to the square of the input current is employed as a biasing circuit for the FCS. The main feature of the proposed VDTA is that it exhibits an ability to linearly tune its transconductane gains by electronic means through the external DC bias currents. To illustrate the application of the proposed VDTA, the design of active voltage-mode multifunction filter with single input and triple outputs is considered. It realizes simultaneously the three standard biquadratic filters namely lowpass (LP), bandpass (BP) and highpass (HP) from each output of the circuit. Orthogonal electronic programmability of wo and Q is also discussed in detail. PSPICE simulations with TSMC 0.25-|mm CMOS process parameters are also reported, which demonstrate the linearity and effectiveness of the proposed VDTA and its application. ' 0 0 0 0' ~vf ' in 0 0 0 0 Vn iz S mF S mF 0 0 Vx Jx . _ 0 0 S mS 0_ _ Vz _ (1) yP o "n o- O Vj.. O V,_ Figure 1: Circuit symbol of the VDTA. where gmF and gmS are the first and second transconductance gains of the VDTA, respectively. In (1), the differential input voltage applied across the p and n terminals (vp - vn) is converted to a current flowing out of the z terminal (¡J by gmF. Similarly, a voltage across the z terminal (vz) is transformed to the current outward from the x+ and x- terminals by gmS. 3 Basic functional circuits 3.1 Current-squaring circuit Fig.2 shows a current squaring circuit (M1-M3) based on the square-law characteristic of MOS transistors biased in the strong inversion region [8-10]. The current-controlled biasing circuit (MB1-MB2) is introduced in order to supply the bias voltage VB, where IA is the bias current. Assuming that all transistors are properly biased to operate in saturation mode and obey the ideal square-law function, the relation between the output current ISQ and the input current IB is given below. 2 Basic concept of the VDTA Basically, the VDTA is an alternative versatile active building block, having five high-impedance terminals, as symbolically shown in Fig.1. The characteristic between terminal voltages and currents can be described by the following matrix relation: 1SQ 8I, (2) To guarantee a proper operation, the input current IB is restricted within the range: 4 L < h < 4L (3) 34 W. Tangsrirat; Informacije Midem, Vol. 49, No. 2(2019), 61 - 68 Figure 2: Current squaring functional circuit. We observe from eq. (2) that ISQ is the squaring function of IB with the gain equal to (1/8!^). In addition to eq. (2), the current ISQ is ideally temperature insensitive. Figure 3: CMOS FCS circuit. 3.2 Floating Current Source 4 Proposed linearly tunable VDTA Fig.3 shows the circuit diagram of the floating current source (FCS) [11], which will be used as a fundamental circuit for exhibiting the transconductance gain of the proposed VDTA. The circuit can be viewed as two long-tailed differential pairs of PMOS and NMOS connected in parallel. It converts the differential input voltage (vd = v+ - v) into two balanced output currents i and io-. The NMOS transistors M4 and M5 are identical and the PMOS transistors M and M, are also identical. Assum- 6 7 ing that all the transistors are working in saturation region, an effective small-signal transconductance of the FCS can be expressed as [11]: g m o+ Vd g mn + g mp "td 2 (4) where g and g are respectively the transconduct- mn -'mp 1 7 ance values of the NMOS and PMOS transistors, equal to : Smn( p) = -\J Kn( p )10 In above expression, Kn(p) = _ Mn(p)Cox W (5) m ,, is the aver" n(p) age carrier mobility for NMOS and PMOS transistors, Cox is the gate-oxide capacitance per unit area, Wand L are the effective channel width and length, and IO is the external DC bias current. Evidently from eqs.(4) and (5), the gm-value of the FCS circuit in Fig.3 is proportional to a square-root of the control current IO. A complete circuit diagram of the proposed linearly tunable VDTA (LT-VDTA) and its symbol are shown in Fig.4. Basically, it consists of two FCSs (M9F-M11F and M9S-M11S) in Fig.3 and two current squaring circuits (M1F-M3F and M1S-M3S) in Fig.2. The current-controlled DC level-shifting circuit MB1-MB2 and IA provide a bias voltage VB for the circuit. As seen in Fig.4, the currents ISQF and ISQS are mirrored to be the bias currents IOF and IOS of two FCSs by means of the current mirrors M4F-M8F and M-M, respectively. It can be arranged that if (W/L) = (W/L)5F = 8(W/L)4F and (W/L)6S = using eq.(2) and considering lOF have : J 2 I — bf lOF ~ J i A (W/L)5S = 8isqf and os 8(W/L)4S, then, : ^SQ, We (6) and 12 T _ 1 BS 1OS T A (7) Substituting eqs.(6) and (7) into (5), and solving for the first and second transconductance gains of the proposed LT-VDTA in Fig.4, the results are : SmF Km1 BF and SmS ~ Km^BS (8) (19) o- 63 W. Tangsrirat; Informacije Midem, Vol. 49, No. 2(2019), 61 - 68 where K = (a) 4K 2[Ta (10) parameters of TSMC 0.25-|mm CMOS technology. The transistor sizes used for simulation are listed in Table 1. Bias voltages were ±V = 1.5 V and bias currents IA were 50 |A +v Q> ^(p MB, Mb; VB 1 1 MiF ni 1 1 — 1 'SQF VB I Mj5 L* 1 l 1 1 — 1 1 -| Mils Mi25 0 E I' Mas Ml 2L VB , IBS Mls M3S Mis (b) rp O- v„ p x+ LT-VDTA n x- -O V,- -O V,, Figure 4: Proposed CMOS VDTA with linearly transcon-ductance tuning. (a) complete circuit diagram; (b) its circuit symbol Since Km is considered as a constant value, eqs.(8) and (9) imply that the transconductances gmF and gmS of the proposed LT-VDTA can be adjusted electronically and linearly by IBF and IBS, respectively. As was stated earlier, in order for the proposed circuit to operate correctly, the linear operating condition for the input controlling currents IBF and IBS is bounded according to eq.(3). Owing to the performance of the traditional FCS stage used in the proposed LT-VDTA structure of Fig.4, the output resistances at terminals z, x+ and x- are not high enough for some applications. In order to increase the output resistance level, the improved FCS [12] can be employed for this structure. However, while the output resistance value is improved, the output voltage swing drops by up to VDS(a). 5 Simulations, results and discussions For all the circuits examined in this work, the computer simulations with PSPICE are performed using model -v Table 1: Transistor sizes of the proposed LT-VDTA in Fig.4. Transistors W (mm) L (mm) MBI - MB2, MIF - M2F, MIS - M2S, M4F, M4S, M7F, M7S 7 0.25 M3F, MSS 6 0.25 M5F - M6F, MSS - M6S 49 0.25 M8F, M8S 6.2 0.25 M9F - M10F, M9S - M10S 17 0.25 M11F - M12F, M11S - Mi2S 24 0.25 The CMOS current squaring circuit in Fig.2 is simulated. Fig.5 illustrates the DC current transfer curves of the current squaring circuit in Fig.2, obtained for the input controlling current IB value ranging from -200 ||A to 200 ||A. It can be deduced from the simulation results that the circuit performs the current squaring operation as expected. Figure 5: DC current transfer curves of the current squaring circuit in Fig.2. In order to demonstrate the linear tuning performance of the proposed LT-VDTA in Fig.4, the simulation for the 64 W. Tangsrirat; Informacije Midem, Vol. 49, No. 2(2019), 61 - 68 transconductance gmF is carried out. Fig.6 shows the gmF variations as a function of the input controlling current lBr In these plots, the simulated results and the expected values are compared, and in good agreement over a considerable input range from 20 mA to 180 mA. It is clear from the curves that the proposed circuit can be tuned linearly by means of the current IBF. 3.02.82.6- 2.4- 2.2- 2.01.8- 1.6- > X 1.4 bo 1.21.0 0.8 0.4 0.2 0.0- simulated s / / > ✓ / S / sS r. // // // A J / -o 0 40 60 8 0 1( )0 i: 0 U 10 li 0 U 10 200 220 240 260 280 3C Ibf OA) Figure 6: Expected and simulated gmF of the proposed LT-VDTA of Fig.4 as a function of IBF. The DC transfer functions of the proposed LT-VDTA in Fig.4 are also simulated and shown in Fig.7, with v.d (= vp - vn,) continuously changing from -400 mV to 400 mV, and IBF being equal to 50 mA, 100 mA and 150 mA, respectively. For B = 150 mA, the circuit has a linear region over ±180 mV and non-linearity error is less than 9.16%. 200 -200 -400 -400 \ \ 1 Ibf ---50//A -100 //A y / -200 0 v*(mV) 200 400 Figure 7: Simulated DC transfer characteristics between v.d and iz with tuning ^ To study the AC transfer characteristic of the proposed LT-VDTA, the simulated frequency responses for gmS when Ibs is swept from 50 mA to 150 mA with 50 mA step size are plotted in Fig.8. According to Fig.8, the useful bandwidth of about 400 MHz can be observed. In addition to the simulation results, the maximum power dissipation is 6.25 mW, when vjd, = 180 mV, and Ibf = B 150 mA. The quiescent power dissipation is 1.34 mW, when v , I and I are zero. id BF BS Figure 8: Simulated frequency characteristics of gmS with tuning IbS. 6. Active voltage-mode multifunction filter realization To demonstrate the effectiveness of the proposed LT-VDTA, an active voltage-mode multifunction filter of Fig.9 is realized as a design example [13]. The circuit consisting of two proposed LT-VDTAs in Fig.4 and two grounded capacitors realizes three standard biquadratic filtering functions, i.e. lowpass (LP), bandpass (BP) and highpass (HP), simultaneously without changing its configuration and without the need to impose component constraints. Straightforward analysis of Fig.9 using eq.(1) yields the following three voltage transfer functions. H LP = VM = H f \ g mF 2 g mS 2 Vn (s) CC D(s) H = VM BP Vn (s) =H and VHP(s) TT _ ' HP\"/ _ TT H hp =-— He vm (s) where _ gmF\ / \ gmF 2 s V 1 J L D(s) J ' s1 ' . D(s). (11 (12) H (13) (14) SmSl 1 65 W. Tangsrirat; Informacije Midem, Vol. 49, No. 2(2019), 61 - 68 D(s) = s2 + gmF 2 gmS 2 S + gmF1gmF 2 gmS 2 gmS1C1C2 (15) and gmR and gmSj (i = 1, 2) are respectively first and second transconductance gains of the i-th LT-VDTA. It follows from eqs.(11)-(15) that the natural angular frequency (w) and the quality factor (Q) of the filter are gmF1 gmF 2 gmS 2 g mS1 C] (16) and Q = SmF lSmS1C1 SmF 2 gmS 2C2 (17) Figure 9: Actively tunable voltage-mode multifunction filter realization using the proposed LT-VDTAs. To achieve independent filter parameter control, a proper design can be developed by setting equal transconductances such that gm1 = g = gmS1 and gm2 = gmF2 = gmS2, then wo and Qfrom eqs.(16) and (17) turn to g m 2 C C 12 (18) and Q _ gm1 C1 gm2\ C2 (19) The parameter wo can be tuned separately by changing g v The transconductance ratio of g , and g ^ can be used for an adjustment of the parameter Q. However, if independent electronic control is needed, only gm1 could be used for Q control. Furthermore, from eqs.(16) and (17), the active and passive sensitivities of w and Q can be expressed as: S SmF\> gmF 2>SmS 2 and —S SmS 1 S , Sc c 2 C1,C2 1 -- (20) 2 sQ g =-sq g = -, sQ =-SQ =1 (21) gmFl, SmSl SmF 2>SmS 2 ^ C 2 _ qQ Both are low, and equal to 0.5 in magnitude. As a design example, the multifunction filter of Fig.9 has been realized to obtain the LP, BP and HP responses with the natural angular frequency fo = wo/2p @ 5.50 MHz and the quality factor Q = 1. For this purpose, the circuit components were set to: IB = = /^ = = IBS2 = 70 mA (gm = gmF1 = gmS1 = gmF2 = 9mS2 @ 0.66 mA/V), and C1 = C2 = 20 pF. The simulated LP, BP and HP amplitude responses of the circuit are shown in Fig.10, where the simulated values of f were found to have a maximum o deviation of 2.83% from the expected values. In this simulation, the total power consumption of the designed filter is about 4.51 mW. Figure 10: Simulated AC transfer responses for the actively voltage-mode multifunction filter in Fig.9. In Fig.11, the electronic adjustment of the BP characteristic is illustrated by simulating multiple values of fo (i.e. fo = 4.50 MHz, 7.60 MHz, and 11.35 MHz), and keeping a constant Q = 1. Its responses for three values of fo are obtained by tuning identical bias currents IB = 50 mA, 100 mA, and 150 mA, respectively. = = 66 W. Tangsrirat; Informacije Midem, Vol. 49, No. 2(2019), 61 - 68 £ -20 o > —A- 4.50 MHz 7.60 MHz -fo = 11 .3 Al 8 Acknowledgements 1M 10M Frequency (Hz) 100M Figure 11: Simulated BP responses of Fig.9 with tuning fo. The simulation results of the BP response for variable Q and fixed fo are given in Fig.12. In this way, the values of Q were tuned via LT-VDTA 1, for Q = 5, 7, 10, which correspond to B (i.e., B = 1BF1 = 1BS1) = 250 mA, 350 jmA, 500 mA (gmi @ 2.40 mA/V, 3.33 mA/V, 4.86 mA/V). A constant f = 4.50 MHz was set with the bias currents of LT-VDTA 2 ^ 1B2 = 1BF2 = 1BS2 = 50 mA (g.2 @ 0.57 mA/V). 60 -20 -50+ 100k Q = 5 Q = 1 £=10 \ 1M 10M Frequency (Hz) Figure 12: Simulated BP responses of Fig.9 with tuning Q. 7 Conclusions In this work, a linearly and electronically tunable CMOS VDTA circuit is realized. The circuit realization is based on floating current sources (FCSs) for implementing the transconductance stages. The CMOS current squaring circuit is used for supplying the long-tail bias current of the FCs stages. Its transconductance gains are linearly tuned and accurately determined by the external DC supplied currents. The use of the proposed VDTA is illustrated with a realization of an electronically tunable voltage-mode multifunction filter, which employs two VDTAs and two grounded capacitors. PSPICE simulations, performed using TSMC 0.35-^m CMOS technology and confirming the performance of the proposed circuit and its application, are also given. This work was supported by King Mongkut's Institute of Technology Ladkrabang Research Fund [grant number KREF116001]. The author is grateful to Mr. Natchanai Roongmuanpha for his circuit simulation on an earlier version of the manuscript. Also, the author gratefully acknowledges the constructive comments and suggestions of all the anonymous reviewers, which have been very useful in the preparation of the revised version of the manuscript. 9 References 1. D. Biolek, R. Senani, V. Biolkova, Z. Kolka, "Active elements for analog signal processing: classification, review, and new proposals", Radioengineering, vol.17, no.4, pp.15-32, 2008. 2. A. Yesil, F. Kacar, H. Kuntman, "New simple CMOS realization of voltage differencing transconductance amplifier and its RF filter application", Radioengineering, vol.20, no.3, pp. 632-637, 2011. 3. A. Yesil, F. Kacar, "Electronically tunable resistor-less mixed mode biquad filters", Radioengineering, vol.22, no.4, pp.1016-1024, 2013. 4. J. Jerabek, R. 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Tangsrirat, "Voltage-mode multifunction filter using VDTA and grounded capacitors', Proc. the 6th Conf. Electrical Eng. Network of Rajamangala University ofTech. 2014 (EENET 2014), pp.533-536, 2014. mons Attribution (CC BY) License (https://creativecom-mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 11. 04. 2019 Accepted: 21. 05. 2019 © ® Copyright © 2019 by the Authors. This is an open access article distributed under the Creative Com- 68 Informacije imidem https://doi.org/10.33180/InfMIDEM2019.203 Journal of Microelectronics, Electronic Components and Materials Vol. 49, No. 2(2019), 69 - 77 Simulation on the Interfacial Singular Stressstrain Induced Cracking of Microelectronic Chip Under Power On-off Cycles Xiaoguang Huang China University of Petroleum (East China), Department of Engineering Mechanics, Qingdao, China Abstract: Thermal fatigue failure of a microelectronic chip usually initiates from the interface between the solder joint and substrate due to the mismatch in coefficients of thermal expansion (CTE). Because of the viscoelastic creep properties of the solders, the stress and strain at the solder/substrate interfaces are strongly dependent on temperature and time. Based on the established creep constitutive models of the solder materials, a three-dimensional thermomechanical analysis of the microelectronic chip undergoing power on-off cycles is conducted based on the finite element method (FEM). The singular interfacial stress-strain fields are obtained and the singular field parameters are quantitatively evaluated. Furthermore, the crack nucleation in power on-off fatigue test of the microelectronic chip is observed, to verify the conclusion that the singular stress-strain induces thermal fatigue failure from the solder/ substrate interface. Keywords: Thermal fatigue; microelectronic chip; creep; singular field; crack nucleation Simulacija razpok mikroelektronskega čipa zaradi posameznih mejnih stresov pri ciklih vklapljanja napajanja Izvleček: Različni termični koeficienti materialov so večinoma vzrok za odpvedi zaradi termične utrujenosti in pri čipu izhajano iz stične površine med lotom in substratom. Zaradi viskoelastičnosti lota je stress na mejni površini močno odvisen od časa in temperature. Uporabljena je tridimenzionalna termo-mehanična analiza vplivov ciklanja vklapljanja napajalne napetosti z uprabo metode končnih elementov. Kvantitativno so ocenjeni posamezni parametri in opažen je bil pojav nastajanja razpok zaradi stresa na stiku lot/substrat. Ključne besede: termična utrujenost; mikoelektronski čip; polzenje; nastanek razpok * Corresponding Author's e-mail: huangupc@126.com 1 Introduction The flip flat package technology is currently widely used in electronic engineering to meet the demands of high-speed functions and system miniaturization [1]. The high density and cost-effective requirements of the package structure have led to the emergence of small size and multiple input/output (IO) points in chip design. Solder joints, as the mechanical, electrical and heat-dissipating components, require excellent reliabilities during soldering and service [2-3]. In the soldering process, the formation of intermetallic compounds (IMCs) is a necessary condition for the forma- tion of solder joints, and the reliability of solder joints is highly dependent on the formation and growth of IMC at the interface [4]. With the growth of intermetal-lic compounds, stress concentration easily appears at the interface of solder joint due to the mismatch of coefficients of thermal expansion of the materials, which causes the cracking and reduces the service life of solder joints [5-6]. Due to the increase of packaging density, both the size and shape of solder joints appear in various combinations, a quantitative evaluation method of the strength and life for solder joints is strongly expected. 69 X. Huang; Informacije Midem, Vol. 49, No. 2(2019), 69 - 77 Under thermal cyclic loading, failure or fatigue crack generally initiates from the interface edge or near to the interface between the solder joint and substrate, and its mechanism is strongly affected by the stress singularity at the interface edge or stress concentration induced by the interface [7-9]. Therefore, it is of practical importance to determine the stress state at the interface, so that the susceptibility to thermome-chanical failure can be predicted for new geometry-to-material combinations. The traditional strength-based methods are not suitable since the stresses are singular even at the idealized interface edges or corners [10-12]. To overcome this concern, Hattori et al. [13] have suggested a singularity parameter approach for the interface reliability of plastic IC packages using two stress intensity parameters that characterize the stress distribution near a bonded edge along with the interface. Other authors [14-16] argued that the two parameters: singular order A and stress intensity factor K, can be used in a criterion for crack initiation or delamination for certain structure configurations. Generally, FEM is a valuable tool for determining the constants A and K. At the same time, finite element modeling enables the design to be evaluated before it is physically produced thus minimizing time and cost. The results obtained from the FEM modeling will be useful in suggesting design changes in terms of package geometry and choice of packaging materials. The purpose of this study is to develop an objective method to analyze the thermal cyclic behavior and to evaluate the failure of solder joints in a microelectronic chip. According to the creep results of solder materials, the nonlinear creep constitutive models are established. The three-dimensional thermomechani-cal analysis of the microelectronic chip under power on-off cycles is conducted, and the time-dependent stress and strain at the solder/substrate interfaces are obtained. Finally, the details that the singular stressstrain promotes the thermal fatigue failures from these interfaces are discussed when compared with the results from fatigue tests. 2 Package description The structure of the microelectronic chipset is presented in Fig. 1. It has nineteen pieces of chips, including two pieces of chip Q1, one piece of chip Q2, six pieces of chip Q3, four pieces of chip Q4 and six pieces of chip Q5, respectively. Their working powers are 35.7, 33.3, 25.8, 20.0 and 14.5 w, respectively. The schematic cross-sections of chip Q1-5 in layered structure are similar, i.e., substrate, insulate layer, Cu, SnAg3Cu0.5, Cu, Pb-5Sn, wafer and silica gel from bottom to top, as shown in Fig. 2. The main dimensions of chips Q1-5 are listed in Table1. Figure 1: Structure of the microelectronic chipset Silica gel Silicon Soider-PbSSn 1 - 1 Solder-SnAg^CuO.S Cu Insulate layer Substrate Figure 2: Schematic cross-section of the single chip Table 1: Dimension of five different types of chips (unit: mm) Chip type Wafer aqxbqxcq Solder Pb-5Sn A1xB1xC1 Solder SnAg3Cu05 A2xB2xC2 Q1 6.6x6.6x0.38 6.6x6.6x0.08 13x13x0.12 Q2 5.4x5.4x0.46 5.4x5.4x0.08 8x8x0.12 Q3 3.6x4.2x0.38 3.6x4.2x0.08 8x11.5x0.12 Q4 3.3x3.3x0.25 3.3x3.3x0.08 5.5x5.5x0.12 Q5 3.2x3.2x0.46 3.2x3.2x0.08 8x11.5x0.15 3 Numerical simulation process 3.1 Constitutive model of solder materials According to the theory of viscoelasticity, the typical strain rate-stress relationship of the solder is linear at 70 X. Huang; Informacije Midem, Vol. 49, No. 2(2019), 69 - 77 low stress, and power law creep at middle and high stresses. On the basis of the previous literature [17-18], a hyperbolic sine power constitutive model is adopted, in which the relationship of strain rate with stress is linear at low stress and is hyperbolic sine power at middle and high stresses, as shown in Eq. (1). At each temperature T, there exists a critical stress ov (T), which is used to separate the linear and power law creep stages. According to the creep results of two solder materials Sn3Ag0.5Cu and Pb5Sn, the strain rates under various stress levels and temperature-dependent ov are determined, as shown in Table 2 [19]. Sn3Ag0.5Cu: ¿= Pb5Sn: ^(sinh Ba)" exp(-H / RT) ifcrv (4,-4(r-rJ))