Kaotični kriptografski sistem z uporabo vezij FPGA - Jarc, Bojan (Informacije MIDEM, 2007)
In this paper we present a chaotic cryptographic system and its hardware realization. The core of chaotic cryptographic system is a multi-shift cipher (eq. 2, 3) or decipher (eq. 4) and pseudo-chaotic sequence generator (fig. 3),realized with second order digital filter. Relatively simple structure and executions of simple mathematical functions (addition, subtraction, scalar multiplication) allows us to use a hardware realization, suitable for high frequencies. A chaotic cryptographic system is composed of cipher and decipher circuit (fig. 5). For its realization we have used 16 bit fixed point arithmetic and FPGA XC3S500E circuit of Spartan 3E family. Plaintext digits was 16 bit long. At designing stage we have used combined schematic and language VHDL description approach (fig. 6). Maximum c1ock frequency at which cipher and decipher were inversive was 25 MHz (fig. 8 a, bl. Choosing the multi-shift function repetition number N = 7, al1ows us to encrypt the plain text with frequency 3,125 MHz. Performance was estimated for other FPGA circuits (table 1). For Virtex 4 FPGAs we've achieved maximal clock frequency 77,71 MHz at N -1.
Keywords: digitalni fitri; FPGA; kriptografski sistemi