Izvedba nerekurzivnega digitalnega sita s programirljivim poljem logičnih vezij v strukturi porazdeljene aritmetike - Osebik, Davorin (Informacije MIDEM, 1997)
In this article the hardware realization of a 15 tap general FIR digital filter in the distributed arithmetic structure with field programmable gate arrays is presented. This hardware structure is suitable for the implementation of digital filters with an arbitrary frequency response. The comparison between the standard and the modified distributed arithmetic structure is also presented, and the increase of the dynamic range of the output signal for 6 dB with the modified distrubuted arithmetic structure is shown. The digital filter consists of 12 bit analog to digital and 12 bit digital to analog converters,two Xilinx LCA circuits XC 3042 and 32k x 16 bit EPROM capacity with an access time of 100 ns. The response of the implemented low pass filter with the pass band frequency fp = 0.1 fs and the stop band frequency fs = 0.2 fs is obtained as frequency sweep method and for comparison with FFT of the output signal when the filter is exited with digital white noise signal in the input. In this complexity the attenuation of 30 dB and sample frequency fs of 333 kHz is obtained. Because of the 19 bit complexity of the arithmetic unit the quantization error of the output signal is less than 10?$sup-3$?.
Keywords: digitalna elektronika; digitalna obdelava signalov; električni filtri; LCA vezja; logična vezja; mikroelektronika