A MULTILAYER CHIP LOW VOLTAGE : THE FUTURE IN THE SUPPRESSION Characteristics Z. Živič KEKO, Žužemberk, Slovenia Keywords: voltage transients, protective devices, protection components, SMT, surface mount technology, multilayer chip Varistors, MLV chip Varistors, ZNO Varistors, thin sheet laminating technology, ceramic technology, leakage currents, surge currents, response times, nonlinear coefficients, surge absorptions, electrical breakdowns, fabrication processes, electrical properties Abstract: A low voltage ZnO multilayer chip varistor for surface mounting was developed using tape casting and green sheet laminating ceramic technology. Differently sized chip Varistors with breakdown voltage ranging from 4 V to 100 V were realised, featuring low leakage current, high nonlinear coefficient in a wide current range, very high surge current withstand capability (> 2000 A) and response time shorter than 5 ns. Very good stability on repetitive pulse of high amplitude and high energy level was also recorded. All these characteristics make multilayer chip varistor a very promising low voltage protection device. del: Izdelava in lastnosti Ključne besede: pojavi prehodni napetostni, naprave zaščitne, elementi zaščitni, SMT tehnologija montaže površinske, MLV chip varistorji večslojni, chip varistorji, ZNO varistorji, tehnologija nalivanja plasti tankih, tehnologije obdelave keramike, tokovi uhajavi, tokovi udarni, časi odzivni, koeficienti nelinearni, absorpcije udarov, preboji električni, procesi proizvodni, lastnosti električne Povzetek: Nizko napetostni ZnO večplastni čip varistor za površinsko montažo je bil razvit s pomočjo keramične tehnologije nalivanja tankih plasti. Narejeni so čip varistorji različnih dimenzij, s prebojnimi napetostmi v obsegu od 4 V do 100 V, z naslednjimi lastnostmi: nizki tok puščanja, visoki nelinerni koeficient v širokem tokovnem področju, sposobnost absorpcije tokovnih sunkov višjih od 2000 A in čas odziva krajši od 5 ns. Zelo dobra stabilnost proti tokovnim sunkom visoke amplitude ter visokih energij je tudi bila ugotovljena. Vse te lastnosti kažejo da je večplastni čip varistor zelo obetavna nizko napetostna zaščitna komponenta. 1. Introduction Electronic and electrical circuits can be subject to severe and sudden impulse voltage transients generated by lightning, switching and electrostatic discharge accumulated on the human body. A contemporary development in the field of electronics and especially microelectronics requires miniaturised, highly integrated and low power consumption devices. As a result of this, the requirements for reducing device sizes and operation at low voltages are becoming extremely important for all electronic components including protective or surge absorbing devices. Namely, lowering of the device geometrical dimensions, or scaling down principle, is widely used to improve * - This paper presents a part of the results accomplished within the project titled "Multilayer Electronic Ceramic Components", no. B-669, which was partially financially supported by Slovene Ministry of Science and Technology from 1991 -93. CMOS IC's performances as: speed, density, complexity, reliability and cost. The dimension lowering is followed by operating voltage lowering as well. At the same time, internal protection devices built into IC's (typically containing monolithic connected diffused resistor with two or four Zener diodes) have been reduced in size to minimise their impact on speed and circuit area. Therefore, protection efficiency of the internal protection decrease, so CMOS IC's become more sensitive to damage or malfunctions caused by supply voltage transients and electrostatic discharges. As a solution, electronic designers can either overspe-cify the circuits or use external protection. Final stability and quality of systems as well as economic balance call for the use external protection, not only of the whole systems or subsystems but of the individual sensitive components as well. Transient voltage overstress protective devices can be divided into three categories: filters ( R-C, R-L-C, etc.), crowbars such as gas discharge tubes orthyristors and low voltage clamps like varistors and Zener diodes. As far as low voltage surface mount devices are concerned only multilayer chip varistor (MLV) and Zener diode will be discussed. Both exhibit the necessary voltage - current relationship: at low voltages the current is very small, but when the applied voltage exceeds some predefined value (threshold), the device impedance decreases drastically and dissipates the excess energy which would be absorbed by the active component being protected. AZnO MLV as well as Zener diode have this property although the operating physical principles and technology are different as shown in Table 1. Both planar Si processing technology and pn-junction physics as a basis of Zener diode functioning are very well covered in literature^Shallow pn- junction depletion region directs the operation of Zener diode. Its breakdown mechanism is tunnelling and avalanche multiplication one. Zener diode breakdown voltage is regulated by the depletion layer width, i.e. by the charge carrier concentration on both sides of pn-junction as well as by its geometry. When the diode is in breakdown, the greatest part of the energy is dissipated exactly in the shallow depletion layer. In the case of varistor the physical model of its operation is not so 'clear', which will be one of the subjects of the discussion to follow. Table 1: General differences between Zener diodes and multilayer varistor General Characteristics Zener Diode MLV Basic material Si ZnO Structure Monocrystal Polycrystal Physical mechanism Tunneling & avalanche multiplication Thermoionic emission & hot carrier injection effect Barrier type Abrupt junction Double Shotky barrier Technology Planar Si Ceramic-thin sheet laminating 2. Fundamental Characteristics of ZnO Varlstors 2.1. Basic material While Zener diode is semiconductor component made on monocrystailine Si, varistor is polycrystalline semi-conductive electronic component on ZnO. Semiconducting ZnO of wurzite crystallographic structure is basic varistor material amounting to more than 90 % wt. This stnjcture is relatively 'open' allowing easy building-in of dopants and influencing the nature of defects and diffusion mechanism®. The most common defect in ZnO is the metal ion in the open interstitial site, leading to a nonstochiometric metal excess N-type semiconductor with band gap of 3.3 eV. Within the band gap there are donor and acceptor levels occupied by thermally induced intrinsic defects as shown in Fig. 1. _ 3.15 > 2 CJ ,8 >. Ol o š 1. ,2 2 |o. 7- lo i 0,05 e^Vo 2.8eV Vo' 2eV 5 aVeV 3.2 eV Figure 1: Energy - band diagram ofZnCf 2.2. Varistor Mlcrostructure Varistor is realised by homogenisation of ZnO powder with the oxide additives of Bi, Sb, Mn, Co, Cr, Ni, AI, etc. Forming of such a composite is performed by one of the ceramic procedures (dry pressing for example). After sintering, final polycrystalline ceramic structure, characterised by unique grain boundary properties that contribute to the nonlinear l-V varistor characteristics is obtained. As the flow of the electric current is controlled by electrostatic potential barrier of the grain boundaries, its electrical activity and mlcrostructure can be adapted to provide the desired special properties of the material. For this reason many material scientists have been extensively studied ZnO varistor mictrostructures, especially those of the grain boundaries'*'®. Their main concern was to investigate various crystalline phases, their 50 |jm Pyrochlqre Spinel ''■■'}.] B'Srnuth oxide Figure 2: Actual structure of ZnO varistor^ SiO Bi^Oj sintering 2^3 Compound ZnO Spinel Chemical formulation ZnO Zn-jSb20^2 Doping element Co, Mn Location Grains Co, Mn, Or Intergranular phase Pyrochlore Bij ^ m Q 0. X C z « <• M + C - 1 1, I Figure 4: ZnO varistor grain boundaries AES chemical analysis characteristic in the prebreakdown region changes its shape^°. Similarly, no correlation has been found between net charge stored at the grain boundary and Bi concentration. That's why it is generally assumed that absorbed Bi ions create some intrinsic interface defects which are capable of capturing an excess electron. Unlike Bi ions, O ions are completely mobile^", their concentration on the grain boundary being in the direct correlation to the i-V characteristic change, i.e. to the potential barrier height and the net charge stored at the grain boundary". The role of Bi in grain boundary activation is very interesting. On the one hand, no varistor effect is obtained without Bi doping. On the other hand Bi concentration at the grain boundary stays unchanged in the cases of postsintering annealing or electric loading, when l-V 2.3. Varistor Physics Several physical models have been proposed in the past to explain conductive mechanism in varistor^^'^®. Their inadequacy was in the fact that they could explain just some of the experimental results. Advances in micro-stajctural analysis at the atomic level and a wide range of electrical and spectroscopical measurement techniques helped Pike to establish the most comprehensive model, being later refined by Greuter and Blatter^^''"®. The model is based on the fact that a net interface charge at the grain boundary results from the trapping of an excess electron (or hole) by the appropriate interface states. The interface charge Qi is screened by the ionised bulk defects No, associated with intrinsic defects such as Zinc interstitial or Oxygen vacancies, in order to establish the overall charge neutrality. Visualising this process in an energy band diagram corresponds to the formation of a double Schottky potential barrier at the grain boundary as shown in Fig. 5. The current flowing across the grain boundary is controlled by the applied bias and the temperature dependent height of the potential barrier 0b (V, T). Solving the Poisson equation, several authors'"^'''®'''obtained that the potential barrier height is 0.9-1.0 eV. It should be pointed out that an increase in Qi results in a larger 0b, whereas a higher No reduces 0b. Applying thermoionic emission model, current flow through the grain boundary can be described by the equation: J = AT^ exp (-(e0s - en)/kT) (1 - exp(-eV/kT)), where A is a constant containing Richardson's constant, 6n= Ec - Ef and V is the applied voltage. The existence of the following four current components on the interface is obvious: the thermally emitted electrons travelling from the left to the right and backwards (being suppressed by the factor exp(-eV/kT)) and small current of the electrons being trapped and remitted from the interface states. The two last currents are responsible for the updating of Qi, and actually control the main current flowing over the barrier''®. When a bias is applied to the junction (V< 3 V), 0b will rapidly decay for a fixed Qi. However, if through the lowering of 0b new empty interface states can be filled, Qi increases and 0b is efficiently stabilised keeping the leakage current low. This is usually referred to as a pinning of b by the interface states. The strong pinning leads to a concentration of the voltage drop within a 10G0Ä wide region on the positively biased side of the junction. Near the top of the barrier, electric fields as high as 1 MV/cm can build up. Under this condition some electrons can get enough kinetic energy (became "hot") to create minority carriers by means of the impact Ionisation. The holes created in this way, diffuse back to the interface (tt < 10"''° s), partly compensate Qi and abruptly lower 0b initiating the breakdown. Energy-band diagram of "hot" electron-hole induced varistor breakdown, different trajectories of "hot" electrons and the creation by impact Ionisation are shown in Fig. 6. As the optical-phonon scattering at low energies (0.1 -0.4 eV) is the dominant loss mechanism in ZnO, a high starting field near the interface is the most important to overcome this critical energy range. On the basis of the ballistic Figure 5: Double Schottky barrier at a negatively charged grain boundary Figure 6: Energy-band diagram of a grain boundary barrier illustrating the hole induced breakdown Slip: homogenous, low viscosive Row materials : ZnO, Bi203,... Organic system: acrylic binder solvents,... 1 MILUNG i 1 CASTING Green sheeis: .^0 + 1 urn ! 1 Ag Pd electrode ink i ELECTRODE Ag or Ag Pd ink PRINTING i ELECTRODE 'TERMINATING FIRING TESTING Figure 7: ML V fabrication process steps data on threshold energy for electron-hole pair creation in ZnO (Eth« 3.7 eV) and the yield of the hole production and using the described model Greuter et. al.''® estimated single grain boundary junction breakdown to be Vb = 3.3-3.8 V, which is in a very good agreement with the experimental results. Besides, "hot"-electron-hole induced avalanche breakdown model can explain most basic experimental observations such as: high coefficient of nonlinearity (a > 40) and its dependence on doping, small negative signal capacitance at large bias, voltage overshoot effect under the excitation with fast pulses, electroluminescence phenomena observed at grain boundaries and many other''^ 3. Multilayer Chip Varlstor Ceramic tape casting and especially green sheet lamination technology have been very intensively developing during the last twenty years, in the first place owing to the development of the multilayer ceramic capacitor and hybrid integrated circuit substrates. These technologies set the basis for the development of the multilayer chip Varistor. Although the first article was published by Shohata et. a!.^® in 1981 there has been little published about this new protection component, which became commercially available not more than two years ago. 3.1. Technology 3.1.1. Fabrication Process Green sheet lamination process applied in presented MLV production experience is shown in Fig. 7. Varistor processing was based on fine particle high purity ZnO and other dopants. They were mixed in a nonaqueous system based on an acrylic binder in a ball mill for 15-20 h. The homogeneous low viscosity ceramic slip was tape cast into 30-100 ^m thick sheets. Tape cutting was followed by AgPd internal electrode screen printing and their stacking into 10 x 10 cm large green ceramic blocks. Ceramic blocks were then laminated and cut into chips sized 2.5 x 1.5 mm, 3.2 x 2.5 mm and 5.7 x 5.0 mm, which are popular SMD dimensions. After binder burn out, chips were sintered in an air atmosphere furnace at the temperature of 950-1100°C. Finally, external AgPd electrodes were attached and fired to make contact with comb-like inner electrodes as shown in Fig. 8.. Fig. 9 illustrates the outside view and final dimensions of realised chips while Fig. 10 shows optical microscope photographs of the microstructure of the cross sectioned MLV. Fired Ceramic Internal External Electrodes Electrodes Figure 8: A cross sectional illustration of a MLV # ....................................................... j ? 4 ^ 6 Figure 9: Outside view of differently sized hJiL Vs Figure 10: Microstructure photographs of a cross section of an MLV 3.1.2. Varistor Compositions Shohata et. al.^^ concluded that the utilisation of Bi203 in MLV ceramic system is not possible because it easily reacts with any metal used for internal electrodes, destroying the multilayer structure. That's why, instead BiaOa, they especially developed and suggested the usage of borosilicate-lead-zinc glass. Microstructurai analysis of the ceramic- electrode interface^® showed increased concentration of Bi in the case of low sintering temperatures (950°C), while at higher temperatures (1100°C) a lamelar reaction product, identified as PdBi204, was observed only in the "pockets" of a melt at the interface. TEM/EDS studies of the interface confirm that the reaction layer is neither continuous nor monophase. Due to that and opposite to the statements in it was shown in and it will be shown in this paper that usage of BiaOs is possible in varistor system without consequences either to the electrical characteristics or varistor reliability. Having this in mind, special varistor composition was designed^°'^^, comprising ZnO (>92 wt %) and oxide additives such as BiaOa, MnO, CoO, Sb203, etc. As the composition presents one of the design parameters, the care was also taken of the fact, that some differences exist in the case of the bulk Varistors and MLV, the final ceramic layer thickness being both small and comparable to the grain size in the later. Two such examples are illustrated in Fig. 11. and Fig. 12.. They show the dependence of nonlinearity coefficient and specific voltage on sintering temperature in the case of MLV (layer thickness » 17 jam) and bulk varistor (d = 1 mm), realised with the same composition. 1000 1050 T (°C) 1150 Figure 11: Nonlinear coefficient - a Versus sintering temperature 900 950 1000 1050 1100 1150 T (°C) Figure 12: Specific voltage versus sintering temperature 3.1.3. Ceramic Foil Presently, it is possible to use two processes for thin ceramic foil formation: extrusion & stretching process and doctor-blade tape casting process. We applied both processes to form varistor ceramic foil. The results of the second process will be shown in this paper. Nonaqueous tape casting system, containing acrylic binder, solvents, defloculants, plasticiser and some other additives, was used, enabling formation of homogeneous, stabile, low viscosity slurry, during homogenisation of varistor ceramic system. After homogenisation, the slurry travels on the carrier surface beneath the blade of the knife, that controls the thickness of the out-coming layer. When the solvent evaporates, the fine solid particles coalesce into a relatively dense flexible film that may be stripped from the carrier surface in a continuous sheet. Foils obtained in such a way have good mechanical firmness (enabling simple manipulation) and no pin hole defects. Besides, in the whole range of thicknesses no "skin" effect has been observed as illustrated in Fig. Figure 13: SEM photograph of the tape cast foil surface 13., Showing the appearance of the surface of the varistor tape cast foil. 900 1000 1050 T ( "O 1100 1150 Figure 14: Breal . -V »» ~ » , ■ , i •> ' » , , , " - - 4 > . 3.2 Chip Design and Structure Based on considerations in #2.3. the overall varistor breakdown voltages could be calculated as n x 3.6 V, n being the mean number of grain boundaries along the shortest linear path between electrodes. Following this principle a low voltage MLV can be designed combining the ratio of the ceramic foil thickness and ZnO grain size. However, this procedure is limited by the opposing requirements for certain electrical characteristics, processing and surface mount technology. Fig. 14. shows the breakdown voltages (at 1 mA) dependencies on sintering temperature with green sheet thickness as a parameter, while Fig. 15. shows the photograph of a) 4 V and b) 56 V sectioned MLV at the same magnification. t-M/' SÄÄÄilifji^Ä Figure 15: Photograph of cross-sectioned 4 V and 56 y MLV are encircled with varistor ceramics, so that there are no parasitic structures between adjacent electrodes, meaning that there are no paths causing surface leakage currents or enabling flash-over breakdown. Moreover, this way of electrode design enables their relatively large active surface with respect to chip volume. This is especially evident when compared with the bulk varistor. This electrode disposition enables very uniform current and energy volume distribution, avoiding "hot" spots in the structure, which is of great importance when stability and reliability are concerned. Beside inner electrode surface, their periphery is important as well. Being very long it facilitates peripheral electrode current injection, similarly as with high current power transistors and acts as an "amortiser" of extremely high current surges. Being good heat conductors inner electrodes have dual positive role, in the case of ambient heating, they minimise large temperature differences between chip sides, helping uniform microstructure formation and prevent defect diffusion and electrical characteristic degradation. In this case they act as ideal internal heaters. On the other hand, during internal heating due to DC, AC or pulse loading, they conduct heat outwards and act as coolers. This provides fast varistor heat dissipation through the volume, shifting failure mechanism toward highertemperatures. This is one of the reasons that MLV is the only varistor capable of operating at +125°C, whereas the maximum operating temperature of other Varistors is +85°C. 3.3. Electrical Properties 3.3.1. Current-Voltage Characteristics MLVs with breakdown voltage in the range from 4 V to 100 V were realised in the above described way. It should be emphasised, that 4 V breakdown is practically, the lowest theoretically possible breakdown in ZnO varistor (see #2.3,). Achieved result illustrates that, it is possible to realise controllable microstructure, such, that in the cross section between the adjacent large surface electrodes there is only one grain boundary on the average, i.e. the whole structure acts as one large equivalent monobarrier. Fig. 16 a) and b) shows symmetrical AC 1-V characteristics of 4 V and 56 V varistor respectively. The sharp breakdown knee is typical for these high devices with a clearly defined threshold voltage. This is even more evident in Fig. 17, presenting measured 1-V relationships. Wide current range measurements were provided using DC technique up to 10 mA and the pulse (8/20 |is) technique above this value. In both cases characteristics show distinct difference between the prebreakdown and breakdown region, which extends over six (for 4 V MLV) to seven (for 56 V MLV) orders of magnitude of current. Typical values of the nonlinear coefficient a measured iBn SHI Figure 16: AC current-voltage characteristics of the a) 4 V and b) 56 V MLV by the ALPHA meter in the current range from 1-10 mA usually exceeds 25 and in some cases reaches values over 50. It is especially important that a has so high value within the whole breakdown region. Fig.18. illustrates the example of 33 V MLV (5.7 x 5.0 mm), where a has the value >15 in the current range up to 1000 A, above which its value decreases and correlates with upturn region on the 1-V characteristics. Protection level coefficient, defined as the ratio of clamping voltage for any specified current and the breakdown voltage at 1 mA, has the value < 2.5 up to the current value of 1000 A, increasing for the higher currents. It means that MLV provides very effective protection in the wide current range. In the prebreakdown region MLV shows very low leakage current (typically < 5 j,iA), meaning at the same time, a low DC watt loss upon steady state operating voltage, typically set between 75-85 % of the threshold voltage. Although the leakage current increases with temperature, as shown in Fig. 19., for the case of 4 V MLV measured at Vdc = 3 V, it holds relatively low value even for the temperatures as high as +125°C, enabling its normal operation in that temperature range as well (see #3.2.). The linear relationship between current and temperature in semilogarithmic scale confirms the th'er-moionic emission mechanism, i.e. the validity of physical model described in #2.3.. The measured threshold voltage temperature coefficient is much lower than 0.01 %/°C in the temperature range from +25°C to +85°C. 1E + 04 1E + 03 1E + 02 1E + 01 1 E + 00 1E-01 1E-02 1E-03 1E-04 1E-053 J 1E-06; 1E-07 1 E-08J 1 lE-ogi 1E-10 0,1 Vn = 4 V Vn - 56 V ill! i I I iiiüi i I I i i i liiiii 1.0 10.0 100.0 1000.0 ( v 1 Figure 17: Current-voltage characteristics of 4 V (3.2x2.5 mm) and56 V (5.7X 5.0 mm) MLV 75 T ( I Figure 19: Temperature dependence of DC stand-by current (Vüc = 3 V) of ttie 4 V MLV 3.3.2. Capacitance and Response Time Dielectric constant of ZnO is relatively small (=10), while the effective dielectric constant of the vari sto r ceramics is about 100 higher as the consequence of intergranular barriers and their nature (see #2.3.). Capacitance of MLV with different breakdown voltages measured at 1 kHz, ranged from 0.5-40 nF, depending on the chip dimensions, layer thickness and their number. MLV capacitance is relatively stable over a wide frequency range, up to 1 MHz, as shown in Fig. 20.. The same figure shows bell shaped frequency-loss factor characteristics with the minimum value typically at 10 kHz. , The capacitance temperature change, in the temperature range from +25° to +85°C, is < 15 %. Such a medium MLV capacitance value, which to a certain extent can be designed is especially desirable in specific applications to be discussed in the Part II: Advantages and Applications. MLV chip has very low inductance, typically < 1.5 nH. The voltage response overshoot effect, being controlled by inherent parasitic lead inductance, is typically not observed in the case of 8/20 |.is pulse, as illustrated in Fig. 21.. This figure shows 54 V pulse response charac- E. 1E07 1E-01 cc ■ lE+01 1E+02 tE+03 1E+04 1E+05 1E+06 1E+07 Ffequeiicy ( Hz ) . Figure 18: Nonlinear coefficient-a and protective ievei versus current Figure 20: Capacitance and loss factor variation with frequency of the 8 V MLV R5;0 raW/d 1 fiß isV iW: ß iiE/d 1 V -5f;i:an ;!S I V ■w Figure 21: Pulse absorption characteristics of 33 VMLV (8/20 lis, 20 A; Hor.; 10 ns/d/V, Ver.: 351 x 25 mV/div) teristics of a 33 V MLV after triggering with 20 A of 8/20 las pulse. Our present equipment has enabled us to estimate the response time of MLV to be definitely < 5 ns, being adequate for protection in electrostatic discharge environment. 3.3.3.Stability and Reliabiilty MLV stability and reliability are especially important regarding the fact that it is intended to be protective device. To estimate its stability and reliability a number of tests were performed. The result of high current amplitude and high energy surge withstand capability tests are shown in Fig. 22 and 23.. Standard surge pulse shapes of 8/20 |is and 10/1000 \is were used. The relative threshold voltage change is plotted as a function of the number of surges. It is evident in Fig. 22. that in the case of 8/20 |is pulse threshold voltage increases somewhat faster during the first 10 surges, the change being slower afterwards. The change is lower than 5 %, even after 500 surges. The value of this result can be fully evaluated, having in mind that threshold voltage change of 33 V standard 20 mm disc varistor is higher than 10 % already after 100 to 150 surges. Similar results were obtained in the case of 10/1000 s pulse as shown in Fig. 23. It illustrates excellent stability of MLV 2" > 0 \ ž -2 -4 -6 -8 -10 I pulse ~ fjOO A Vn =33 V Chip size = 5.7 x 5.0 mm T = 25 °C Pulse 8/20 jis 1 10 too Number o£ surges Figure 22: Repetitive puise capability (30 s between pulses) 10 8 6 4 2-0 •2 -4 -6 -8 -10 puLse = 12Ü A : puLse = 12.5 J Vn = 33 V Chip SKC = 5.7 X 5.0 mm T = 25 PuLse 10/1000 iim 10 100 Number of surges 1000 Figure 23: High energy repetitive pulse capability (30 s between pulses) even in the case of 12.5 J pulses. During this test 33 V MLV was cumulatively absorbing the energy of more than 6 kJ in the period of 4 h, without substantially changing its characteristics. Similar threshold voltage change in the cases of different MLV pulse loading, suggests activation of the same failure mechanism, with no regard to the pulse duration or its shape. As, Varistors are, generally speaking, very sensitive to DC loading in the prebreakdown region, a continuous power dissipation life test was performed on 4 V MLV. The DC applied voltage was higher than the threshold voltage, i.e. the 4 V MLV was subjected to a 10 mA and 30 mA current. A stability that can not be obtained with any low voltage disc varistor is apparent in Fig. 24. Even after 80 min of loading with current of 30 mA, the threshold voltage change was not higherthan 15%. This result, as well as all the others, again confirms the consideration in #3.2. and proves the possibility of realising of a very homogeneous and ordered mictrostruc-ture by means of thin ceramic layer technology. 1 ■ \ ■ ............................................t......... V (-) \ / ■ Idc = 10 mA idc = 30 mA ■■■■■■■ (-) 0 10 20 30 40 50 60 70 80 90 1CX) t iminl Figure 24: Continuous power dissipation life test of 4 I/ MLV. The marks (+) and (-) indicate the Vn change in the same and the opposite polarity with DC bias. 4. Conclusion A low voltage MLV was developed using tape casting and green sheet lamination technology. Obtained electrical characteristics showed that the utilisation of BiaOa is possible in MLV ceramic system. Namely, MLV has high nonlinearity coefficient in the whole breakdown range, i.e. low clamping level, providing high protection efficiency. It was also shown that with respect to its planar surface MLV can withstand pulse density loading higher than 7000 A/cm^, being far higher than in any protective device known today. Besides, leakage current in prebreakdown region has relatively small value even in the temperature range around +125°C. Very low inductance of chip MLV enables response time shorter than 5 ns, eliminating to a great extent voltage response overshoot effect. Life test results, and especially repetitive pulse capability tests show MLV excellent capability to withstand great number of short high voltage surges as well as long high energy surges. Practically all static and dynamic characteristics as well as MLV stability lead to the conclusion that and MLV is favourable low voltage protective device. Acknowledgement The author would like to thank Dr. M. Kosec, Dr. M. Trontelj and Prof. Dr. D. Kolar and D. Ročak from the Institute Jožef Stefan in Ljubljana for helpful discussions and advice and the colleague and spouse A. Živič for encouragements and many valuable suggestions throughout this work as well as to all colleagues from KEKO for their support. References 1. S. M. Sze, "Physios of Semiconductor Devices", Wiley, N. Y. 1981,pp.63-133 2. A.S. Grove, "Physics and Technology of Semiconductor Devices", Wiley, N. Y. 1967, pp.1-208 3. F. A. Kröger, "Chemistry of Imperfect Crystals ", Wiley, N. Y. 1974, Vol. 2, p. 752 4. D. R. Clarke, "The Microstructural Location of the Intergranular Metal RROxide Phase in a Zinc Oxide Varistor", J. Appl. Phys. 49 (4), pp. 2407- 11, 1978 5. A. T. Sauthanam, T. K. Gupta, W. G. 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Samardžija, "The Microstructure of a Multilayer Varistor", Proc. of Conf. MIEL-SD'93, Bled, Sept. 1993, pp. 143-148 19. Z. Živič, M. Kosec, "Properties of a 4 V Multilayer Varistor", Proc. of Conf. MIEL-SD'92, Portorož, Sept. 1992, pp.419-424 20. Z. Živič, "Universal Composition for Varistor Production", Pat. No. 9200421, Slovene Patent Bureau, LJubljana, 1992 21. Z. Živič, "Low Leakage Current Varistor Composition", Pat. No. 9300426, Slovene Patent Bureau, Ljubljana, 1993 Zoran Živič, M.S.E.E. KEKO, d.d. Ceramic Capacitor Factory Grajsl