Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 4(2017), December 2017 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 47, številka 4(2017), December 2017 ISSN 0352-9045 192 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 4-2017 Journal of Microelectronics, Electronic Components and Materials VOLUME 47, NO. 4(164), LJUBLJANA, DECEMBER 2017 | LETNIK 47, NO. 4(164), LJUBLJANA, DECEMBER 2017 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2017. All rights reserved. | Revija izhaja trimesečno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale – Društvo MIDEM. Copyright © 2017. Vse pravice pridržane. Editor in Chief | Glavni in odgovorni urednik Marko Topič, University of Ljubljana (UL), Faculty of Electrical Engineering, Slovenia Editor of Electronic Edition | Urednik elektronske izdaje Kristijan Brecl, UL, Faculty of Electrical Engineering, Slovenia Associate Editors | Odgovorni področni uredniki Vanja Ambrožič, UL, Faculty of Electrical Engineering, Slovenia Arpad Bürmen, UL, Faculty of Electrical Engineering, Slovenia Danjela Kuščer Hrovatin, Jožef Stefan Institute, Slovenia Matija Pirc, UL, Faculty of Electrical Engineering, Slovenia Matjaž Vidmar, UL, Faculty of Electrical Engineering, Slovenia Editorial Board | Uredniški odbor Mohamed Akil, ESIEE PARIS, France Giuseppe Buja, University of Padova, Italy Gian-Franco Dalla Betta, University of Trento, Italy Martyn Fice, University College London, United Kingdom Ciprian Iliescu, Institute of Bioengineering and Nanotechnology, A*STAR, Singapore Malgorzata Jakubowska, Warsaw University of Technology, Poland Marc Lethiecq, University of Tours, France Teresa Orlowska-Kowalska, Wroclaw University of Technology, Poland Luca Palmieri, University of Padova, Italy International Advisory Board | Časopisni svet Janez Trontelj, UL, Faculty of Electrical Engineering, Slovenia - Chairman Cor Claeys, IMEC, Leuven, Belgium Denis Đonlagić, University of Maribor, Faculty of Elec. Eng. and Computer Science, Slovenia Zvonko Fazarinc, CIS, Stanford University, Stanford, USA Leszek J. Golonka, Technical University Wroclaw, Wroclaw, Poland Jean-Marie Haussonne, EIC-LUSAC, Octeville, France Barbara Malič, Jožef Stefan Institute, Slovenia Miran Mozetič, Jožef Stefan Institute, Slovenia Stane Pejovnik, UL, Faculty of Chemistry and Chemical Technology, Slovenia Giorgio Pignatel, University of Perugia, Italy Giovanni Soncini, University of Trento, Trento, Italy Iztok Šorli, MIKROIKS d.o.o., Ljubljana, Slovenia Hong Wang, Xi´an Jiaotong University, China Headquarters | Naslov uredništva Uredništvo Informacije MIDEM MIDEM pri MIKROIKS Stegne 11, 1521 Ljubljana, Slovenia T. +386 (0)1 513 37 68 F. + 386 (0)1 513 37 71 E. info@midem-drustvo.si www.midem-drustvo.si Annual subscription rate is 160 EUR, separate issue is 40 EUR. MIDEM members and Society sponsors receive current issues for free. Scientific Council for Technical Sciences of Slovenian Research Agency has recognized Informacije MIDEM as scientific Journal for microelectronics, electronic components and materials. Publishing of the Journal is cofi- nanced by Slovenian Research Agency and by Society sponsors. Scientific and professional papers published in the journal are indexed and abstracted in COBISS and INSPEC databases. The Journal is indexed by ISI® for Sci Search®, Research Alert® and Material Science Citation Index™. | Letna naročnina je 160 EUR, cena posamezne številke pa 40 EUR. Člani in sponzorji MIDEM prejemajo posamezne številke brezplačno. Znanstveni svet za tehnične vede je podal pozitivno mnenje o reviji kot znanstveno-strokovni reviji za mikroelektroniko, elektronske sestavne dele in materiale. Izdajo revije sofinancirajo ARRS in sponzorji društva. Znanstveno-strokovne prispevke objavljene v Informacijah MIDEM zajemamo v podatkovne baze COBISS in INSPEC. Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madić Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana 193 Content | Vsebina 195 211 223 233 241 247 255 261 273 Journal of Microelectronics, Electronic Components and Materials vol. 47, No. 4(2017) Pregledni znanstveni članek V. Sverdlov, J. Weinbub, S. Selberherr: Sestavljivi 2D Vernier TDC na osnovi obročnih oscilatorjev Izvirni znanstveni članki M. Faseehuddin, J. Sampe, S. Shireen, S. H. Md Ali: Nov univerzalen filter z mešanim načinom delo- vanja z enim aktivnim elementom in minimalnim številom pasivnih komponent M. Jurgo, R. Navickas: Sestavljivi 2D Vernier TDC na osnovi obročnih oscilatorjev R. Hemalatha, R. Mahalakshmi: Metahevrističen pristop določitve valovne dolžine optičnega sistema Long-Haul M. Hasan-Sagha, M. Jalali: Novo vzorčevalno vezje nizke moči na osnovi hitrih dinamičnih stikal X. Wang, Z. Wang, H. Li, R. Tian, J. Liu, F. Yu: Izboljšan LC-VCO z nizkim faznim šumom in širokim področjem nastavljanja frekvence za uporabo v PLL s črpalko nabojev B. Tunaboylu: Karakterizacija konektorja prostorskega pretvornika za testni sitem silicijevih rezin M. Hodžić, A. Mujčić, N. Suljanović, M. Zajc: Modeliranje komponent prenapetostne zaščite: Simulacija serijske vezave prenapetostnih odvod- nikov MOV in GDT v jeziku Verilog Napoved in vabilo k udeležbi: 54. Mednarodna konferenca o mikroelektroniki, napravah in materialih z delavnico o senzorjih in senzorskih tehnologijah Naslovnica: Napetostno krmiljen oscilator (Wang et al.) Review scientific paper V. Sverdlov, J. Weinbub, S. Selberherr: Spintronics as a Non-Volatile Complement to Modern Microelectronics Original scientific papers M. Faseehuddin, J. Sampe, S. Shireen, S. H. Md Ali: A Novel Mix-Mode Universal Filter Employing a Single Active Element and Minimum Number of Passive Components M. Jurgo, R. Navickas: Synthesizable 2D Vernier TDC Based on Gated Ring Oscillators R. Hemalatha, R. Mahalakshmi: A Meta-Heuristic Approach for Wavelength Assignment in Long-Haul Optical System M. Hasan-Sagha, M. Jalali: A New Low-Power CMOS Sample-and- Hold Circuit Based on High-Speed Dynamic Body Biased Switches X. Wang, Z. Wang, H. Li, R. Tian, J. Liu, F. Yu: An Improved Low Phase Noise LC-VCO with Wide Frequency Tuning Range Used in CPPLL B. Tunaboylu: Space Transformer Connector Characterization for a Wafer Test System M. Hodžić, A. Mujčić, N. Suljanović, M. Zajc: Modelling Overvoltage Protection Components: Verilog Simulations of Combined MOV and GDT Arresters Announcement and Call for Papers: 54th International Conference on Microelectronics, Devices and Materials with the Workshop on Sensors and Sensor Technologies Front page: Voltage controlled oscillator (Wang et al.) 194 Editorial | Uvodnik Dear reader, This issue brings a review scientific paper in an exciting field of microelectronics that already proves but much more promises to contribute to further progress. It covers fascinating progress of spintronics that was presented as a pla- nary talk at the MIDEM conference that we organize in late September every year. The 53rd MIDEM Conference under the Chairmanship of Asst. Prof. Slavko Bernik and Prof. Barbara Malič was a big success with the highlight on Materials for Energy Conversion and their Applications: Electrocalorics and Thermoelectrics as the Workshop. Year 2017 almost ran out and this editorial brings up some statistics about manuscripts submitted. In 2017 we have received more than 180 manuscripts, out of which only 23 have been accepted for publication and more than 140 manuscript were rejected. Despite clearly defined title of our journal and on-line instructions for authors we continue to receive each year a dozen of manuscripts that are out of our journal’s scope. In 2017 we published 1 review sci- entific paper and 25 original scientific papers. The success rate below 15% in 2017 reflects determination for quality that will path long-term quality growth. Increase in citation metrics (JCR IF-2016=0.478, SNIP-2016=0.482 and Cit- eScore-2016=0,60) is certainly a proof for that. I sincerely thank all reviewers and Editorial Board Members for their valuable contribution to the journal quality growth. Three associate editors, Prof. Vanja Ambrožič, Asst. Prof. Danjela Kuščer Hrovatin and Prof. Matjaž Vidmar received the Society MIDEM Editor Award for their valuable editorial contri- bution over the last 5 years. Let the festive days bring joy and peace in each home, office or research laboratory. It is the time to look ahead and make plans for the coming year. This brings me to editorial wishes for 2018. As a part of your success we look forward to receiving your future manuscript(s) on our submission page (http://ojs.midem-drustvo.si/). Merry Christmas and a Happy, Healthy and Prosperous New Year! Prof. Marko Topič Editor-in-Chief P.S We look forward to receiving your next manuscript(s) in our on-line submission platform: http://ojs.midem-drustvo.si/index.php/InfMIDEM 195 Review scientific paper  MIDEM Society Spintronics as a Non-Volatile Complement to Modern Microelectronics Viktor Sverdlov1, Josef Weinbub2, and Siegfried Selberherr1 1Institute for Microelectronics, TU Wien, Wien, Austria 2Christian Doppler Laboratory for High Performance TCAD, Institute for Microelectronics, TU Wien, Wien, Austria Abstract: Continuous miniaturization of semiconductor devices has been the main driver behind the outstanding increase of speed and performance of integrated circuits. In addition to a harmful active power penalty, small device dimensions result in rapidly rising leakages and fast growing stand-by power. The critical high power consumption becomes incompatible with the global demands to sustain and accelerate the vital industrial growth, and an introduction of new solutions for energy efficient computations becomes paramount. A highly attractive option to reduce power consumption is to introduce non-volatility in integrated circuits. Preserving the data with- out power eliminates the need for refreshment cycles and related leakages as well as the necessity to initialize the data in temporarily unused parts of the circuit. Spin transistors are promising devices, with the charge-based functionality complemented by the electron spin. The non-volatility is introduced by making the source and drain ferromagnetic. Recent advances in resolving several fundamental problems including spin injection from a metal ferromagnet to a semiconductor, spin propagation and relaxation, as well as spin ma- nipulation by the electric field, resulted in successful demonstrations of such devices. However, the small relative current ratio between parallel/anti-parallel source and drain alignment at room temperature remains a substantial challenge preventing these devices from entering the market in the near future. In contrast, a magnetic tunnel junction is an excellent candidate for realizing power-reducing approaches, as it possesses a simple structure, long retention time, high endurance, fast operation speed, and yields high integration density. Magnetic tunnel junctions with large magnetoresistance ratio are perfectly suited as key elements of non-volatile magnetoresistive memory compatible with the complementary metal-oxide-semiconductor technology and capable to replace dynamic and potentially static random access memo- ries. We review the present status of the technology, remaining challenges, as well as approaches to resolve the remaining problems. Regarding active power reduction, delegating data processing capabilities into the non-volatile segment and combining non-volatile elements with CMOS allows for efficient power gating. It also paves the way for a new low-power and high-performance in-memory processing paradigm-based on an intrinsic logic-in-memory architecture, where the same non-volatile elements are used to store and to process the information. Spintronics kot trajno dopolnilo moderne mikroelektronike Keywords: Spintronics; non-volatility; spin field-effect transistors; spin relaxation; magnetic tunnel junctions; magnetic random access memory (MRAM), spin-transfer torque MRAM, spin-orbit torque MRAM; voltage-controlled MRAM; logic-in-memory Sestavljivi 2D Vernier TDC na osnovi obročnih oscilatorjev Izvleček: Nenehno zmanjševanje polprevodniških naprav je bila glavna gonilna sila izjemnega povečanja hitrosti in zmogljivosti integriranih vezij. Poleg škodljivega povečevanja aktivne moči majhne dimenzije naprav vplivajo tudi na višje uhajalne tokove in večjo porabo v stanju mirovanja. Visoka poraba energije je postala nekompatibilna z zahtevami vzdržnosti rastoče industrije, zato so potrebne nove rešitve učinkovite rabe energije. Zelo privlačna možnost zmanjšanja porabe energije je uvedba trajnosti v integriranih vezjih. Ohranjanje podatkov brez porabe energije odpravlja potrebo po osveževalnih ciklih in uhajanjih ter nujnosti inicializiranja podatkov v začasno neuporabljenih delih vezja. Spin tranzistorji so obetavni elementi, ki temeljijo na osnovi naboja z dopolnitvijo vrtilne količine elektrona (spin). Trajnost se ustvari tako, da sta vir in ponor feromagnetna. Nedavni napredek pri reševanju številnih temeljnih problemov, vključno s injektiranjem vrtilne količine iz kovinskega feromagnetika v polprevodnik, vzpostavitev in relaksacija vrtilne količine ter upravljanje vrtilne količine z električnim poljem, Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 4(2017), 195 – 210 196 1 Introduction The breathtaking increase in performance and speed of integrated circuits has been enabled by continu- ous miniaturization of complementary metal-oxide semiconductor (CMOS) devices. On this exciting path numerous outstanding technological challenges have been resolved. Among the most crucial technological changes recently adopted by the semiconductor in- dustry to boost CMOS performance while maintaining gate control over the semiconductor channel are the introduction of strain [1], high-k gate dielectrics and metal gates [2], and a three-dimensional (3D) tri-gate transistor architecture [3-5]. The successes and innova- tive solutions developed for the microelectronics tech- nology have been always supported by sophisticated simulation tools, which allow reducing the research and development costs by 35-40% [6]. Although transistor sizes are scaled down, the on-cur- rents cannot be further decreased due to the need to charge/discharge the load capacitances and to main- tain the clock, which is saturated at approximately 4.0 GHz. Increasing the clock frequency results in an active power penalty, while continuous transistor scaling re- sults in growing leakages and stand-by power. Novel revolutionary approaches are desperately needed in the long run to sustain the vital societal and industrial progress in computing performance whilst simultane- ously reducing power consumption. The ultimate solution to one of the primary issues – the power reduction – is to introduce non-volatility into the circuits. Non-volatility is the ability to preserve data, when the supply power is turned off. It enables stand- by power-free integrated circuits as no information is je bil ključen za uspešno demonstracijo takšnih naprav. Kljub temu ostaja relativno majhno razmerje tokov med vzporednim/nasprotnim položajem izvora in ponora pri sobni temperaturi ključen izziv, ki preprečuje vstop teh naprav na trg v bližnji prihodnosti. V nasprotju s tem je magnetni tunelski spoj odličen kandidat za uresničevanje pristopov zmanjšanja moči, saj ima preprosto struk- turo, dolg čas zadrževanja, visoko vzdržljivost, hitro obratovalno hitrost in visoko gostoto integracije. Magnetni tunelski spoji z visokim razmerjem magnetoresonance so idealni za uporabo v trajnih megnetorezistivnih spominih, ki so združljivi s komplementarno kovina- oksid-polprevodnik tehnologijo in sposobni zamenjati dinamičen in statičen spomin z naključnim dostopom. V članku je podan pregled tehnologije, izzivi in postopki, kako rešiti obstoječe probleme. Zmanjševanje porabe energije se lahko doseže s prenosom obdelave podatkov v trajne segmente in kombinacijo trajnih elementov s CMOS. Prav tako se utira pot novi paradigmi procesiranja v pomnilniku z nizko porabo energije in visoko zmogljivostjo, ki temelji na arhitekturi logike v pomnilniku, kjer se za shranjevanje in obdelavo podatkov uporabljajo isti trajni elementi. Ključne besede: Spintronika; trajnost; tranzistorji z vrtilnim poljem; relaksacija vrtilne količine; magnetni tunelski spoj; magnetni spomin z naključnim dostopom (MRAM); navor prenosa vrtilnosti MRAM; navor orbite vrtilnosti MRAM; napetostno krmiljen MRAM; spominska logika * Corresponding Author’s e-mail: sverdlov@iue.tuwien.ac.at lost and there is no need to recover the data, when the power is turned on. Non-volatility is crucial for elimi- nating the leakage power dissipation and data refresh- ment cycles. Apart from stand-alone applications, e.g., critical program and data storage devices in extreme environments employed in the air and space industry, it is particularly promising to use non-volatility in the main computer memory as a replacement of conven- tional volatile CMOS-based dynamic random-access memory (DRAM) [7], which will drastically reduce en- ergy consumption. In modern multicore processors, much of the energy consumption appears in the hier- archical multi-level cache memory structure. To reduce this energy consumption, a viable approach is to re- place the caches with a non-volatile memory technol- ogy which also offers a reduced memory cell size com- pared to static random-access memory (SRAM) [7]. This will help bridging the speed gap between the last-level cashes and main memory, since CMOS SRAM is much faster compared to CMOS DRAM. To be competitive with the traditional volatile memory technologies and also with non-volatile flash memo- ry, emerging non-volatile memories must offer a fast switching time, a high integration density supported with good scalability, a long retention time, a high en- durance, and a low power consumption. At the same time, they must possess a simple structure to reduce fabrication costs and the new non-volatile circuit ele- ments must be compatible with CMOS technology to benefit from advantages provided by the well-devel- oped CMOS fabrication technology. A spin field-effect transistor (SpinFET) is a promising fu- ture semiconductor device with a performance poten- V. Sverdlov et al; Informacije Midem, Vol. 47, No. 4(2017), 195 – 210 197 tially superior to that achieved in the present transis- tor technology. The non-volatility in SpinFETs is added by replacing the non-magnetic source and drain in a FET by its ferromagnetic counterparts. The two ferro- magnetic contacts (source and drain) are linked by a non-magnetic semiconductor channel region. Metallic ferromagnetic contacts serve not only as an injector/ detector of the spin-polarized electron charge current in the channel, but, because of their magnetization, the source and drain electrodes provide an additional current modulation due to their capabilities to inject/ detect spins [8]. Indeed, the electron current gets en- hanced in the case of parallel alignment between the source/drain electrodes as electrons are injected with spins parallel to the drain magnetization and can easily escape from the channel to the drain, while the current is suppressed for anti-parallel magnetization align- ment [8]. As the magnetization of the source/drain can be manipulated by means of an external magnetic field and/or current (by means of the spin-transfer torque), the two on-current states for parallel/anti-parallel mag- netization alignment potentially enable reprogramma- ble logic [9]. Importantly, the relative magnetization orientation between source and drain is preserved without external power, which makes reprogramma- ble logic partly non-volatile. Below we discuss recent advances and remaining challenges to realize SpinFET- based logic in detail. We only stress the most impor- tant, in our opinion, shortcoming to overcome, namely, a small relative difference between the on-currents in parallel and anti-parallel source/drain alignment. Magnetoresistive random access memory (MRAM) and in particular spin transfer torque (STT) MRAM possesses many, if not all, of these advantages and is considered as a perfect candidate for future universal memory ap- plications. MRAM is CMOS-integrable, which increases its potential to replace the typical processor-embed- ded SRAM and DRAM. With STT MRAM currently emerging as a commercial product for stand-alone applications, it will be critically important to introduce STT MRAM in the main com- puter memory, i.e., to replace conventional DRAM and SRAM. This will create a new innovative multi-billion dollar industry and will sustain the breathtaking path of electronics by delivering cheaper, faster, and envi- ronmentally friendlier compact and mobile devices. Bringing STT MRAM into the vast computer memory market as embedded and stand-alone applications for traditional high-performance and low-power mobile platforms will result in an exponential growth of the non-volatile memory market share in the near future. Regardless of the first commercial STT MRAM-based products for stand-alone applications being available, one critical aspect of the currently used STT MRAM technology is a relatively high switching current, which again is in sharp contrast to the overall demand for re- duced energy consumption. This obviously prevents the MRAM from successfully entering the vast com- puter memory market. The problem of high switching current and large active writing energy jeopardizes the advantages provided by non-volatility, such as zero stand-by power, no data refreshment, and no data re- covery. Several plausible approaches to address these issues are conceivable including the replacement of the in-plane magnetization orientation in magnetic tunnel junctions (MTJs) with perpendicular magneti- zation, the use of composite free recording layers, de- coupling the write and read current paths, controlling magnetization by voltage, and employing new materi- als with improved properties and characteristics. 2 Spin transistor In a SpinFET [8] schematically shown in Fig.1 the elec- trons with spin aligned to the drain magnetization di- rection can easily leave the channel to the drain thus contributing to the current. The total current through the device depends on the relative angle between the magnetization direction of the drain and the electron spin polarization at the end of the semiconductor channel. The electron spin orientation at the end of the channel is determined by the source magnetization and can be additionally manipulated by the modula- tion which is achieved by tuning the strength of the effective spin-orbit interaction in the channel induced by the gate voltage. As a non-equilibrium quantity, the injected spin relaxes to its equilibrium zero value while propagating through the channel. Spin relaxation is an important detrimental ingredient as it reduces the cur- rent modulation and affects the SpinFET functionality. Figure 1: Datta-Das SpinFET [8]. Spin-polarized elec- trons are injected from a ferromagnetic source and ab- sorbed by in a ferromagnetic drain. The electron spins in the channel are manipulated by means of the gate voltage-dependent spin-orbit interaction. 2.1 Spin-Orbit Interaction The spin relaxation is governed by the spin-orbit inter- action (SOI) and scattering, both spin-dependent and V. Sverdlov et al; Informacije Midem, Vol. 47, No. 4(2017), 195 – 210 198 spin-independent, and manifests itself differently in semiconductors with and without the inversion sym- metry [10,11]. In crystals obeying the inversion symmetry (silicon, germanium) the spin relaxation is governed be the Elli- ott-Yafet mechanism [10,11]. The wave function with a fixed spin projection (defining the quantization axis) is not an eigenstate of the Hamiltonian due to the elec- tron momentum-dependent SOI. In other words, the SOI forces the eigenstate wave function to possess a small but finite contribution with an opposite spin pro- jection in the fixed basis. Therefore, the small but finite amplitude to flip the electron spin appears at every spin-independent scattering event – the Elliott process [12]. This is complemented by the Yafet spin-flip events due to SOI-dependent electron-phonon scattering. In silicon the electron spin relaxation is determined by the inter-valley transitions [12] and can be efficiently controlled by stress [13]. In silicon channels, uniaxial stress generating shear strain is particularly efficient to suppress the spin relaxation [14] as it lifts the degen- eracy between the two unprimed subband ladders [15]. In addition, choosing the spin injection direction also boosts the spin lifetime by a factor of two [16], as shown in Fig.2. Figure 2: Spin lifetime in (001) thin Si film as a function of shear strain. The spin lifetime is a factor of two longer for spins injected in-plane as compared to the time for spins injected perpendicular to the film. The factor of two is preserved for both inter- and intra-valley scat- tering and is independent of the scattering mechanism (electron-phonon and surface roughness scattering). In III-V materials without inversion symmetry the de- generacy between the up and down spin states with the same electron momentum is lifted, and the spin relaxation is governed by the Dyakonov-Perel mecha- nism [10,11]. However, the SOI does not always play a detrimental role. In semiconductor channels the SOI may also be used efficiently to manipulate the electron spins in the channel [8]. The inversion symmetry in the channel can additionally be violated by applying the gate voltage. In this case the strength of the effective SOI depends on the effective electric field perpendicu- lar to the channel [17]. The strength of the gate voltage- dependent SOI can be used to modulate the current between the ferromagnetic source and drain by means of an additional spin modulation in the channel result- ing in a different spin orientation relative to the drain as compared to the case without SOI [8]. Importantly, as the strength of the SOI in the channel depends on the effective electric field, the suggested method provides a purely electrical mean of manipulating the electron spins and thus the current in the channel. The voltage-induced SOI in III-V materials can be used for an efficient spin injection in the channel from the point contacts [18]. Additional gates are used to cre- ate the point contacts to the two-dimensional (2D) electron gas by confining the 2D gas in the III-V chan- nel under the gates. Application of different voltages to these gates generates the spin-orbit Rashba field perpendicular to the point contact. By properly tuning the chemical potential one can achieve that, due to this SOI, all electrons moving to the right are spin-polarized (while electrons moving to the left are polarized in the opposite direction). Thereby an efficient and purely electrical spin injection/detection is achieved. Using this injection scheme, the ever first reliable demonstra- tion [18] of a working SpinFET [8] suggested in 1990 was achieved. Not long ago, new 2D materials (graphene, transition metal dichalcogenides), become attractive for future microelectronics applications. Recently, a new concept for realizing a spin switch with a graphene channel was demonstrated [19]. Spin-polarized electrons are in- jected into the graphene, a good spin conductor due to low SOI, and reach the drain electrode, if the elec- trochemical potential in MoS2 is tuned into the energy gap. In this case the electrons do not enter MoS2. The situation is completely changed, if the electrochemical potential is tuned by the gate into the MoS2 conduction band. In this case a parallel path for electrons through a material with high SOI is open, which results in strong spin relaxation, so that the current reaching the drain is not spin-polarized. Regardless of the successful demonstration of the SpinFET, the conductance modulations were only re- solved at temperatures far below 300K. The spin switch [19] discussed above was demonstrated to work at 0 0.6 1.2 1.8 2.4 εxy (%) 10-4 10-3 10 -2 10-1 100 101 102 10 3 104 10 5 106 Sp in li fe tim e [n s] in-plane out-of-plane intra-valley inter-valley V. Sverdlov et al; Informacije Midem, Vol. 47, No. 4(2017), 195 – 210 199 temperatures below 200K and requires additional cool- ing, which modern microelectronics working at room temperature is striving to avoid. Recently, the first suc- cessful demonstration of a silicon spin metal-oxide- semiconductor field-effect transistor (SpinMOSFET) at room temperature [20] was presented. In silicon the strength of the Rashba SOI is much smaller compared to that in III-V semiconductors. Therefore, the SOI can- not be used for spin manipulation. Thus, the current modulation in the SpinMOSFET is achieved by altering the relative magnetization between the ferromagnetic source and drain. This way, a high difference between the on-currents in parallel and anti-parallel source/ drain configuration was demonstrated. However, the relative ratio of the currents, a characteristic similar to the tunnel magnetoresistance (TMR) ratio, is still sever- al orders of magnitude lower [20] than the TMR in MTJs. Fig.3 shows the TMR in a silicon SpinFET as a function of the SOI strength, for several channel lengths for an ideal case when the spin relaxation is neglected. In or- der to facilitate the spin injection and detection, delta function-like Schottky barriers between the source, drain, and the channel of the strength 2 2 F F EhU mπ = were h is the Plank constant, EF and mF are the Fermi energy and the electron mass in the ferromagnetic contacts, are assumed. Even in this ideal case the TMR is about 10%, much inferior to that in MTJs. A TMR less than 1% was experimentally observed at room tem- perature [20]. Figure 3: The ratio of the resistance difference in an- tiparallel and parallel configurations to the resistance in parallel configuration of the source and drain in Si- based SpinFETs as a function of the spin-orbit interac- tion strength, for several channel lengths. 2.2 Spin Injection and Spin-Dependent Tunneling The device described above can function only if the electron spins are efficiently injected/extracted in/ from the channel. As there are no semiconductor fer- romagnets at room temperature, to achieve the ef- ficient injection/detection from metal ferromagnets in the semiconductor channel and vice versa, a thin tunneling barrier must be placed between the elec- trodes and the channels [21] to mitigate the spin im- pedance mismatch. However, the signal attributed to the spin injection [22] appears to be much weaker as compared to the large effect [23] currently attributed to the spin-dependent resonant tunneling [24-26], and the development of efficient ways to electrically inject spins from a ferromagnetic metal in a semiconductor has become an area of active research. To summarize, although many fundamental challenges have been resolved and both a SpinFET and a SpinMOS- FET have been successfully demonstrated, an enhance- ment of the on-current ratio between the parallel and anti-parallel source/drain magnetization alignment at room temperature remains one of the main challenges. In addition, both SpinFET and SpinMOSFET still rely on the charge current to transfer the spin, which may set some limitations for the applicability of such devices in main-stream microelectronics in the future. Non-vola- tile devices based on MTJs possess the TMR suitable for practical applications and are reviewed below. 3 Magnetoresistive random access memory Applications driven by magnetic moments and in- duced magnetic fields have a large share in typical information technology products. Coupling between magnetic fields and currents in coils was employed in the first electronic devices. However, the coupling is relatively weak, resulting in low efficiency and high energy supply costs. An efficient coupling between the electrical and the magnetic degree of freedom is possi- ble on a quantum mechanical level and was discovered in 1986 as a phenomenon called the giant magneto- resistance (GMR) effect. This facilitated a reliable, purely electrical read operation of the information encoded in the magnetization orientation. Based on this principle hard drive storage devices with extremely high density appeared on the market. The enormous impact of this discovery on the development of information technol- ogy was recognized by awarding the inventors the No- bel Prize in 2007 [27,28]. 0 10 20 30 40 50 β [µeVnm] -0.1 -0.05 0 0.05 0.1 TM R L=2µm L=4µm L=8µm V. Sverdlov et al; Informacije Midem, Vol. 47, No. 4(2017), 195 – 210 200 The next generation of storage devices with higher density is based on the unique properties of the MTJ. It was discovered that, if the non-magnetic metal layer in a GMR memory element is substituted by a thin di- electric, the tunneling current through the structure strongly depends on the relative polarization of the fer- romagnetic contacts (Fig.4). The difference in the MTJ resistivity can reach several hundred percent at room temperature [29]. Thanks to this technology a new gen- eration of hard drives with even higher storage densi- ties has been developed. Figure 4: A magnetic tunnel junction possesses low (high) resistance for parallel (antiparallel) relative ori- entation between the ferromagnetic electrodes. In order to be used in memories, MTJs must be com- plemented with the ability to efficiently convert charge information into magnetic moment orientation. Writ- ing the state by the magnetic field is currently used in toggle switching commercial MRAM. This method, however, is not scalable as the magnetic field is gener- ated by the current, which leads to a current increase with scaling [30]. 3.1 Spin Transfer Torque Magnitoresistive Random Access Memory The STT effect [31,32] has been proven to be a perfect alternative to the magnetic field for magnetization switching. The STT is used for purely electrical data writing by passing the current through the MTJ. The memory technology based on MTJs and the STT effect has resulted in the development of STT MRAM. STT MRAM is characterized by lower power-consumption and better scalability than conventional MRAM, where the switching is performed by the magnetic field [33] generated by an electric current passing through the write lines next to the cell. Several cells are arranged in a matrix connected with bit and world lines. A cell in this cross-point architecture is written by simultane- ously selecting the cell with current pulses applied to the corresponding world and bit lines. The problem of half-selected cells [30] is solved by the application of a certain pulse sequence to the lines supplemented with a special design of the free layer arranged as a synthetic anti-ferromagnet [34]. This results in a deterministic, toggle-like fast switching of the free layer. The magnetic field employed for switching prevents MRAM from scaling down beyond 90nm [35] as the current needed for the field generation rapidly in- creases with scaling. STT [31,32] opened a new way of manipulating magnetization dynamics by using spin- polarized currents instead of magnetic fields. The spin- polarized current allows writing the information into the memory cell by purely electrical means. When elec- trons pass through a fixed ferromagnetic layer, their spins become aligned with the magnetization. When these spin-polarized electrons enter the free layer, they become aligned with the magnetization of the free layer within a transition layer of a few angstroms. The electron spins change results in a torque exerted on the magnetization of the free layer. This torque causes magnetization switching, if it is large enough to over- come the damping. By altering the current polarity the magnetization of the free layer can be switched from the anti-parallel to the parallel state and back with re- spect to the reference layer. The interest in STT MRAM has increased significantly after the observation of spin torque induced switch- ing in AlOx-based [36] and MgO-based [37] STT MRAM cells. Depending on the orientation of the layer mag- netizations the magnetic pillars can be divided into two categories: (1) perpendicular with out-of-plane magnetization direction and (2) in-plane with the mag- netization lying in the plane of the magnetic layer. The introduction of STT MRAM with in-plane magnetiza- tion orientation to the market has already begun with the first demonstration by Everspin Technologies [38] of a 64Mb chip. The size of the MTJ bits is 80–90nm with an aspect ratio of 2 and 3. An MgO barrier was used and MTJs with a TMR ratio above 110% were exploited. The chip is able to operate within a broad temperature range. Switching the magnetization can occur spontaneously due to thermal fluctuations. This is an undesired event, which leads to the loss of the stored information. An important parameter of MRAM is the thermal stability V. Sverdlov et al; Informacije Midem, Vol. 47, No. 4(2017), 195 – 210 201 factor which is defined as the ratio of the thermal sta- bility barrier to the operating temperature. For gigabit applications the thermal stability barrier should be at least 80kT to guarantee the required retention time of 10 years. Achieving large thermal stability and a low switching current for fast switching simultaneously represents one of the main challenges to engineer a good MRAM cell. Perpendicular MTJs (p-MTJs) with the thermal barrier equal to the switching barrier are pre- ferred for applications, because they allow to reduce the switching current. In addition, p-MTJs are better suited for high-density memory [39]. Both field-induced and STT switching can be comple- mented with heat assisted switching [30]. This tech- nology was routinely used in hard drives in order to facilitate writing. Presently methods using thermally assisted switching in MRAM have already been devel- oped. In addition to assisting switching, heat can fa- cilitate new unique functionalities, for instance, using an MRAM cell with a soft reference layer as a magnetic logic unit [40]. This extends the MRAM research and development area towards logic-in-memory architec- tures and non-volatile computing. Regardless of the undisputable success of the first MRAM products on the market, several important chal- lenges remain. The general requirements for any mem- ory type including MRAM are: - ability to write the data with low energy without damaging the device; - data retention within a given long time interval; - ability to read the recorded data without destroy- ing the data. Improving one or two aspects of its functionality usu- ally leads to a degradation of the remaining function- ality [30]. Therefore, a careful parameter optimization specific to a particular technology is the main subject which must be addressed in order to facilitate produc- tion of high density memory arrays suitable for replac- ing SRAM caches and DRAM-embedded main comput- er memory. One of the main problems of STT MRAM is a relatively high critical current required for STT-induced mag- netization switching. This fact has several implications. Firstly, due to the relatively high energy required for writing, the current generation of STT MRAM cannot be used in high-level processor caches due to the high activity factor in these elements and the high level of generated heat. The necessity to switch memory fre- quently negates the benefits of non-volatility provided by MRAM. Secondly, large switching currents are sup- plied via an access transistor. This potentially puts scal- ing limitations on the transistor dimensions of a one- transistor (1T)-1MTJ memory cell. However, a careful and innovative design yielded already a successful im- plementation of 8Mb 1T-1MTJ STT MRAM embedded in a 28nm CMOS logic platform [41]. Finally, a large switching current density can result in serious reliabil- ity issues like MTJ’s resistance drift and eventually its dielectric breakdown. The critical current density de- pends on the switching pulse duration, with a substan- tial current increase for faster, sub 10ns switching. A plausible way to reduce the switching current density is to work with p-MTJs. The problem of data retention is related to thermally agitated magnetization fluctuations. During these fluc- tuations the magnetization can switch spontaneously via a potential barrier separating the two states with opposite magnetization directions. As already noted, for about 10 years data retention the thermal stabil- ity barrier must be at least 80kT for gigabit MRAM ar- rays. However, increasing the barrier also results in an increase of the switching current density, which is proportional to the thermal barrier for p-MTJs. In order to reduce the switching current density and preserve the large thermal barrier at the same time one has to reduce the Gilbert damping and increase the spin cur- rent polarization. An interface-induced p-MTJ structure with a composite free layer CoFeB/Ta/CoFeB with two MgO interfaces [42] allows simultaneously boosting the thermal barriers and reducing damping. For in-plane MTJs, the faster switching can also be achieved, when the composite free layer is made of two half-ellipses separated by a narrow gap. The pecu- liarities of the magnetization dynamics of the two parts of the composite free layer [43,44], which occur in op- posite senses to each other, lead to the magnetization switching in-plane. This way the large demagnetiza- tion penalty of the magnetization getting out of plane is avoided, and the switching barrier becomes equal to the thermal barrier. Because the thermal barrier depends on the free layer volume, the required large thermal stability factors of ~80kT are easily achieved in this structure. A large TMR ratio is needed for reliably reading the information in MRAM. Indeed, the middle reference resistance to which the low and high resistance MTJ states are compared must be well separated from ei- ther of them. However, since a bit-to-bit resistance vari- ation within a memory array is increasingly difficult to control with device sizes scaling down, the dispersion increases and so must the TMR. Obtaining a large TMR is more difficult in interface-induced p-MTJs, because the layer width must be reduced in order to boost the magnetic anisotropy; however, a TMR ratio as large as 350% has been demonstrated [45]. V. Sverdlov et al; Informacije Midem, Vol. 47, No. 4(2017), 195 – 210 202 With growing data services such as Big Data analysis the need for additional memory capacity and speed as well as in-memory computing has increased dramati- cally. The last-level cache memory must be increased [46-48] to bridge the memory-bandwidth gap between central processing units (CPUs) and the main memory. The CPU performance can be significantly boosted by using fast non-volatile memories in cache for data stor- ing without the need to address the main memory. In particular, the use of STT MRAM as the last-level cache memory helps bridging the memory-bandwidth gap between multi-core CPUs and the main memory. Ultra-large volatile DRAM devices are available; how- ever, due to the high refresh rate and thus high power consumption their use as last-level caches has been limited. The introduction of non-volatility to reduce en- ergy consumption in last-level cache memory can in- crease the CPU performance significantly by using this cache for data storing and processing without the need to address the main memory. Advanced STT MRAM is characterized by high-speed access with less than 10ns. It is thus suitable for last- level cashes where it guarantees about ten times pow- er reduction [49-51], while other types of non-volatile memories are much slower and cannot provide such a high speed access. 4Gbit density STT MRAM arrays with p-MTJs and compact memory cell were recently report- ed [39]. On May 26th, 2017, Samsung [52] reaffirmed the beginning of production of embedded STT MRAM based on the 28nm silicon-on-insulator technology node [41] in 2018. On September 15th, 2017, Global- foundries announced the beginning of embedded STT MRAM production based on the 22nm fully-depleted silicon-on-insulator technology [53]. We are therefore witnessing the beginning of non-volatile STT MRAM entering the DRAM and potentially SRAM markets, tra- ditionally dominated by CMOS-based volatile devices. If successful, it will result in an exponential expansion of the STT MRAM market with a momentous impact on information storage and processing in the near future. 3.2 Advanced MRAM Although STT MRAM is competitive with DRAM for em- bedded memory applications and can also be used in level three caches in CPUs, increasing write currents for faster switching prevents it from being used in level one caches, where very fast switching is required. An ultimate swap to p-MTJs and Gilbert damping reduc- tion are two common paths to reduce the switching current; however, these efforts are counteracted by the necessity to maintain high thermal stability which requires high perpendicular magnetic anisotropy [30]. There are indications that by downscaling the p-MTJ di- ameter the switching current decreases faster than the thermal stability factor, which has been shown to be as high as 120 in p-MTJs with a diameter of 30nm [54]. Nevertheless, it is preferred to have an alternative way to switch the free layer. Interface-induced perpendicular magnetic anisotropy materials provide a sufficiently large thermal stability factor for free layers with diameters down to 12-14nm. Since the anisotropy is determined by the interface properties, it can be altered by applying an electric field. The electric field polarizes the charge densities of the interfacial atoms, thereby modifying overlap integrals and exchange interactions. This may soften the perpendicular magnetic anisotropy thus reducing the switching energy barrier and even changing it to in-plane. The magnetization can easily be pushed over the barrier by a small current and stabilized in the state with an opposite magnetization after the voltage is re- moved. 3.2.1 Voltage-controlled MRAM An MRAM controlled by voltage [55-58] is a viable op- tion for last-level cache applications. The voltage-con- trolled MRAM switching principle is based on voltage- mediated removal of the potential barrier separating the two stable magnetization orientation states. With- out the barrier the magnetization precesses around the effective magnetic field and can be put into the alter- native magnetization state, when the potential barrier is re-introduced at the end of the voltage pulse [59]. Because the voltage-induced switching is unipolar, the voltage controlled MRAM is free from the read disturb which is characteristic to STT MRAM. Although voltage controlled MRAM is a two-terminal device, the separa- tion between read and write is performed by alternat- ing the polarities during these two operations. Voltage controlled MRAM has a few unsolved issues so far preventing it from being broadly used in applica- tions. One of the problems originates in the preces- sion at switching and thus depends on the initial state determined by the fluctuating thermal and unwanted variability. This variability results in write errors and must be suppressed. The second problem is a larger resistance of the memo- ry cell compared to STT MRAM, which results in smaller currents. Small currents lead to a longer delay while reading the state by a sense amplifier. As it was shown recently [60], both problems can be solved by carefully tailoring and optimizing the entire circuit. V. Sverdlov et al; Informacije Midem, Vol. 47, No. 4(2017), 195 – 210 203 Extending the ideas of voltage-controlled magnetic anisotropy, the voltage pulse can be applied not only to lower the potential barrier between the two mag- netization states but also to boost it to make the switching harder [60]. The switching is mediated by a spin-orbit and/or spin Hall torque generated by the current flowing through a conductive line made of a heavy metal underneath the magnetic MTJ, ensuring the write operation without an external magnetic field [61]. If reading is performed by applying the voltage pulse with its polarity opposite to that used for writing, the potential barrier is increased, hardening the cell im- munity against read disturb errors. 3.2.2 Spin-orbit torque MRAM Among the newly discovered physical phenomena suitable for next-generation MRAM are the spin Hall ef- fect and the spin-orbit torque (SOT) switching [62-66]. Current passing in a material with a high spin Hall an- gle/SOI results in spin-orbit torques capable to switch the free layer of an MTJ. This way the read and write cur- rents are decoupled, which prevents the tunnel barrier from damage and improves device reliability. The spin Hall effect and/or SOT alone do not provide switching in devices with perpendicular magnetiza- tion. To provide switching, it is required to apply an external magnetic field. In addition, innovative materi- als are required to increase the torques and to boost the switching efficiency. New materials with a strong SOI, e.g., topological insulators, allow the current to flow only at their interface states [67]. Due to the spin- momentum locking characteristic to these states the passing current results in a large spin accumulation at the interface [68,69] and the SOT aids the magnetiza- tion to switch. A potential disadvantage of the write and read cur- rent paths’ separation is that these devices appear in a three-terminal cell configuration [70]. Therefore, they can be used only for applications in which the density is not the top priority, but for high-speed reliable op- eration competing with SRAM. There exists a different design of a three-terminal MRAM cell, where the switching is done by the current induced fast domain wall motion within a ferromag- netic material between the two ferromagnetic elec- trodes, while reading is done by means of an additional ferromagnetic contact grown on top of the ferromag- netic layer [70]. The domain wall is pushed by both STT and spin SOT, with the relative strength of each con- tribution tuned by proper engineering the magnetic layer structure. The domain walls can be moved very fast [71,72], which is attractive for high speed applica- tions. However, the critical current densities obtained experimentally are still high. A reduction of the critical currents by minimizing the domain wall pinning in do- main wall MRAM may compromise the data retention. Similar to SOT-based MRAM, the reduction of the cur- rent density, while maintaining the domain wall speed, remains a critical challenge for domain wall motion based MRAM. The need to lower the critical current in advanced MRAM accelerates the search for new materials with large SOI. A promising candidate for such a material is a topological insulator, for which a large spin Hall angle has been demonstrated [67]. A general form of the relevant torque terms in the presence of spin-orbit interaction can be determined by symmetry considera- tions [73,74]. As SOTs appear at the interface between a material with high SOI and a ferromagnet, a description of these torques by means of boundary conditions was recently suggested [75,76]. The corresponding bound- ary conditions allow to relate the non-equilibrium spin accumulation at both sides of the interface in presence of the in-plane current and couple them to the mag- netization dynamics. 4 Non-volatile logic MRAM is CMOS compatible and attractive to use with CMOS-based logic applications. Fast non-volatile mem- ory combined with non-volatile processing elements is a fertile ground for realizing the first microprocessors with reduced power consumption working on an en- tirely new principle. In addition, MRAM arrays are em- bedded directly on top of CMOS logic [77]. This allows reducing the length of interconnects and the corre- sponding delay time. 4.1 CMOS-MRAM hybrid logic The computer architecture where non-volatile ele- ments are located on a chip with CMOS devices is traditionally called logic-in-memory, although as of yet no information is processed in non-volatile ele- ments. Power-efficient MRAM-based logic-in-memory concepts have already been demonstrated [78]. They include field-programmable gate arrays and ternary content addressable memory as well as other variants. These CMOS/spintronic hybrid solutions are already competitive in comparison to the conventional CMOS technology with respect to power consumption and speed. The power consumption problem in modern integrat- ed circuits with ultra-scaled CMOS devices is becoming critical, which prompts various power reduction tech- nologies to be used for keeping the heat dissipation V. Sverdlov et al; Informacije Midem, Vol. 47, No. 4(2017), 195 – 210 204 under control. The techniques based on reduced volt- age operation, clock gating, and power gating modes allow to address the problem to a certain extent, how- ever, they also result in an increase of the time delay to get into or out from these modes. The use of non-vola- tile MRAM-based devices [79-81] with fast access to the stored data allows cutting out the penalty of stand-by power and eliminates the delays when using energy saving modes. The first microcontroller unit with zero standby power featuring non-volatile elements is op- erating at 8MHz [82]. In order to boost the operating frequency, spin-based non-volatile flip-flops were re- cently used to demonstrate a power-gating microcon- troller unit [78] fabricated with standard 90nm CMOS technology with an additional MTJ process. The chip features a very short delay in entering/exiting power- on/power-off with the potential to be further reduced by optimizing parasitic capacitances. Another new circuit example is a field programmable gate array built with non-volatile devices. Here, tempo- ral data is quickly saved in magnetic tunnel junctions before the power is turned off. This has a great poten- tial to reduce the power consumption, which becomes a critical issue in conventional SRAM-based gate arrays [83-85]. By using a logic-in-memory structure [86,87], replacing SRAM cells with non-volatile flip-flops [88] and smartly connected redundant MTJs to avoid resist- ance variations [89], the area of a six-input look-up ta- ble is shown to be reduced by about 50% [78]. Ternary content-addressable memory (TCAM) is able to perform a very high-speed search to match an input [90]. CMOS-based TCAM suffers from standby power losses and relatively high costs due to its complex struc- ture [90]. Employing a 2T-2MTJ structure for the equality search logic part reduces the TCAM cell area [91,92]. A 1Mb non-volatile TCAM chip with a 6T-2MTJ cell struc- ture fabricated in 90nm CMOS and perpendicular MTJ technologies has been demonstrated [93], with 9T- 2MTJ [94], 7T-2MTJ [95], 4T-2MTJ [96], and 5T-4MTJ [97] modifications for high-speed accessibility and reduced variation effects have been also reported. Currently, the TCAM cell structure design as well as the word segmen- tation algorithm optimization is under intense investiga- tion [78] in order to increase speed and reduce the area. With the continued rapid development of smartphones and mobile video applications it becomes necessary to introduce non-volatile elements into important cir- cuits responsible for performance acceleration. A mo- tion-vector prediction circuit is critical for performing mobile video compression by finding motion vectors between two adjacent frames. It has been demon- strated that the introduction of non-volatile elements to implement a full adder helps making the circuit compact, fast, and stable [98-102]. The introduction of non-volatility and a logic-in-memory architecture helps reduce power consumption by 45% [103]. With the activation ratio of embedded clusters decreased a reduction of 97% is possible [78]. Another example of an application specific circuit currently under thorough investigation is a brain-inspired computing network with non-volatile elements, which also demonstrates a large, i.e., more than 90%, power reduction on average when compared to its CMOS based counterparts [78]. 4.2 Intrinsic logic-in-memory The current age of Big Data requires an unprecedented level of data storage capacity complemented with ef- ficient processing capabilities. The data processing is typically confined in large data centers, which appears to customers as a cloud computing environment to en- able resource flexibility. The scale of data centers (and their power consumption) is increasing exponentially. One of the limitations of current computing systems is the overhead of transferring data between memory and processors. As already mentioned, the problem can be solved by placing the main memory closer to processors. Another efficient solution will be to per- form at least part of the data processing already in the storage by designing a memory architecture with en- hanced functionalities capable to directly perform a set of Big Data-oriented, memory-centric operations. This methodology promises a dramatic reduction in the need for data transfers between memory and proces- sor, eliminating the interconnection bottleneck, by cre- ating a new high performance and low power efficient computing paradigm, where the data is not only stored but also analyzed by non-volatile stand-by-power free processing units. Placing the actual computation into the magnetic domain reduces the need of converting magnetically stored information into currents and voltages for pro- cessing and helps not only to simplify the circuit layout but also increases the integration density. The idea is to use MTJs as elementary blocks for non-conventional logic-in-memory architectures. Our invention, which shows that on an MRAM array any two of the coupled 1T-1MTJ cells can serve simultaneously as non-volatile memory and computing units by performing a logical implication operation, has been granted a patent [104]. These structures inherently realize non-volatile logic- in-memory circuits with zero-standby power, where the same elements are used for storing and also pro- cessing information. They have a great potential for Big Data storing and computing, as they are also opening a path for developing computing architectures concep- tually different from the still standard Von Neumann architecture. A new design of an implication-based full V. Sverdlov et al; Informacije Midem, Vol. 47, No. 4(2017), 195 – 210 205 adder involves six 1T-1MTJ cells with 27 subsequent FALSE and material implication operations [105]. The paradigm of employing memory for information processing is perfectly suited for the Big Data revolu- tion we are experiencing now by providing computa- tion capabilities within memory itself, thus eliminating the need for data communication between memory and the processor. However, precisely because of the absence of a clear division between memory and the computing unit this intrinsic logic-in-memory archi- tecture is completely different from the Von Neumann architecture currently employed, and a development of a conceptually new calculation paradigm using this architecture is needed. An alternative option is to follow a more conventional path with memory and computing units separated, where, however, both elements are non-volatile and implemented in a magnetic domain. Placing the actual computation into the magnetic domain reduces the need of converting magnetically stored information into the currents and voltages for processing. It also simplifies the circuit layout and boosts the integra- tion density. The idea of combining MTJs with a com- mon free layer enables the realization of an efficient nanooscillator [106] and a non-volatile magnetic flip- flop [107]. The computation unit is represented by the STT based non-volatile majority gate, with non-volatile magnetic flip-flops [107] used as memory registers. Be- cause all the data processing elements are performed in the magnetization domain, the flip-flops could be put at the legs of the majority gates thus removing the need of data transfer and interconnects between the processing unit and memory. By using the non-volatile computation unit the realization of a 1-bit full adder in magnetic domain is demonstrated [108]. Finally, we mention a completely different neural net- work based approach to calculations. Non-volatile MTJs fit for neural network realizations as they can be considered as a current-driven programmable resistor – memristor – and they significantly advance program- ming and storage functions. MTJ based neural net- works have been demonstrated featuring non-volatile synapses [109] for high-speed pattern recognition with about 70% reduction of gate count and 99% improve- ment in speed. Neuromorphic computing is becoming a reality, with the first self-learning chip revealed on September 25th, 2017 by Intel [110]. 5 Conclusions Spin transistors have been recently successfully dem- onstrated, however, an enhancement of the on-current ratio between the parallel and anti-parallel source/ drain magnetization configuration at room tempera- ture remains one of the main challenges. As both Spin- FET and SpinMOSFET still rely on the charge current to transfer the spin, it sets limitations for the applicability of such devices in main-stream microelectronics, and new ideas are needed for the future. Non-volatile devices based on MTJs possess a TMR suit- able for practical applications. Several companies an- nounced embedded STT MRAM production in 2018. Although STT MRAM is positioned as a successor not only for flash, but also for CMOS-based main computer memory, the relatively high switching current and pow- er may confine STT-MRAM to replacing flash memory in data-intensive and low-power mobile, automotive, or Internet of Things applications. Because of the large switching currents and insufficient speed, STT-MRAM is unlikely to replace SRAM in high-level core caches. Novel innovative non-volatile devices with improved switching characteristics and low power consumption are required for processor-embedded memories. Finally, the successful adoption of non-volatility in mi- croelectronic systems by developing various logic-in- memory architectures and in-memory processing will inevitably result in increasing disseminations of this technology for other applications such as ultra-low- power electronics, high-performance computing, the Internet of Things, and Big Data analysis. 6 Acknowledgments Fruitful discussions with Dr. T. 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Sverdlov et al; Informacije Midem, Vol. 47, No. 4(2017), 195 – 210 211 Original scientific paper  MIDEM Society A Novel Mix-Mode Universal Filter Employing a Single Active Element and Minimum Number of Passive Components Mohammad Faseehuddin1, Jahariah Sampe1, Sadia Shireen2, Sawal Hamid Md Ali3 1Institute of Microengineering and Nanoelectronics (IMEN),University Kebangsaan Malaysia (UKM), Bangi, Selangor, Malaysia 2Department of Electronics and Communication, Indus Institute of Technology and Management, Kanpur, India. 3Department of Electrical, Electronic and Systems Engineering, University Kebangsaan Malaysia, Abstract: A Novel biquadratic mixed mode tunable universal filter is presented. The mix mode filter is based on a new versatile active element dual X current conveyor differential input transconductance amplifier (DXCCDITA). The filter is capable of realizing high pass (HP), low pass (LP), band pass (BP), notch pass (NP) and all pass (AP) responses in voltage mode (VM), current mode (CM) and trans- impedance mode (TIM). In trans-admittance (TAM) mode the filter can realize HP and BP responses. The striking feature of the design is that it is the first reported mix mode Multi Input Single Output (MISO) filter employing a single active element for the design. Only a few passive elements are required for the design (two capacitors and two resistors). The second resistor is required only for obtaining TIM filter response. By properly exciting the filter structure with appropriate current or voltage signals the filter response in all four modes can be obtained. Additionally, VM response can be obtained both in inverting and non-inverting form simultaneously. The pole frequency and quality factor of the filter are tunable. The analysis of non-idealities and sensitivity is conducted to further study the effect of process variability on the filter response. The filter is simulated in Spice using 0.35µm CMOS model parameters obtained from TSMC. Additionally, the DXCCDITA is also constructed using commercially available integrated circuits (ICs) AD844 and LM13700. The ideal and measured results of the filter for Voltage mode are given to further validate its performance. Keywords: Current mode; Current conveyor; Cascadable; Mix Mode; Tunable Nov univerzalen filter z mešanim načinom delovanja z enim aktivnim elementom in minimalnim številom pasivnih komponent Izvleček: Predstavljen je nov dvokvadrantni univerzalen in nastavljiv filter v mešanem načinu. Filter temelji na novem prilagodljivem aktivnem dvojnem X tokovnem diferencialnem transkonduktančnem ojačevalniku (DXCCDITA). Deluje lahko v visoko, nizko ali pasovno prepustnem načinu (HP, LP ali BP) ter tokovnem, napetostnem ali transimpedančnem načinu (CM, VM, TIM). Je prvi dizajn filtra, ki omogoča mešan način delovanja z le enim aktivnim elementom. Uporabljeni so le štirje pasivni elementi (dva upora in dva kondenzatorja), pri čemer je drugi upor potreben le za doseganje TIM odziva. S pravim tokovno napetostnim vzbujanjem lahko filter deluje v vseh štirih načinih. Dodatno, VM način omogoča simultan invertiran in neinvertiran odziv. Filter je simuliran v SPICE okolju v 0.35µm CMOS tehnologiji. DXCCDITA filter je realiziran s komercialnimi integriranimi vezji AD844 in LM13700. Validacija je prikazana na osnovi simuliranih in merjenih vrednosti v napetostnem načinu delovanja. Ključne besede: Tokovni način; tokovni ojačevalnik; kaskade; mešan način * Corresponding Author’s e-mail: faseehuddin03@siswa.ukm.edu.my Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 4(2017), 211 – 221 212 M. Faseehuddin et al; Informacije Midem, Vol. 47, No. 4(2017), 211 – 221 1 Introduction Filters are an integral part of almost every electronic system and so their synthesis and development re- mains an ever evolving field. They find applications in signal processing, bio-medical, instrumentation, com- munication systems etc. Among various filter struc- tures universal filters are the most versatile as all the standard filter functions can be derived from them [1]. They serve as standalone solution to many filtering needs. Owing to their inherent advantage of wide bandwidth, high slew rate, low power consumption, simple cir- cuitry and excellent linearity [1-3] current conveyors (CC) are widely used in electronic design. Moreover, the requirement of low voltage low power operation put forward by portable electronic devices and the energy harvesting systems [4] etc. further encourages the use of CC. In the present day mixed mode design environment where many systems interact, many times the need arises for the current mode and volt- age mode circuits to be connected together. This re- quirement can be met by employing trans-admittance mode (TAM) and trans-impedance mode (TIM) filter structures which can serve as the interface providing distortion free interaction. Although a number of TAM and TIM filter structures can be found in the literature but a single topology providing the CM, VM, TAM and TIM responses will be an added advantage in terms of area and power requirements. In the past two de- cades, a number of mixed mode filters have been pro- posed utilizing different current mode active elements like dual output current controlled current conveyor (DOCCCII), multi output current conveyor (MOCCII) [3], current controlled current conveyor transconductance amplifier (CCCCTA) [3], Current feedback operational amplifiers (CFOA) [3], fully differential current conveyor (FDCCII) [3], differential difference current conveyor and digitally programmable current conveyor (DPCCII) [3] etc. The filter structures can be classified in three basic groups single input multi output (SIMO) [9], multi in- put multi output (MIMO) [5], multi input single output (MISO) [6]. The mix mode filters can be categorized based on many criteria like number of active elements utilized, number of passive components employed, re- quirement of components matching, whether the filter is tunable, number of filter responses realized in each mode, cascadability of the filter etc. The designs in [5, 6, 7, 8, 11, 12, 13, 17] require three or more active ele- ments which results in large chip area and increased parasitic effects. The filter topologies in [10, 14, 16] re- quires two active elements but four or more passive elements. The mix mode filters in [5, 7, 8, 11] cannot re- alize all standard filter responses in all the four modes. In addition, filter structures in [6, 12, 13, 14, 16] did not posses inbuilt tuning capability. A comprehensive comparison of some of the exemplary mix mode filter designs with the proposed filter is presented in Table 1. The literature survey shows that except [15] no other single active element based filter to date exists that can function in all the four modes. Furthermore, the design of [15] is MIMO type filter which uses a complex build- ing block, the FDCCII and did not posses inbuilt tun- ing property and cascadability for all responses in any mode. The filter in [15] requires a matching condition Table 1: Comparison of the proposed filter with state of art filter topologies available in the literature Reference Filter responses realized Number/Type of Active Block Passive Elements used VM CM TAM TIM C R 5 LP, BP, HP, NP LP, BP, HP, NP LP, BP, HP, NP LP, BP, HP, NP 4/CCCII 2 0 6 All Five All Five All Five All Five 7/CCII 2 8 7 LP, BP, HP All Five All Five LP, BP, HP 3/CCCCTA 2 0 8 Fig. 4 Not Realized All Five Not Realized All Five 2/CCII, 1/MOCCII 2 3 9 All Five All Five Not Realized Not Realized 2/DO-CCCII 2 0 10 All Five All Five All Five All Five 2/CCCII 2 2 11 LP, HP, BP LP, HP, BP LP, HP, BP LP, HP, BP 5/MOCCCII 2 0 12 All Five All Five All Five All Five 4/CFOA 2 9 13 Not Realized All Five Not Realized All Five 3/MOCCII 2 5 14 All Five All Five All Five All Five 3/DDCC 2 4 15 All Five All Five HP, BP All Five 1/FDCCII 2 3 16 All Five All Five All Five All Five 1/FDCCII, 1/DDCC 2 6 17 All Five All Five All Five All Five 4/MOCCCII 2 0 Proposed All Five All Five HP, BP All Five 1/DXCCDITA 2 2 213 to realize AP response in all three modes. Moreover, ex- cessive number of Input/output terminals are used in the design. In addition, the circuit cannot be construct- ed using the off the shelf popular ICs AD844 which is a slight disadvantage since every time it is not possible to fabricate the concept. The proposed filter on the other hand can be readily constructed using AD844 [33] and LM13700 [34] making it possible to test our design in hardware or employ the design in practical applica- tions. Furthermore, the proposed mix mode filter real- izes non-inverting responses in all four modes unlike [15]. The proposed filter is further compared with the state of the art recently published filter structures us- ing single active elements to highlight the merits of the structure. The survey shows that majority of the single active element based implementations work in a single mode. The Table 2 presents the detailed comparison. In this research the authors propose a mixed mode universal filter synthesized by single DXCCDITA [35]. The filter uses only two capacitors and two resistors. The second resistor is required only for obtaining TIM filter response. The filter can be termed as MISO since for a particular mode all the filter responses are ob- tained from a single node. By proper excitation with appropriate current or voltage signals the filter struc- ture can perform in all four modes. The filter is capable of realizing all five standard filter responses in VM, CM and TIM modes. Additionally, in VM both inverting and non-inverting outputs are available simultaneously. In TAM mode the filter can realize HP and BP responses. The merits of the filter includes (i) it is the first reported MISO type mix mode filter using single active element (ii) no matching for VM, TAM, CM (HP, BP) and TIM (LP, BP) responses (iii) tunability of pole frequency via bias current (iv) use of minimum number of passive ele- ments (v) availability of VM output at low impedance node (vi) availability of CM and TAM output at high im- pedance node (vii) low active and passive sensitivities (viii) provision for independent control of frequency and bandwidth (ix) provision for gain tuning in TIM mode. The simulations in 0.35μm technology param- eters obtained from TSMC are conducted to test the performance of the filter. The DXCCDITA utilized in the filter design is also constructed using ICs AD844 and LM13700 to further validate the filter design. 2 Dual X current conveyor differential Input transconductance amplifier (DXCCDITA) The proposed Dual X current conveyor differential Input transconductance amplifier (DXCCDITA) [35] is functionally a connection of DXCCII and OTA. The new block carries features of CCII, ICCII and tunable trans- conductor in one single architecture which is also sim- ple to implement as an integrated circuit. The Voltage current characteristics of the developed DXCCDITA are given in matrix Equation 1 and the block diagram is presented in Fig. 1. Table 2: Comparison of the proposed filter with state of art MISO filter topologies available in the literature Reference Type of Ac- tive Block Filter responses realized Number of Capacitors/ Resistors Used Matching Condition Number/Type of Filtering Modes realized Whether Tunable Is output available from a sin- gle Node 18 CCII LP, HP, BP, NP ,AP 2C/3R Yes 1/VM No No 19 Fig. 16 DVCCII LP, BP 2C/3R No 1/VM No Yes 20 Fig. 4 FDCCII LP, HP, BP, NP ,AP 2C/2R No 1/VM No Yes 21 Fig. 8 DDCCTA LP, HP, BP, NP ,AP 2C/1R No 1/CM Yes No 22 VDIBA LP, HP, BP, NP ,AP 2C/1R No 1/VM Yes No 23 VDTA LP, HP, BP, NP ,AP 2C/1R No 1/VM Yes Ye 24 VDTA LP, HP, BP, NP ,AP 2C/1R No 1/VM Yes Yes 25 VD-DIBA LP, HP, BP, NP ,AP 2C/1R No 1/VM Yes Yes 26 CDBA LP, HP, BP, NP ,AP 4C/4R Yes 1/VM No Yes 27 CFOA LP, HP, BP, NP ,AP 2C/3R Yes 1/VM No Yes 28 CDTA LP, HP, BP, NP, AP 2C/3R Yes 1/CM Yes Yes 29 CFOA LP, HP, BP, NP ,AP 2C/3R Yes 1/VM No Yes 30 CDBA LP, HP, BP, NP, AP 2C/5R Yes 1/VM No Yes 31 CCII LP, HP, BP, NP, AP 2C/2R Yes 2/VM, CM No No 32 Fig. 2 FDCCII LP, HP, BP, NP ,AP 2C/2R No 1/CM No No Proposed DXCCDITA LP, HP, BP, NP, AP (only HP, BP in TAM) 2C/2R No (Only CM Mode) 4/CM, VM,TIM,TAM Yes Yes M. Faseehuddin et al; Informacije Midem, Vol. 47, No. 4(2017), 211 – 221 214 (1) Figure1: Block diagram of DXCCDITA The CMOS implementation of DXCCDITA is presented in Fig.2. It is a eight terminal active element. The first stage consists of DXCCII transistors (M1-M24). The volt- age at Y appears at VXP and in inverted form at VXN. The current input at Vp node is transferred to nodes ZP1 and ZP2. In the same way the input current from XN node is transferred to ZN1 and ZN2. The second stage is com- posed of OTA transistors. The transconductance is real- ized using transistors (M25-M34).The output current of the trans-conductor depends on the voltage difference between voltages at terminals ZP1 and ZN1. Assuming saturation region operation for all transistors and equal W/L ratio for transistors M25 and M26 the output cur- rent Io of the OTA is given by Equation 2. ( ) ( )( )1 1 1 12O mi ZP ZN Bias i ZP ZNI g V V I K V V= − = − (2) Where, the transconductance parameter 2i ox WK µC L= , (i=25, 26) W is the effective channel width, L is the ef- fective length of the channel, Cox is the gate oxide ca- pacitance per unit area andm is the carrier mobility. It is evident from (2) that the transconductance can be tuned by the bias current thus imparting tunability to the structure. 3 The Proposed Single Active Element Mixed Mode Filter The proposed mix mode universal filter is presented in Fig. 3. The filter utilizes two resistors and two capaci- tors. The second resistor R2 is only needed to obtain TIM response. The VM, CM and TAM responses can be obtained using only three passive elements. The filter can realize all five generic filter responses in VM, CM, TIM while it can realize HP, BP functions in TAM mode of operation. Figure 3: Mix Mode filter topology 3.1 Voltage Mode Operation In voltage mode operation the input currents I1 to I5 are set to zero. The filter transfer function is given in Equa- tion 3. The filter is capable of realizing all five standard filter functions. The input excitation sequence is given Figure 2: CMOS Implementation of DXCCDITA M. Faseehuddin et al; Informacije Midem, Vol. 47, No. 4(2017), 211 – 221 215 in Table 3. The output of the filter is available at low impedance XP terminal. It is worth emphasizing that by tapping the output from XN node inverting VM re- sponse can also be obtained simultaneously which is an added advantage of the filter. In addition, in VM LP response both the capacitors are grounded which is again an advantage. 2 1 1 1 2 2 3 1 1 m Out(VM) 2 1 1 2 1 1 m RVS C C -V +V SC RgV = RS C C +SC R +1g (3) Table 3: Input Excitation sequence for VM realization VOut (VM) V1 V2 V3 Matching Required LP 0 -1 0 No HP 1 0 0 No BP 0 0 1 No NP 1 -1 0 No AP 1 -1 -1 No 3.2 Current Mode Operation In current mode the voltages V1 to V3 are set to zero. Hence all the passive elements are grounded. The input currents are applied as shown in Fig. 3. It is to be noted that input current I5 and resistance R2 are not needed for CM operation so only four current inputs are nec- essary to achieve five standard filter responses. The transfer function is presented in Equation 4 and filter excitation sequence is given in Table 5. All the outputs are available at high impedance ZP2 node which is good for cascadability. 3.3 Trans-Impedance Mode Operation In TIM mode the voltages V1 to V3 are set to zero grounding all the passive elements. In TIM mode an ex- tra resistor is needed to obtain the output. In this mode input current I4 is not required. To realize HP and NP re- sponses a matching condition of R1 = 1/gM is required which can be easily set by fixing R1 and changing the bias current of the trans-conductor. The analysis of the filter leads to the transfer function as given in Equation 5. The excitation sequence of the filter is given in Table 5. The gain of the filter can be varied by changing the value of R2 which is an advantage. Table 4: Input Excitation sequence for CM realization IOut l1 l2 l3 l4 Matching Required LP -1 0 -1 0 C1=C2 HP 0 -1 0 0 No BP 0 0 1 0 No NP 0 0 -1 1 C1=C2 AP 0 0 -2 1 C1=C2 Table 5: Input Excitation sequence for TIM realization VOut(TIM) l1 l2 l3 l5 Matching Required LP 0 0 -1 0 No HP 1 0 1 1 R1=1/gM BP 1 0 0 0 No NP 1 0 0 1 R1=1/gM AP 1 -1 0 1 R1=R2=1/gM AP (alternative op- tion to make filter gain tunable) 2 0 0 1 R1=1/gM 3.4 Trans-Admittance Mode Operation In TAM operation the filter transfer function is given in Equation 6. The filter can only realize HP and BP func- tions. The excitation table is given in Table 6. The out- put of the filter is available at high impedance 2PZ node. ( ) ( ) ( ) ( )2 21 1 2 1 2 2 2 3 1 2 1 Out TAM 2 1 1 2 1 1 M V C C R SC V SC V C C R I RS C C SC R 1g S S− + − + = + + (6) IOut(TAM) V1 V2 V3 Matching Required HP 0 0 1 No BP 0 -1 0 No ( ) ( )2 21 14 1 2 1 1 1 1 1 2 1 2 3 2 1 M M Out CM 2 1 1 2 1 1 M R RI (S C C SC R 1) I SC R 1 I (S C C ) I (SC R )g gI RS C C SC R 1g + + − + − + = + + ( ) 2 1 2 1 2 1 1 5 1 2 1 1 2 2 1 2 3 2 M M M Out TIM 2 1 1 2 1 1 M R R SC R SC RI (S C C SC R R R ) I I I (R )g g g V RS C C SC R 1g    + + − + −    = + + (4) (5) M. Faseehuddin et al; Informacije Midem, Vol. 47, No. 4(2017), 211 – 221 216 The expression for pole frequency, quality factor and bandwidth for all four modes are given in Equations 7-9. It can be inferred by examining the equations that if R1 or RM(1/gM) is varied but their ratio is kept constant then frequency can be varied independent of the qual- ity factor. This can be easily achieved by changing R1 and adjusting the bias current of transconductance amplifier. The frequency and bandwidth also enjoy non interactive tuning capability through R1 and RM. 1 2 1 1 P MC C R R ω = (7) 2 1 1 MR CQ C R = (8) 2 1 M BW R C= (9) where RM = 1/gM is the transconductance of the trans- conductance amplifier. The property of tunability allows changing the pole frequency of the filter without changing the passive components and it is also advantageous for cancelling out the variations in the pole frequency caused due to slight change in capacitance values during fabrication. The tuning can be achieved by changing the bias cur- rent of the OTA, any variation in the pole frequency in- troduced due to random variations in capacitance and device parasitics can be easily nullified. Moreover, the two resistors can be designed using the MOS transis- tors [36-37] this will impart dual tunability to the filter structure hence by properly tuning the control voltage of the MOS resistors and the bias current of the trans- conductance amplifier changes in the capacitance val- ues can be easily accommodated. 4 Non-Ideal Analysis In this section the Non-idealities of the DXCCDITA are considered and their influence on the proposed mix mode filter circuit is analyzed. A simplified non-ideal model of DXCCDITA is presented in Fig. 5 for analysis. The most important aspects contributing to the devia- tions in frequency performance are the non-ideal fre- quency dependent current and voltage transfer gains ai(s) and bi(s), where ai(s) = a0i/(1 + s/wai) and bi(s) = b0i/ (1 + s/wbi). Ideally, ai = b0i = 1 and wai = wβI = ∝. Another (10) ( )2 2 2 24 1 1 2 3 2 1 Out(CM) 2 I (α S A+SB+α ) I α α S A+BS+α I (α S A) I (S A) I (SC R ) I α S A+BS+α P P N N P P P N N P P P P P P N N β β β β β β β β β − + − + = ( ) 2 1 2 5 2 2 2 1 2 3 2 m m Out TIM 2 SC R SBI (α S R A SBR α R ) I α α I α I α (R )g g V α S A+BS+α P P N N P N N N N N N P P N N β β β β β β β    + + − + +    = ( ) ( ) ( )3 211 1 2 2 2 2 2 1 3 1 2 1 m Out TAM 2 RV α S C C C V α SC α SC V V C C Rg I α S A+BS+α P P N P P N P P N N Sβ β β β β   − − +  = (12) (13) (14) M. Faseehuddin et al; Informacije Midem, Vol. 47, No. 4(2017), 211 – 221 2 1 2 3 Out(VM) 2 α VS -α V +V SBV = α S A+SB+α P N P P N N A β β (11) Where, A=C1C2R1/gm, B= C1R1 217 important performance parameter is the associated parasitics at the X nodes which can be quantified as ZXP = ZXN = RX(N,P) + sLX(N,P). The parasitic resistances and capacitance associated with the Y and Z nodes are RZP, RZN and RY, while the associated capacitances are CZP, CZN and CY. There ideal values are equal to zero. γ represents the transconductance transfer inaccuracy of the OTA while Ro and Co are parasitics at the OTA output. The modified V-I relations of DXCCDITA including the non- ideal gains and parasitic elements are given in Equa- tion 10. Considering only the effect of the non-ideal gains the transfer functions, pole frequency and quality factor of the above filter will be modified as presented in Equations 11-16. 1 2 1 N N P M P PC C R R α βω α β = (15) 2 1 1 M N N P PR CQ C R α β α β = (16) Figure 4: Non-Ideal model of DXCCDITA The sensitivity analysis of the filter is also carried out to get a measure of active and passive sensitivities of the filter. It can be deduced from the analysis that the filter has low sensitivities. 1 2 1 1 2R C C gm S S S Sω ω ω ω− = − = − = = 1 2 1 1 2 Q Q Q Q R C C gmS S S S− = = − = − = 1 2 1 1 2P P R C C N N gm S S S S S S S Sω ω ω ω ω ω ω ωα β α β− = − = − = − = − = = = = 1 2 1 1 2 Q Q Q Q Q Q Q Q P P R C C N N gmS S S S S S S Sα β α β= = − = = − = = = =− 5 Simulation results In order to establish the performance of the proposed dual X current conveyor differential input transcon- ductance amplifier (DXCCDITA) it was designed in 0.35 μm parameters from TSMC. The circuit was simulated in SPICE to measure the important design metrics. The aspect ratios of the transistors are given in Table 7. The supply voltages are kept at VDD = -VSS = 1.5V. The bias voltage was fixed at Vbias = 0.55V. The bias current of OTA was set to 50 μA which resulted in a transconductance of gm = 0.1 mS. The proposed active element is char- acterized using the method stated in [38]. The perfor- mance parameters of the active block are summarised in Table 8. Table 7: Aspect Ratios of the Transistors Transistor Width (W μm) Length (L μm) M1- M2 1.4 0.7 M3- M5 2.8 0.7 M6- M7 2.4 0.7 M8- M10 4.8 0.7 M11-M24 9.6 0.7 M25-M32 2 1 Table 8: Performance Parameters of the Proposed DX- CCDITA Voltage Gain (VXP/VY) 0.98 Voltage Gain (VXN/VY) 0.95 Current Gain (IZP/IXP) 1.05 Current Gain (IZN/IXN) 1.05 DC Voltage transfer range ±400mV DC Current Transfer range (IZP) ±60μA DC Current Transfer range (IZN) ±60μA Voltage Transfer B.W. (VXP/VY) 632MHz Voltage Transfer B.W. (VXN/VY) 728MHz Current Transfer B.W. (IZP/IXP) 932MHz Current Transfer B.W. (IZN/IXN) 1.32GHz Parasitic Resistance at XP node RXP 71.1Ω Parasitic Resistance at XN node RXN 38.2 Ω Resistance at ZN node RZN 305K Ω Resistance at ZP node RZP 305 K Ω Resistance at O node Z0 1.05M Ω The operation of the filter in voltage mode is analyzed first. The filter is designed for unit quality factor (Q=1) and pole frequency of 318.30KHz by selecting the pas- sive components values as R1 =10KΩ, C1 = 50pF, C2 = 50pF the bias current is set at Ibias = 50mA. The filter re- sponses are given in Fig. 5-6. Next, the tunability of the filter is examined by varying the bias current and ob- serving the BP response. It can be inferred from the Fig. 7 that the filter is perfectly tunable. The total harmonic distortion (THD) of the filter is evaluated and plotted for different signal amplitudes as shown in Fig. 8. It can be seen that THD is within acceptable limit for wide range of voltage signal amplitudes. To study the effect of process variability on the filter performance Monte M. Faseehuddin et al; Informacije Midem, Vol. 47, No. 4(2017), 211 – 221 218 Carlo analysis, assuming Gaussian distribution, for 10% deviation in capacitor values (C1&C2) is conducted for 100 runs as shown in Fig. 9. It can be deduced from the figure that there is only slight deviation from the ex- pected value which can be easily nullified by adjusting the bias current of the filter as discussed in the preced- ing section. Figure 5: VM filter responses Figure 6: VM All Pass filter gain and phase response Figure 7: Band pass response of VM filter for different bias currents Figure 8: Total Harmonic Distortion of filter in voltage mode operation for BP response The current mode filter is now designed for a pole frequency of 318.30 KHz by selecting R1 = 10KΩ, C1 = 50pF, C2 = 50pF the bias current is set at Ibias = 50mA. The response of the filter is given in Fig. 10-11. The total harmonic distortion (THD) of the filter is evaluated and plotted for different signal amplitudes as shown in Fig. 12. It can be seen that THD is less than 1.5% for wide range of signal amplitudes. Figure 10: CM filter responses Figure 11: CM All Pass filter gain and phase response Figure 12: Total Harmonic Distortion of filter in current mode operation for BP response Now the TIM response is analysed. The passive ele- ments are fixed at R1=R2=10KΩ, C1 = 50pF, C2 = 50pF. The bias current is selected as Ibias = 50mA(gM = 0.1ms) Figure 9: Monte Carlo analysis of the low pass response for 10% variation in capacitance value M. Faseehuddin et al; Informacije Midem, Vol. 47, No. 4(2017), 211 – 221 219 to satisfy the condition of R1 = 1/ gM. The resulting pole frequency is 318.30 KHz. The responses of the filter are shown in Fig. 13-14. Figure 13: TIM filter responses Figure 14: CM All Pass filter gain and phase response To further validate the performance of the proposed topology. The DXCCDITA is constructed using the com- mercially available ICs AD844 and LM13700. The pos- sible implementation of DXCCDITA is given in Fig. 15. Figure 15: Implementation of the DXCCDITA from the commercially available ICs The hardware implemented DXCCDITA is then used to measure the VM filter responses. The Agilent tech- nologies MSO-X 3024A oscilloscope, IDL-800 digital lab prototype board, and Agilent technologies function generator were used in the test setup. The passive com- ponents values selected were C1 = 560pF, C2 = 560pF, R1 = 10KΩ. The supply voltage are kept at VDD = -VSS = 5V. The theoretical pole frequency of the filter is found to be 28.420 KHz. The ideal and measured filter responses are given in Fig. 16 (a-d). The all pass response is given in Fig. 17 (a-b). Figure 16: The VM filter responses constructed using the AD844 and LM13700 ICs a) b) c) d) Figure 17: The VM filter all pass response constructed using the AD844 and LM13700 ICs (a)Gain (b) Phase a) b) M. Faseehuddin et al; Informacije Midem, Vol. 47, No. 4(2017), 211 – 221 220 6 Conclusion A novel minimum component MISO type mix mode universal filter is presented. The filter is designed using a single DXCCDITA as active element. To the best knowl- edge of the authors the reported filter is the first MISO type mix mode single active element based implemen- tation capable of working in all four modes. The filter can realize all five standard responses in voltage mode, current mode and trans-impedance modes. The filter gives HP and BP responses in trans-admittance mode. No components matching condition are required in any mode except for trans-impedance mode (LP, NP, AP) and current mode (LP, NP, AP) responses. The filter offers low impedance voltage mode output and high impedance current and trans-admittance mode output leading to cascadability. The pole frequency, quality factor and bandwidth of the filter are tunable. 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Fabre, O. Saaid, H. Barthelemy, “On the frequen- cy limitations of the circuits based on second generation current conveyors”, Analog Integrated Circuits and Signal Processing, vol. 7, no. 2, pp.113- 129, 1995. Arrived: 09. 06. 2017 Accepted: 14. 09. 2017 M. Faseehuddin et al; Informacije Midem, Vol. 47, No. 4(2017), 211 – 221 222 223 Original scientific paper  MIDEM Society Synthesizable 2D Vernier TDC based on gated ring oscillators Marijan Jurgo, Romualdas Navickas Micro and Nanosystems Design and Research Laboratory of Electronics faculty, Vilnius Gediminas Technical University, Vilnius, Lithuania. Abstract: Time to digital converter (TDC) is a device, which measures time interval between two edges of signals and converts it to digital code. Lately it is used as phase detector in all-digital frequency synthesizers. One of main parameters of TDC is resolution, which describes smallest time interval, which can be measured using TDC. Resolution of basic inverter-based TDC improves with reduction of delay of inverter in modern nanometric CMOS technology nodes. But in more mature technologies delay of inverter does not provide needed TDC resolution. In this paper sub-inverter-resolution 2D Vernier TDC, which is based on gated ring oscillators and is implemented in VHDL hardware description language for easy migration to various technology nodes, is presented. It is synthesized, placed and routed in 65 nm CMOS technology. Main blocks of TDC are two gated ring oscillators, their lap and edge counters, arbiter matrix, output decoder and control block. Frequency and single stage delay of gated ring oscillators is changed by switching parallel- connected sections of three-stage oscillators. Tuning step of single stage delay of gated ring oscillator, which is equal to the resolution of TDC, can be changed from 3.2 to 0.8 ps at typical operation conditions, when number of enabled stages of oscillator is changed from 22 to 48. TDC occupies 123,0 µm × 148,8 µm area of silicon. Keywords: CMOS; integrated circuit; time to digital converter; Vernier; gated ring oscillator Sestavljivi 2D Vernier TDC na osnovi obročnih oscilatorjev Izvleček: Časovno digitalni pretvorniki (TDC) so naprave, ki merijo časovni interval med dvema roboma signal in ga pretvorijo v digitalno obliko. Pretvornik je uporabljen kot fazni detektor v digitalnih frekvenčnih sintetizatorjih. Glavni parameter TDC je resolucija, ki je opisana kot najmanjši časovni interval, ki ga še lahko izmeri. Resolucija osnovnih invertirajočih TDC se izboljša z znižanjem zakasnitev inverterja v moderni nanometrski CMOS tehnologiji. Pri zrelih tehnologijah zakasnitev ne omogoča doseganja željene resolucije TDC. V članku je predstavljen 2D Vernier TDC na osnovi obročnega oscilatorja s podinvertersko resolucijo. Zaradi lažje migracije v različne tehnologije je realiziran v VHDL strojnem jeziku. Sestavljen je v 65 nm CMOS tehnologiji. Glavni bloki TDC so: dva krožna oscilatorja na osnovi vrat, njihov krog, robni števci, arbitna matrika, izhodni dekoder in kontrolni blok. Frekvenčne in enostanjske zakasnitve se spreminjajo s preklapljanjem vzporedno vezanih sekcij tristanjskega oscilatorja. Korak je nastavljiv od 3.2 do 0.8 ps pri tipičnem delovanju in predstavlja resolucijo TDC. Velikost TDCja je 123,0 µm × 148,8 µm. Ključne besede: CMOS; integrirana vezja; časovno digitalen pretvornik; Vernier; obročni oscilator * Corresponding Author’s e-mail: marijan.jurgo@vgtu.lt Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 4(2017), 223 – 231 1 Introduction Time to digital converter (TDC) is electronic device which converts time interval between edges of two signals into digital code. It is often used as phase detector in all-digital phased locked loops, which are used as high frequency synthesizers. Such synthesizers are gaining popularity in recent years, since it becomes harder to implement conventional charge-pump synthesizers in modern nanometric integrated circuit (IC) technology nodes. Therefore, there is a lot of effort put into research and development of all-digital frequency synthesizers and their constituting blocks. The output of TDC is digital, therefore due to quantization, which is related to resolution of TDC, it affects phase noise of whole synthesizer [1]. The most 224 basic TDC is based on inverter delay line. In such TDC signal generated by digitally controlled oscillator (DCO) propagates through delay line and its value after each inverter is sampled by the edge of reference signal. At the output, there is a pseudo thermometric code, which shows how many inverters are between edges of reference and generated signals. The minimal time interval, which can be measured by this TDC, is equal to inverter delay. Therefore, performance of this TDC increases and its quantization decreases in newer technology nodes as the delay of inverters decreases. Although in more mature technology nodes performance of such TDC decreases and consequently there is a need for TDC which can measure time intervals lower than inverter’s delay. There are several structures of TDC with sub-inverter delay resolution, such as multi-stage TDC, Vernier family of TDC’s (1 dimensional (1D), 2 dimensional (2D), 2D Gated Ring Vernier), stochastic TDC etc. [2]–[7]. Although these structures can achieve high resolution, their complexity is much higher compared to TDC based on inverter delay line. Also, often TDCs are manually designed and routed despite of digital nature of TDC, what defeats one of the advantages of all-digital frequency synthesizers – easy migration from one IC technology to another. The aim of this work is to design time to digital converter, which has sub-inverter delay resolution, large input time range and can be easily implemented in various IC technology nodes. Proposed TDC is implemented using VHDL hardware description language and is fully synthesized in 65 nm CMOS technology. It employs 2D Vernier properties and as in 2D Gated Vernier TDC [6], its delay lines are replaced with gated ring oscillators. Also, compared to [6] different phase detection technique and structure of oscillator and its tuning method is used to make design synthesisable. Output decoding procedure and its issues in 2D Vernier architecture are also addressed in this paper. 2 Structure of TDC The structure of proposed time to digital converter is presented in Fig. 1. Two main inputs for reference and DCO signals are respectively marked as FREF and FDCO and output is marked as TDCOUT. Main blocks of TDC are lower frequency gated ring oscillator (GROL), higher frequency gated ring oscillator (GROH), lap counter of lower frequency oscillator, edge counter of higher frequency oscillator, matrix of arbiters, control block and output decoder. 2.1 Gated ring oscillators and counters Lower and higher frequency gated ring oscillators share same structure, which is shown in Fig. 2. They are composed of N parallel-connected three-stage gated ring oscillators, made of tristate inverters, similar as in [8]. Such inverters are available in most IC manufacturing technologies. Therefore, usage of these inverters does not prevent synthesis of oscillators. The frequency of an oscillator can be tuned by turning on different numbers of parallel-connected sections of oscillator. M. Jurgo et al; Informacije Midem, Vol. 47, No. 4(2017), 223 – 231 Figure 1: Structure of proposed time to digital converter 225 Figure 2: Structure of Gated Ring Oscillators The output of oscillators is a periodic signal, but in this case oscillators are turned on only when the edge of the reference signal or the edge of the signal generated by the frequency synthesizer (i.e. DCO output signal) is received and oscillators are treated as infinite delay lines. To calculate the output of TDC we need to know through how many delay elements (oscillator’s stages) signal has propagated. For this task lap counters are used to calculate through how many oscillator’s laps the signal has travelled and edge counters to calculate signal’s edges in one lap (i.e. through how many delay elements the signal has traveled in current lap). From values of both counters the total number of propagated delay elements may be calculated. Only rising edges of gated ring oscillator’s signals are used to calculate the time interval between edges of TDC input signals to avoid mismatch between edge rise and fall times [9]. Since oscillators are made of tristate inverters, edges used for calculation are distributed not in succession as shown in Fig. 2 (ports E1, E3, E2), because the signal is inverted after each stage. Therefore, one logical delay element is made of two tristate inverters and one logical lap is counted after two laps. 2.2 Arbiters Often D type flip-flops are used as arbiters in time to digital converters – data input can be used as input for delayed versions of reference signals and clock inputs are used as input for delayed versions of generated signals. As it is known, for correct operation of D flip-flop, its data signal should be constant during setup and hold time near clock signal edge i.e. in metastability window (time interval TS + TH, shown in Fig. 3). Otherwise, if signal changes in metastability window, the output of the flip-flop can acquire any value (Fig. 3, (b)). Correct operation of flip-flop is essential in TDC application, because in locked state of the frequency synthesizer or when the edge of generated signal catches up with the edge of reference signal (in Vernier operation), edges of clock and data signals are very close to each other. One of the common method to address this issue is to use sense amplifier flip-flops, which have a narrow metastability window [1]. But unfortunately, these flip- flops are not suitable for synthesis. Figure 3: Operation of D type Flip-Flop: correct output (a) and possible metastability (b). TS – setup time, TH – hold time Figure 4: Arbiters made of SR latch and D flip-flop (a) and symmetrical structure of SR latch, composed from NOR gates (b) Arbiters made of SR latch and D type flip-flop shown in Fig. 4, (a), can be used to narrow the metastability window [5], [9]. Latch is a level sensitive device, so even if edges of input signals are received close to each other, the output of the latch will settle to a known logic level. D type flip-flop is edge sensitive, so its metastability is eliminated by connecting data input to constant logical “1” level and the output of the SR latch is used as a clock signal. It should be noted, that the D flip-flop in such an arbiter should be reset before each M. Jurgo et al; Informacije Midem, Vol. 47, No. 4(2017), 223 – 231 226 measurement, since it can’t change its state to logic “0” after it was set to “1”, because its data input is constant high. Also, SR latch made of NOR or NAND gates has symmetrical structure (Fig. 4, (b)), so it is equally loading both ring oscillators, although if it is implemented in hardware description language, designer is dependent on foundry-provided standard cells and usually cannot affect schematics and layout of individual gates. 3 Operation of TDC. The control algorithm of proposed TDC is shown in Fig. 5. To simplify overall design of the TDC and lower used area of silicon, TDC is measuring only positive time intervals, i.e. when the edge of the reference signal is received earlier than the edge of the signal generated by digitally controlled oscillator. On the other hand, negative delays are equal to large positive delays (larger than half of the period of the reference signal). Figure 5: Control algorithm of proposed time to digital converter At the beginning of the measurement TDC is waiting for the rising edge of the reference signal. When it is received, the lower frequency gated ring oscillator and its lap counter are started and the TDC’s input for the reference signal is disabled. After that TDC is waiting for the rising edge of the signal generated by synthesizer’s DCO. When it is received, the state of lower frequency oscillator (signal levels after each inverter) is saved, higher frequency oscillator and its edge counter are started and the TDC’s input for the signal of DCO is disabled. When both oscillators are started, the output values of arbiters are monitored. When the output of any arbiter changes to high logic level, position of that arbiter is searched and depending on that position, the output signal of TDC is decoded. After that, all counters are reset, both inputs of TDC are enabled and TDC is waiting for another pair of the input signals for new measurement. Such operation allows to avoid usage of complex phase detector, introduced in [6]. Distinct case of 2D Vernier operation is obtained when the delays of stages composing two oscillators (or de- lay lines) are related with such dependency [5, 6]: ( )res 1 2 1 2; ; 1k k∆ = τ = τ − τ τ = ⋅ ∆ τ = − ⋅ ∆ (1) where τ1 and τ2 are delays of respectfully lower and higher frequency oscillator’s stages. Coefficient k should be set depending on values of τ1 and τ2 to meet this dependency. In this case, the resolution of 2D Vernier TDC is same as of 1D Vernier TDC, but we are obtaining continuous Vernier plane of TDC’s output time samples without breaks or missing points. The values of this plane can be calculated as shown in equation (2). ( )OUT 1TDC k X k Y= ⋅ − − ⋅ (2) where X and Y are coordinates of Vernier plane, which show through how many stages propagated respect- fully reference and DCO’s signal. Fragment of calculated plane of TDC’s output time samples, when τ1 is set to 10 ps, τ2 is set to 9 ps, and k = 10, is shown in Fig. 6. GROLL and GROHL are lap counts of respectfully lower and higher frequency gated ring oscillator, GROLE and GROHE are edge counts in one lap of respectfully lower and higher frequency gated ring oscillator. Part of the plane, which is marked in green is used for calculation of TDC output. Grey area is not used for calculation - it marks negative time intervals which aren’t measured by TDC. White area of the plane can be used for TDC output calculation if coefficient k is set to a different value, e.g. if k is set to 15, green area in first diagonal would extend to 15, recalculated values of second diagonal would be equal from 16 to 30, values of third diagonal – from 31 to 45, etc. One of the main tasks in 2D Vernier TDC, which is based on gated ring oscillators, is output decoding. The out- put of arbiter will change to high logic level when arbi- ter’s input, connected to GROH stage, will be high and M. Jurgo et al; Informacije Midem, Vol. 47, No. 4(2017), 223 – 231 227 input, connected to GROL stage, is low. Since arbiters in 2D structure are connected between all stages of both gated ring oscillators, even first rising edge of GROH will trigger one or two arbiters. It happens because in three-stage ring oscillator, at any given moment the output signal of one or two inverters is low (it can be seen in Fig. 8, provided in next section). For this rea- son, such TDC can’t measure time intervals lower than k using 2D structure and it is needed to evaluate if the output of arbiter is valid. E.g. in our example, if input time interval is lower or equal to 10, arbiter connected between first stage of GROH and second stage of GROL will become high with first GROH edge, since it will al- ways lead second edge of GROL and output of TDC will be incorrectly set to 11 (X = 2, Y = 1 position in Fig. 6). This issue is solved by saving the state of arbiters after first GROH edge, which corresponds to GROLE in Fig. 6. This value, combined with lap count of GROL, will give total number of propagated GROL stages – coordinate X. After that checking is done in 1D Vernier manner: go- ing diagonally up in Vernier plane, but only in diagonal, which is starting at coordinate X. As discussed earlier, value of the coefficient k should meet equation (1). Coefficient k shows, that the total delay of k-1 stages of the lower frequency oscillator should be equal to the total delay of k stages of the higher frequency oscillator. Therefore, stage counters of the both oscillators can be employed to set needed value of the coefficient k. Following guidelines can be used to set the values of coefficient k and number of turned on oscillator’s sec- tions (NOSC) for both oscillators. At the beginning (e.g. after power-on of the chip) NOSC for higher frequency oscillator can be set to highest available value NOSCH, since, as it will be seen in the following section, fre- quency step, which corresponds to the resolution of TDC, is smaller at highest values of NOSC, and NOSC for lower frequency oscillator can be set to NOSCH-1. After that both oscillators should be enabled and counters should count through how many stages of each oscil- lator signal has propagated. When value of stage coun- ter of higher stage oscillator reaches targeted value of k, stage count of lower frequency oscillator should be checked: - if it is equal to k-1, correct values of NOSC are set for both oscillators; - if it is equal to k – tuning step is too small for cur- rent value of coefficient k. Value of NOSC for lower frequency oscillator should be decreased by one and measurement should be repeated. After that, if value of the counter drops to k-2, NOSC for higher frequency oscillator should be decreased by one and measurement should be repeated. Also, coef- ficient k can be increased, since, as it can be seen from equation (1), higher k value is needed for lower tuning step when value of stage delay is constant. - if it is equal to k-2 – tuning step is too large for cur- rent value of k. coefficient k should be decreased and measurement should be repeated. After initial settings, measurement can be repeated for longer period of time, to validate correct values e.g. count to 4×k higher frequency oscillator’s stages and check if count of lower frequency oscillator’s stages is equal to 4×(k-1). Additional fine-tuning can be done by using technique, described in [8] which takes advantage of the irregular- ity in automatic place-and-route, when different sec- tions of the oscillator have different effective driving strength, resulting in different tuning step. i.e. same number of the enabled oscillator’s sections can result in different stage delay, depending on the position in chip layout of the sections. It should be noted, that incorrect value of k will intro- duce nonlinearity when TDC is operating in 2D Vernier mode i.e. measuring large input time intervals. When input time intervals are small and TDC is operating in 1D Vernier manner, value of the coefficient k has no ef- fect for it. Another advantage of 2D Vernier TDC is faster calcula- tion of output signal, compared to 1D structure. The time duration to calculate the output of proposed TDC can be expressed as: IN 2 OUT2D IN 2T T T k+ τ ≤ ≤ + ⋅ τ (3) where TIN – TDC’s input time interval. M. Jurgo et al; Informacije Midem, Vol. 47, No. 4(2017), 223 – 231 Figure 6: Calculated plane of TDC’s output time samples, when τ1 = 10 ps, τ2 = 9 ps, k = 10 228 As it can be seen from equation (3), the time duration of TDC’s output signal calculation depends nonlinearly on input time interval. Maximal time duration to calcu- late output signal of TDC is equal to TIN + k∙τ2, i.e. after receiving the rising edge of DCO signal, it has to propa- gate through k stages of higher frequency gated ring oscillator. The output of 1D Vernier TDC is calculated after: IN OUT1D IN 1 TT T= + ⋅ τ ∆ (4) Output calculation time dependency on input time interval, when 2D and 1D TDC structure is used, is shown in Fig. 7. If τ1 = 10 ps, τ2 = 9 ps and TDC input time interval is 21 ps, from equations (3) and (4) it can be seen that TDC output will be calculated after 30 ps, when proposed TDC is used, and it will take 231 ps to calculate the output signal, if 1D Vernier TDC is used. Such long interval in latter case is obtained, because arbiters in 1D Vernier TDC are comparing signals only after respectful stages of ring oscillator (or delay line). After each stage, time interval between edges of reference and DCO output signals is reduced by Δ ps. Therefore, after receiving rising edge of DCO signal, it has to travel TIN/Δ stages, to catch up with the edge of reference signals. Figure 7: Output calculation time dependency on input time interval of proposed 2D time to digital converter and 1D Vernier time to digital converter 4 Modeling results Functional modelling of TDC, implemented in VHDL hardware description language, was done using ModelSim environment. Figure 8 shows the results of functional modelling and main signals of TDC, when τ1 and τ2 are respectfully set to 10 ps and 9 ps. As it can be seen, when input time interval is equal to 8 ps, the output of TDC is calculated when eighth edge of higher frequency oscillator outruns eighth edge of lower frequency oscillator. When input time interval is equal to 32 ps, the output of TDC is calculated when second edge of higher frequency oscillator outruns fifth edge of lower frequency oscillator. These results correspond to data in Vernier plane, shown in Fig. 6. TDC was synthesized, placed and routed in 65 nm CMOS technology using Cadence software. 48 parallel GRO sections were used to form both oscillators used in TDC. It is hard to model oscillators and their tuning using digital IC design tools. Therefore, additional post-layout transient simulations of synthesized oscillators were made using analog design approach to investigate its frequency and stage delays dependency on enabled number of GRO sections. Simulations were made in three conditions: - Typical: typical process corner, 1.2 V supply volt- age, 40 °C temperature; - Worst: slow process corner, 1.1 V supply voltage, 80 °C temperature; - Best: fast process corner, 1.3  V supply voltage, -40 °C temperature; Simulation results of frequency FOSC dependency on number of turned on oscillator’s sections NOSC is shown in Figure 9 and corresponding stage delay τ is shown in Figure 10. Figure 8: Time to digital conterver’s functional modeling results, when input time interval is equal to 8 ps (a) and 32 ps (b) M. Jurgo et al; Informacije Midem, Vol. 47, No. 4(2017), 223 – 231 229 of coefficient k at different values of temperature (e.g. at 25 °C and 65 °C), tuning technique from [8], which was mentioned earlier, can be used. The frequency of GRO can be tuned from 0.68 GHz to 3.38 GHz in typical conditions, from 0.70 to 2.10 GHz in worst conditions, from 0.68 GHz to 4.93 GHz in best conditions. At least 3, 6 and 2 sections of oscillator need to be enabled respectfully in typical, worst and best condition for oscillator to start. Delay of single stage can be changed from 491 ps to 98 ps in typical conditions, from 479 ps to 158 ps in worst conditions and from 491 ps to 67 ps in best conditions. As it can be seen, dependency of frequency and stage delay on turned on number of oscillator sections is nonlinear, similar to hyperbolic. Its slope is higher at low values of NOSC and lower at higher values of NOSC. Therefore, to achieve higher resolution of Vernier TDC, higher numbers of NOSC should be used, where steps of oscillator’s frequency and stage delay are smaller, since step of stage delay Δ = τ(NOSC-1) - τ(NOSC) corresponds to the resolution of TDC if NOSC sections are enabled in higher frequency oscillator and NOSC-1 sections are enabled in lower frequency oscillator. Figure 11: Step of oscillator’s stage delay when number of enabled oscillator’s sections changes from 22 to 48 Table 1: TDC’s performance comparison to other works Reference Structure Technology Resolution, ps Supply, V Current, mA Area, mm2 Synthesised This work 2D Vernier GRO 65 nm 3.2-0.8 1.2 3.0 0.008 (core); 0.018 (full) Yes [1] Delay line 65 nm 10-30 1.2 N/A N/A No [2] Three-step 0.13 µm 1 1.2 2.9 N/A No [3] Two-step 0.13 µm 4 1.2 3.7 0.028 No [5] 2D Vernier delay line 65 nm 4.8 1.2 1.42 0.02 (core) No [6] 2D Vernier GRO 90 nm 2.2 1.0 2.3 0.068 No [7] Stochastic 0.13 µm 0.7 1.2 2.25 0.11 No [8] 1D Vernier GRO 65 nm 5.5 1.0 1.4 0.006 Yes [9] 1D Vernier GRO 90 nm 3.2 1.2 3.0 0.027 No Figure 10: Dependency of stage delay τ on number of turned on oscillator’s sections NOSC M. Jurgo et al; Informacije Midem, Vol. 47, No. 4(2017), 223 – 231 Figure 9: Dependency of frequency FOSC on number of turned on oscillator’s sections NOSC As it can be seen from Fig. 9 and Fig. 10, the stage de- lay changes depending on working conditions (process, voltage, temperature). Although in the 1D and 2D Vernier operation the difference of time delay is more important than the absolute value of stage delay, to compensate variation of the stage delay and to maintain same value 230 Recalculated step of oscillator’s stage delay in close to linear fragment of Figure 10, when NOSC changes from 22 to 48, is shown in Figure 11. In this part step of stage delay changes from 3.2 ps to 0.8 ps in typical conditions, from 4.0 ps to 1.1 ps in worst conditions and from 1.8 ps to 0.5 ps in best conditions. It should be noted, that the correct value of coefficient k should be set to meet the requirements of equation (1) as it was described in the previous section. Summary of TDC’s parameters and comparison to other works is presented in Table 1. 5 Layout Layout of proposed time to digital converter, synthesized in 65nm CMOS technology is shown in Figure 12. The core of TDC occupies 75 µm × 100.8 µm space of silicon, total area of TDC including power rings is 123 µm × 148.8 µm. Figure 12: Layout of proposed time to digital converter 6 Conclusions In this paper, synthesizable 2D Vernier time to digital converter (TDC) based on two gated ring oscillators and its control algorithm was proposed. Such TDC can measure sub-inverter delay time intervals and its re- sult is calculated faster, compared to 1D Vernier TDC. Proposed TDC is implemented using VHDL hardware description language, therefore it can be easily migrat- ed to various technology nodes. It was synthesized, placed and routed in 65 nm CMOS technology. Main blocks of TDC are two oscillators, made of parallel- connected three stage gated ring oscillators (GRO), their lap and edge counters, arbiter matrix, decoder and con- trol block. Frequency of oscillators and corresponding de- lay time of single stage are controlled by changing num- ber of enabled GROs. To reduce metastability window of arbiters, they are composed of SR latches and D flip-flops. Tuning step of single stage delay of gated ring oscilla- tor, which is equal to the resolution of TDC, ranges from 3.2 ps to 0.8 ps at nominal conditions, when number of enabled oscillator’s sections is changed from 22 to 48. Total area of silicon occupied by time to digital converter, including power rings, is equal to 123 µm × 148,8 µm. 7 Acknowledgment The authors are grateful to the Research Council of Lithuania for partly supporting this work under grant DOTSUT-235 for project Nr. 01.2.2-LMT-K-718-01-0054 . 8 References 1. R. B. Staszewski, K. Waheed, F. Dulger, and O. E. Eliezer, “Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2904–2919, Dec. 2011. https://doi.org/10.1109/JSSC.2011.2162769 2. Y. G. Pu, A. S. Park, J. S. Park, and K. Y. Lee, “Low- power, all digital phase-locked loop with a wide- range, high resolution TDC” ETRI J., vol. 33, no. 3, pp. 366–373, 2011. http://dx.doi.org/10.4218/ etrij.11.0110.0295 3. A. Samarah and A. C. Carusone, “A digital phase- locked loop with calibrated coarse and stochastic fine TDC” IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1829–1841, 2013. https://doi.org/10.1109/ JSSC.2013.2259031 4. P. Dudek, S. Szczepański, and J. V. Hatfield, “A high-resolution CMOS time-to-digital con- verter utilizing a Vernier delay line” IEEE J. Solid- State Circuits, vol. 35, no. 2, pp. 240–247, 2000. https://doi.org/10.1109/4.823449 5. L. Vercesi, A. Liscidini, and R. Castello, “Two-di- mensions vernier time-to-digital converter” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1504–1512, 2010. https://doi.org/10.1109/JSSC.2010.2047435 M. Jurgo et al; Informacije Midem, Vol. 47, No. 4(2017), 223 – 231 231 6. P. Lu, Y. Wu, and P. Andreani, “A 2.2-ps Two-Dimen- sional Gated-Vernier Time-to-Digital Converter with Digital Calibration” IEEE Trans. Circuits Syst. II Express Briefs, vol. 63, no. 11, pp. 1019–1023, 2016. https://doi.org/10.1109/TCSII.2016.2548218 7. V. Kratyuk, P. K. K. Hanumolu, K. Ok, U.-K. M. U.- K. Moon, and K. Mayaram, “A Digital PLL With a Stochastic Time-to-Digital Converter” Cir- cuits Syst. I Regul. Pap. IEEE Trans., vol. 56, no. 8, pp. 1612–1621, 2009. https://doi.org/10.1109/ TCSI.2008.2010109 8. Y. Park and D. D. Wentzloff, “A cyclic vernier TDC for ADPLLs synthesized from a standard cell library” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 58, no. 7, pp. 1511–1517, 2011. https://doi.org/10.1109/ TCSI.2011.2158490 9. P. Lu, A. Liscidini, and P. Andreani, “A 3.6 mW, 90 nm CMOS gated-vernier time-to-digital convert- er with an equivalent resolution of 3.2 ps” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1626–1635, 2012. https://doi.org/10.1109/JSSC.2012.2191676 Arrived: 19. 06. 2017 Accepted: 12. 09. 2017 M. Jurgo et al; Informacije Midem, Vol. 47, No. 4(2017), 223 – 231 232 233 Original scientific paper  MIDEM Society A Meta-Heuristic Approach for Wavelength Assignment in Long-Haul Optical System R. Hemalatha, R. Mahalakshmi Department of EEE, Kumaraguru College of Technology, Coimbatore, India Abstract: Routing and Wavelength Assignment (RWA) problem is one of the optimization problems in optical networks. The aim is to minimize the blocking probability and the number of wavelengths used. The RWA problem can be solved by number of algorithms like Genetic Algorithm (GA), Ant Colony Optimization (ACO), etc. In the proposed research, Shuffled Frog Leaping Algorithm (SFLA) has been implemented in optical networks to solve the RWA problem. The optimization parameters considered are cost, number of wavelengths, hop count and blocking probability. The problem is analyzed for different wavelength assignment methods such as first fit, random, round robin, wavelength ordering and Four Wave Mixing (FWM) priority based wavelength assignment. Fitness function devised includes cost, number of wavelengths, hop count and setup time. The proposed SFLA algorithm has been compared with GA and is found to minimize the blocking probability, cost and computational complexity. Keywords: GA; RWA; SFLA; WDM Metahevrističen pristop določitve valovne dolžine optičnega sistema Long-Haul Izvleček: Osnoven problem optičnih omrežjih je njihova pot in določitev valovne dolžine (RWA). Namen je minimizacija verjetnosti združevanja in števila uporabljenih valovnih dolžin. RWA problem se lahko reši s številnimi algoritmi, kot so generičen algoritem (GA), Ant Colony optimizacija (ACO) in drugi. V predstavljeni raziskavi je bil uporabljen Shuffled Frog Leaping Algoritem (SFLA). Parametri optimizacije so bili strošek, število valovnih dolžin ter število poskokov in verjetnost združevanja. Problem je bil analiziran za različne določitve valovnih dolžin, kot so prvi približek, naključnost, sistem vsak s vsakim, urejanje valovnih dolžin ter Four Wave Mixing (FWM) prednostna določitev valovne dolžine. Predlagan SFLA algoritem je bil primerjan z GA algoritmom. Izkazalo se je, da SFLA zmanjšuje verjetnost združevanja, strošek in kompleksnost računanja. Ključne besede: GA; RWA; SFLA; WDM * Corresponding Author’s e-mail: hemalatha.r.ece@kct.ac.in Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 4(2017), 233 – 240 1 Introduction In high capacity telecommunication networks, Optical networks play a major role. Routing, grooming and res- toration are the wavelength based services provided by optical networks. Fiber optics is to transmit data in the form of light. Electrically powered switching equip- ment such as a router or a switch aggregator is used in active optical system. It is used to regulate signal distri- bution and to direct the signals to different users. The switch controls the incoming and outgoing signals. Optical splitters are used to isolate and collect optical signals. The aim of optical communication systems is to transfer large amount of information with simple equipments (Batagelj 2014).Optical fiber communica- tion performs better in terms of transmission capacity and communication range (Vidmar 2001). An optical Wavelength Division Multiplexing (WDM) network is a network with fiber optic transmission links designed to utilize the features of fibers and WDM. Wavelength-division multiplexing meets the high bandwidth demand. Several routing and wavelength assignment problems that exist in optical wavelength division multiplexing are traffic grooming , optimal routing and wavelength assignment, survivability, Quality of service(QoS) routing and physical layer im- pairment aware (PLI aware) problems (Bhanjaa and Mahapatra 2013). A lightpath is an optical connection 234 between two nodes. Depending on the wavelength of the lightpaths, data are optically routed at intermedi- ate nodes (Le et al 2005 and Bisbal et al 2004). Con- ventional methods to solve these complex problems consume more computational time (Wang et al 2014 and Triay et al 2010). Multi-objective evolutionary algo- rithms based on swarm intelligence are used to solve the RWA problem, which are in real- world optical net- works (Kavian et al 2013 and Largo et al 2012). In the proposed method Shuffled Frog Leaping Algorithm is used to solve this problem. Similar algorithms available are either simple leading to poor performance or too complex to be used. The aim is to use computationally feasible algorithm for better network performance. In this research paper, routing and wavelength assign- ment problem model is described with two optimiza- tion algorithms, genetic algorithm and shuffled frog leaping algorithm. Genetic Algorithm is used to solve many problems in variety of fields and hence compari- son of SFLA is done with this algorithm. The discussions include simulation results, analysis, conclusions of the study and possible future work. 2 Routing and wavelength assignment problem 2.1 Problem Definition In dynamic routing and wavelength assignment, the lightpath requests arrive dynamically. A lightpath in a network is the path that satisfies the wavelength con- tinuity constraint (that is, same wavelength should be used by the l ightpath on all the links i n its path). For each lightpath request, source node, destina- tion node and holding time are defined. Holding time is the time during which a lightpath and the associated resources remain occupied. The resources become free, when the holding time elapses and can support other lightpath requests. Fig.1 shows the model to solve the RWA problem (Bhanjaa et al 2013). Figure1: Block diagram of optimization method 2.2 Network Model A network with N nodes can be modeled as a graph G(V,E), where V is the set of nodes denoting the routers or switches and E is the set of edges denoting connec- tivity between the nodes. The links between the nodes are assumed to be bidirectional. In dynamic routing and wavelength assignment problem, V is the set of nodes denoting routers or wireless routing networks and E is the set of fiber links denoting physical connec- tivity between the nodes. 2.3 Routing Model Routing and Wavelength Assignment (RWA) is one of the major problems in optical networking. The goal is to maximize the number of optical connection. A route and wavelength must be assigned for each connection request. Throughout the path, wavelength must be the same, unless the usage of wavelength converters is as- sumed. Two connections requests can share the same optical link, if different wavelength is provided (Bhan- jaa et al 2012). Fitness function to be maximized is given by 1 , ( ), ( 1) ( , ) 1 x x x x x k x i j x gx j gx j i j E j W W Wf H TC − + ∈ = = + + ∑∑ (1) Wx is free wavelength factor and takes the value of one, if same wavelength is available in all the links of path x or otherwise, zero. Summation in the first term de- fines the total link cost of the path and summation in the second term represents the total number of hops in the path. The variable Hxi,j is one, if link (i, j) is a part of path x and is zero otherwise. Variable Tx represents the set up time of path x. Variable Kx represents the length of the x-th chromosome or number of memeplexes. The route is optimal when the objective function maxi- mizes with the following constraints being satisfied. ( , ) ( , ) 1, if i=S, lp LPlp lpij ij i j E j i E I I ∈ ∈ − = ∈∑ ∑ (2) ( , ) ( , ) 1, if i=D, lp LPlp lpij ij i j E j i E I I ∈ ∈ − = − ∈∑ ∑ (3) ( , ) ( , ) 0, if i S, i D, lp LPlp lpij ij i j E j i E I I ∈ ∈ − = ≠ ≠ ∈∑ ∑ (4) ( , ) 1, if i D, lp LPlpij i j i j E I ≠ ∈ ≤ ≠ ∈∑ (5) ( , ) 0, if i=D, lp LPlpij i j i j E I ≠ ∈ = ∈∑ (6) R. Hemalatha et al; Informacije Midem, Vol. 47, No. 4(2017), 233 – 240 235 0 ( , ) , for t Tlpij i j E I h ∈ ≤ ≤∑ (7) 0 ( , ) ( 1), for t Tlpij i j E h I N ∈ < ≤ − >∑ (8) Equations (2) to (6) represent the flow conservation constraint. Equations (7) and (8) represent the hop count constraint. 2.4 Wavelength Assignment Model First fit and Random fit are the wavelength assignment techniques that are used generally. First Fit method de- cides the available wavelength with the lowest index while random fit method identifies the available wave- lengths and chooses randomly amongst them. O(w) is the complexity of both algorithms, where w is the number of wavelengths. First Fit outperforms Random Fit. Other wavelength assignment techniques used here are round robin technique, wavelength ordering technique and Four Wave Mixing aware wavelength as- signment technique. In FWM aware wavelength assign- ment technique, since the FWM crosstalk power will be more over the center of transmission window, priority is given to the wavelengths towards the edges of the transmission window. O(N3log2N) is the complexity of this method, where N is the number of nodes in the network. In the proposed fitness function, Wx the free wavelength factor is updated after the wavelength as- signment phase. In the wavelength assignment model, if the link (i, j) is used by the lightpath lp, the variable Iij lp assumes one else it assumes zero. Variable Iijw lp is the lightpath wavelength indicator. It shows whether the lightpath lp uses wavelength ‘W’ on link (i, j). Variable Iijw lp(x,y) is the lightpath wavelength link indicator and is one when the lightpath uses wavelength ‘W’ on link (i, j) between the nodes x and y. l(x,y) equals one if a physical link exists between the nodes x and y (Bhanjaa et al 2010). The wavelength continuity constraints are 1 0 , (i,j) W lp lp ij ijw w I I − = = ∀∑ (9) ( , ) , (i,j), (x,y), wlp x y lpijw ijwI I≤ ∀ ∀ ∀ , (10) ( , ) , 1, (x,y), wlp x yijw i j I ≤ ∀ ∀∑ (11) 1 1 ( , ) ( , ) ( , ) ( , ) 0 0 , y=j W W lp x y x y lp y x y x lp ijw ijw ij w x w x I l I l I − − = = − =∑∑ ∑∑ (12) 1 1 ( , ) ( , ) ( , ) ( , ) 0 0 , y=I W W lp x y x y lp y x y x lp ijw ijw ij w x w x I l I l I − − = = − = −∑∑ ∑∑ (13) 1 1 ( , ) ( , ) ( , ) ( , ) 0 0 0, y i, y j W W lp x y x y lp y x y x ijw ijw w x w x I l I l − − = = − = ≠ ≠∑∑ ∑∑ (14) 3 Optimization algorithms 3.1 Genetic Algorithm The methodology of Genetic Algorithm is shown in Fig.2. This method works iteratively on an initial solu- tion set which is referred to as population and con- verges to arrive on best solution (Kavian et al 2009). Figure 2: Flow diagram of GA 3.2 Representation of chromosome and Initialization of population Route or path encoded from source to destination is represented by a chromosome. A sequence of nodes creates each chromosome and is generated randomly satisfying the topology of particular network. The chro- mosomes are of variable length, each of which is the encoding of a path from the source node S to the des- tination node D. Random selection of solutions create R. Hemalatha et al; Informacije Midem, Vol. 47, No. 4(2017), 233 – 240 236 initial population. The initial population has only one chromosome. 3.3 Crossover and Mutation Crossover does not depend on the position of nodes in routing paths. One pair is randomly taken and the crossing site of each chromosome is identified by the locus of each node. The crossing points of two chromo- somes may be different from each other (Ahn and Ram- akrishna 2002). During mutation, the mutation site of the parent chromosome is chosen randomly. From the mutation site to the destination, different path chosen is based on the topology database. 3.4 Calculation of fitness function The fitness function is formulated as in equation (1) and is to evaluate the quality of the chromosomes. 3.5 Shuffled Frog Leaping Algorithm Shuffled Frog Leaping Algorithm (SFLA) is a natural inspired metaheuristic algorithm. Novelty of this al- gorithm is its fast convergence speed. It combines the advantages of the both the genetic-based memetic algorithm and the behavior-based Particle Swarm Op- timization (PSO) algorithm. In the SFLA, possible solu- tions are defined by a group of frogs which is referred to as population. These groups of frog are partitioned into several communities referred to as memeplexes. Each frog in the memeplexes perform local search. The behavior of individual frog is influenced by behaviors of other frogs within each memeplex and it develops through a process of memetic evolution. After a cer- tain number of memetic evolutions, the memeplexes are forced to mix together and through shuffling pro- cess, new memeplexes are formed. Until convergence criteria are satisfied, the local search and the shuffling processes continue. The flowchart of Shuffled frog leaping algorithm is illustrated in Fig.3 (Roshni et al 2016). The various steps are as follows: a) SFLA involves a population ‘P’ of possible solu- tion, defined by a group of virtual frogs(n). b) Frogs are sorted in descending order based on their fitness and partitioned into subsets called as memeplexes (m). c) Frog i is expressed as Xi = (Xi1, Xi2, …..Xin) where X represents number of variables. d) Frogs with worst and best fitness are identified as Xw and Xb within each memeplex. e) Frog with global best fitness is identified as Xg. f ) The frog with worst fitness is improved based on the following equation. Di=rand() (Xb -Xw) (15) Xneww=X oldw+ Di (16) Rand() is a random number in the range of [0,1] (Muzaf- far 2006). Figure 3: Flow diagram of SFLA R. Hemalatha et al; Informacije Midem, Vol. 47, No. 4(2017), 233 – 240 237 Di is the step size of i-th leaping frog and Dmax is the maximum step size allowed. If the fitness value of new Xw is better than the current one, Xw will be accepted. Otherwise, the calculated step size of leaping frog Di and new fitness Xneww are recomputed with Xb replaced by Xg. Further if no improvement is achieved, a new Xw is generated randomly. The update operation is repeat- ed for specific number of iterations. After a predefined number of memetic evolutionary steps within each memeplex, the solutions of evolved memeplexes are replaced into new population. This is called shuffling process. Global information exchange among the frogs is promoted by the shuffling process. The population is then sorted in order of decreasing performance values and updates the population based on best frog’s posi- tion, repartition the frog group into memeplexes and progress the evolution within each memeplex until the convergence criteria are satisfied (Samuel and Rajan 2014). 4 Simulation results The optimization algorithms have been carried out in MATLAB R2012b. Simulations are carried out for a 14 node network similar to NSFNET network topology with 21 bidirectional links. Fig.4 depicts the fitness of the genetic algorithm and shuffled frog leaping algo- rithm against the execution time. The fitness function involves cost, number of hops and holding time. Better fitness is achieved for a smaller execution time. Figure 4: Fitness function of GA and SFLA Fig.5 and 6 shows the variation in the blocking proba- bility assuming different values of adjacent wavelength rejection ratios for GA and SFLA respectively. In each case by executing the program several times and then by computing the average, mean blocking probability is estimated. In FWM aware priority based wavelength assignment, the mean blocking probability decreases for a reduction in each of the adjacent wavelength re- jection ratio. To reduce the FWM crosstalk equal and unequal channel spacing is also used which is said to be spectrum separation technique. The comlexity is lower in this technique. But the mean blocking prob- ability is lesser and fitness score is better in the dynam- ic wavelength allocation based on FWM aware based priority assignment that makes it advantageous to be used. Figure 5: Mean blocking probability for a fixed net- work load using GA Figure 6: Mean blocking probability for a fixed net- work load using SFLA Fig.7 shows the rate of convergence of genetic algo- rithm and shuffled frog leaping algorithm for first fit, random, round robin, wavelength ordering and FWM aware priority based wavelength assignment tech- niques. By randomly selecting an individual and fix- ing the best fitness value, the curves are plotted. The average fitness score decreases with increase in gen- erations. Average fitness score for GA and SFLA using different wavelength assignment techniques are ap- proximately the same. FWM priority based assignment has higher average fitness score. R. Hemalatha et al; Informacije Midem, Vol. 47, No. 4(2017), 233 – 240 238 Figure 7: Average fitness score for GA and SFLA The mean execution time of the five wavelength as- signment techniques for different network load in Er- lang using GA and SFLA are in Table 1. FWM aware pri- ority based wavelength assignment technique has the least mean execution time for different network loads in both the algorithms. However, the mean execution time is minimum using SFLA compared to GA. The experimental results in Table 2 show that wave- length ordering and round robin exhibits less mean blocking probability with respect to channel rejection ratio and number of generations respectively. Average fitness score is higher and the mean execution time is minimum in FWM aware priority based wavelength assignment technique. Comparing Genetic Algorithm and Shuffled Frog Leap Algorithm, Shuffled Frog Leap Algorithm achieves least mean blocking probability and a mean execution time for different wavelength as- signment techniques such as First Fit, Random, Round Robin, Wavelength Ordering and FWM aware priority based wavelength assignment though the average fit- ness score is approximately same for both the algo- rithms. 5 Conclusions Routing and Wavelength Assignment (RWA) problem is one of the most complex optimization problems in optical networks. In the proposed work, Genetic Algo- Table 1: Mean Execution Time of different wavelength assignment techniques using GA and SFLA Wavelength As- signment Tech- niques Mean Execution Time (w.r.to network load(Erlang)) using GA Mean Execution Time (w.r.to network load(Erlang)) using SFLA 0 1.4 2.7 3.6 4.4 0 1.4 2.7 3.6 4.4 First Fit 0.1200 0.0432 0.0689 0.1038 0.1019 0.1191 0.0423 0.0654 0.1018 0.1003 Random 0.3000 0.2372 0.2328 0.3155 0.3762 0.2987 0.2372 0.2328 0.3155 0.3762 Round Robin 0.1200 0.1736 0.1613 0.2004 0.2251 0.1198 0.1703 0.1610 0.2001 0.2248 Wavelength Ordering 0.0500 0.0062 0.0123 0.0302 0.0415 0.0490 0.0059 0.00117 0.0295 0.0409 FWM priority based Assignment 0.0050 4.275e-11 8.509e-11 2.1167e-10 2.94e-10 0.038 4.257e-11 8.503e-11 2.1068e-10 2.85e-10 Table 2: Comparison of GA and SFLA for different wavelength assignment techniques Wavelength Assignment Techniques GA SFLA Mean Blocking Probabil- ity (w.r.to channel rejection ratio) Average fitness score Mean Block- ing Probabil- ity (w.r.to no. of genera- tions) Mean Execution Time Mean Blocking Probability (w.r.to chan- nel rejection ratio) Average fitness score Mean Block- ing Probabil- ity (w.r.to no. of genera- tions) Mean Execution Time First Fit 0.8910 2.1184 0.5176 0.0829 0.8899 2.1184 0.4508 0.008025 Random 0.7875 0.6087 0.6035 0.2711 0.7802 0.6087 0.5805 0.2709 Round Robin 0.5225 1.023 0.2018 0.1619 0.1009 1.023 0.0010 0.1618 Wavelength Ordering 0.0959 0.08175 - 0.0266 0.0947 0.08175 - 0.0256 FWM based Assignment - 12.481 - 0.00070 - 12.481 - 0.00067 R. Hemalatha et al; Informacije Midem, Vol. 47, No. 4(2017), 233 – 240 239 rithm and Shuffled Frog Leaping Algorithm are used to solve this problem. The fitness function minimizes the cost, number of hops and blocking probability. Five different wavelength assignment techniques such as first fit, random, round robin, wavelength ordering and FWM aware priority based wavelength assignment are used while evaluating the performance of GA and SFLA. In SFLA, better fitness value is achieved compared to GA. Among different wavelength assignment tech- niques, FWM aware priority based wavelength as- signment technique gives maximum average fitness score and least mean execution time. Comparing these optimization algorithms, SFLA is better than GA with minimum mean blocking probability, less mean execu- tion time and better fitness value. SFLA approach has a lower time complexity compared to Genetic Algorithm and hence the proposed scheme may provide certain degree of flexibility in the network design. 6 References 1. A. Adhya and D. Datta, 2009. Design methodol- ogy for WDM backbone networks using FWM- aware heuristic algorithm. Optical Switching and Networking, 6: 10–19. 2. C. W. Ahn and R. S. Ramakrishna, 2002. A genetic algorithm for shortest path routing problem and the sizing of populations. IEEE Transactions on Evolutionary Computation, 6: 566–579. 3. A´ lvaro Rubio-Largo, Miguel A. Vega- Rodriguez, Juan A. Gomez-Pulido and Juan M. Sanchez- Pe´rez, 2012. A Comparative Study on Multi ob- jective Swarm Intelligence for the Routing and Wavelength Assignment Problem. IEEE Transac- tions on systems, man, and cybernetics , 4: 1644– 1655. 4. David Bisbal, Ignacio de Miguel and Fernando Gonzalez, 2004. Dynamic Routing and Wave- length Assignment in Optical Networks by Means of Genetic Algorithm. Photonic Network Commu- nications, pp: 43-58. 5. G. Giftson Samuel and C. Christober Asir Rajan, 2014. A Modified Shuffled Frog Leaping Algo- rithm for Long-Term Generation Maintenance Scheduling. Springer, 258: 11-24. 6. Joan Triay and Cristina Cervello-Pastor, 2010. An Ant-Based Algorithm for Distributed Routing and Wavelength Assignment in Dynamic Optical Net- works. IEEE journal on selected areas in communi- cations , 28: 542-552. 7. V. T. Le, X. Jiang, S. H. Ngo and S. Horiguchi, 2005. Dynamic RWA Based on the Combination of Mo- bile Agents Technique and Genetic Algorithms in WDM Networks with Sparse Wavelength Conver- sion. IEICE Transactions on Information and Sys- tems, 9: 2067-2078. 8. Muzaffar, Kevin and Fayzul Pasha, 2006. Shuffled frog-leaping algorithm: a memetic meta-heuristic for discrete optimization. Engineering Optimiza- tion, 38, 2: 129–154. 9. R. Ramaswami and K.N. Sivarajan, 2000. Optical Networks: A Practical Perspective. Morgan Kauf- mann Publishers, San Francisco. 10. D. Srinath and J. Janet, 2013. Secured Ant Colony Optimization Routing for Wireless Network. Asian Journal of Information Technology, 12: 83-90. 11. Urmila Bhanjaa, Sudipta Mahapatra and Rajar- shi Roy, 2010. A novel solution to the dynamic routing and wavelength assignment problem in transparent optical networks. International Jour- nal of Computer Networks and Communications, 2: 119-130. 12. Urmila Bhanjaa, Sudipta Mahapatra and Rajarshi Roy, 2012. FWM aware evolutionary program- ming algorithm for transparent optical networks. Photonic Network Communications, 3: 285-299. 13. Urmila Bhanjaa and Sudipta Mahapatra, 2013. A metaheuristic approach for optical network op- timization problems. Elsevier-Applied Soft Com- puting, 13: 981–997. 14. Urmila Bhanjaa, Sudipta Mahapatra and Rajarshi Roy, 2013. An evolutionary programming algo- rithm for survivable routing and wavelength as- signment in transparent optical networks. Elsevi- er-Information Sciences, 222: 634–647. 15. X. Wang, M. Brandt-Pearce, and S. Subramaniam, 2014. Distributed Grooming, Routing, and Wave- length Assignment for Dynamic Optical Networks Using Ant Colony Optimization. IEEE/OSA Journal of Optical Communications and Networks, 6: 578- 589. 16. Y. S. Kavian ,W. Ren , H. F. Rashvand, M. S. Leeson , M. Naderi and E. L. Hines, 2009. Genetic Algorithm for Designing DWDM Optical Networks under De- mand Uncertainty. Proceedings of ICTON Medi- terranean Winter Conference, December 10-12, 2009, Angers, pp: 1-4. 17. Yousef S. Kavian, Arash Rashedi, Ali Mahani and Zabih Ghassemlooy, 2013. Routing and wave- length assignment in optical networks using Ar- tificial Bee Colony algorithm. Elsevier-Optik, 124: 1243-1249. 18. Roshni. V. V, R. Hemalatha and R. Mahalakshmi, 2016. Optimization of Routing and Wavelength assignment in passive optical networks. Pak. J. of Biotechnology, Special issue on innovations in information embedded and communication sys- R. Hemalatha et al; Informacije Midem, Vol. 47, No. 4(2017), 233 – 240 240 tems, Vol. 13: 247-251. 19. B. Batagelj, V. Janyani and S. Tomazic, 2014. Re- search Challenges in optical communications to- wards 2020 and beyond. Informacije MIDEM, Vol. 44:177-184. 20. M. Vidmar, 2001. Optical-fiber communications: components and systems. Informacije MIDEM, Vol. 31:246-251. Arrived: 04. 07. 2017 Accepted: 03. 10. 2017 R. Hemalatha et al; Informacije Midem, Vol. 47, No. 4(2017), 233 – 240 241 Original scientific paper  MIDEM Society A New Low-Power CMOS Sample-and-Hold Circuit Based on High-Speed Dynamic Body Biased Switches Mohamad Hasan-Sagha and Mohsen Jalali Electrical Engineering Department, Shahed University, Tehran, Iran Abstract: In this paper, a low-power open-loop CMOS sample-and-hold (S/H) circuit with improved linearity is presented. The incorporated switches utilize dynamic body connection technique to reduce distortions due to threshold voltage variations during track mode as well as signal feedthrough in the hold mode. To accomplish dual-edge sampling characteristic and differential operation, the proposed S/H circuit utilizes two pairs of the proposed switch and a 2:1 multiplexer. A current mode logic multiplexer without tail current is utilized to reduce power consumption while still fulfilling the speed and linearity requirements. The proposed S/H circuit is designed in a 90-nm CMOS process where it consumes approximately 610 μW from a 1.2 V supply voltage. Post-layout results show that a SFDR of about 73 dB is achieved when sampling a 1 GHz differential sinusoidal input at 2 GS/s rate using both edges of a 1 GHz clock signal. Keywords: Sample and hold circuits; high-speed switches; body biasing; dual-edge sampling Novo vzorčevalno vezje nizke moči na osnovi hitrih dinamičnih stikal Izvleček: Članek opisuje odprtozančno CMS vzorčevalno vezje nizke porabe z izboljšano linearnostjo. Vgrajena stikala vnašajo dinamično povezovalno tehniko za zmanjševanje distorcij pri nihanju pragovne napetosti v načinu sledenja, kakor tudi prenos signala v stanju zadržanja. Za zagotaljanje dvorobne vzorčevalne karakteristike in diferencialnega delovanja sta v predlaganem vzorčevalnem S/H vezju uporabljena dva para stikal in 2:1 multiplekser. V tokovnem načinu je uporabljen logični multiplekser za zniževanje porabe energije, pri čemer se hitrost in linearnost ohranjata. Predlagano S/H vezje je načrtano v 90 nm CMOS tehnologiji in pri napajalni napetosti 1.2 V porabi okoli 610 μW. Rezultati izkazujejo 73 dB SFDR pri vzorčenju z 2 GS/s in difenecialni sinusni vzorčevalni frekvenci 1 GHz. Ključne besede: vzorčevalna vezja; stikala velikih hitrosti; dvorobno vzorčenje * Corresponding Author’s e-mail: mjalali@shahed.ac.ir. Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 4(2017), 241 – 246 1 Introduction High speed sample-and-hold (S/H) circuits have found many applications in emerging communication sys- tems such as software defined radio, direct RF sampling receivers and sub-sampling RF architectures [1-3]. The S/H circuits are substantially classified into two main groups of closed-loop and open-loop configurations. There is a main trade-off between linearity and speed in both types. Closed-loop S/Hs [4], [5] are more linear than open-loop counterparts while open-loop S/Hs [6-8], on the other hand, have relatively higher speed, less power consumption and less circuit complexity [7]. However, in very high speed applications, distortions imposed by embedded switches seriously limit their application. Charge injection and signal feedthrough, in the hold mode, beside threshold voltage variation due to body effect along with amplitude and phase distortion due to finite channel resistance, in the track mode, are blamed as the main sources of distortions [9], [10]. Transmission gates implemented by parallel connec- tion of PMOS and NMOS transistors are the simplest way to implement a CMOS switch. However, the un- equal turn-on and turn-off delays of PMOS and NMOS transistors makes them suitable only for applications with moderate precisions especially when fast switch- ing operation is required [11]. A vast varieties of boot- 242 M. Hasan-Sagha et al; Informacije Midem, Vol. 47, No. 4(2017), 241 – 246 strap switches have been reported as linear and high- precision switches [12-14]. However, due to their circuit complexity and thus relatively lower speeds, they are not applicable in high speed applications. In this paper, a low-power high-speed sample-and-hold (S/H) circuit is proposed which takes the advantage of dynamic body connection technique to improve the linearity and speed of the incorporated switches. The paper is organized as follows; Section 2 illustrates the operation and analysis of the employed CMOS switches in details and then illustrates the implementation of the pro- posed S/H circuit. The results and discussion are provid- ed in Section 3 followed by the conclusion in Section 4. Figure 1: A simple differential CMOS switch 2 Proposed S/H circuit Shown in Fig. 1, a simple differential switch can be re- alized using a pair of nMOS (or pMOS) transistors M1, M2 and holding capacitors CH1, CH2. When the switch is conducting (Clk=1), the transistors are in deep triode region and exhibit a channel resistance of: )( 1 thGSoxn ON VVSC R − = µ (1) where mn is the electron mobility, Cox is the gate-oxide capacitance, S denotes the transistor’s aspect ratio and VGS and Vth are gate-source voltage and threshold volt- age, respectively. Reducing both RON and CH results in better speed performance, however, a small CH will sig- nificantly increases the impact of signal feedthrough on the sampled values leaving RON as the main means for alleviating the speed constraints. The simple switch shown in Fig. 1 also imposes phase and amplitude dis- tortion during track mode mainly due to non-negligi- ble switch resistance which can be evaluated as ( ) ( ) ( ) ( )1 2 1 exp tan 1 out in V j j V j ω τω ω τω −= − + (2) where τ =RONCH is the switch time constant. Charge injection and clock feedthrough are other sources of distortion in CMOS switches. Methods such as differential design and using dummy transistor have been suggested [11] to mitigate these problems. How- ever, in the case of differential design, each side of the differential switch receives different input voltage, which causes unequal impact of charge injection and clock feedthrough on each side that cannot be totally removed in a common mode scheme. Moreover, pro- cess-related variations also worsen the problem so that charge injection and clock feedthrough always partial- ly impose inevitable residues at the output. a) b) Figure 2: (a) MOS switch with constant body bias, (b) Signal feedthrough via parasitic capacitances when the body is connected to the source. Shown in Fig. 2(a), to reduce the effects of non-ideali- ties, there is benefits to using body-biasing technique. It is well-known that by applying a bias voltage to the bulk terminal of a MOS transistor, the threshold voltage decreases, which according to (1) and (2), lightens the amplitude and phase distortion. Obviously, the body bias voltage, VB, should be applied to both switch tran- sistor (M1) and the dummy transistor (M2) as it should be noted that an appropriate value for VB, which allows for maximum input dynamic range with a symmetrical swing of at most 0.5 V, is the common-mode level of the input signal Vin. However, a problem which arises with applying a constant body bias to the bulk is that since the source-bulk voltage (Vsb) of switch transistor varies with Vin, its threshold voltage depends on the input signal, acting as a main cause of distortion. This problem can be solved by connecting the bulk termi- nal to the source instead of connecting it to a constant voltage of VB. Nonetheless, an advantage of applying a positive voltage to the bulk, in comparison to tying the bulk to the source, is preventing the input signal to leak 243 to the output through drain-bulk parasitic capacitance in the hold mode. To elaborate more on this issue, Fig. 2(b) schematically illustrates this problem indicating that the ratio of the leaked signal to the output is 1 1 out in H V C V C C = + (3) where C1 = CBD1+CBS2+CBD2 in which CBD and CBS are drain- bulk and source-bulk parasitic capacitances, respec- tively, so that subscripts 1 and 2 associate the param- eters to M1 and M2, respectively. The both mentioned problems of the threshold voltage variation of con- stant-body-biased switches and signal feedthrough of switches with their body connected to the source can be effectively solved using body-bias control circuit first introduced in [15], and modified and then called here as dynamic body bias (DBB) switch. Shown in Fig. 3, the M3 connects the body terminal of M1 to its source terminal during track mode thus preventing threshold voltage variation due to the body effect. During hold mode, M3 turns off disconnecting M1 body node from its source node avoiding signal feedthrough through drain-bulk parasitic capacitance. Figure 3: MOS switch with dynamic body connection technique. M3 connects the body nodes to the input to prevent distortion due to threshold voltage variation. To analyze the feedthrough issue in the proposed DBB switch during hold mode (Clk=0), Fig. 4(a) shows how a capacitive coupling path between input and output is constructed by the parasitic capacitances of the M1 and M2. The equivalent circuit of the parasitic path is shown in Fig. 4(b) where the amount of feedthrough can be expressed by ( ) ( ) 1 1 1 1 1 1 1 . . out BS in B H H BS BS V C C V C C C C C C C C = + + + + (4) Since CB and CH are sufficiently larger than CBS1 and C1, (4) simplifies to ( ) 1 1 1 out BS in B H V C C V C C C ≈ + (5) Comparing (5) with (3), the amount of feedthrough has been considerably reduced by a factor of CBS1/CB. The dual edge triggered S/H circuit is realized using a pair of the proposed switch in differential configura- tion and a 2:1 multiplexer (MUX) circuit as conceptu- ally illustrated in Fig. 5(a). The circuit is designed fully differential to improve its performance against com- mon-mode distortions as well as supply and substrate noises [16]. Fig. 5(b) depicts the schematic circuit of Figure 4: (a) The signal feedthrough via parasitic ca- pacitances of the proposed switch, (b) equivalent cir- cuit of the parasitic path. a) b) Figure 5: (a) The block diagram of the proposed dual- edge triggered S/H, (b) schematic circuit of the 2:1 CML MUX. a) b) M. Hasan-Sagha et al; Informacije Midem, Vol. 47, No. 4(2017), 241 – 246 244 the incorporated 2:1 MUX. A high-speed current mode logic (CML) MUX without any specific tail current is uti- lized. The reason is to reduce the number of stacked transistors allowing for higher output swing. The M1 and M2 operate as current switches working in deep tri- ode region (when turned on) with a small drain-source voltage. In addition, since higher voltage headroom is now available for M3-M6, their transconductances can be higher. In other words, we can reduce the sizes of these transistors while still having the same value of gm comparing to the case with a specific tail current. Thus, the parasitic capacitances are reduced resulting in an improved speed. Fig. 6(a) shows the structure of the proposed S/H cir- cuit. The operation of the circuit is as follows. On the ris- ing edge of the Clk, the switches B1 and B2 turn off pro- viding a sample of the input signal at their output. At the same time, the switches A1 and A2 are conducting and track the input signal. On the falling edge of the Clk, the input will be sampled by the switches A1 and A2. Thus, on each clock edges a sample of the input is provided and thus the 2:1 MUX can choose the samples on each proper switch output. The circuit implementa- tion of the proposed S/H circuit is shown in Fig. 6(b). Each differential switch is implemented using a pair of DBB switch where no explicit holding capacitor (i.e. CH and CB) is utilized. In fact, parasitic capacitances of the associated circuit nodes are sufficient for holding the samples over a short time. a) b) Figure 6: (a) The structure of the proposed S/H circuit, (b) The schematic circuit of the proposed dual-edge triggered S/H circuit. 3 Simulation results The proposed S/H circuit is implemented in a 90 nm CMOS process and post-layout simulations are carried out with a 1.2 V supply voltage while it consumes about 610 µW. To evaluate the performance of the switches, Fig. 7 compares the outputs of the switch with constant body bias (CBB) (shown in Fig. 2(a)) and the switch with dynamic body bias (DBB) (depicted in Fig. 3) when tak- ing samples from a 500 MHz sinusoidal input having 200 mV amplitude (over 0.5 V common mode level). Their sampled values include an error voltage of about 12 mV and 7.5 mV, respectively. The dynamic body bias switches offer higher speed and less distortion. Figure 7: Comparison of samples taken by constant body bias (CBB) and dynamic body bias (DBB) switches. Fig. 8 indicates the SFDR of the proposed S/H circuit em- ploying various switches, i.e. the simple switch (shown in Fig. 1) and the CBB and DBB switches, supposing a differential sinusoidal waveform with 0.2 V amplitude is applied to the inputs sampled at a rate of 2 GS/s. The SFDR at Nyquist rate when incorporating the proposed DBB switch is about 73 dB. If using CBB switch the SFDR drops to about 69 dB. For the sake of comparison, the SFDR if using simple nMOS switch is also shown that is about 48 dB. Obviously, the circuit that benefits from Figure 8: SFDR of the proposed S/H circuit versus input frequency incorporating different switches. M. Hasan-Sagha et al; Informacije Midem, Vol. 47, No. 4(2017), 241 – 246 245 proposed switch achieves better SFDR since threshold voltage variations are reduced. Table 1: Performance summary of the proposed dual edge triggered S/H circuit and its comparisons with some prior work Design This work Ref. 3 Ref. 6 Ref. 8 Ref. 5 Ref. 7 Technology 90 nm 90 nm 0.35 µm 0.18 µm 0.35 µm 0.18 µm 0.35 µm Sampling rate 2 GS/s ∼810 MS/s 250 MS/s 200 MS/s 400 MS/s 500 MS/s 250 MS/s Supply voltage 1.2 V 1.2 V _ 1.8 V 2 V _ _ Power consumption 610 µW - _ 12.5 mW 6.7 mW _ _ SFDR 73dB@ 1GHz 27.3dB* @ ∼20GHz _ 76dB@200MHz _ _ _ Configuration type Open-loop Open-loop Open- loop Open-loop Closed- loop Open- loop Open- loop The output of the circuit in response to a 1.25 GHz sinu- soidal input sampled at a rate of 5 GS/s is also shown in Fig.9. The delay from the clock edges to the time that the samples settle at the output implies that the whole circuit has less than 0.1 ns delay from input to the out- put. Table 1 shows the proposed S/H circuit perfor- mance summary and its comparison with other recent- ly published CMOS realizations. The circuit do not have static power consumption and the input switches are fully passive without extra power consumption caus- ing the overall circuit to operate with a lower power. The ability of the circuit to operate at a relatively high sampling rate mainly comes from appropriate MUX ar- chitecture and the optimized switches. Figure 9: Sampling a 1.25 GHz sinusoidal input at a rate of 5 GS/s using a 2.5 GHz clock signal. 4 Conclusion In this paper, a new architecture for open-loop S/H circuits was presented providing higher precision in sampling. The switches were optimized using dynamic body bias technique in order to reduce distortions. It utilizes a CML multiplexer at the output operating in a switching manner as a means for dual edge sampling. The proposed S/H has some advantages compared to other open-loop counterparts, such as low complexity, low-power operation and fully differential configura- tion. 5 References 1. R. Bagheri et al., “An 800-MHz–6-GHz Software- Defined Wireless Receiver in 90-nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2860-2876, Dec. 2006. 2. M. Motoyosh, T. Koizum, T. Maehata, S. Kameda and N. Suematsu, “High SNR CMOS S/H IC for mul- ti-carrier direct RF under sampling receiver,” 2016 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Taipei, 2016, pp. 1-3. 3. J. Cheng, N. Qi, P. Y. Chiang and A. Natarajan, “A Low-Power, Low-Voltage WBAN-Compatible Sub- Sampling PSK Receiver in 65 nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 3018-3030, Dec. 2014. 4. T. Koizumi et al., “A CMOS series/shunt switching type S/H IC for Ka-band direct RF under sam- pling receiver,” Asia-Pacific Microwave Conference (APMC), Nanjing, 2015, pp. 1-3. 5. T. S. Lee, C. C. Lu, S. H. Yu, and J. T. Zha, A very- high-speed low-power low-voltage fully-differen- tial CMOS sample-and-hold circuit with low hold pedestal, Proc. IEEE Int. Symp. Circuits and Systems (ISCAS) (2005), pp. 3111-3114. 6. M. Mousazadeh, K Hadidi, and A. Khoei, A novel open-loop high-speed CMOS sample-and-hold. AEU-Int. Journal of Electronics and Communica- tions. 62 (2008) 588-96. 7. K. D. Sadeghipour, A new passive sample and hold structure for high-speed, high-resolution ADCs. AEU-Int. Journal of Electronics and Commu- nications. 65 (2011) 799-805. M. Hasan-Sagha et al; Informacije Midem, Vol. 47, No. 4(2017), 241 – 246 246 8. A. Shirazi, S. Mirhaj, S. Ashtiani, and O. Shoaei, Lin- earity improvement of open-loop NMOS source- follower sample and hold circuits, IET Circuits, De- vices & Systems. 5 (2011) 1-7. 9. M. Hasan-Sagha, and M. Jalali, Very high speed and low voltage open-loop dual edge triggered sample and hold circuit in 0.18 µm CMOS technol- ogy, Proc. IEEE Int. Conf. Semiconductor Electronics (ICSE) (2012), pp. 645-648. 10. A. Boni, A. Pierazzi, and C. Morandi, A 10-b 185- MS/s track-and-hold in 0.35 µm CMOS, IEEE J. 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Yamashita, A 1-GHz, 56.3-dB SFDR CMOS track-and-hold cir- cuit with body-bias control circuit, Journal of IEICE Electronics Express 4 (2007) 701-706. 17. H. Movahedian, B. Sedighi and M. S. Bakhtiar, Wide-range single-ended CMOS track-and-hold circuit, Journal of IEICE Electronics Express 4 (2007) 400-405. Arrived: 18. 07. 2017 Accepted: 17. 10. 2017 M. Hasan-Sagha et al; Informacije Midem, Vol. 47, No. 4(2017), 241 – 246 247 Original scientific paper  MIDEM Society An Improved Low Phase Noise LC-VCO with Wide Frequency Tuning Range Used in CPPLL Xiaofeng Wang, Zhiyu Wang, Haoming Li, Rongqian Tian, Jiarui Liu, and Faxin Yu School of Aeronautics and Astronautics, Zhejiang University, Hangzhou, China Abstract: Based on TSMC 0.18μm CMOS process, a complementary cross-coupled differential LC voltage controlled oscillator (LC-VCO) used in charge pump phase-locked loop (CPPLL) frequency synthesizer for satellite receiver with low phase noise and wide frequency tuning range is designed and implemented. The VCO adopts self-bias structure to remove flicker noise produced by tail current. Programmable LC tanks are introduced at the common source of cross-couple transistors to eliminate second harmonics of resonant frequency. Distributed biasing is applied for a wider linear tuning range. An optimized switch is proposed to lower on-resistance. The measured results show that the VCO exhibits a 53.8% tuning range from 1.02GHz to 1.77GHz. From the carrier frequency of 1.4 GHz, the phase noise of the VCO can reach -131.2 dBc/Hz at 1MHz offset. The core circuit consumes 7.7mA with 1.8V supply voltage. Keywords: low phase noise; wide tuning range; distributed biasing; optimized switch Izboljšan LC-VCO z nizkim faznim šumom in širokim področjem nastavljanja frekvence za uporabo v PLL s črpalko nabojev Izvleček: Razvit in uporabljen je bil komplementarni sklopljen difencialni LC napetostno krmiljen oscilator (LC-VCO) za uporabo v frekvenčnem sintetizatorju s fazno-skelnjeno zanko (PLL) s črpalko nabojev, namenjen uporabi v satelitskih sprejemnikih z nizkim faznim šumom in širokim področjem nastavljanja frekvenc. Izveden je v TSMC 0.18 um CMOS tehnologiji. VCO uporablja samonapajalno strukturo za izničenje šuma 1/f, ki bi ga povzročal tokovni vir. Za izločanje drugega harmonika frekvence so uvedene nastavljive LC zapore na skupnem viru napajanja križno sklopljenih tranzistorjev. Za širšo območje nastavljanja je uporabljeno porazdeljeno napajanje uglaševalnih varaktorjev. Rezultati izkazujejo 53.8% nastavljivo območje VCOja med 1.02 GHz in 1.77 GHz. Pri nosilni frekvenci 1.4 GHz in odmiku 1 MHz lahko fazni šum VCO doseže -131.2 dBc/Hz. Pri napajalni napetosti 1.8 V jedro vezja porablja 7.7 mA.GHz. Ključne besede: nizek fazni šum; široko območje nastavljanja; porazdeljeno napajanje; optimizirano stikalo * Corresponding Author’s e-mail: jrliu@zju.edu.cn Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 4(2017), 247 – 253 1 Introduction Frequency modulation is widely used in communica- tion system especially for long distance communica- tion. A wide utilization of frequency synthesizer in the RF system makes it possible to generate an accurate frequency signal for frequency modulation [1]. In the RF system, noise produced by frequency synthesizer di- rectly deteriorates the overall noise performance of the system [2]. Meanwhile, the VCO is one of the major con- tributors of the out-of-band noise in a PLL frequency synthesizer [3]. Thus, to design a low phase noise VCO is necessary and significant for a high performance com- munication system, which is a challenge for us in con- sideration of tuning range, power consumption and other characteristics. With a mature understanding of phase noise mecha- nism [4]-[6], many attempts to optimize phase noise of VCO have been made in recent years. In reference [7], switchable cross-coupled pairs are used for lower transconductance and thereby improve 1/f 3 noise. However, as a result, the complexity of the timing logic is inevitably increased. In order to prevent the Q-factor degradation of resonant tanks in VCO, MOS switches 248 X. Wang et al; Informacije Midem, Vol. 47, No. 4(2017), 247 – 253 featuring high off-on resistance ratio (ROFF/RON) are used, and transistors with large gate width are intro- duced to achieve a sufficiently low RON. However, the COFF associated with such wide transistors will cause se- rious performance degradation [8, 9]. This paper introduce how VCO contribute phase noise to CPPLL, presents a complementary cross-coupled dif- ferential LC-VCO that can achieve low phase noise and large frequency tuning range. Self-bias structure is ap- plied to remove flicker noise produced by tail current. Programmable LC tanks are introduced at the source of cross-coupled transistors to eliminate second harmon- ics of resonant frequency. Distributed biasing is adopt- ed to widen the linear tuning range of every selected band. The switches used in the design have been op- timized to enhance the Q-factor. The presented VCO is fabricated using TSMC 0.18μm CMOS technology, measurement of which is performed for validation. 2 CPPLL noise analysis We choose CPPLL rather than others for its stability and larger acquisition range. A brief block diagram of the CPPLL is shown in Fig. 1. Phase/frequency detectors (PFD) sense phase and frequency differences between reference clock signal and output of divider. Charge pump sinks or sources current for a limited period of time according to the voltage produced by the pre- vious PFD. The loop filter (consisting of R1, C1 and C2) following CP produces voltage which controls VCO. The low dropout regulator (LDO) supplies for the VCO. The frequency divider (FD) between VCO output and PFD input makes a feed-back loop to ensure that out- put signal frequency is independent of process, supply voltage, temperature and other interferences. Figure 1: CPPLL block diagram. To formulate the CPPLL output phase noise contribut- ed by VCO, we need to derive the transfer function from the VCO phase to the CPPLL output phase. Although CPPLL is a nonlinear system, in the vicinity of lock state we can make a linear approximation in phase domain for intuitive understanding. A linear model is construct- ed in Fig. 2, where p 1 1 2 1 1// 2π I R sC sC  +   , VCOK s and 1 N repre- sent CP, VCO and FD respectively. Figure 2: Phase-domain linear model for deriving VCO’s effect on CPPLL phase noise In order to analyze VCO’s effect, we make Fin = 0 to signify that reference clock signal is noiseless. Starting from the output, we have: out p VCO 1 VCO out 1 2 1 1[ // ] = 2π I KR N sC sC s φ φ φ − + ⋅ +   (1) Equation （1） allows us to derive phase transfer func- tion from VCO to PLL output as : 1 23 2 out 1 1 2 1 2 p VCO p VCOVCO 3 2 1 1 2 2 1 1 2 (s) 1 1 2π 2π C Cs s R C C C C I K I Ks s s R C C N C N R C C φ φ ++ ⋅ = ++ ⋅ + ⋅ ⋅ + ⋅ (2) The transfer function contains two zeros at the origin and one zero near origin, three poles on the right of the zeros, exhibiting a high-pass behavior. The VCO phase noise is shaped by the transfer function. It can be proved that the phase noise out of loop bandwidth follows VCO’s phase noise [3]. Taking other noise sources (reference clock, PFD, CP, FD and etc.) into consideration, we can make a conclusion that PLL’s output phase noise measured at high offset frequencies is worse than VCO’s. 3 Circuit Design The theories to derive the phase noise of VCO have been researched for many years. Based on the deriva- tion in [10], the theory proposed by D.B. Leeson [4], which can make a qualitative prediction about the phase noise is described in equation (3): 32O{ } 10 log 1+ 1+ 1Hz [dBc/Hz] 2 2 f s L fFkTL P Q f ff f 1/    ∆    ∆ = ⋅ ⋅ ⋅ ⋅     ∆ ∆       (3) where F is the noise figure of the active device used under large signal conditions in this design, k is Boltz- mann’s constant in Joules/Kelvin, T is the temperature in Kelvin, Ps is the average power dissipated in the resis- tive part of the tank in Watt, fO is the carrier frequency 249 (Hz), QL is the effective quality factor of the tank, ∆f is the offset frequency (Hz) from the carrier and 3ff1/∆ is the frequency (Hz) of the corner between the 1/f3 and 1/f2 regions. The corner frequency of the semiconduc- tor process we used in the design is about 20 kHz, which means 3ff1/∆ is about 20 kHz. In this design, guided by equation (3), the LC-VCO with optimized phase noise is presented, the core schematic of which is shown in Fig. 3. Figure 3: The proposed VCO core schematic. There is no current source in the schematic, so the flick- er noise due to current source can be removed totally. A complementary cross-coupled structure is adopted rather than only a cross-coupled structure because the structure can produce twice the voltage swing for a given current and inductor design, which can reduce phase noise according to equation (3). The direct-cur- rent operating points are determined by diode-con- nected MOS transistors between power and ground provided by LDO which can reduce VCO’s sensitivity to supply voltage. MOS transistors here are used to work as negative resistor, cancelling loss in the LC tank due to parasitic resistance of inductor, capacitor and others. In this design, the parameters of PMOS and NMOS are set to produced symmetric output swing by simulation iteration operation for a given frequency range, which benefits phase noise optimization [11]. The parameter of main components in VCO is shown in Table 1. Table 1: Parameters of main components in VCO Components Parameter Value L1 Inductance[nH] 2.95 L2(L3) Inductance[nH] 1.69 Mn1(Mn2) W/L[μm/μm] 32*(2/0.2) Mp1(Mp2) W/L[μm/μm] 32*(6/0.2) There are two 7-bit binary-weighted switched capaci- tor arrays controlled by the same digital codes, D<6:0>, in the proposed topology. For a compromise of the linearity and layout area, the codes are implemented with a segmented architecture, in which the 2 LSBs are implemented using a binary architecture while the 5 MSBs are implemented in a unary way. The capacitor array in parallel with L1 is proposed to extend the tun- ing range instead of increasing VCO gain, which can realize coarse tuning. The other connected between nodes P and N is in parallel with L2 and L3, whose pur- pose is to compose a narrow band circuit for resonance at second harmonic, preventing the degradation of the Q-factor of the tank when the transistors operate in the triode region [12]. We choose programmable switched capacitors between nodes P and N rather than a fixed capacitor because we can choose appropriate resonant frequency according to the band selection. In order to perform the fine tuning of VCO with a wide linear range, distributed MOS varactor biasing is ap- plied [13].The varactor we used in the design is accu- mulation-mode MOS varactor, which is shown in Fig. 4 (a). This structure is obtained by placing an NMOS transistor inside an n-well. If VG,(b) PLL output phase noise measured at 700MHz, (c)phase noise per- formance across VCO frequency tuning range at 1-MHz offset a) b) c) 253 11. Y.H. Kao and M.T. Hsu, “Theoretical analysis of low phase noise design of CMOS VCO,” IEEE Microwave & Wireless Components Letters, vol.15, no.1, pp. 33- 35, 2005. 12. E. Hegazi, H. Sjoland, and A.A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, 2001. 13. J. Mira, et al. “Distributed MOS varactor biasing for VCO gain equalization in 0.13 μm CMOS technol- ogy,” IEEE Radio Frequency Integrated Circuits Sym- posium, pp. 131-134, 2004. 14. J. Kim, J.O. Plouchart, N. Zamdmer, et al., “A 44 GHz differentially tuned VCO with 4 GHz tuning range in 0.12 μm SOI CMOS,” IEEE Int Solid-State Circuits Conf, Dig Tech Papers, pp. 1-416, 2005. Arrived: 27. 07. 2017 Accepted: 06. 11. 2017 X. Wang et al; Informacije Midem, Vol. 47, No. 4(2017), 247 – 253 254 255 Original scientific paper  MIDEM Society Space transformer connector characterization for a wafer test system Bahadir Tunaboylu Istanbul Sehir University, Department of Industrial Engineering, Altunizade Mh., Uskudar- Istanbul, Turkey, Tubitak Marmara Research Center, Gebze, Kocaeli, Turkey Abstract: Standard connections from the probe head to the PCB for vertical type probe cards in wafer test are individual separate wires in space transformers (STs), traditionally used for device pitches 80 µm and above for quick turn inexpensive solutions compared to multilayer ceramic substrates. There are inherent signal integrity issues using separate wires in controlling impedance, bandwidth, and cross-talk of STs and probe cards. A method of wiring that includes parallel pairs and twisted pairs is proposed and electrical characterization was performed to establish predictive specifications on the test cards. Keywords: Semiconductor test; space transformers; paired-wiring schemes Karakterizacija konektorja prostorskega pretvornika za testni sitem silicijevih rezin Izvleček: V nasprotju s keramičnimi substrati se za razmake nad 80 µm uporablja poceni in hitre standardne priključke. Standardni priključek med glavo sonde in PCBjem vertikalnih sond pri testiranju silicijevih rezin predstavljajo ločene žičke in prostorski pretvorniki (ST). Uporaba posameznih žičk predstavlja problem inherentne integritete signala pri kontroli impedance, pasovne širine in presluha med ST in sondami. Predlagana je metoda povezovanja s prepletenimi paralelnimi pari. Opravljena je bila električna karakterizacija in napovedane specifikacije testnih kartic. Ključne besede: test polprevodnikov; prostorski pretvorniki; sheme parnega ožičenja * Corresponding Author’s e-mail: btunaboylu@sehir.edu.tr Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 4(2017), 255 – 259 1 Introduction In wafer test, main space transformers which provide connection between the probe head to the PCB in the test system include two common types. First one is typically wired space transformers (WST) and the sec- ond one is multilayer ceramic (MLC) or multilayer or- ganic (MLO) types. Although MLC or MLO type space transformers offer better signal integrity for the test system, there are lead time and cost issues affecting the first silicon arrival on test floor. Typical WSTs utilize individual and separate wires for signals or gnd/power lines and are simple to produce mechanically without requiring photolithography. It makes them inexpensive and allow for quick turn vertical probe cards for mainly testing area-array devices such as logic, SoC, and mi- croprocessors as the requirements for finer pitch, high- er densities and lower cost of test are accelerating [1-3]. Higher total pin counts above 1000 for area array con- figurations are more difficult to accommodate depend- ing on the designs compared to MLC type STs. It is difficult to manufacture a ST with separate-wire- method according to well defined bandwidth or cross- talk specifications for vertical probe cards since there are inherent signal integrity issues using separate indi- vidual wires in controlling impedance, bandwidth, and cross-talk. High-speed data transmission using twisted pair cables for transport of telecommunication services or computer networks have been used in the telecom field [4-5]. These type of cables constitute larger diam- eters with long distances (i.e. Cable lengths of 100 m). 256 B. Tunaboylu; Informacije Midem, Vol. 47, No. 4(2017), 255 – 259 In this study, we have designed these interconnections with new wiring schemes and applied them on con- ventional space transformers where there is only one guide plate mounted on a PCB. We have experimentally measured the electrical characteristics of these wiring schemes on conventional or wired space transformers (WST). We have proposed earlier the interconnection and wiring schemes in a patent (US 8,430,676 B2) [6] and however, no measurement data was provided in the patent. The space transformer designs proposed were modular type which were different compared to electrical connection assembly of WSTs. In the patent, both parallel-pair or twisted wiring schemes were de- signed to apply to modular space transformers where there are two guide plates and wiring distances are much shorter, typically less than 20 mm, since spring pin contacts were (Fig 1D and 1E) also used. The top plate had spring pins inserted to mounting holes. The wire ends were connected via several means to the bottom ends of the pin springs inside an aperture. However, wire lengths required for WSTs are typically much higher from the guide plates to the solder con- nection pads on PCBs. This study provides actual ex- perimental measurements on WSTs for the first time using paired wiring schemes to improve their electrical performance. In this investigation, we propose a simple method of wiring that includes parallel and twisted pairs to im- prove performance and establish reliable ST specifica- tions for semiconductor test system environment. The electrical characterization was performed on the test cards. 2 Design of wired ST and test prototypes Fig. 1a shows a probe card showing a mechanical as- sembly of a probe-head (PH), wired space transformer and PCB (printed circuit board). It shows wire connec- tion starting from PH side all the way to PCB sites. A probe card with a PH with probes, MLC and an inter- poser structure making connection to PCB is shown in Fig. 1b. A test vehicle was designed and manufactured to char- acterize the bandwidth and cross-talk for three main vertical probe types corresponding to three different wire diameters, 50µm, 95µm, and 135µm. Wires are made of copper conductors. Bandwidth tests for wires corresponding to 2, 3, 4-mil probes according to wiring configuration which represents the parallel wire and the twisted wire. Crosstalk tests were designed with 3-mil probe configured ST wires according to new wir- ing configuration: parallel wire and twisted wire pairs. Standard ST electrical performance is not very predict- able and the bandwidth is typically limited to 350 MHz and variable crosstalk values were observed based on simulations and characterizations done previously [3, 7]. The wire separation distances may vary greatly de- pending on the manufacturing process. We assume 10 mm to 15 mm in our studies for standard wiring. With newer configurations of wire connectors proposed, it will be possible to establish the specifications of the bandwidth and the crosstalk for both twisted wire vs parallel wire pairs for WST. The wire length for the ex- periments was fixed to 60 mm for all samples. Fig. 2 il- lustrates samples prepared for WST used in RF testing for bandwidth (50µm, 95µm, and 135µm wire pairs) tests on the left and for crosstalk tests for wire pairs for 135µm on the right. Parallel pairs were also inserted in a sleeve for better control of distances on separate wires. Distances between pairs were kept to 1 mm. The measurement of S parameters was carried out us- ing network analyzer, HP8722D, on a Gigatest GTL3030 probe station using Model Pico probes with appropri- ate pitch for contacting probe tips. Time domain re- flectometry (TDR) measurements were also done to observe impedance variations in the same setup. Figure 1: Illustrations of cross-sections of cards with two configurations; a) Probe card showing probe-head (PH) and wired space transformer; b) Probe card with PH, MLC and interposer structure a) b) 257 Figure 2: Wire configurations for test vehicle; a) Sam- ples for bandwidth tests; b) Samples for crosstalk tests Both parallel and twisted paired wiring and the stand- ard wiring in ST were built in a similar fashion and the wire still must travel through the PCB and over me- chanicals. For simplicity, only critical and high speed lines were paired on the ST to keep manufacturing cy- cle short and achieve optimum performance. The de- sign of device and pin configurations, location of signal and return paths, is important to establish GNDS on either side of the critical signal for a given test system. On probe heads, the characteristic impedance and the bandwidth are mainly dependent on the electrical pitch since we can assume relatively short probes (< 4 mm in total length) are used compared to much longer wires in ST. The electrical signal-return path and pitch of the test system may not be the same as the device pitch, because other forward and return path probes can be utilized. It is critical to determine forward and return current paths in the design cycle of STs. Simu- lations indicated that speeds up to 10 GHz are possi- ble for 2 or 3 mil-dia probes for their minimum allow- able pitch configurations. However, this performance is not achieved for wired STs because the length of wires needed is much longer and it is difficult to con- trol separation distance along the wire connection. So for a test system, we can ignore the PH for test speed requirements of 1 GHz, the critical components of the assembly become the space transformer and its con- nection to the PCB. Table 1: Bandwidth measurements on the test vehicle with three different wire types and configurations for STs. Configuration/ Wire Diameter 1 cm sep- aration 1 mm sep- aration Parallel pair Twisted pair 50 µm 100 MHz 180 MHz 640 MHz 3 GHz 95 µm 50 MHz 230 MHz 1.45 GHz 1.29 GHz 135 µm 100 MHz 270 MHz 1.65 GHz 1.27 GHz 3 Results Table 1 summarizes the findings for three different di- ameters of wires for STs. For 4-mil probes (135µm wire ST configuration), results are very close to simulation results done earlier. As expected at 10mm wire separa- tion, the bandwidth is measured close to 100 MHz at – 3 dB. It indicates that at 1mm separation, the band- width rises to 270 MHz at – 3 dB. When the parallel pair inside sleeve version is tested for the same wire diam- eter, it is good up to 1.6 GHz at – 3 dB. The bandwidth for the twisted pair is close to that of parallel pair, but it has little bit less bandwidth, 1.3 GHz at – 3 dB. This may be due to the fact that the twisted-pair wire separation is too close and there are variations along the length. A difference on the bandwidth is not expected between the twisted-wire versus the straight-wire on the meas- urements. The difference may be created if the twist- ed wire length is more than the straight wire length. The measured length of the wires on probe card was 60 mm on average. It is expected that the twisting of wire will provide crosstalk performance improvement since the induced voltage from different segments of the wire cancels out. For this type of wire layout with a. Bandwidth test b. Crosstalk test B. Tunaboylu; Informacije Midem, Vol. 47, No. 4(2017), 255 – 259 258 1mm distance, the crosstalk is less than 30 dB (Fig. 3). To prevent serious crosstalk problems, the wire pairs should be close to each other. It is typically assumed that the distance between the two wires (ground and signal) is kept same along the 60 mm wire connection. In reality however, this is not the case for the end con- nections, especially for the ground connections near the probe-head side. The variation in the separation distance between the ground and the signal wire on main body of wires can introduce serious bandwidth performance issues. As a general rule, the wire diameter is not the main source of the bandwidth limitation since the distance in between can be adjusted to achieve 50-ohm for a given diameter as long as mechanical probe card de- sign rules allow. It is possible then to achieve the ex- pected bandwidth with 95 µm dia. wire on built parts and the same bandwidth can be obtained with 135 µm or 165 µm dia. wires as long as the separation dis- tance is adjusted properly. To optimize the probe card, the distance between two wires for a 95 µm wire case should be close to 105 µm. The insulation thickness for the wire should be 5 µm. The distance between two wires for a 135 um dia. wire case should be close to 147 µm. This implies the insulation thickness should be 6 µm. The distance between two wires for a 165 µm dia. wire case should be close to 181 µm. The insulation thickness needed is 8 µm. For a proper manufacturing of a twisted-wire pair, wires should be in close contact with each other and irregu- lar air gaps should not be allowed. For the optimum connection trace lines, the total length of wires should be reduced as much as possible. The total electrical performance of this structure is mostly dominated by the length of the wires (60 mm) rather than the wire diameter in the design. It is known that the number of twists on wire pairs will affect the crosstalk. A higher crosstalk cancellation on higher frequencies is expect- ed, as the number of twist rises. To cancel the crosstalk, it is best at least to make one twist per one tenth of the wavelength for a given frequency. To calculate the wavelength we can use ‘wavelength = speed of light / frequency’. For example, a twist per 3-mm will give rise to a crosstalk attenuation up to 10 GHz. Similarly, a twist per 6-mm of wire pair length will support a crosstalk at- tenuation up to 5 GHz. Another effect to consider is the angle between the victim line and aggressor line when they are less than 180 degree. This would also make the analysis complex. More number of twists allow for bet- ter attenuation on crosstalk. It should be noted that if the twisting increase the total wire length significantly compared to a straight-wire case, the bandwidth will be reduced compared to a straight-line case. There- fore, moderate twisting in wire-pair formation process should be preferred for optimal results. 3.1 S-parameter in dB Figure 3: S21 data-Crosstalk for ST with 1 mm-distance for parallel and twisted pairs of 135µm diameter wires. In wafer test, there are many configurations of device types especially for logic and mixed signal applications and the multi-device testing is always critical from the test efficiency and yield perspectives. However, the fab teams require very short lead times for initial test re- sults from the design time and fab to the first silicon. This forces teams to use certain vertical probe-card types which allow versatile designs and short cycles. In this family, vertical or cobra type probe cards with WSTs offer a good solution due to their simplicity and cost. The pitch is easy to customize and several suitable wire types with proper diameters are readily available for WSTs. WSTs offer lead time advantages of at least 4-5 weeks (1-2 weeks vs 6-8 weeks) compared to MLC (multilayer ceramic substrate) or MLO (multilayer or- ganic substrate) in the probe card assembly. This lead time differential is crucial in some cases for the first sili- con test. The cost for MLC/MLO is also 5-10 times more expensive. If the lead time is not critical and the volume count for probe cards are high, only then the probe card solutions with MLC/MLO assembly become a rea- sonable option. The factors to consider when choosing the best fit of STs for device types include the pitch, line numbers per device (1 or 2 rows), peripheral rows (1-3), number of DUTs (device under test), configuration (par- tial area array or full array) and area size for each DUT. There are five common classes of substrate systems of interconnects different than WSTs that are used in con- necting probe heads to PCB and tester system. These can mostly support impedance-matched traces for signal transmission lines, except for via-sections, pro- duced by layered-lithographic production methods. Frequency/GHz B. Tunaboylu; Informacije Midem, Vol. 47, No. 4(2017), 255 – 259 259 MLC: Multi-Layer Ceramic, can be with standard thin film or Multi-layer Thin Film (MTF) MLC: LTCC (low-temperature co-fired ceramic) or HTCC (hi-temperature co-fired ceramic) types. MLO: Multi-Layer Organic made from packaging tech- nology, laminated core with several microvia build-up layers HDI PCB: High Density Interconnect made from PCB technology, laminated layers with through hole and microvia on 1 buildup layer Direct Attach: PCB with embedded pads in the center area These substrates or space transformers are either con- nected by BGA (Ball Grid Array) using soldering or spring pin connected by PGA (Pin Grid Array) to main PCB and the test system. Interconnects with BGA-arrays are hard to repair due to solder-connection in case of channel failures. PGA-type interconnects are repair- able, however, they can apply very high force levels when pin counts are above 2500. PGA-type connec- tion is used mainly for HTCC since they are strong and thick ceramic substrates can better withstand bending. WSTs are typically repairable and do not induce any pin force into the PCB or the probe-head. They are also the lowest cost STs. HDI PCB density limitations arise as the pitch shrinks and Direct Attach process are only feasi- ble when large pitch allows manufacturing PCBs for a particular design. Fine pitch device testing typically cannot be supported by HDI PCB or Direct Attach. 4 Conclusion Electrical characterization of proposed designs of wire pairs of parallel and twisted types was carried on test vehicles for vertical probe card applications. When the parallel pair inside sleeve version is tested for the wire diameter of 95 µm, it is good up to 1.45 GHz at – 3 dB. To optimize the probe card, the distance between two wires for 95 µm wire should be close to 105 µm. So the insulation thickness for the wire should be 5 µm. Studies on wire diameters of 50µm, and 135µm were performed and presented for both parallel pair and twisted wire types for space transformers. 5 Acknowledgments Author thanks SV Probe Inc. for support in the study. B. Tunaboylu, (Istanbul Sehir University, Department of Industrial and Systems Engineering, Altunizade Mh, Kusbakisi sok, No: 27, 34662, Istanbul, Turkey) E-mail: btunaboylu@sehir.edu.tr 6 References 1. ITRS roadmap 2015: https://www.semiconduc- tors.org/clientuploads/Research_Technology/ ITRS/2015 2. Yoo, S.K., Kim, T.K., Cho, Y.A. and Yook, J.K.: ‘Opti- mization for polyimide circuit design of space transformer on probe card’, IEEE Semiconductor Wafer Test Workshop, San Diego, USA, June 2016, S05-01 3. Mialhe, L., Garidi, I. and Tunaboylu, B: ‘Cobra FP probe card for multidut, logic and memory ap- plications’, IEEE Semiconductor Wafer Test Work- shop, San Diego, USA, June 2005, S04-02 4. Mahmoud, A. F. and Abdallah, M. I.: ‘Performance testing of twisted pair cables’, J. of Computer Sys- tems, Networks and Communications, 2008, pp. 1-8. http://dx.doi.org/10.1155/2008/586427 5. Siebert, W. P.: ‘High frequency cable connector for twisted pair cables’, IEEE Trans. Comp. and Pack. Tech., vol 26, 3, 2003, pp. 642-650. 6. S. Dang, R. Kazmi, G. Back, B. Tunaboylu. ‘Modular space transformer for fine pitch vertical probing application’, Patent No: US 8,430,676 B2, 2013. 7. Kilicaslan, H. and Tunaboylu, B: ‘Bandwidth im- provement techniques on probe cards’, IEEE Semiconductor Wafer Test Workshop, San Diego, USA, June 2006, S07-03 Arrived: 14. 08. 2017 Accepted: 12. 10. 2017 B. Tunaboylu; Informacije Midem, Vol. 47, No. 4(2017), 255 – 259 260 261 Original scientific paper  MIDEM Society Modelling Overvoltage Protection Components: Verilog Simulations of Combined MOV and GDT Arresters Mujo Hodžić1, Aljo Mujčić2, Nermin Suljanović2, Matej Zajc3 1BH Telecom d.d. Sarajevo, Sarajevo, Bosnia and Herzegovina 2Faculty of Electrical Engineering, University of Tuzla, Tuzla, Bosnia and Herzegovina 3Faculty of Electrical Engineering, University of Ljubljana, Ljubljana, Slovenia Abstract: Overvoltage protection systems are used to protect sensitive electrical and electronic equipment from voltage surges and lightning strikes. These systems are mostly based on the use of gas discharge tubes (GDTs) and metal-oxide varistors (MOVs), which are utilised individually or in various combinations. Adequate computer simulations play an important step in the process of designing overvoltage protection systems and selecting adequate parameters. In this paper, the modelling of low-voltage GDT and MOV components is performed using the Verilog-A hardware description language. The presented models are designed for integration with other overvoltage protection system components to form an integrated overvoltage protection system. The current–voltage characteristics of the GDTs and MOVs are highly nonlinear and frequency dependent. The developed Verilog-A mixed behavioural and structural models of GDTs and MOVs ensure a stable convergence of numerical processes during the simulations of circuits with these elements. The simulations of overvoltage protection systems were completed using a TINA circuit simulator. Two laboratory tests were performed using GDT and MOV components. In the first test, the time responses of the current and voltage on a GDT and MOV serial connection were measured in the laboratory. In the second test, the response of the GDT and MOV serial connection was tested in a power line network environment, where a surge current impulse and power line voltage of 400 V peak and frequency of 50 Hz existed simultaneously. The dynamic response of the GDT and MOV serial connection obtained through the simulations agrees well with the measurement results. Keywords: Verilog; modelling; gas discharge tubes; metal-oxide varistor; overvoltage protection. Modeliranje komponent prenapetostne zaščite: Simulacija serijske vezave prenapetostnih odvodnikov MOV in GDT v jeziku Verilog Izvleček: Sistemi prenapetostne zaščite se uporabljajo za zaščito občutljive električne in elektronske opreme pred prenapetostjo in udari strele. Običajno so ti sistemi zasnovani na plinskih odvodnikih prenapetosti (GDT) in metal-oksidnih varistorjih (MOV), ki se uporabljajo posamezno ali v različnih vezavah. Računalniške simulacije predstavljajo pomemben korak pri načrtovanju sistemov prenapetostne zaščite in izbiri ustreznih parametrov. V tem članku predstavimo modeliranje nizkonapetostnih komponent GDT in MOV v jeziku Verilog-A. Predstavljeni modeli so namenjeni integraciji z drugimi komponentami, ki tvorijo integriran sistem prenapetostne zaščite. Tokovno- napetostne karakteristike GDT in MOV so močno nelinearne in frekvenčno odvisne. Razviti modeli GDT in MOV v jeziku Verilog-A uporabljajo opis obnašanja in strukturni opis, kar zagotavlja stabilno konvergenco numeričnih procesov. Simulacije sistemov prenapetostne zaščite so potekale z uporabo simulatorja TINA. V praktičnem delu smo izvedli dva laboratorijska testa. V prvem testu so bili v laboratoriju izmerjeni časovni odzivi toka in napetosti na serijski vezavi GDT in MOV. V drugem testu smo preizkusili odziv serijske vezave GDT in MOV ob hkratni prisotnosti impulza prenapetostnega toka in omrežne napetosti amplitude 400 V in frekvence 50 Hz. Dinamični odziv serijske vezave GDT in MOV, pridobljen s simulacijami, se dobro ujema z rezultati meritev. Ključne besede: Verilog; modeliranje; plinski odvodnik prenapetosti; metal oksidni varistor; prenapetostna zaščita. * Corresponding Author’s e-mail: matej.zajc@fe.uni-lj.si Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 4(2017), 261 – 271 262 M. Hodžić et al; Informacije Midem, Vol. 47, No. 4(2017), 261 – 271 1 Introduction Overvoltage protection components have become an inevitable part of the devices aimed to protect sensi- tive equipment against overvoltage surges caused by atmospheric discharges and transients in power networks. An overvoltage protection system must be designed to capture the atmospheric discharge to a preferred point, conveying the energy into the ground and protecting all incoming power and communica- tion lines using surge protection devices (SPDs). SPDs must discharge high-magnitude impulse cur- rents and limit the overvoltage levels [1, 2]. SPDs are primarily based on metal-oxide varistors (MOVs) and gas discharge tubes (GDTs), which are used individu- ally or in serial combinations. Overvoltage protection components can be divided into voltage switching and voltage limiting compo- nents [1]. Voltage switching components operate by switching from a high to low resistance state at certain breakdown voltages and behave as a short circuit. GDTs operate in accordance with this principle. The compo- nents in the second group limit a transient overvoltage impulse to a predefined voltage level. MOVs belong to this set of overvoltage components. Modelling and simulation can significantly facilitate the process of designing overvoltage protection sys- tems. Typically, simulations are based on models of the individual components comprising the overvoltage protection system, commonly described with math- ematical expressions. The modelling and simulation process is more complex when some of the components have nonlinear charac- teristics and states that vary depending on excitation input values. In addition, the models need to be devel- oped in a form that allows their integration with the existing components within the electronic simulation program. MOVs and GDTs have highly non-linear current–volt- age characteristics [1–4]. The simulation of a system with these components can lead to non-convergent numerical calculations [5], which is especially critical during the transition of individual components from one state to another. The simulation of overvoltage protection systems is mostly based on SPICE models and implemented us- ing SPICE-based simulation tools [5]. Using intrinsic components as the basic building blocks for a larger model, designers can define new SPICE models. SPICE accepts netlists as a text description of a circuit that is comprised of interconnected basic components [6]. The models of these basic components are provided within the simulator. The existing GDT models available in the literature are largely SPICE based, in the form of structured netlists composed of basic components [7–9]. The solution presented in [7] uses controlled switches and diodes with specified breakdown voltages. The model in [8] is created with transistors, providing theoretical triac voltage–current characteristics. Conversely, the GDT models in [10–12] are based on mathematical descrip- tions of basic operational principles developed for the Matlab/Simulink environment. Several MOV models have been proposed in the lit- erature [5, 12–17], aiming to properly represent MOV’s nonlinear characteristics and frequency dependence behaviour. The IEEE W.G. 3.4.11 proposed a frequency- dependent model with two nonlinear resistors [14], which was further simplified by [15], preserving its basic principle. In [16], the authors neglected the first inductance in the IEEE model as well as the simplified parameter determination procedure [16]. The MOV model presented in [12] was developed in the Matlab/ Simulink environment for simulations of transients in low voltage power-lines. A review of the existing mod- els and their implementation for transient behaviour of electrical circuits is presented in [13]. Verilog-A, a subset of Verilog-AMS, has emerged as a standard language for the development of compact models of circuit components based on mathematical descriptions of the electrical behaviour of individual components [18]. This language allows the description and simulation of components and circuits at a higher level of abstraction [18, 19]. The compact models were originally coded in FORTRAN or C, with relatively com- plex codes [18]. The compact models should be suffi- ciently simple to be easily developed and incorporated in circuit simulators. Verilog-A, as a hardware design language (HDL) for analog circuits and system design, uses a text-file code to describe the mathematical models [19, 20]. The Verilog-A code is converted into low-level C language by a code generator [19]. The gen- erated C code is then directly compiled into the simula- tor, resulting in an equivalent SPICE model. In this way, it is possible to simulate electronic circuits that include both Verilog and SPICE models. TINA supports simula- tions including Spice netlists along with components modelled in Verilog, Verilog-A and Verilog-AMS [21]. The presented MOV and GDT Verilog-A models are based on mathematical descriptions of the transfer function in the MOV modelling and transition between states during the GDT modelling. The developed mod- 263 els ensure a stable convergence of numerical process during simulations of circuits with these elements. Verilog-A models of MOV and GDT are used to simulate a serial connection of these components. Using such a serial connection reduces some of the shortcomings that arise when using these components individually, especially in the first stage of overvoltage protection systems. For example, high GDT resistance eliminates leakage currents in MOVs. On the other hand, the use of MOVs in serial connections resolves fast surge dis- charges, as GDTs have a much longer response. The performed simulations demonstrated that the devel- oped models ensure stable convergence of the numer- ical processes. The validation of the developed models was per- formed by comparing the simulation results with the measurement results of the residual voltage measured on the GDT and MOV serial connection. In the laborato- ry, waveforms of residual voltage under surge currents of 40 kA (10/350 µs) and 20 kA (10/700 µs) were meas- ured. The results obtained by performing simulations with the TINA program tool were verified by laboratory tests. In the first scenario, the residual voltage at the GDT and MOV serial connection ports were measured after stress with the current pulse shape. In the second scenario, the overvoltage protection was focused on measurement of voltage waveform at the terminals of the MOV and GDT serial connection when a surge impulse and power line voltage of 50 Hz existed simul- taneously. The second scenario corresponds to a real application of an overvoltage protection device. The rest of this paper is structured as follows: Section II describes the basic operational principles of GDTs and MOVs and appropriate current/voltage characteristics. Verilog-A GDT and MOV models (presented with sim- plified pseudo codes) are developed using the TINA circuit simulator and described in Section III. Section IV presents the results of the measurements and numeri- cal simulations for two overvoltage protection system scenarios. Conclusions and recommendations for fu- ture research are given in the last section of the paper. 2 Overvoltage Protection Components A basic description of the GDT and MOV components is given in this section to simplify the presentation of the developed models described in the next section. GDTs consist of two or more metal electrodes separat- ed by a small gap filled with a gas insulation medium and held by a ceramic or glass cylinder [1–3]. During normal operation at nominal voltage, GDTs behave as an insulator. GDTs dissipate voltage transients through a contained plasma gas when an overvoltage pulse reaches the spark-over (breakdown) voltage (Fig. 1). The spark-over voltage is not constant but rather depends on the rate of rise of the surge voltage. As the voltage increases across the GDT, the gas in the tube starts ionising due to the charge developed across it [1-3]. In this region, known as the glow region with voltage Uglow, the in- creasing current flow generates an avalanche effect, transitioning the GDT into a virtual short. This is the arc burning phase. The glow region is shown in Fig. 1. During the short-circuit event, the voltage developed across the device is known as the arc voltage, Uarc. This region is known as the arc region (Fig. 1). The transition time between the glow and arc regions is dependent on the physical characteristics of the GDT [3]. In the arc region, the GDT diverts the transient current away from the protected device. During the extinguishing pro- cess, the transition from the arc to glow regions may be at a lower current than during the transition from the glow to arc regions (dashed line in Fig. 1.). Figure 1: GDT U-I characteristics GDT components have high insulation resistance and low capacitance. When a voltage applied to the GDT electrodes is below its spark-over voltage, the leakage current through the arrester is close to zero. A low leak- age current ensures minimal influence on the normal operation of the equipment. MOVs are resistors with a nonlinear U-I characteris- tic (Fig. 2.). Unlike GDTs, these elements do not cause short-circuits in the power supply network. MOVs are produced of a ceramic material obtained by mixing zinc oxide (ZnO) with a small amount of additives. The I U Sparkover voltage Glow region Glow to Arc transition Arc region M. Hodžić et al; Informacije Midem, Vol. 47, No. 4(2017), 261 – 271 264 ZnO grains have low resistance and are surrounded by granular layers of additives with high resistance [1]. This structure behaves like diodes connected in series/ parallel, ensuring that the MOV has nonlinear charac- teristics. When a low voltage is applied to the MOV electrodes, the diodes are not conductive and the MOV behaves as an insulator. After the electric field reaches a value above 100 kV/mm, the current starts to flow and varies from 1 mA to 1 kA. With a high electric field, the volt- age drop in the MOV is linear since it is determined by the voltage drop in the ZnO grain resistance [1]. The voltage drop at the barrier can be neglected due to the tunnel effect. This part of the U-I characteristic is linear. Figure 2: MOV U-I characteristics The ability of components to withstand high-energy pulses is measured by the different pulse shapes (8/20 μs, 10/350 μs, 10/700 μs, and 1.2/50 μs) and amplitudes. 3 Verilog-A Models of Overvoltage Protection Components The Verilog-A hardware description language is accept- ed for the modelling of electronic components and cir- cuits due to its simplicity and flexibility when writing model code. The descriptions of the developed models of overvoltage components are based on pseudo code. For presentation purposes in this text, some blocks of the code are represented with mathematical equations. GDTs can be in three different states, as described in the previous section [1, 7, 9]. A simplified GDT model can be presented as a symmetrical low-capacitance voltage and current controlled switch, whose resist- ance may instantly change from several GΩ during normal operation to values less than 1 Ω after ignition caused by a surge voltage. The transition from an open to closed switch includes an ionising state, and the GDT model must include these three states. The Verilog- A GDT model presented in this paper includes these three states, defined in accordance with the character- istic shown in Fig. 1. The modelling of the GDT transition in SPICE is imple- mented with voltage and current control switches. The required voltage levels are ensured by diodes with the specified breakdown voltages [7]. The model present- ed in [8] does not include switches. The transition from a high-value impedance state to a very low impedance state in [8] is solved using bipolar transistors connected to provide theoretical triac behaviour of the GDT mod- el as a whole. The Verilog-A module may contain equations for be- havioural modelling and instantiations of other mod- ules such as structural modelling. The behavioural models define the relationships between the out- puts and inputs, and they contain procedural state- ments that control the simulation and manipulation of the variables of the defined data types. The behav- ioural models are more abstract, and the focus is on the functionality of the design.  Structural modelling defines the system in terms of basic components and their interconnections, describing the interconnection between the predefined components in the model. The model in Verilog-A is defined with the nodes and branches, so the behaviour of each branch must be specified. The simplified pseudo-Verilog-A code of the proposed GDT model is shown in Fig. 3. The first line, discipline.va, provides common definitions that are used to specify the type of a continuous wire. The discipline includes a collection of related natures as physical signal types. Electrical discipline, used in our models, consists of voltages and currents. The second line defines the name of the component, in this case GDT, and the in- put/output nodes. The nodes a and c are declared as inout ports and presented with electrical discipline. The a and c pins are nodes that the GDT shares with the rest of the circuit (line 3). The pins are then declared as be- ing electrical, meaning that the potential of each pin is a voltage and the flow into the pin is a current. The parameters, defined below, are treated as constants within the module and cannot be changed from within the module (lines 5 to 12). In Verilog-A, the description of the model is given as an analog process, which is de- noted with the keyword analog in line 13. The initial values and state of GDT is defined in (Fig. 3, line 14). The capacity C of GDT shows the behaviour at I U M. Hodžić et al; Informacije Midem, Vol. 47, No. 4(2017), 261 – 271 265 nonconductive state, and is modelled using ddt func- tion in line 16. The charge is first calculated in line 15 [18]. The construction of GDT is such that it has very low capacitance C. This allows GDT usage in high-frequen- cy circuit applications protecting communication and data lines from overvoltage. The inductance L takes into account dynamic response. If the voltage at GDT terminals has low rate of rise, the spark-over voltage will be determined by electrode spacing, the gas type and pressure, and pre-ionization of the enclosed noble gas [3]. When the overvoltage pulse has fast rate of rise the spark-over voltage of GDT will be increased. This is caused by the finite time necessary for the gas to ionize. The estimation of spark- over voltage is based on measured voltage levels for different values of rate of rise and provided by manu- facturers of GDT components. The estimation of spark- over voltage is listed in lines 20 and 21. GDT stressed by overvoltage impulse can be in previ- ously described three states. The Verilog-A model of GDT, including descriptions of three states, can be sim- plified by using an ‘IF THEN ELSE’ conditional statement. From the current-voltage characteristic curve shown in Fig. 1, it is clear that the GDT has bi-directional symmet- rical characteristics. The GDT can operate or function in either direction or overvoltage pulse polarity, and the GDT model must take this property into account. When the voltage at the GDT terminals is greater than the spark-over voltage, the GDT goes into an ON state (line 23). After ignition, the voltage drops from the spark-over voltage to the glow voltage level. This transition can lead to a loss of convergence during the process of solving the voltage and current waveforms. In order to avoid this loss of convergence, the transi- tion from the high resistance state to the glow region is modelled using the transition function (line 30): ( ) ( ) 1 810 t t p glow glowu t U U e U − − − = − + (1) where u(t) is the voltage at the GDT terminals, Up is the spark-over voltage, Uglow is the voltage in the glow re- gion and t1 is the time at the moment when the over- voltage pulse reaches the spark-over voltage. The volt- age in the glow region is represented by Uglow. A similar transition exists when the GDT switches from the glow to arc regions. This transition can also lead to a loss of convergence. Hence, the transition from the glow to arc regions is modelled using the following equation: ( ) ( ) glow arcI Iglow arc arcu t U U Uτ −= − + (2) where Uarc is the voltage in the arc region, Iglow is the cur- rent in the glow region before transition and Iarc is the current in the arc region after transition. This transition is presented on line 33 in Fig. 3. Using the two previously described functions, a smooth transition from one state to another is provid- ed, and the standard use of switches in the GDT model is avoided. The resistance of the GDT in normal opera- tion is ROFF and is calculated in line 42. The calculated voltage U, using the contribution operator (<+) in line 44, determines the value of the potential between the n and c nodes V(n,c). MOVs are voltage-dependent resistors with a highly non-linear voltage-current relation, and they have dif- ferent delays in the conduction mechanism at different surge current wavefronts. The IEEE model is the most used model in the literature for transient analysis of varistors. The Verilog-A model of MOV, presented in this paper, is based on the IEEE model. The model is frequency dependent and is suitable for the numerical simulation of fast transients [4, 5]. The simplified pseu- do-Verilog-A code of the MOV model is shown in Fig. 4. The non-linear voltage-current relation is represented by two non-linear branches separated by an R, L filter. This filter has an important role in taking into account different delays in the conduction mechanism at differ- ent surge current wavefronts [4, 5, 16]. The first line in Fig. 4 defines the discipline required for analog simulations. The second line lists the module name of the component, in this case MOV, and the list or node names (p and n). The port direction (line 3) and port and node types (line 4) are then declared. The pa- rameters provide a way to pass values into the mod- ule at the time of instantiation. The parameters of the MOV model were computed using the procedure given in [14, 15]. The analog block describes the MOV model and includes lines from 18 to 45. The series inductance is first introduced (line 20). The L1 represents the inductance of the current path through the arrester. The resistance R1 in line 21 pro- vides convergence in the numerical simulations. These two components (R1 and L1) also represent the input filter of the model. The first and second nonlinear elements are modelled with the following expression [17]: I c nU U kb I= (3) where U is voltage across the varistor, Un clamping voltage and I is the current through the varistor. The M. Hodžić et al; Informacije Midem, Vol. 47, No. 4(2017), 261 – 271 266 coefficients k, b, and c are obtained from fitting of the curves proposed by the IEEE Working Group. The first nonlinear element is listed in lines 22 to 30. The non- linear VI characteristic is divided in three regions. The code of second nonlinear branch is listed in lines 36 to 44. The nonlinear elements are divided by the R-L filter (lines 34 and 35). The MOV capacitance C is presented in line 32. MOV and GDT components are described using the module in Verilog-A [19]. These two components are then combined as a GDT and MOV serial connection (Fig. 5). The GDTMOV model uses previously presented models (Fig. 3, Fig. 4) of the GDT and MOV, which are in- cluded in the code (lines 10 to 13). In line 14, the mod- ule starts with the name of the model and the input and output nodes. Next, the direction of two electrical nodes are defined: p and n (line 16). Internal node i1 is defined as electrical. The nodes are used as intercon- nection points for ports. Figure 4: The pseudo Verilog-A code of MOV model The GDTMOV model itself is constructed by creating instances of predefined GDT and MOV modules, wir- ing them together by connecting them to nodes and then specifying parameters for them. This is done for the GDT model (line 18) and the MOV model (line 19). 1: ‘include "disciplines.va" 2: module GDT(a, c); 3: inout a, c; 4: electrical a, c, n; 5: parameter real Cgap = 0.5e-12; 6: parameter real Riso = 1.0e9; 7: parameter real L =1.0e-9; 8: parameter real Uglow=150.0; 9: parameter real Uarc=40.0; 10: parameter real tau=0.01; 11: parameter real Iarc=9.0; 12: parameter real Imin=90.0e-3; 13: analog begin 14: Initialize basic values and state of GDT 15: q=Cgap*V(a,c); 16: I(a,c) <+ ddt(q); 17: V(a,n) <+ L*ddt(I(a,n)); 18: I(a,n) <+ V(a,n)/Rp; 19: Estimation of sparkover voltage Up 20: absslope=abs(ddt(V(a,c))*1e-6); 21: Up < +table_model(absslope, ”table_slope.tbl”, ”L”); 22: if U > Up then 23: GDT goes into ON state 24: define time t1 25: else 26: GDT remains in OFF state 27: end if 28: if GDT is in ON state then 29: if I < Iarc then 30: U = (Up − Uglow)e− t−t1 10−8 + Uglow 31: else 32: if I > Iarc +∆I then 33: U = (Uglow − Uarc)τ I−Iarc + Uarc 34: else 35: U = Uarc 36: if I < Imin then 37: GDT goes into OFF state 38: end if 39: end if 40: end if 41: else 42: U = I ·ROFF 43: end if 44: V(n,c)<+U; 45: end 46: endmodule Figure 3: The pseudo Verilog-A code of the GDT model 1: ‘include "disciplines.va" 2: module MOV (p, n); 3: inout p, n; 4: electrical p, n, n1, n2; 5: parameter real L1 = 0.6e-9; 6: parameter real L2 = 45e-9; 7: parameter real R1 = 0.3; 8: parameter real R2 = 0.195; 9: parameter real k1 = 1.2968167; 10: parameter real k2 = 0.9713959; 11: parameter real b1 = 1.000005; 12: parameter real b2 = 1.000004; 13: parameter real c1 = 0.0376332; 14: parameter real c2 = 0.0510025; 15: parameter real Imin=1e-5; 16: parameter real Un=450.0; 17: parameter real C = 0.3e-12; 18: analog begin 19: // The first RL filter 20: V(p,n1) <+ L1 * ddt(I(p,n1)); 21: V(p,n1) <+ I(p,n1) * R1; 22: // Te first nonlinear branch 23: i1 = I(n1, n); 24: if i1 > Imin then 25: U1 = Un · k1 · bi11 · i c1 1 26: else 27: RL = Un · k1 · bImin1 · I c1 min/Imin; 28: U1 = RL ∗ i1; 29: end if 30: V(mid1, n) <+ U1; 31: // Varistor capacity 32: I(n1, n) <+ C * ddt(V(n1, n)); 33: // The second RL filter 34: V(n1,n2) <+ L2 * ddt(I(n1,2)); 35: V(n1, n2) <+ I(n1, n2) * R2; 36: // The second nonlinear branch 37: i2 = I(n2, n); 38: if i2 > Imin then 39: U2 = Un · k2 · bi22 · i c2 2 40: else 41: RL = Un · k2 · bImin2 · I c2 min/Imin; 42: U2 = RL ∗ i2; 43: end if 44: V(n2, n) <+ U2; 45: end 46: endmodule M. Hodžić et al; Informacije Midem, Vol. 47, No. 4(2017), 261 – 271 267 The statement in line 18 directs that an instance of the module GDT be connected to nodes p and i1 and be named GDT1. The parameters of GDT are defined in the GDT module and are not stated here. The second statement (line 19) directs that an instance of MOV be named MOV1 and connect to i1 and n. The module ter- minates with the endmodule statement. Figure 5: The pseudo Verilog-A code of GDT and MOV in serial connection The parameters of the GDT and MOV models are adapt- ed to the components used in the experimental tests. These parameters are based on data provided by the producers of the overvoltage components. 4 Numerical Simulations and Measurements The validation of the developed GDT and MOV mod- els is based on comparisons of the residual voltages obtained using numerical simulations and experimen- tal tests when the MOV and GDT serial connection is stressed with a current pulse of a given shape and amplitude. The model of the MOV and GDT serial con- nection, developed in Verilog-A, is simulated using the TINA circuit simulator. In the first scenario, the residual voltage at the GDT and MOV serial connection ports is measured after stress with a 10/350 µs current pulse shape with an amplitude of 40 kA. The measurement setup of the first test system is presented in Fig. 6. For this measurement, a surge generator (TUG-200 generating an impulse of direct atmospheric discharge 10/350 μs short circuit), a digital scope Tektronix (100 MHz, 1 GSample/s), and a Pearson current monitor model 1423 were used. The test system from Fig. 6 is simulated in the TINA software tool. The scheme of the circuit with the GDT and MOV serial connection as an integrated component mod- elled in Verilog-A is presented in Fig. 7. The 10/350 µs current pulse is modelled using the piecewise linear signal definition as a set of Time/Value pairs. The residual voltage is measured at the terminals of the MOV and GDT serial connection and presented in Fig. 8. The residual voltage waveform obtained by the simulation is presented in Fig. 9. The time response of the GDTs and MOVs depends on the rate of rise and the magnitude of the surge pulses [3–5]. Figure 6: Measurement setup of the GDT and MOV in serial connection (surge current shape is 10/350 µs and the amplitude is 40 kA) GDTs provide insulation between the protected lines and the ground potential during normal operation. High GDT resistance eliminates the leakage current that occurs when MOV-based surge devices are used. GDTs are also characterised by a high surge current dis- charge capacity, which can take more than ten thou- sand amperes (8/20 μs). However, GDTs have a slightly slower response compared to MOVs. The voltage drop in GDTs remains constant and low regardless of the surge current and behaves as a low impedance switch. MOVs can also be used to meet the requirements of lightning protection class I with low protection levels due to high-performance varistor ceramics and the ability to discharge high surge pulses in acceptable in- stallation spaces. The fast response time of MOVs (na- nosecond range) makes them suitable for limiting even particularly dynamic surge voltage phenomena. In normal operation, GDTs cut off leakage currents. During the surge pulse, the GDT and MOV serial con- nection effectively discharges the transients to ground and limits the voltage below the dielectric strength of the end device. The typical dielectric strength value of end devices is about 1.5 kV. 1: //////////////////////////////// 2: //TINA HDL Macro Description Begin 3: //entity_name:GDTMOV; 4: //arch_name:ignored; 5: //ports:p,n;; 6: //Mode:VerilogAMSTyp; 7: //TINA HDL Macro Description End 8: //////////////////////////////// 9: ‘include "disciplines.va" 10: module GDT(a, c); 11: The code of GDT from Fig. 3. 12: module MOV (p, n); 13: The code of MOV from Fig. 4. 14: module GDTMOV (p, n); 15: inout p, n; 16: electrical p, n; 17: electrical i1; 18: GDT #( ) GDT1( .a(p), .c(i1) ); 19: MOV #( ) MOV1( .p(i1), .n(n) ); 20: endmodule M. Hodžić et al; Informacije Midem, Vol. 47, No. 4(2017), 261 – 271 268 The serial connection of GDTs and MOVs takes advan- tage of both technologies and eliminates certain de- ficiencies of the single components. GDTs and MOVs together provide faster response and require lower capacitance when power lines are used as communi- cation media. The MOV in this configuration eliminates follow-on currents and allows the GDT arc to be extin- guished. The follow-on current is supplied by the elec- trical power system and flows through the GDT after the discharge current impulse disappears. The residual voltage at the GDT and MOV terminals (Fig. 6) is observed by a digital oscilloscope and presented in Fig. 8. The residual voltage obtained by measure- ments is 940 V. Equal values for residual voltage and a similar waveform of voltage at the GDT–MOV terminals is obtained by numerical simulation (Fig. 9). Figure 9: The waveform of the residual voltage ob- tained by simulation in TINA The second case of the overvoltage protection labora- tory tests and simulations is focused on the measure- ment of the voltage waveform at the terminals of the MOV and GDT serial connection when the surge im- pulse (10/700 µs surge pulse shape) and a power line voltage of 50 Hz exist simultaneously. The surge im- pulse appears on the LV network during its operation. In the laboratory measurements and in the numerical simulations, it is assumed that a surge wave appears at a certain moment on an energised LV conductor. The SPD device is connected to a phase conductor, and phase voltage exists during the measurements and nu- merical simulations. A schematic representation of the measurement setup is presented in Fig. 10. Measurement equipment con- sists of: a surge generator TUG-200 (generating an im- pulse of direct atmospheric discharge 10/700 μs short circuit), an auto-transformer for the power line volta- ge, an oscilloscope LeCroy (350 MHz, 2,5 GSample/s), a digital scope Tektronix (100 MHz, 1 GSample/s), and a Pearson current monitor model 1423. The currents are measured in the MOV and GDT branch and the power line branch. The voltage drop at the terminals of the GDT and MOV serial connection is also measured. Isurge GDT MOV Ures Figure 7: The circuit for numerical simulation of the MOV and GDT in serial connection Figure 8: The residual voltage measured using the measurement setup presented in Fig. 6 Figure 10: Measurement setup of the GDT and MOV in serial connection M. Hodžić et al; Informacije Midem, Vol. 47, No. 4(2017), 261 – 271 269 The measurement setup from Fig. 10 is simulated using the TINA software tool. The scheme of the circuit with the GDT and MOV serial connection when the surge impulse (10/700 µs surge pulse shape) and a power line voltage of 400 V peak and frequency of 50 Hz ex- ist simultaneously is presented in Fig. 11. An RC circuit is used to simulate a 10/700 µs single output impulse generator. This type of surge generator is designed according to the description of impulse generators proposed in [22]. The scheme of the 10/700 µs surge generator is shown in Fig. 11. An overvoltage pulse is generated using a capacitor with initial voltage, and with a switch defining the time of the pulse. A capaci- tor bank, represented by C1, will be charged to an ini- tial DC voltage, Udc. The capacitor will be discharged through a wave-shaping RC network. The voltage of the power frequency is added as a branch connected in parallel with the surge generator (Fig. 11). Figure 11: The circuit for the measurement setup of the GDT and MOV in serial connection The measured values of these three waveforms are presented in Fig. 12. The three signals, presented on the screen of an oscilloscope, have different  horizon- tal scales. The current waveform is indirectly observed through the voltage waveform and presented on the oscilloscope screen as an F1 waveform (Fig. 12). The waveform F1 has a time base of 200 µs/div and a verti- cal scale of 10 kA/div. The second waveform is current flowing through the power line branch. This signal has a time base of 200 ms/div and a vertical scale of 200 A/ div. The third signal is the voltage at the terminals of the GDT and MOV serial connection. This waveform has the same time base as the second signal. The vertical scale is 500 V/div. After the appearance of the surge current impulse (F1 in Fig. 12), the surge arrester react- ed and started to conduct. The surge current amplitude is 21 kA, with a 10/700 µs current pulse shape. It is evi- dent from Fig. 12 that the surge wave appeared after 40 ms. The current from the surge generator also flows through the power line branch. The maximum value of the current in the power line branch during the surge current pulse is 198 A. Figure 12: Surge current pulse, current in the power frequency branch and the voltage across the GDT and MOV serial connection Fig. 13a shows the time diagram of the surge current generator presented in Fig. 11. After the appearance of the surge current pulse, the GDT and MOV responded and started to conduct. The voltage drop across the GDT and MOV stayed below 1000 V (Fig. 13b). The main part of the surge current was grounded through the GDT and MOV surge arrester. A small portion of the surge current during the conductive phase of the GDT and MOV was flowing through the power line branch. Extinguishing of the electric arc is assured when the MOVs are connected in series with GDTs. Igen I_GDTMOV R3 25 C 2 2 0 0 n R 2 5 0 t SW1 R1 15 C 1 2 0 u GDT MOV Lline 1mRline 500m + Ug Uload Power line Surge generator Figure 13: Surge current pulse, current in the power line branch and voltage of power frequency. a) a) M. Hodžić et al; Informacije Midem, Vol. 47, No. 4(2017), 261 – 271 270 5 Conclusions This paper presented overvoltage component models based on the Verilog-A language utilising a simplified approach to modelling components with nonlinear transfer characteristics and their description with built- in nonlinear functions. GDT and MOV Verilog-A models were provided, and simulations were completed using the TINA circuit simulator. A serial connection of GDTs and MOVs was constructed by creating instances of developed modules. The developed Verilog-A models were used together with SPICE models of other com- ponents for the simulation of surge protection devices. The GDT and MOV serial connection was analysed, and the simulation results were compared with adequate laboratory measurements. Two types of measurements of the response of overvoltage components during the overvoltage impulse are presented. The validation of the developed models is based on a comparison of the residual voltages obtained by measurements and simulations. The first measurement is a standard test of overvoltage components, while the second measure- ment tests overvoltage components in a real environ- ment. The difference between simulation results and meas- urements is directly dependent on the accuracy of mathematical description of physical components at a higher abstraction levels. The compact models of GDT and MOV are based on presented mathematical de- scriptions. The differences that arise between the sim- ulations and measurement results have been recog- nized by adjusting the models of surge pulse sources to better fit the measurement results. In the first case, a piecewise linear description of surge pulse is utilized and in the second case modelling with discrete ele- ments is used. We conclude that varistors connected in series with the arrester are well suited for limiting the follow-on cur- rent. The advantages of the serial connection of GDTs and MOVs are proven, and we showed that this topol- ogy eliminates certain deficiencies of individual com- ponents. 6 References 1. R. B. Standler, Protection of electronic circuits from overvoltages, Dover, Publications, Inc. New York, 1989. 2. V. Murko, N. Suljanović, A. Mujčić, J. F. Tasič, Uni- versal SPD coordination towards an effective surge protection of power supply networks, Jour- nal of Electrical Engineering and Computer Science/ Elektrotehniški vestnik, Volume 78, No. 3, 2011. 3. T. Ardley, First Principle of Gas Discharge Tube (GDT) Primary Protector, www.bourns.com. 4. H. Chen, Y. Du, A comprehensive study on the nonlinear behavior of metal oxide varistors, 33rd International Conference on Lightning Protection (ICLP), September 2016. 5. N. Suljanović, A. Mujčić, V. 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Thot- tappillil, Numerical modelling of metal oxide varistors, Proceedings of the XIVth International Symposium on High Voltage Engineering, Tsinghua University, Beijing, China, August 25-29, 2005. M. Hodžić et al; Informacije Midem, Vol. 47, No. 4(2017), 261 – 271 271 18. C. McAndrew, et al. Best Practices for Compact Modeling in Verilog-A, Journal of Electron Devices Society, Vol, 3, No. 5, September 2015. 19. K. S. Kundert, O. Zinke, The Designer’s Guide to VERILOG-AMS, Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow, 2004. 20. Accellera, “Verilog-AMS Language Reference Manual, version 2.2”, 2004, http://www.accellera. org, 2010. 21. TINA v10, The Complete Electronics Lab for Win- dows, DesignSoft, Inc., 1990-2014. M. J. Maytum, Impulse generators used for testing low-voltage equipment, IEE PES- Surge Protective Devices Committee, 2012. 22. M. J. Maytum,  Impulse generators used for testing low-voltage equipment, IEE PES- Surge Protective Devices Comittee, 2012. Arrived: 23. 10. 2017 Accepted: 27. 11. 2017 M. Hodžić et al; Informacije Midem, Vol. 47, No. 4(2017), 261 – 271 272 273 Announcement and Call for Papers October 3rd – 5th, 2018 Jožef Stefan Institute, Ljubljana, Slovenia ORGANIZER: MIDEM Society - Society for Microelec- tronics, Electronic Components and Materials, Ljublja- na, Slovenia CONFERENCE SPONSORS: Slovenian Research Agen- cy, Republic of Slovenia; IMAPS, Slovenia Chapter; IEEE, Slovenia Section GENERAL INFORMATION The 54th International Conference on Microelectronics, Electronic Components and Devices with the Work- shop on Sensors and Sensor Technologies continues a successful tradition of the annual international confer- ences organised by the MIDEM Society, the Society for Microelectronics, Electronic Components and Materi- als. The conference will be held at Jožef Stefan Insti- tute, Ljubljana, Slovenia, leading Slovenian scien- tific research institute, from OCTOBER 3rd – 5th, 2018. Topics of interest include but are not limited to: - Workshop focus: Sensors and sensor technologies - Novel monolithic and hybrid circuit processing techniques, - New device and circuit design, - Process and device modelling, - Semiconductor physics, - Sensors and actuators, - Electromechanical devices, - Microsystems and nanosystems, MIDEM 2018 54th INTERNATIONAL CONFERENCE ON MICROELECTRONICS, DEVICES AND MATERIALS WITH THE WORKSHOP ON SENSORS AND SENSOR TECHNOLOGIES Call for papers Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 4(2017), 273 – 273 - Nanoelectronics - Optoelectronics, - Photonics, - Photovoltaic devices, - New electronic materials and applications, - Electronic materials science and technology, - Materials characterization techniques, - Reliability and failure analysis, - Education in microelectronics, devices and materials. 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