Original scientific paper 91 92 93 94 95 97 ISSN 0352-9045 Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 2(2021), June 2021 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 51, številka 2(2021), Junij 2021 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 2-2021 Journal of Microelectronics, Electronic Components and Materials VOLUME 51, NO. 2(178), LJUBLJANA, JUNE 2021 | LETNIK 51, NO. 2(178), LJUBLJANA, JUNIJ 2021 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2020. All rights reserved. | Revija izhaja trimesecno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale – Društvo MIDEM. Copyright © 2020. Vse pravice pridržane. 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Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madic Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina placana pri pošti 1102 Ljubljana Journal of Microelectronics, Electronic Components and Materials vol. 51, No. 2(2021) Content | Vsebina 95 101 113 119 135 147 Izvirni znanstveni clanki M. Konal, F. Kacar: Metoda razširjene pasovne širine na simetricnem operacijskem ojacevalniku in filtru P. Bhattacharjee, B. K. Bhattacharyya, A. Majumder: Vektorsko nadzorovana zakasnilna celica s skoraj enakim casom vzpona/ padca za uporabo procesorske ure K. Orman, Y. Babacan: Uporaba logicnih vrat le z uporabo nevristorja na osnovi memristorja G. Nanjareddy, V. Mysuru Boregowda, C. Prasanna Raj: Nastavljiv modulator-demodulator s frekvencnim multipleksiranjem s 160 do 2560 ortogonalnimi podnosilci, zasnovan na arhitekturi sistolicnih polj s porazdeljeno vpogledno tabelo M. Vidmar: Razširitev Leesonove Enacbe Napoved in vabilo k udeležbi: 56. Mednarodna konferenca o mikroelektroniki, z delavnico o osebnih senzorjih za oddaljeno spremljanje zdravstvenega stanja Naslovnica: Simuliran OEO fazni šum. (M. Vidmar) Original scientific papers M. Konal, F. Kacar: Extended Bandwidth Method on Symmetrical Operational Transconductance Amplifier and Filter Application P. Bhattacharjee, B. K. Bhattacharyya, A. Majumder: Vector Controlled Delay Cell with Nearly Identical Rise/Fall Time for Processor Clock Application K. Orman, Y. Babacan: The Implementation of Logic Gates Using Only Memristor Based Neuristor G. Nanjareddy, V. Mysuru Boregowda, C. Prasanna Raj: Low Power Area Optimum Configurable 160 to 2560 Subcarrier Orthogonal Frequency Division Multiplexing Modulator-Demodulator Architecture based on Systolic Array and Distributive Arithmetic Look-Up Table M. Vidmar: Extending Leeson’s Equation Announcement and Call for Papers: 56th International Conference on Microelectronics, Devices and Materials with the Workshop on Personal Sensor for Remote Health Care Monitoring Front page: Simulated OEO phase noise. (M. Vidmar) https://doi.org/10.33180/InfMIDEM2021.201 Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 2(2021), 95 – 100 Extended Bandwidth Method on Symmetrical Operational Transconductance Amplifier and Filter Application Mustafa Konal1, Firat Kacar2 1Tekirdag Namik Kemal University, Electronics and Telecommunication Engineering Department, Tekirdag, Turkey 2Istanbul University-Cerrahpasa, Electrical and Electronics Engineering Department, Istanbul, Turkey Abstract: In this paper, a method for extending the bandwidth of a symmetrical operational transconductance amplifier (OTA) circuit is proposed. Resistive compensation technique is applied to all current mirrors of the symmetrical OTA circuit. A passive resistor is connected between the gate and the drain of each primary transistor of the current mirrors in the symmetrical OTA structure. The performance of the proposed OTA with extended transconductance bandwidth is analyzed by implementing filter structures. The advantage of using the resistive compensation technique is demonstrated. The proposed symmetrical OTA and the filters are simulated with LTSPICE by using TSMC 0.18 µm CMOS process parameters. Keywords: Symmetrical OTA, Extended bandwidth, Filter, Resistive compensation technique Metoda razširjene pasovne širine na simetricnem operacijskem ojacevalniku in filtru Izvlecek: V clanku je predlagana metoda za razširitev pasovne širine vezja simetricnega ojacevalnika (OTA). Tehnika uporovne kompenzacije je uporabljena na vseh zrcalih simetricnega vezja OTA. Pasivni upor je vezan med vrati in ponorom vsakega primarnega tranzistorja trenutnih zrcal v simetricni OTA strukturi. Ucinkovitost predlaganega OTA z razširjeno pasovno širino transkonduktance je analizirana z uporabo filtrirnih struktur. Dokazana je prednost uporabe uporovne kompenzacijske tehnike. Predlagani simetricni OTA in filtri so simulirani z LTSPICE v TSMC 0,18 µm CMOS tehnologiji. Kljucne besede: Simetricni OTA, razširjena pasovna širina, filter, tehnika uporovne kompenzacije * Corresponding Author’s e-mail: mkonal@nku.edu.tr 1 Introduction Operational transconductance amplifiers (OTA) are significant active elements for continuous-time signal processing applications. In the literature, many OTA based circuit blocks such as filters [1-6], oscillators [7-9], mem-elements [10-11] and inductance simulators [12-14] etc. have been reported. For several applications operating at high frequencies, it is necessary to use in­tegrated circuits with wide bandwidth. Therefore, a re­sistive compensation technique can be used to widen bandwidth of the circuits [15-17]. A wide bandwidth second-generation current conveyor based four-quad­rant mixed mode analogue multiplier is presented in [15]. A conventional low voltage cascode current mir­ror is analyzed in [16]. In this paper, a symmetrical operational transconduct­ance amplifier with extended transconductance band­width is proposed. Resistive compensation technique is applied to the current mirrors of the OTA in order to in­crease the transconductance bandwidth. The transcon­ductance of the OTA can be adjusted electronically by changing the biasing current and resistive compensa­tion technique can be applied to the circuit with dif­ferent resistor values. Temperature performance of the OTA is analyzed for different temperatures. In addition, in order to demonstrate the performance of the pro­posed OTA, it is used in a second order low-pass filter structure. Both symmetrical OTA and filter circuits are analyzed with LTSPICE using 0.18 µm TSMC CMOS pro­cess parameters. 2 Extended bandwidth symmetrical OTA Resistive compensation technique is applied to the symmetrical OTA in order to extend its bandwidth. A passive resistor is connected between the gate and drain of each main transistor of the current mirrors in the presented symmetrical OTA. The current mirror circuits without and with resistive compensation are given in Fig. 1a and Fig. 1b. (a) (b) Figure 1: Simple current mirror (a) without resistive compensation (b) with resistive compensation. Small signal models of the simple current mirrors with­out and with resistive compensation are given in Fig. 2a and Fig. 2b, respectively. (a) (b) Figure 2: Small-signal model of the current mirrors (a) without resistive compensation (b) with resistive com­pensation. By considering transistors M1 and M2 are identical, the relationship between the input and the output cur­rents is given in [15] as the following equations for the simple current mirror circuit for which the equivalent circuit given in Fig. 2a (Cgs1 = Cgs2 = Cgs, ro1 = ro2 = ro, gm1 = gm2 = gm). The bandwidth of the circuit depends on the gate-source capacitance Cgs and transconductance gm as given in Eq (2) [15]. (1) (2) After the resistive compensation technique is applied to a simple current mirror (equivalent circuit given in Fig. 2b), the relationship between the input and the output currents is given by Eq (3) [15]. By choosing the value of resistor as R = 1/gm, the expression for frequen­cy as given in Eq (4) is obtained. It can be seen from the equation that the bandwidth of the current mirror with compensation technique is increased by a factor of two compared to the simple current mirror [15]. (3) (4) The symbol and the CMOS realization of a symmetrical OTA with extended transconductance bandwidth are shown in Fig. 3a and Fig. 3b, respectively. The terminal relations of the symmetrical OTA is given by Eq (5) as follows; (5) The supply voltages and biasing current are chosen as VDD = – VSS = 1.5V and IB = 400 µA, respectively. The transconductance of the OTA is calculated as 1.02 mA/V and the passive resistors are taken as RP1 = RP2 = RN = 1/gm = 980.. The aspect ratios of the transistors are given in Table 1. The frequency dependence of the transcon­ductances of a symmetrical OTA without and with resis­tive compensation is given in Fig. 4a and the zoomed-in version is shown in Fig. 4b. It can be seen that the bandwidth of the gm is extended by approximately . The transconductance of the OTA can be adjusted by changing the biasing current IB. For values of biasing current 50 µA, 100 µA, 200 µA and 400 µA the trans­conductance of the symmetrical OTA is 796.9 µA/V, 925.4 µA/V, 986.5 µA/V and 1.02 mA/V, respectively. The dependence of transconductance on the value of compensation resistor is depicted in Fig. 5. In order to make the circuit suitable for analog integrated circuit implementations passive resistors can be replaced by MOS resistors. Table 1: Transistors aspect ratios. Transistors W(µm) L(µm) M1, M2 0.72 0.18 M3, M4, M5, M6 1.8 0.18 M7, M8 5.4 0.18 VDD=-VSS=1.5 V, IB=400 µA, RP1=RP2=RN=980 . Figure 5: Transconductance gains of the symmetrical OTA without and with resistive compensation for differ­ent biasing currents. The temperature performance of the symmetrical OTA with resistive compensation is simulated for the resis­tor values of 1.25 k. and 980 . for various tempera­tures from 0oC to 100oC as shown in Fig. 6. It can be seen from the figure that the transconductance of the OTA decreases with increasing temperature. Figure 6: Temperature performance of the symmetri­cal OTA with resistive compensation. 3 Filter application of the symmetrical OTA A filter structure is proposed to demonstrate the ad­vantage of using the resistive compensation tech­nique. The proposed filter based on symmetrical OTA is given in Fig. 7. Figure 7: Filter structure based on symmetrical OTA. The proposed circuit can simultaneously realize low-pass, high-pass, and band-pass filter functions. De­pending on the voltage status of Vin1, Vin2, and Vin3, one of the following three filter functions is realized: i) Vin1 = Vin and Vin2 = Vin3 = 0, second order low-pass filter. ii) Vin2 = Vin and Vin1 = Vin3 = 0, second order band-pass filter. iii) Vin3 = Vin and Vin1 = Vin2 = 0, second order high-pass filter. Fig. 8 shows the gain-frequency responses of all filter structures designed for cutoff frequency of 3.25 MHz. The passive capacitor values are chosen as C1 = C2 = 50 pF. Symmetrical OTAs with resistive compensation given in Fig 3b are used as active elements. Figure 8: Gain-frequency responses of the symmetrical OTA based filter structures. The gain-frequency responses of the low-pass filter based on symmetrical OTA with resistive compensa­tion technique for the resistor values of 980 . and 1.25 k. are shown in Fig. 9. The bandwidth of the filter is extended from 3.2 MHz to 3.9 MHz as shown in Fig. 9b and improved about 18%. (a) (b) Figure 9: (a) Gain-frequency responses of the low-pass filters based on symmetrical OTA with resistive com­pensation (b) zoomed-in version. 4 Conclusion In this study, a symmetrical OTA structure with extend­ed transconductance bandwidth is proposed. Resis­tive compensation technique is applied to the current mirrors of the OTA structure. Due to the use of resistive compensation, bandwidth of the symmetrical OTA is improved. Using resistors and matching them to the gm value adjusted using the biasing currents of the OTA, the bandwidth can be increased. Furthermore, the transconductance value of the OTA with resistive compensation is simulated for the varied temperatures and the improved performance is demonstrated. Pas­sive resistors can be replaced by MOS resistors in or­der to make the circuit suitable for analog integration. Additionally, a low-pass filter circuit is realized with the proposed OTA and the gain-frequency response of the filter is analyzed. Bandwidth of the filter is extended by 18%. The simulations of the symmetrical OTA and filter structures are performed with LTSPICE using 0.18 µm TSMC CMOS technology. 5 Conflict of interest We have no conflict of interest to declare. 6 References 1. Psychalinos, C., Kasimis, C., & Khateb, F. (2018). Multiple-input single-output universal biquad filter using single output operational transcon­ductance amplifiers. AEU-International Journal of Electronics and Communications, 93, 360-367. https://doi.org/10.1016/j.aeue.2018.06.037 2. Bano, S., Narejo, G. B., & Shah, S. U. A. (2019). Low Voltage Low Power Single Ended Operational Transconductance Amplifier for Low Frequency Applications. Wireless Personal Communica­tions, 106(4), 1875-1884. https://doi.org/10.1007/s11277-018-5726-1 3. Ali, H. K., & Abdaljabar, J. S. (2017). Analysis and Simulation of Active Filters Using Operational Transconductance Amplifier (OTA). European Sci­entific Journal, 13(15), 170-184. https://doi.org/10.19044/esj.2017.v13n15p170 4. Mathad, R. S. (2014). Low frequency filter de­sign using operational transconductance ampli­fier. IOSR Journal of Engineering (IOSRJEN), 4(4), 21-28. https://doi.org/10.9790/3021-04462128 5. Rezaei, F., & Azhari, S. J. (2011). Ultra low voltage, high performance operational transconductance amplifier and its application in a tunable Gm-C fil­ter. Microelectronics Journal, 42(6), 827-836. https://doi.org/10.1016/j.mejo.2011.04.012 6. Abuelma’Atti, M. T., & Quddus, A. (1996). Program­mable voltage-mode multifunction filter us­ing two current conveyors and one operational transconductance amplifier. Active and passive electronic components, 19(3), 133-138. https://doi.org/10.1155/1996/29750 7. Prommee, P., & Dejhan, K. (2002). An integrable electronic-controlled quadrature sinusoidal os­cillator using CMOS operational transconduct­ance amplifier. International Journal of Electron­ics, 89(5), 365-379. https://doi.org/10.1080/713810385 8. Abuelma’Atti, M. T., & Khan, M. H. (1996). Ground­ed capacitor oscillators using a single operational transconductance amplifier. Active and passive electronic components, 19, 91-98. https://doi.org/10.1155/1996/17943 9. Senani, R., & Kumar, B. A. (1989). Linearly tunable Wien bridge oscillator realised with operational transconductance amplifiers. Electronics Let­ters, 25(1), 19-21. https://doi.org/10.1049/el:19890014 10. Babacan, Y. (2018). An Operational Transconduct­ance Amplifier-based Memcapacitor and Memin­ductor. Electrica, 18(1), 36-38. https://doi.org/10.5152/iujeee.2018.1806 11. Taskiran, Z. G. C., Ayten, U. E., & Sedef, H. (2019). Dual-output operational transconductance am­plifier-based electronically controllable mem­ristance simulator circuit. Circuits, Systems, and Signal Processing, 38(1), 26-40. https://doi.org/10.1007/s00034-018-0856-y 12. Koomgaew, C., Petchmaneelumka, W., & Riewruja, V. (2009, August). OTA-based floating inductance simulator. In 2009 ICCAS-SICE (pp. 857-860). IEEE. 13. Jaikla, W., & Siripruchyanan, M. (2006, October). Floating positive and negative inductance simu­lators based on OTAs. In 2006 International Sym­posium on Communications and Information Technologies (pp. 344-347). IEEE. 14. Singh, V. (2003). Floating operational transcon­ductance amplifier based grounded imped­ance. IEE Proceedings-Circuits, Devices and Sys­tems, 150(1), 27-30. https://doi.org/10.1049/ip-cds:20030367 15. Ettaghzouti, T., Hassen, N., Garradhi, K., & Besbes, K. (2018). Wide bandwidth CMOS four-quadrant mixed mode analogue multiplier using a second generation current conveyor circuit. Turkish Jour­nal of Electrical Engineering & Computer Scienc­es, 26(2), 882-894. https://doi.org/10.3906/elk-1708-179 16. Gupta, M., Singh, U., & Srivastava, R. (2014). Band­width extension of high compliance current mir­ror by using compensation methods. Active and passive electronic components, 2014. https://doi.org/10.1155/2014/274795 17. Voo, T., & Toumazou, C. (1995). High-speed current mirror resistive compensation technique. Elec­tronics Letters, 31(4), 248-250. https://doi.org/10.1049/el:19950207 Arrived: 28. 11. 2020 Accepted: 07. 04. 2021 M. Konal et al.; Informacije Midem, Vol. 51, No. 2(2021), 95 – 100 M. Konal et al.; Informacije Midem, Vol. 51, No. 2(2021), 95 – 100 (a) (b) Figure 3: a) Circuit symbol b) CMOS realization of a symmetrical OTA with extended transconductance bandwidth. (a) (b) Figure 4: (a) Transconductances of the symmetri­cal OTA without and with resistive compensation (b) zoomed-in version. M. Konal et al.; Informacije Midem, Vol. 51, No. 2(2021), 95 – 100 M. Konal et al.; Informacije Midem, Vol. 51, No. 2(2021), 95 – 100 M. Konal et al.; Informacije Midem, Vol. 51, No. 2(2021), 95 – 100 Copyright © 2021 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. https://doi.org/10.33180/InfMIDEM2021.202 Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 2(2021), 101 – 112 Vector Controlled Delay Cell with Nearly Identical Rise/Fall Time for Processor Clock Application Pritam Bhattacharjee1, Bidyut K. Bhattacharyya2, Alak Majumder3 1Department of Computer Science & Engineering, Amrita Vishwa Vidyapeetham, Amritapuri, Kerala, India. 2Packaging Research Center at Georgia Institute of Technology, Atlanta, USA. 3National Institute of Technology (NIT), Department of Electronics & Communication Engineering, Integrated Circuit And System (i-CAS) Laboratory, Arunachal Pradesh, India. Abstract: In the design of modern processor chips, proper clock distribution is a very important aspect which impacts the chip performance. It is the active cell of delay circuits and cells with variable delay that have the major involvement in clock distribution, thereby deciding the time slacks of all functionalities inside the chip. Because they help in proper input to output signal transmission with the adjustment of variable timing delays and monitor the output signal to have equal rise/fall time, which most of the existing delay elements fail to deliver. Therefore in this article, we have proposed an input vector based design of variable delay with balanced rise time and fall time for the output signal. We have also estimated the delay and output voltage in terms of a mathematical model. This new configuration is executed across the commercial platform of Cadence Virtuoso® using 90nm technology node while steered by a 1GHz input signal and power supply of 1.1 V. The execution outcome confirms the desired features of our proposed design under typical conditions and even in process corner variations. Keywords: vector-controlled circuit design; variable delay cell, Rise/Fall time; Processor Clock; CMOS process technology Vektorsko nadzorovana zakasnilna celica s skoraj enakim casom vzpona/ padca za uporabo procesorske ure Izvlecek: Pri zasnovi sodobnih procesorskih cipov je ustrezna razporeditev ure zelo pomemben vidik, ki vpliva na delovanje cipa. Aktivna celica zakasnilnih vezij in celic s spremenljivo zakasnitvijo ima glavno vlogo pri porazdelitvi ure in tako odloca o casovnih zakasnitvah vseh funkcij znotraj cipa. Pomaga pri pravilnem prenosu vhodnega signala s prilagoditvijo spremenljivih casovnih zamikov in nadzoruje izhodni signal, da ima enak cas vzpona / padca, kar vecina obstojecih elementov zakasnitve ne dosega. V clanku predlagamo zasnovo spremenljive zakasnitve na osnovi vhodnega vektorja z uravnoteženim casom vzpona in padca izhodnega signala. Zakasnitev in izhodno napetost smo ocenili z matematicnim modelom. Nova konfiguracija se izvaja na komercialni platformi Cadence Virtuoso® z uporabo 90nm tehnologije s 1 GHz krmilnim signalom in napajanjem 1.1 V. Rezultat izvedbe potrjuje želene znacilnosti našega predlaganega nacrta v tipicnih in netipicnih pogojih. Kljucne besede: zasnova vektorsko krmiljenega vezja; celica s spremenljivo zakasnitvijo; cas vzpona / padca; procesorska ura; tehnologija CMOS * Corresponding Author’s e-mail: pritambhattacharjee@am.amrita.edu 1 Introduction Since the past few decades, we are able to witness a lot of advancement in the consumer electronics like com­puters, computer accessories, mobile phones as well as their inner components for example, central-process­ing-unit (CPU) or even the graphics-processing-unit (GPU). Semiconductor giants like Intel, AMD and QUAL­COMM have successfully brought up the discrete-level integration of CPU and GPU on a single platform [1, 2]. However, as result of this integration, clock signaling and its efficient routing have become very important in order to maintain proper functioning and performance of each CPU and GPU. The efficacy of clock signaling and transmission to CPU/GPU is ascertained by the components involved in clock distribution as seen from Fig. 1(a). Basically, the clock signal traverses through multi-buffer stages (in the form of tree-like structure, viz. clock tree) before reaching the dedicated CPU, Graphics or PCIe sockets. All these units operate at dif­ferent frequencies, but they are supposed to function in parallel. Therefore, the timing parameters involved in the signal transmission are always a matter of concern so as to extract the best performance out of the end-product [3]. (a) (b) Figure 1: (a) Typical style of clock distribution inside a processor chip (b) clock tree design. In fact, it is these buffers which play a crucial role in forming the clock tree for the clock distribution net­work (CDN) as shown in Fig. 1(b), wherein, CDN is pur­posed to output a synchronizing signal to coordinate the functioning of each circuit block inside the pro­cessor chip. The buffers of clock tree set up the delay for signal transmission along the branches of tree so that the timing of signals can be balanced at each and every node (or leaf as directed in Fig. 1(b)) connected to the units like CPU, graphics or PCIe socket. However, the delay incorporated through these buffer cells is of constant value and most often it is required to use dif­ferent sized buffers (i.e., the sizes of Buffer_1 . Buffer_2 . Buffer_3 and so on) such that the clock arrival time across all sequential elements inside CPU or GPU chip remains synchronized. But, nowadays the CDN design­ers are more interested and dependent on the use of var­iable delay cells (with proper control to adjust the delay variability) so that the clock trees inside CDN are more versatile in terms of their functioning. In fact, the use of variable delay cells is quite popular in other CDN com­ponents like locked loops (both DLL and PLL), oscillators, frequency multipliers and dividers and many other Sys­tem-on-Chips (SoCs). As a matter of fact, the use of these delay elements in the form of cluster (i.e., delay line) is also popular for the construction of SoC time measure­ment circuits (TMC) that are installed to measure internal timing parameters of the chip [4-6]. Hereby, the design creditability of delay circuits offering fine-tuned values of delay indirectly supports the working performance of TMCs. Nevertheless, the circuit design of such delay elements for modern SoCs is difficult to tackle because of their own trade–offs in design specifications and the concern is also relatively high while considering their in­volvement in the computational aspects of embedded systems [7]. Therefore, many researchers and circuit de­signers have invested themselves in the development of different delay circuits. 1.1 Background of delay cell design Although the research on delay circuit design has been present for quite a long time and there are several liter­atures, but we have focused on basic design structures like transmission gate-controlled delay cell element (Trans-DE) [8,9], concatenated inverter-controlling de­lay cell element (viz., CI-DE) [8, 10] and current starved controlling delay element (viz., CS-DE) [8, 10]. Up to now, any circuital modifications done on the delay circuit design revolve around this delay cell primitives and all of them produce delay based on the change of physical dimensions of devices used in the architecture. But nowadays, substantial research is invested into the design of delay cell architectures with fixed dimensions that are capable of generating variable delay values at the output. Such design was pioneered with the ad­vent of Vernier Delay Line (VDL) [12, 13], as presented in Fig. 2. It has many buffers that are connected along the customised rows and columns. The delays intro­duced by a buffer is equal to one of two values §1 and §2 (§1.§2). The delay value obtained at a circuit node is given by depending on input cycle time viz., ‘t’. The magnitude difference of §1 and §2 (i.e., |§1-§2|) represents the adjustability of the delay in this design. As the buffers are typically designed using complementary metal-oxide-semiconductor (CMOS) technology, the input gate of every MOS along the cus­tomised rows and columns serves as the knob to tune the delay value, which is not convenient and the archi­tecture is unnecessarily crowded. Figure 2: Design style of Vernier delay line [12]. In [14] the concept of Voltage Controlled based Delay Element i.e., VC-DE was presented. This has also been the foundation for designing digitally-controlled or even the digital-based programmable delay elements (DC-DE/DP-DE). From design prospective, DC-DE is not much different from DP-DE and they are treated as a sub-class of vector-controlled delay elements. The changes of delay value in DC-DE or DP-DE are based on the various combinations of input vectors [15-17]. In case of VC-DE, typically different bias/control volt­ages are employed to obtain the variable delay values. However, the design layover of both DC-DE, VC-DE along with DP-DE centres on the concept of controlling terminal voltages/currents across MOS devices of the fundamental designs viz., Trans-DE, CI-DE, also some­times the CS-DE. The value of channel resistance (RON) when the device is ON and the logical gate capacitance (CG’) as stated in equation (1) and (2) directly impact the propagation delay (t = RON × CG’) of the delay circuit [18, 19]. (1) (2) Parameter ‘k’ comprises of device related terms, VGS is the gate-to-source voltage, Vth is threshold voltage of MOS devices, Vdd is the power supply voltage, and .QG is the gate charge which depends on VGS [20]. The matter of associating DC/DP with the delay circuits is to make the delay cell design strong and stable. It is the proper capacity of these DC/DP techniques to tune the delay values which determine how they can gen­erate variable delay at the output. So, it is important to understand how well these techniques suit with the fundamental delay elements. 1.2 Consequences in the design of delay cell structures During the literature survey, we concluded that the DC/DP-DE implementation is more compatible with delay elements viz., CI-DE and CS-DE, instead of being incor­porated with Trans-DE. The reason for this can be seen in Fig. 3(a) where the n-channel MOS (nMOS) i.e., M2 and the p-channel MOS (pMOS) i.e., M1 of the transmis­sion gate (TG) are ON for most of the time to maintain proper signaling integrity from the input (Vin) to the output (herein, the node ‘P’) and results in a significant amount of power dissipation across Vdd. That questions the appropriateness of the Trans-DE cell design. (a) (b) Figure 3: (a) CMOS based Schmitt trigger attached to TG (b) Design style of CI-DE. The CI-DE, being one of the primitive architectures of delay elements comprises of 2 CMOS inverters back-to-back depicted in Fig. 3(b). Its physical time delay is giv­en by equation (3) where ‘CA’ is the capacitance across node ‘A’ and Vout is the amount of voltage change at the output. (3) In this case, ‘I’ denotes the charging current and the discharging current (viz., Ich and Idis, respectively) based on input steady-state condition. When these delay ele­ments (i.e., specifically CI-DE) are being used in on-chip sections like CDN, it is really important that the output rise/fall time (viz., trise/tfall or also indicated as rise/fall delay) of the delay element is almost equal. The near-symmetric rise/fall time is required or else there are many negative consequences that appear inside the chip signaling such as the inequality in the clock pulse-width which results in variation of the ON-OFF time as shown in Fig. 4. Figure 4: Output signal depicted across the operation of CI-DE. If Ich=Idis, trise is equal to tfall which results in equal ON-OFF time for a clock signal. In a CI-DE it is not possible to guarantee Ich=Idis since it is a CMOS inverter based de­sign. This kind of design has a pull-up section made of pMOS transistors that charge-up the output load and a pull-down section that discharges it through nMOS transistors. The device dimension of nMOS and pMOS must differ for CI-DEs to match the charge-carrier mo­bility because nMOS transistors have a higher mobility than pMOS transistors. To compensate this difference, pMOS transistors must have greater channel width. Due to this CI-DE a not a symmetric architecture which can deliver nearly balanced output timing components (viz. rise time and fall time). Even if the input signal has trise=tfall, the CI-DE output fails to replicate this and the effect is further increased by a long buffer chain. Since our concern is the delay elements of CDN, it can be inferred that the output of CI-DE (if used inside CDN) will have a tendency to incorrectly drive the on-chip sequential circuits, especially the ones that are level-trigger sensitive. So, it is quite important that Ich and Idis are matched. For that, some extra transistors are added to CI-DE (viz., P3 and N3 as shown in Fig. 5(a)), the design which is commonly referred as CS-DE. The use of P3 and N3 is to provide a source of current flowing from Vdd such that the values of Ich and Idis can be matched. However in the design of CS-DE, there are also P4 and N4 that have current limiting features and obstruct the sup­ply voltage-level to the inverter (constituted by P2 and N2). This even has the possibility to induce power sup­ply noise into the CS-DE output impacting the output signal integrity. Often, the design structure of CS-DE is improvised as shown in Fig. 5(b) so that this problem can be avoided. Initially, most of its nodes in CS-DE (viz., M and N) are stuck-at logic ‘0’ which allows P1 to be ON and therefore the output node ‘out’ is high. This ena­bles P3 and N3 to be OFF at an early stage. Though the logic state of ‘N4’ is dependent on the input ‘in’, it does not impact the real-time signal transmission of ‘in’ to ‘out’. This stability in the transmission is due to a CMOS inverter in addition to an nMOS ‘N1’ at the output. Inter­estingly, this version of CS-DE provides matching rise/fall delay by tweaking the charging as well as discharg­ing capacitances (viz., Co1 and Co2 respectively) across the output. Despite this the problem still prevails i.e., Ich.Idis (since the paths of Co1 and Co2 are different) and as a whole that affects the magnitude of trise and tfall. Above all, prevalent DC/DP techniques [15-17] which are utilized for obtaining the different values of delay possibly enhance the difference in expected equality that Ich also Idis should have. In fact, the problem is there in almost all the kinds of delay circuits as reviewed and displayed in Table 1. Very few circuit designers has looked into this aspect and tried to balance rise delay of the output with its fall delay. Hence, it is our motiva­tion to design a new delay element delivering almost equal values of Ich and Idis such that it is able to gen­erate near symmetric output trise and tfall. Besides, we have also concentrated on using a DC/DP based tech­nique which will help to generate variable delay using the proposed delay element. This technique can be thought of as simplistic all-digital approach to produce variable delay at the output having near symmetric trise/tfall. 1.3 Organization of this article This article is structured as follows: In section 2, we provide justification for our proposed circuit design. In section 3, we introduce the new design of delay ele­ment and demonstrate a simple mathematical model. We also introduce our alternative approach to DC/DP technique in the same section. The performance analy­sis of the whole circuit setup is described in section 4. In the last section 5, we conclude our work by stating once again the relevancy of our proposed delay circuit design in modern processor systems. 2 Major Highlights An efficient design of a delay circuit is only possible if the outputs exhibit almost equal trise/tfall. So in this arti­cle, we have focused on a delay cell structure such that it is efficient in projecting varied input-to-output physi­cal time delay based on the tweaking of proposed al­ternative of DC/DP technique and also the output sig­nal is able to feature trise˜tfall. The contents of this article are as follows: - Need of variable delay cells in modern processors. - Development of new delay cell complying with nearly balanced output timing components (viz. rise time and fall time). - Constructing an alternate of DC-DE or DP-DE methodology to control variant values of delay across the proposed delay cell. - Detailed performance analyses of schematic and layout based proposed vector-controlled variable delay cell using 90nm process design kit (PDK) [21]. 3 The New Design of CI-DE It has been mentioned earlier that the current designs of CI-DE is not capable of delivering equal trise and tfall at its output. The major issue is non-symmetric design of pull-up-network (PUN) and pull-down-network (PDN) in CMOS based inverters. Despite this, circuit design­ers have been relying on CI-DE design structure and in most cases improvised by adding intermediate shunt capacitors. By doing so, the symmetricity within PUN and PDN is adjusted [22]. But, fabrication of these shunt capacitors in any deep sub-micron technology is difficult. However, an effective solution would be to embed MOS based resistors and capacitors in the CI-DE design instead of using shunt capacitors. In fact, this approach was first published in [20]. It is shown in Fig. 6(a) where the resistance (R1) and the capacitance (C) are placed adjacent to the inverter output as well as another resistance (R2) is placed underneath the pull-down section. Nevertheless, these R1, R2 and C were not MOS-based cells and using them was not efficient in terms of layout design. (a) (b) Figure 6: (a) Inverter design from [23] (b) improvised version based on the circuit from figure 6(a) which is the basis for the new CI-DE. The inverter design in Fig. 6(a) delivered a good amount of propagation delay, provided R2=0. (or there was is­sues in determining output logic level ‘0’) and R1>>R2. Though the value of R1 could be managed, adjusting the value R2 to 0. was technically quite difficult us­ing MOS devices as intrinsic parameters always affect the device ON resistance to some extent. To solve this problem, we modified the circuit in Fig. 6(a) by discard­ing R2 and implementing R1 and C as MOS based resist­ance and capacitance respectively. Since nMOS is faster logic compared to pMOS [24, 25], we have preferred the nMOS based representation of resistance and ca­pacitance. 3.1 Mathematical model of delay estimation Based on the circuit of Fig. 6(a), a different kind of CI-DE is obtained as shown in Fig. 6(b). It can be seen from the fundamentals depicted in equation 1(a) that there can be variation in the value of RON depending on the change in VGS and Vth. In this design, RON of T3 and T7 can be varied based on the value of their common VGS (denoted by ‘X’ in Fig. 6 (b)). Now considering the first modified inverter in Fig. 6(b), let us assess the magni­tude of output voltage at node ‘C’ and the amount of propagation delay incurred. While the node ‘C’ switches from high to low, the nMOS ‘T2’ is in saturation. There­fore, the current flowing across ‘T2’ is given by: (4) In equation (4), where µn is the coefficient of electron carrier mobility and Cox is the oxide-capac­itance per unit area, W/L is the aspect ratio of ‘T2’, VTn is threshold voltage of nMOS. The value of I2 may be put in equation (3) and we have: , where CT4 is the capacitance of the MOS capacitor ‘T4’, VC is potential at node ‘C’. (5) For equation (5), we have not considered to include the squared terms while solving (Vin(t)-VTn)2. Such kind of condition can be taken in account when Vin< f0/(2QL) larger than the Lee­son’s frequency, the oscillator has little effect on the noise spectral density. Other circuits like buffer ampli­fiers, limiters and/or attenuators add their own thermal noise. If required, this thermal noise can easily be fil­tered away using resonators with a similar QL as used in the oscillator itself. At frequency offsets |.f |< f0 /(2QL) smaller than the Leeson’s frequency, the predominant noise is the oscil­lator phase noise. Other circuits like amplifiers, limiters and/or attenuators have little effect on the phase-noise spectral density. The oscillator phase noise can NOT be filtered away using resonators with a similar QL as used in the oscillator itself. Since the oscillator phase-noise is the interesting quan­tity, a simplified Leeson’s equation neglecting thermal noise is frequently used: (21) The result of the simplified Leeson’s equation is shown as a dotted extension on Fig. 4. There is a significant difference from the full equation only at large offsets |.f |> f0 /(2QL )˜150 MHz in the example shown on Fig. 3 and Fig. 4. The Leeson’s equation was derived assuming that the noise amplitude UNout « U0 (.0) is much smaller than the desired-carrier amplitude. This assumption no longer holds at small offsets .f. The Leeson’s equation only holds when the relative phase-noise spectral den­sity is much smaller than the L(.f )«.f -1 limit shown with a dotted line on Fif. 4. In practice, the result on Fig. 4 is only valid at offsets above |.f |>1 kHz. The relative phase-noise density at very small offsets .f is usually not very important in practical electronic os­cillators. It is much more important in laser oscillators. A corrected derivation of the Leeson’s equation for very small offsets .f will be presented later. 4 Effects of phase noise Phase noise was first noted as residual frequency mod­ulation in analog radio links. The unwanted random frequency deviation (root-mean-square value) can be calculated as: (22) The frequency limits fMIN and fMAX of the integral are the band limits of the analog base-band modulation signal. In QAM radio links, phase noise randomly rotates the constellation of the modulation. The unwanted ran­dom angle of rotation (root-mean-square value) can be calculated as: (23) Any phase noise above .f > Bmodulation is filtered away by the channel filter in the receiver. Further it is assumed that the carrier-recovery circuit of the receiver is able to track slow frequency and/or phase changes below .f < Bcarier - recovery. In digital communications, phase noise manifests itself as clock jitter. The unwanted clock jitter (root-mean-square value) can be calculated as: (24) Limiting the bandwidth of the clock, the upper limit fMAX < f0 is less than the clock frequency. Further it is assumed that the clock-recovery circuit of the receiver is able to track slow frequency and/or phase changes below .f < Bclock - recovery. Finally in all radio communications, phase noise causes interference to neighbor channels. The interference power can be calculated as: (25) The frequency limits .f1 and .f2 of the integral are the frequency offsets of the interfered channel from the in­terfering carrier P0(f0 ). Note that all of the above-mentioned integrals start from an offset .f > 0 larger than zero. Radio equipment is usually designed to work with relatively clean sources where the phase-noise power PN. « P0 is much smaller than the carrier power and the Leeson’s equation is valid thanks to L(.f ) « .f -1 in the region of interest. 5 Active-device noise Besides thermal noise, active devices also add flicker noise to the amplified signal. Flicker noise is usually described as an increase of the radio-frequency noise figure F into a frequency-dependent noise figure F'(f ): (26) The parameter describing flicker noise is the corner fre­quency fC. The latter depends on the device technol­ogy [3]. In general, surface devices have higher current densities and more structure defects than bulk devices. Surface semiconductor devices like a silicon MOSFET, a GaAs MESFET or a GaAlAs HEMT may have the corner frequency in the range fC˜1…10 MHz. Bulk semicon­ductor devices like a silicon BJT or a silicon JFET may have the corner frequency in the range fC ˜ 1…10 kHz. Although a HEMT may produce slightly less noise at radio frequencies than a BJT, a HEMT is significantly noisier at low frequencies than a BJT as shown on Fig. 5: Figure 5: Active device noise figure. In an oscillator, the active device operates in saturation while producing steady oscillations. The nonlinear ef­fects associated with saturation up-convert the low-frequency flicker noise into noise side bands very close to the carrier radio frequency. High-performance radio-frequency (microwave) oscillators therefore use silicon bipolar transistors due to their lower flicker noise. The additional up-converted flicker noise can be built into the Leeson’s equation describing the increase the oscillator phase noise at small offsets |.f |f0/(2QL) larger than the Lee­son’s frequency, the oscillator has little effect on the noise while other circuits add their own noise. It therefore makes sense to evaluate (32) at small offsets |.f | 0. Besides bandwidth differences of many orders of magnitude, an electronic oscillator produces a similar signal to the spark radio transmitter or filtered white light in optics. 10 Conflict of Interest The author declares no conflict of interest. The founding sponsors had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, and in the deci­sion to publish the results. 11 References 1. D. B. Leeson, “A Simple Model of Feedback Oscilla­tor Noise Spectrum”, Proceedings of the IEEE 54 (2), February 1966, pp. 329–330, https://doi.org/10.1109/PROC.1966.4682 2. Wikipedia, “Leeson’s equation” https://en.wikipedia.org/wiki/Leeson%27s_equation [Accessed: 08-Feb-2021] 3. Wikipedia, “Flicker noise” https://en.wikipedia.org/wiki/Flicker_noise [Accessed: 05-Apr-2021] 4. M. Vidmar, “TV Satellite Receive System, Part 2: In­door Unit”, VHF COMMUNICATIONS 1/87, pp. 35-56, ISSN 0177-7505 5. R. Poore, “Overview on Phase Noise and Jitter”, Agilent Technologies, 2001, http:// cp.literature.agilent.com/litweb/pdf/5990-3108EN.pdf [Ac­cessed: 01-May-2013] 6. F. Herzel, “An Analytical Model for the Power Spec­tral Density of a Voltage-Controlled Oscillator and Its Analogy to the Laser Linewidth Theory”, IEEE Transac­tions on Circuits and Systems – I: Fundamental Theo­ry and Applications, vol. 45, pp. 904–908, Sept. 1998. 7. E. Rubiola, “The Leeson Effect - Phase Noise in Quasilinear Oscillators”, https://arxiv.org/abs/physics/0502143v1 [Accessed: 17-Feb-2021] 8. L. Bogataj, M. Vidmar, B. Batagelj,“Opto-Electronic Oscilla­tor With Quality Multiplier”, IEEE Transactions on Micro­wave Theory and Techniques, January 2016, 64(2):1-6, https://doi.org/10.1109/TMTT.2015.2511755 9. E. H. Armstrong, “Signaling System”, US patent 1424065, July 25, 1922. 10. Wikipedia, “Ultraviolet catastrophe” https://en.wikipedia.org/wiki/Ultraviolet_catastrophe [Accessed: 24-Apr-2021] Arrived: 18. 02. 2021 Accepted: 20. 05. 2021 M. Vidmar; Informacije Midem, Vol. 51, No. 2(2021), 135 – 146 M. Vidmar; Informacije Midem, Vol. 51, No. 2(2021), 135 – 146 M. Vidmar; Informacije Midem, Vol. 51, No. 2(2021), 135 – 146 M. Vidmar; Informacije Midem, Vol. 51, No. 2(2021), 135 – 146 M. Vidmar; Informacije Midem, Vol. 51, No. 2(2021), 135 – 146 Figure 6: Phase noise including flicker noise. M. Vidmar; Informacije Midem, Vol. 51, No. 2(2021), 135 – 146 Figure 7: Oscillator bias circuit. M. Vidmar; Informacije Midem, Vol. 51, No. 2(2021), 135 – 146 Figure 8: Lorentzian spectral line. M. Vidmar; Informacije Midem, Vol. 51, No. 2(2021), 135 – 146 M. Vidmar; Informacije Midem, Vol. 51, No. 2(2021), 135 – 146 M. Vidmar; Informacije Midem, Vol. 51, No. 2(2021), 135 – 146 M. Vidmar; Informacije Midem, Vol. 51, No. 2(2021), 135 – 146 Copyright © 2021 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Call for papers Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 2(2021), 147 – 147 MIDEM 2021 56th INTERNATIONAL CONFERENCE ON MICROELECTRONICS, DEVICES AND MATERIALS WITH THE WORKSHOP ON PERSONAL SENSOR FOR REMOTE HEALTH CARE MONITORING September 22nd – September 24th, 2021 Faculty of Electrical Engineering, Ljubljana, Slovenia Announcement and Call for Papers Chairs: Prof. dr. Janez Trontelj (UL FE) Doc. Dr. Aleksander Sešek (UL FE) IMPORTANT DATES Abstract submission deadline: May 1, 2021 Acceptance notification: June 15, 2021 Full paper submission deadline: July 31, 2021 Invited and accepted papers will be published in the Conference Proceedings. Deatailed and updated information about the MIDEM Conferences, as well as for paper preparation can be found on http://www.midem-drustvo.si/ GENERAL INFORMATION The 56th International Conference on Microelectronics, Devices and Materials with the Workshop on Personal Sensor for Remote Health Care Monitoring continues a successful tradition of the annual international conferences organized by the MIDEM Society, the Society for Microelectronics, Electronic Components and Materials. The conference will be held at Faculty of Electrical Engineering, Ljubljana, Slovenia from SEPTEMBER 22nd – September 24th, 2021. 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Dr. Hana Uršic Nemevšek, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Danilo Vrtacnik, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Supervisory Board | Nadzorni odbor Prof. Dr. Franc Smole, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Prof. Dr. Drago Strle, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Igor Pompe, retired Court of honour | Castno razsodišce Darko Belavic, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Miloš Komac, retired Dr. Hana Uršic Nemevšek, Jožef Stefan Institute, Ljubljana, Slovenia Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials ISSN 0352-9045 Publisher / Založnik: MIDEM Society / Društvo MIDEM Society for Microelectronics, Electronic Components and Materials, Ljubljana, Slovenia Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale, Ljubljana, Slovenija www.midem-drustvo.si