HOT WIRE DEPOSITED MATERIALS FOR THIN FILM TRANSISTORS R.E.I. Schropp, B. Stannowski, and J.K. Rath Utrecht University, Debye Institute, Physics of Devices, Utrecht, The Netherlands INVITED PAPER MIDEM 2001 CONFERENCE 10.10.01 -12.10.01, Hotel Zlatorog, Bohinj Key words: semiconductors, microelectronics, hot wire technologies, CVD, Chemical Vapour Deposition, HWCVD, Hot Wire CVD, Hot Wire Chemical Vapour Deposition, imaging devices, image sensors, image displays, scanners. X-ray imagers, TFT, Thin Film Transistors, a-Si:H TFT technologies, Hydrogenated amorphous Silicon Thin Film Transistor technologies, cost reduction Abstract: Thin film transistors (TFTs) find widespread application as the switching element in active matrix (AM) liquid crystal displays (LCD), such as the TFT display used in lap top computers, but also in 2-dimensional imaging devices, such as document scanners or in digital X-ray imagers for medical applications. This paper addresses the new challenges that exist in research and development of TFTs: 1) TFTs on plastic substrates, 2) low-temperature poly-silicon (LTPS) for the pixel TFTs and for row and column drivers on glass; 3) addressing of OLEDs (Organic Light Emitting Diodes) by silicon TFTs. For these advanced applications of TFTs the relevant issues are: (i) higher electron mobility, (ii) stability, and (Iii) defect free, uniform deposition of thin silicon films and gate dielectrics at a high deposition rate {for reduced cost). Whereas a high deposition rate is generally needed to reduce the production cost, for novel high current applications the latter two issues have recently become more essential. At Utrecht University, we are investigating Hot Wire (Catalytic) CVD as a deposition technique for novel TFTs that have a high potential to meet the above mentioned requirements. In Hot Wire CVD, the source gases are catalytically decomposed at heated tungsten or tantalum filaments (~ 1800 "O, whereas the substrate is kept at a low temperature. Hydrogenated amorphous silicon (a-Si:H) with device quality can be deposited at a high rate of 1-5 nm/s. Bottom gate, inverted staggered TFTs with Hot Wire CVD silicon films have been made with an electron mobility of 1.5 cm^/Vs, and with field effect characteristics that are completely stable under operating conditions. Top gate, coplanar TFTs with polycrystalline silicon films have been made, showing a mobility of 4.7 cmVVs, in agreement with the Hall mobility measured in individual thin films. This has been obtained without any post deposition treatment, and the Hot Wire technology can thus avoid expensive, time-consuming steps such as the laser recrystallization step that is currently used in the production of the latest poly-Si lap top displays. Hot Wire CVD is also suitable for the deposition of silicon nitride (SiNx:H) gate dielectrics. TFTs with a Hot Wire silicon nitride gate dielectric, deposited below 400 °C, have reached a mobility of 0.6 cm^/Vs and a threshold voltage of 2.9 V. Nanos materialov z metodo vroče žice pri izdelavi tankoplastnih tranzistorjev Ključne besede: polprevodniki, mikroelektronika, tehnologije žice vroče, CVD nanosi kemični s paro, HWCVD nanosi kemični s paro in žico vročo, naprave upodabljalne, senzorji slik, zasloni slikovni, skenerji, upodabljalniki X-žarkov, TFT transistorji tankoplastni, a-Si:H TFT tehnologije silicija amorf-nega hidrogeniziranega za transistorje tankoplastne, zmanjšanje stroškov Izvleček : Tankoplastni tranzistorji ( TFT - Thin Film Transistors ) se na široko uporabljajo kot stikalni elementi v aktivnih matrikah ( AM - Active Matrix ), prikazalnikih na tekoče kristale ( LCD - Liquid Crystal Displays ), kot npr. pri TFT zaslonih prenosnih računalnikov ali tudi pri dvodimenzionalnih slikovnih napravah kot so skenerji ali x žarkovni upodabljalniki v medicini. V prispevku obravnavamo nove izzive v razvoju in raziskavah TFT tranzistorjev : 1) TFT tranzistorji na plastičnih substratih, 2) nizkotemperaturni nanos polisilicija { LTPS ) za izdelavo točkovnih ( pixel) TFT tranzistorjev, oz. za izdelavo krmilnikov vrstic in stolpcev na steklu , 3) krmiljenje OLED diod ( OLED - Organic Light Emitting Diodes ) s TFT tranzistorji. Za vse te naštete napredne uporabe TFT tranzistorjev so pomembne naslednje njihove lastnosti: i) visoka gibljivost elektronov, ii) stabilnost, iii) enakomeren nanos tankih plasti silicija in dielektrika za krmilno elektrodo brez napak pri visokih hitrostih nanašanja. Visoke hitrosti nanašanja so sicer potrebne za zmanjšanje proizvodnih stroškov, vendar zadnje čase postajata vse bolj pomembna zadnja dva dejavnika predvsem zaradi zahtev po visokih tokovih. Na Univerzi v Utrechtu raziskujemo tehniko kemičnega nanosa silicija (CVD ) z metodo vroče žice, s katero si obetamo doseči vse zgoraj naštete lastnosti TFT tranzistorjev. Pri tej metodi se plini katalitično razgradijo na greti tantalovi ali volframovi nitki (temperatura okoli ISOO^C ), med tem ko je substrat na nizki temperaturi. Ustrezno kvaliteten hidrogeniran amorfni silicij ( a-Si:H ) lahko nanašamo s hitrostjo 1 - 5 nm/s. S CVD nanosom z metodo vroče žice smo izdelali TFT tranzistorje z obrnjeno krmilno elektrodo z gibljivostjo elektronov 1,5 cm^/Vs in z električnimi karakteristikami, ki so bile popolnoma stabilne. Koplanarni TFT tranzistorji iz polikristallničnega silicija s krmilno elektrodo na vrhu pa so imeli elektronsko gibljivost 4.7 cm^/Vs, kar je enako Hallovi gibljivosti merjeni v samostojnih tankih filmih. Omenjene lastnosti smo dosegli brez kakršnihkoli dodatnih obdelav, iz česar lahko sklepamo, da se pri CVD nanosu silicija z metodo vroče žice lahko Izognemo dragemu in dolgotrajnemu postopku laserske rekristalizacije tanke plasti, ki je trenutno v rabi v proizvodnji najnovejših polisilioijevih zaslonov za prenosne računalnike. CVD nanos z metodo vroče žice je primeren tudi za nanos dielektrika za krmilno elektrodo iz silicijevega nitrida( SIN* : H ). Tovrstni TFT tranzistorji nanešeni pri temperaturi pod 400"'C so dosegli gibljivost elektronov 0.6 om^/Vs in pragovno napetost 2.9 V, 1. Introduction The application of Thin Film Transistors (TFTs) in image sensors and displays is very widespread. Amorphous silicon (a-Si:H) TFT technology has shown to be a mature technology and thus TFTs are widely used for individually switched display elements (pixels) in Liquid Crystal Displays (LCDs) /1/, primarily in portable laptop computers, but also in 2-dimensional imaging devices, such as document scanners or in digital X-ray imagers for medical applications. In an LCD, the display elements comprise liquid crystals of which the transmissive or reflective optical properties can be altered by electrically charging or discharging them. These elements are arranged in large matrices along with their switching TFTs to form an Active Matrix Liquid Crystal Display (AMLCD). Although the mobility of a-Si:H TFTs is quite low (~ 1 cm^/Vs), these TFTs are very suitable as the pixel switches in AMLCDs, since they can be fabricated over large areas (so that displays with > 15" diameter are no longer an exception), with high yield, and showing very uniform performance, while the low mobility is amply sufficient to charge the pixels within the row addressing time. A possible drawback of a-Si:H TFTs is the threshold voltage shift after prolonged applied bias to the gate electrode. Given the high quality of the currently available gate dielectrics, this effect has been proven to be an intrinsic property of a-Si:H rather than charge trapping in the gate dielectric /2/. Nevertheless, the threshold voltage shift is not an issue in AMLCDs, since the total integrated duration of applied bias to each transistor ("ON time") over the life of a display is too short to produce any significant threshold voltage shift. The duty cycle is very short, because the pixels can be charged within a very short time and the TFT is switched back to the OFF condition once a pixel is charged. 2. Requirements to TFTs 2.1 Mobility Although a-Si:H TFTs are used in mass-produced displays and sensor arrays, new challenges to this field have surfaced recently. The performance of very high-resolution displays is mainly determined by the electron mobility of the pixel TFTs. This is one reason why TFTs with higher mobility would have advantages. Further, one would like to avoid the need for external IC mounting of the row and column drivers. For on-glass peripheral driver circuitry integration, a higher carrier mobility of TFTs is required. For driver circuitry, n-channel and p-ohannel TFTs are required. This would enable Complementary Metal-Oxide-Semicon-ductor (CMOS) circuits, which would make low-power (< 1 mW) on-glass drivers possible and, consequently, the displays could become extremely flat. For row drivers a mobility of 10 cm^Vs is amply sufficient and for column drivers the mobility would need to be 100 cm^Vs /3/. Using multiplexed row and column drivers however, just a moderate improvement of the mobility of TFTs would already be sufficient /4/ while the number of interconnects could already be greatly reduced. For driver TFTs the stability, in addition to the mobility, becomes an issue. 2.2 Stability The stability of the devices has again become an important issue in the following technology fields, (i) Low-tem-perature deposited Thin Fiim Transistors on poiymersubstrates /5,6/. Such low-temperature deposited matrices of TFTs could ultimately be made by roll-to-roll production and be used in curved consumer products, such as mobile phones, and in reliable "electronic paper". The maximum processing temperature that can be used on, e.g., transparent polyethylene terephthalate (PET) is = 150 °C. (ii) TFTs that are used in muitipiexed drivers. In such driver circuits, TFTs have a high duty ratio (i.e., the ON time is long compared to the OFF time) implying prolonged gate bias stress conditions. The threshold voltage shift that results from such prolonged gate bias conditions would lead to a too short life of the driver circuitry. (Hi) TFTs for the addressing of Organic Light Emitting Diodes (OLEDs). When OLED displays become large (i.e., laptop size), active matrix addressing (AMOLEDs) is required in order to reduce the power losses due to capacitive charging, which is a problem in pass/Ve-matrix addressed OLEDs. In contrast to the pixel switching scheme in charge-driven LCDs, the current-driven LED pixels have to be addressed in a constant current mode, which means that the switching transistors remain in the ON state as long as the pixel is required to be ON. Therefore, the TFTs have to be capable of enduring orders of magnitude longer durations of applied bias and should therefore be essentially stable. 2.3 Cost reduction The solution to mobility and stability issues is often found by the introducing poly-Si TFTs. At present, these TFTs are already used in finer pitched displays, such as in the high quality segment of avionics products or in projection displays. In small size display panels, poly-Si TFTs are in use in the driver ICs as well as in the switching transistors /7/. These TFTs always have a top gate structure as this has the advantage that they can be structured using self-aligned photolithographic definition. The challenge in this segment isto produce poly-Si at a low temperature (LTPS; Low Temperature Poly-Silicon), so that inexpensive and larger substrate plates can be used. One of the approaches to LTPS is to deposit amorphous or microcrystalline thin films that which are subsequently (re-)crystallized. The common crystallization techniques are furnace annealing (Solid Phase Crystallization; SPC) /8/, rapid thermal annealing (RTP) with lamps /9/, and exci-mer laser annealing /10/. For glass substrates, furnace annealing is restricted to temperatures < 600 °C due to the softening point of commonly used glass (Corning 1737) and is therefore a method that is very time consuming (in excess of 10 hours). In excimer laser annealing, the short wavelength (308 nm for a XeCI laser) and the short pulse duration (20 -200 ns) promotes rapid melting and fast solidification. This, In principle, enables the use of substrates that are not resistant to high temperatures, such as glass and plastic foil. The base materials for laser recrystallization are either made with Low Pressure Chemical Vapor Deposition (LPCVD) /11/ or with Plasma Enhanced CVD (PECVD) /12/. In the latter case, while PECVD allows for a lower deposition temperature, the recrystallization is actually a two-step process or even a three-step process. It is required to dehydrogenate the film (e.g., at 450 °C for 1 hour) in order to prevent explosive outgassing of hydrogen from the film leading to delamination. After completion of theTFTs, an rf hydrogen plasma (for several hours) is needed to passivate defects, reduce leakage currents, and to enhance the electron mobility. The multitude of complicated processing steps with a long duration that are associated with laser annealing is not straightforwardly compatible with the requirement of a throughput of one plate per minute in the single-substrate processing tools currently employed in the fabrication of AMLCDs /13/. Further, there are problems with the homogeneity of the performance of TFTs over large area substrates due to pulse-to-pulse energy fluctuations and the energy distribution in the beam /10/. This results in mobility and threshold voltage variations in the TFTs, which cause unacceptable non-uniformity in display brightness. Direct deposition of poly-Si TFTs is of interest for obtaining uniformity over large area and for reducing the manufacturing costs. Early results obtained using catalytic chemical vapor dissociation (Cat-CVD) of SiH4 gas at a hot tungsten wire and deposition of the reactants on a substrate held at 300 °C resulted in thin films with a Hall mobility of 10 cm^/Vs /14/. Subsequently, a report appeared on TFTs that were deposited on a thermally-grown SlOa gate dielectric and had a remarkably high optimum in the field effect mobility of 70 cmVVs /15/. Microcrystalline films can also be made using the Layer-by-Layer (LBL) variant of radio frequency (rf) Plasma Enhanced CVD (PECVD) /16/, leading to a mobility of 0.6 cm^/Vs in TFTs. The Princeton group recognized that fluorlnated silane promotes crystallization in PECVD of thin layers /17/ and produced 50 nm thick TRs with an electron mobility of 10 cm^/Vs /18/. Although the deposition rate is only 0.5 Ä/s, the deposition time of the active layer could be limited to 15 min, because only a small thickness was required. Recent results on large area deposition include the achievement of a thickness uniformity of +/- 2.5 % on 20 cm x 20 cm at the University of Kaiserslautern /19/ and a uniformity of +/- 7.5 % on substrates as large as 40 cm x 96 cm, using a novel showerhead design, at Anelva Corporation in Japan /20/. 3. Hot Wire CVD At Utrecht University, we are investigating two deposition techniques for the fabrication of TFTs: Plasma Enhanced CVD in the Very High Frequency domain (VHFCVD) /18c/ and Hot Wire (Catalytic) CVD. This paper will discuss Hot Wire CVD only; for results obtained with VHFCVD we refer to Ref. 21. In Hot Wire CVD, the source gases are catalytically decomposed at heated tungsten or tantalum filaments (~1800 °C), whereas the substrate is kept at a low temperature. heater element li^MiiiMiiiiMiiiMiiiiW substrate filaments shutter. to pumps gas inlet Fig. 1: Schematic cross section of a Hot Wire deposition chamber Figure 1 shows a schematic cross section of a Hot Wire deposition chamber at Utrecht University. It basically contains a substrate holder, a shutter, a hot wire assembly, a gas inlet, and a pump port. The substrate holder is optionally heated with an external heater. One or multiple filaments are located at 3 - 8 cm from the substrate. The gases flow perpendicular to the length of the filaments. In contrast to the conventional PECVD technique, no ions are created: though the hot filament emits a considerable electron current, the energy of these electrons is generally too low to cause impact ionization. At our laboratory, two Hot Wire deposition chambers are connected to one of our multiChamber ultrahigh vacuum (UHV) systems. This offers the opportunity to create geometry and deposition parameters optimized fortwo types of intrinsic layers: amorphous and micro/polycrystalline silicon. Hydrogenated amorphous silicon (a-Si:H) films are obtained using 100 % si-lane (SiH4), whereas polycrystalline silicon films are made using mixtures of hydrogen (H2) and silane (SiH4) gases with a flow ratio of 10 to 15. As a result of systematic and careful optimization procedures we have chosen different substrate-to-wire distances, different wire temperatures, and even different wire materials for a-Si:H and poly-Si:H deposition, respectively (see Table 1). There are two issues of concern in HWCVD, which have been addressed recently: (1) Breaioge of the wires. This can be avoided by preventing excessive silicide formation. This is prevented by avoiding high concentrations of silane near the points where the wire is relatively cool /20/. The life of the wire can be further lengthened by an appropriate annealing treatment with H2 gas prior to deposition; (2) Metallic contamination of the films. This is avoided under normal operating conditions. For instance, for depositions using a W wire at temperatures between 1800 -2000 °C, it has been verified from SIMS measurements that the tungsten concentration in the deposited films is less than 10^® cm"^. Parameter Poly-Si:H a-Si:H Wire material W Ta dsubslr-wire 40 mm 50 mm Twire 1800°C 1700°C Tsub 500°C 250°C Dilution ratio H2/SiH4 15 1 Pressure (mbar) 100 20 Deposition rate (Ä/s) 5 10 Band gap (eV) 1,1 1,8 Activation energy (eV) 0,55 0,8 PhotoVdark conductivity ratio 10=^ 10® Table 1: Key deposition parameters and materials properties of the two intrinsic absorber layers At present, high quality amorphous silicon films can be deposited at a rate between 10 and 50 Ä/s and micro- or polycrystalline silicon films at a rate between 5 and 20 Ä/s. Using pure SiH4 at a substrate temperature of 430 °C, our best material has an ambipolar diffusion length of 260 nm and is deposited at a rate of 18 Ä/s. The hydrogen content is 8 at.-%, leading to an optical (Taue) band gap of 1.70 eV. The first a-Si;H TFTs made with this material immediately showed that the HWCVD technique leads to very stable devices/22/. Polycrystalline or microcrystalline silicon materials are typically obtained using dilution of the SiH4 with H2. We distinguish two main types of poly-Si:H. Type 1 has random oriented small crystals (denoted as Poly1) and type 2 has columnar, strongly oriented (220) crystals (denoted as Poly2). The random-oriented Polyl is obtained at high H2 dilution of the silane. These layers are quite porous and are subject to bulk post oxidation if not shielded by a capping layer. They are useful because they typically show immediate nucleation on any kind of substrate. The deposition rate is relatively low (1 Ä/s). The columnar-oriented Poly2 is obtained at moderate H2 dilution and at a higher deposition rate (5-10 Ä/s). This deposition rate is comparable to the highest deposition rates available for device quality nc-Si:H by VHFCVD /23,24/. Poly2 has unique properties, such as a very intrinsic nature (oxygen levels down to 3 x 10^® cm'®) and a very high compactness, due to good coalescence of the crystals /25/. The latter is illustrated by (i) SiH stretching mode IR absorption only at 2000 cm""', typical for isolated SiH bonds. (ii) H effusion only at 550-650 °C, (ill) low ESR spin density at 7 x 10"'® cm'®, and (iv) low activation energy of the Hall mobility (0.012 eV) /26/. The intrinsic nature of the material is also illustrated by the midgap position of the Fermi-level at 0.54 eV, as deduced from temperature dependent dark conductivity (ad) measurements. The value of Sd at room temperature is also low, at 1.5 x 10"^ i^'^cm'^ This helps in achieving low leakage currents in TFTs. The hydrogen content in Poly2 films is only 0.5 at.-%. The compactness makes these films very suitable as capping layer against penetration of oxygen and water vapor. Typically, the Poly2 growth regime shows an incubation time leading to amorphous or heterogeneous nature near the substrate interface during the first« 50 nm. 3.1 Mobility We applied the Poly2 growrth regime to the preparation of high quality bottom gate TFTs as well as top gate TFTs. The presence of an incubation layer, however, prevents the achievement of typical "polysilicon-like" behavior and therefore these TFTs behave predominantly "amorphous-like", along with the high ON/OFF ratio that is typical for amorphous silicon TFTs. Nevertheless, these TFTs showed an electron mobility of 1.5 cmVs'' /27/, which is higher than that of conventional amorphous TFTs. Moreover, the l-V characteristics were remarkably stable /28/, which will be elucidated in the next subsection. Al, — 100 nm SiO^, 200 nm n+ nc-Si, 60 nm poIy-Si, 1500 nm 1737 Glass, 0.7 mm Fig. 2: Schematic cross section of the top gate TFT structure. To investigate the mobility potential of as-deposited poly-silicon layers made by HWCVD, Utrecht University and S. Wagner's group at Princeton University have fabricated top gate TFTs using the above Poly2 layer In the top gate configuration, the conducting channel is near the surface of the layer. Fig. 2 shows a cross section of the top gate structure. Since the crystals extend conically in the growth direction, the size of the crystals increases from the substrate to the film surface and hence it was expected that the electron mobility at the top of the layer would be higher /29/ (for a film thickness of 1.5 |.im). The transfer characteristics at 0.1 V (linear regime) and 10 V (saturated regime) are shown in Fig. 3. It can be seen that at the lowest Vdsthe drain currents are suppressed. This is possibly due to a small barrier at the source and drain contacts. At Vds = 10 V, the currents are not limited by the contacts. Here, the ON current is 4.8 x 10"^ A and the OFF current is 7.5 x 10"" A. Such a low OFF current is not usually obtained for poly-Si TFT. The subthreshold slope 3 = 9V/3(logio Id) is 1.5 V/decade and the threshold voltage Vth is 8.0 V. The mobility in the saturated regime is calculated from the slope of the square root of Id versus Vg measured at Vd = 10 V (forVg < 15 V) and amounts to 4.0 cm Vs""'. The maximum field effect mobility that was obtained is 4.7 cmVs'"'. -1 0 0 1 0 Gate Voltage (V) Fig. 3: The transfer characteristics at 0.1 V (linear regime) and 10 V (saturated regime) of a HWCVD poiy-Si:H TFT The transistor parameters are fully consistent with the individual thin film properties: the OFF current is in agreement with the dark conductivity of the Poly2 layer and the field effect electron mobility is similar to the result of the Hall measurement, which was 5 cm^V^s"^. The mobility is also consistent with the mobility determined from Time-Resolved Microwave Conductivity (TRMC) measurements performed on the same layers, showing an electron mobility of 4 to 5 cmVs""' /30/. In the TMRC technique, short wavelength pulsed laser illumination of the top surface was used to probe the mobility of the corresponding channel region of the TFT. The lateral current flow does not experience noticeable barriers due to crystal boundaries (consistent with the low activation energy of the Hall mobility of 12 meV). In addition to this 1.5 ,um film, we investigated the effect of a reduced thickness of the silicon film on the TFT characteristics. We employed 750 nm and 300 nm thick films. The results are shown in Table 2. Top-gafeTFTswith films have reduced electron field effect mobility. Thickness (nm) V„ (V) ON/OFF ratio mobility (cm^V-^s"') 300 12 30 1.1 X 10-3 750 6 2 X 10= 1.5 1500 8 4x10== 4.0 1500 9.5 6 X 10= 4.7 Table 2: Summary of the HWCVD poly-Si TFT characteristics for three thicl 5 MV/cm) and a high electrical resistivity (> 10^® i^cm) have been achieved. Fig. 6 shows the FTIR absorption spectrum of HWCVD SiNx deposited with R = 30. For comparison the spectrum of typical nitrogen-rich PECVD SiNx deposited at a substrate temperature of 400 °C /34/ is also shown in this Figure. The composition of HWCVD SiNx was measured with Elastic Recoil Detection (ERD). We determined X = N/Si = 1.35 + 0.05, which is near to the value of x = 1,33 for stoichiometric Si3N4. In the semiconductor industry, Si3N4 is conventionally deposited by LPCVD at a high temperature of ~ 800 °C and therefore it cannot be applied to glass or plastic substrates. The hydrogen content of our films is (10 + 1) at.-7o. This is very low compared to the 22 at.-% present in the PECVD SiNx sample. In the case of the PECVD SiNx the hydrogen is bonded to N only, apparent in the N-H stretching mode at 3340 cm""" and the N-H bending mode at 1180 cm"^ The HWCVD layer, on the other hand, also shows a contribution from Si-Hx stretching at 2100 - 2300 cm""". A refractive index of 1.95 ± 0.02 and a band gap of Eo4 = 4.2 ± 0.1 eV (energy where the absorption coefficient is lO'' cm'^) was determined by spectroscopic ellipsometry. The relatively low bandgap (Eo4 ~ 5 eV for the PECVD SiNx) and the presence of the Si-Hx mode in the FTIR spectrum indicate that the SiNx network contains a considerable fraction of Si-Si bonds and, thus. Si dangling bonds, may act as charge-trapping centers as in case of PECVD SiNx /36/. TFTs with a PECVD channel layer and a Hot Wire silicon nitride gate dielectric, have reached a mobility of 0.6 cm^/Vs and a threshold voltage of 2.9 V. 'All-hot-wire' TFTs with both layers made by HWCVD have reached a mobility of 0.3 cmVVs and a threshold voltage of 4.0V/37/. Although more development work is needed to improve the compatibility between the two layers, it is thus demonstrated that the TFTs can in principle be made using a single process. 4. Conclusion We have addressed the current issues in the development of TFTs for AMLCDs or AMOLEDs and grouped them in the categories mobility, stability, and cost. With reference to these issues we have discussed the potential of Hot Wire CVD for the fabrication of thin film amorphous, micro-, or polycrystalline silicon channel materials and silicon nitride dielectrics. Although there are still large challenges in the further development of the Hot Wire CVD technique, its simplicity makes it a very favorable technique for the formation of the active layers of TFT matrices and driver circuits. 5. Acknowledgements We are thankful to C.H.M. van derWerf and J. Groenewoud for layer and device fabrication, and to the MESA institute, University of Twente (A.A.I. Aarnink) for helping us throughout this research with the etching and TFT lithography. We also thank J. Chapman at Philips Research Laboratories (PRL), Redhill, U.K., for TFT fabrication and M.J. Powell for advice and fruitful discussion. The work is financially supported by the STW Technology Foundation and by the Netherlands Agency for Energy and the Environment (NOVEM). 6. References /1/ R.A. Street, Phys. Status Solidi A 166 (1998) 195. /2/ M.J. Powell, C. Van Berkel, A.R. Franklin, S.C. Deane, and W.I. Milne, Phys. Rev. B 45, (1992) 4160, /3/ S,D, Brotherton, Semicond, Sei, Technol, 10 (1995) 721, /4/ R.I. Hornsey, T, Mahnke, P, Madeira, K, Aflatooni, and A, Nathan, MRS Symp, Proc. 467 (1997) 887, /5/ N,D, Young, R,M, Brunn, R,W, Wilks, D,J, McCulloch, S,C, Deane, M,J, Edwards, G, Harkin, and A,D, Pearson, J, Soc, Inf, Disp, 5/3(1997) 275, /6/ G,N, Parsons, J, Non-Cryst. Solids 266-269 (2000) 23, /7/ S. Morozumi, Proc. 9th Int. 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On Cat-CVD (HW-CVD) Process, Kanazawa, Japan (2000) 265. /35/ M. Sakai, T. Tsutsumi, T. Yoshioka, A. Masuda, H. Matsumura, 1" Int. Conf. On Cat-CVD (HW-CVD) Process, Kanazawa, Japan (2000) 311. /36/ J. Robertson, Philos. Mag. B 63 (1991) 47. /37/ B. Stannowski, M.K. van Veen, and R.E.I. Schropp, MRS Spring Meeting 2001, Symposium A, April 16-20, 2001, San Francisco, CA, to be published in: MRS Symp. Proc. Vol. 664 (2001) A173. R.E.I. Schropp, B. Stannowski, and J.K. Rath Utrecht University, Debye Institute, Physics of Devices, RO. Box 80.000, 3508 TA Utrecht, The Netherlands Tel.:+ 31 30 253 31 70 Fax: + 31 30 254 31 65 e-mail: R.E.l.Schropp@phys.uu.nl Prispelo (Arrived): 10.09.01 Sprejeto (Accepted): 01.10.01