HEURISTIC APPROACH TO CIRCUIT SIZING PROBLEM Janez Puhan, Ärpad Bürmen and Tadej Turna University of Ljubljana, Faculty of Electrical Engineering, Ljubljana, Slovenia Key words; computer aided design, integrated circuits, optimization aigoritinms, circuit sizing. Abstract- Circuit sizing problem in application specific analog integrated circuit design is in most cases limited to setting MOSFET channel widths and lengths It is usually performed by hand by an experienced human designer As the circuit sizing is an optimization process by its nature, optimization methods could be used They always lead to one of the minima of the cost function while eventual other minima stay unknown. To reveal different cost minima an optimisation process composed from many individual optimisation runs is proposed. Individual runs are started from various initial points in the parameter space. A particular initial point is determined by a heuristic method which maximises the probability of finding a new cost function minimum in the next run. The optimization process is demonstrated on several real operating amplifier designs. Heuristični pristop k določevanju elementov v integriranih vezjih Ključne besede; računalnišl- pdV inp>-biasV- vsn>- :r □ diff. pair pd> inp>-innV- TT-n load ir diff.prtr I> i — our. STO. -^ouf Figure 4: Operational amplifier with n-channel differential pair two-stage amplifiers mismatching is simulated by slight modei variations of one of the matching transistors. The shape of such a complicated cost functions in multidimensional parameter space is completely unknown. Finding a global minimum is a difficult task for any optimization method and circuit simulator since it requires many circuit anal- vsp /.....T- ^ ?.........' bp3 .1 Inp^ inn>—j: diffi bn3> bn2;- F i H[ rf H[ H[ ( ' 1 K