Elektrotehniški vestnik 82(4): 191-196, 2015 Original scientific paper Parametric yield optimization with mesh adaptive direct search Arpad Biirmen1 1 Faculty of Electrical Engineering, University of Ljubljana, Trzaska cesta 25, 1000 Ljubljana, Slovenia 1 E-mail: arpad.buermen@fe.uni-lj.si Abstract. Random manufacturing process variations can affect the performance of an integrated circuit to the extent that a significant number of the manufactured circuits must be discarded because they fail to satisfy the specifications. To increase the yield, random variations must be taken into account in the design phase. This can be achieved by choosing appropriate values for the parameters accessible to the circuit designer. This process (circuit sizing) can be automated by means of parametric optimization. As simulators do not compute sensitivities, derivative-free optimization algorithms, like mesh adaptive direct search (MADS), are well suited for optimizing circuits. We propose an MADS-based approach for finding a circuit that satisfies the minimum yield requirement. The approach is tested on two integrated circuit-sizing problems. The results demonstrate its effectiveness and speed. Keywords: circuit sizing, yield analysis, yield optimization, mesh adaptive direct search Optimizacija izplena z adaptivnim mrežnim direktnim optimizacijskim postopkom Naključne variacije postopka izdelave integriranih vezij lahko vplivajo na lastnosti vezja do te mere, da precejšnje število izdelanih vezij ne izpolnjuje specifikacij. Ta vezja morajo biti zavrzena. Da bi povecali iz-plen, moramo te variacije upoštevati pri nacrtovanju vezja. To lahko dosezemo z izbiro ustreznih vrednosti nacrtovalskih parametrov med dimenzioniranjem vezja. Le tega lahko avtomatiziramo s pomocjo parameterske optimizacije. Ker simulatorji ne racunajo obcutljivosti, so brezgradientni postopki, kot so adaptivni mrezni optimizacijski postopki, primerni za optimizacijo vezij. V prispevku predlagamo pristop k dimenzioniranju vezij, ki izpolnjujejo zahtevo po nekem minimalnem izplenu. Predlagani pristop preizkusimo na nacrtovanju dveh integriranih vezij. Rezultati kažejo, daje pristop ucinkovit in hiter. 1 Introduction Due to random variations of the integrated circuit (IC) manufacturing process not all produced circuits satisfy the design requirements over the declared range of operating conditions resulting in a yield that is lower than 100%. With shrinking transistor dimensions, the effect of these variations is increasing with every new process node. Therefore, it is necessary to account for random Received 30 June 2015 Accepted 20 July 2015 manufacturing process variations during the design stage [1], [2], [3]. The effect of process variations can be reduced by increasing the transistor size that contributes most to the variability of the circuit performance. On the other hand, increased transistor sizes result in a larger and more expensive circuit. The process of choosing the transistor dimensions (circuit sizing) can be automated by using optimization algorithms [4]. Unfortunately, computing the metric subject to optimization (yield) is by itself a computationally intensive task, particularly when classical methods, like Monte Carlo analysis, are employed. Furthermore, Monte Carlo analysis requires a large number of samples for reaching a reasonable level of confidence when the circuit yield is close to 100%. Random variations of the manufacturing process can be modeled with statistical parameters. Yield estimation can be significantly accelerated if deterministic methods are used [5]. These methods involve an optimization in the space of statistical and operating parameters. The resulting worst-case point can be used for estimating the circuit yield. Finding the optimal values of the circuit design parameters (i.e. parameters that can be chosen by the circuit designer) is also an optimization problem. This task is commonly referred to as circuit sizing. Mesh adaptive direct search (MADS) [6] is a family of optimization algorithms that do not require the derivatives of the function subject to optimization. Because most circuit simulators do not compute sensitivities (i.e. derivatives), MADS is a good candidate for estimating the yield with a deterministic approach [5] as well as 192 BÛRMEN finding the optimal design parameter values. The paper is organised as follows. Section 2 establishes the connection between the worst-case distance and the circuit yield. Section 3 introduces a methodology for automating the circuit-sizing process with the goal of achieving the target yield. Section 4 gives a brief overview of MADS used for estimating the circuit yield and sizing the circuit. The results obtained on two circuit-sizing problems are given in Section 5. 2 Worst-case performance and parametric yield The m performances of a circuit (e.g. gain, phase margin, swing, etc.) are given by vector f. Every performance fi depends on three groups of parameters: operating parameters xO, statistical parameters xS, and design parameters xD. The operating parameters define the environment in which a circuit operates (e.g. ambient temperature, supply voltage, bias current, etc.). The statistical parameters model random variations of the manufacturing process). Finally, the design parameters are the ones that can be adjusted by a designer (e.g. transistor channel widths and lengths, resistances of resistors, etc.). A circuit satisfies the design requirements at a particular combination of the operating, statistical, and design parameters if all performances satisfy inequalities of the form fi (xO, xS, xD) > Gi, where Gi is the target value. Typically, a circuit must satisfy all the design requirements over a given range of the operating parameters. This range is specified with lower (xO) and upper (xH) bounds on the operating parameters. Let x^ (xS, xD) denote the operating parameters corresponding to the worst performance at given statistical and design parameters. W,i (xs, XD) = arg min f (xo, xs, xc). (1) The inequality applies to vectors component-wise. To simplify the notation, we define f W (xs, xd) = fi (x^ (xs, xd), xs, xDJ (2) where nS denotes the number of the statistical parameters. The origin in the space of the statistical parameters (xS = 0) corresponds to the nominal process parameters. If a particular xS does not belong to the acceptance region of the manufactured circuit corresponding to xS must be discarded. Consequently the parametric yield of a circuit drops below 100%. The designer tries to maximize the acceptance region (and consequently the parametric yield) by adjusting the design parameters. The parametric yield of / can be computed by integrating (3) over A (xD ) as Y (xd ) = / p (xs ) da ■Jxs eAi (XD ) (4) where da is a differential volume element in the space of the statistical parameters. This integral cannot be expressed analytically. Usually, the numerical approaches, like Monte Carlo analysis, are used for estimating (4). The worst-case point xlf'® (xD) is the point on the boundary of the acceptance region closest to the origin of the statistical parameters. Computing the worst-case point is an optimization problem given by x W,i _ Jargminxs/A(xD) l|xs||2, 0 G Ai (xd) arg minxseAi(xn) ||xs1 otherwise. (5) The distance of the worst-case point from the origin is reflected in the worst-case distance which is defined as Pi (xd ) = (xd) || (xd ) W,i 0 G Ai (xd ) otherwise. (6) For given design parameter values (xD) point xs in the space of the statistical parameters belongs to the acceptance region of fi (denoted by xS G A (xD)) if fW (xs, xd) > Gi. The statistical parameters originate from random variations of the manufacturing process. By transforming the process parameters, one can obtain independent normally-distributed random variables with zero mean and variance one. We refer to these variables as statistical parameters. The joint probability density of the statistical parameters is p (xs) = (2n) -ns/2e-||xs lr/2 (3) Figure 1 illustrates the worst-case point and the worst-case distance when 0 g A (xD). It is possible to compute a good analytical approximation of (4) by linearizing the circuit performance in the neighborhood of the worst-case point xlf^ (xD). Integration of (3) over the acceptance region obtained with a linearized circuit performance (shaded in light grey) results in the approximate yield Yi(xD) = 1 (l +erf (xd) /V2)) « Y (xd). (7) The error of this approximation is equal to the integral of (3) over the region shaded in dark grey in Figure 1. In most cases, this error is small [5]. Therefore, it is reasonable to expect that maximizing the worst-case distance maximizes the parametric yield. 3 Finding a circuit with a given minimum yield Suppose one wants to find the design parameters for which Y (xd) > Yo, i =1, 2,..., m, (8) s 2 o PARAMETRIC YIELD OPTIMIZATION WITH MESH ADAPTIVE DIRECT SEARCH 193 f?{xs,xDy Figure 1. Worst case point x^ in the space of the statistical parameters for ns = 2 at the design parameters given by xd . The boundary of the acceptance region (shaded) is depicted by a thick line. Linearization of the boundary at the worst-case point (dashed line) makes it possible to analytically compute the approximate yield. The error corresponds to the integral of (3) over the region shaded in dark grey. where Y0 is the target yield. By replacing Y with Y, we can approximate (8) with ßi (XD ) > i = 1, 2, . m, (9) where ^o is the worst case-distance that corresponds to approximate yield Y0. It can be obtained by solving Y = 2(l + erf (ßo/V2 (10) For (9) to hold, the m worst-case points must satisfy Ixoll > ^o. Consequently, (11) fW (xs, XD) > Gi for ||xs||< Ao and i = 1, 2,..., m. Requirement (11) can be reformulated as min fi (xo, xs, xd) > Gi, i = 1, 2, ...,m. (12) llxs ||<0O xO Gi Vc 6 Ck and i = 1,..., /* Circuit sizing problem ends here if no such xD found then | Exit with failure; end k Gi; Set B0 = 0 for i = 1,...,m; xD is the initial point; k 1; while True do added ^ False; for i ^ 1 to m do c ^ arg minceCi fi (c if ceB: k-1 Gi Vc eBi and i if no such xD found then | Exit with failure; end k ^ k + 1; end A circuit performance in one corner is evaluated from the results of one or more simulations. Solving the circuit sizing problem requires many evaluations of all circuit performances (fi) over the corresponding corners in Ci. As the number of the corners grows with the number of the outer loop iterations of Algorithm 1, it makes sense to identify the corner cW G Ci with the lowest (worst) value of fi at xD. It is sufficient to size the circuit with the corner sets reduced to just this one element (i.e. Ci = {c^}). Algorithm 2 identifies this corner iteratively. A corner set used in the k-th iteration of Algorithm 2 (denoted by Bp) is a superset of the set used in iteration k-1. This strategy makes the outer loop finite and generally reduces the number of the required simulations. In most cases, two iterations are sufficient for solving the circuit-sizing problem corresponding to one iteration of the outer loop of Algorithm 1. 4 Mesh adaptive direct search MADS [6] is a family of derivative-free optimization algorithms [7] that rely on a dense set of normalized poll directions for guaranteeing convergence properties on nonsmooth and constrained optimization problems of the form min f (x) (16) The points examined in the k-th iteration lie on mesh Mp which has a finite countable intersection with any bounded subset of the search space. The mesh density is controlled by the mesh size parameter (AJ1) which approaches zero in the limit (i.e. the mesh becomes infinitely dense). Note that the superscript m is a standard notation used in papers on MADS and has nothing to do with the number of the circuit performances. The length of the steps taken by MADS is controlled by the step size parameter Apk. The step size parameter approaches zero at a slower rate compared to the mesh size parameter (AJ/Ak ^ 0). MADS can handle constraints with the extreme barrier approach where f is replaced with fn which is equal to f if x G 0 and otherwise. The incumbent solution and the corresponding value of fn in iteration k are denoted by xk and fk . Algorithm 3: Iteration k of a MADS algorithm using the extreme barrier approach. /* Search step */ Evaluate fn on a finite subset Sk C 0; /* Poll step */ Evaluate fn (xk + d) for all d g D; /* Update incumbent solution, AJ, and Apk */ Let x' be the point with the lowest value of fn evaluated in this iteration; if fn (x') < fp then xp+i ^ x'; else Choose Ak+i > Ak and AJf+i > A^; end xp+i ^ xp; Choose Ap+i < Ap and AJ+i < AJ; The algorithm outline is given by Algorithm 3. Set D is a set of the scaled poll steps in iteration k. Note that its members are chosen in such manner that xk + d G Mp. The convergence properties of MADS are guaranteed by the poll step if certain requirements are satisfied [6]. The search step does not affect the convergence properties, but it can significantly speed up the algorithm. In our implementation, the members of Sk are chosen using a quadratic model of the objective and constraint functions. An overview of the convergence properties and implementation details can be found in [8]. MADS is used for solving the optimization problem in the inner loop of Algorithm 1 [9] and for solving the circuit-sizing problem. It can also be used for computing the worst-case distance (by solving problem (5) and inserting the obtained result into (6)). 1 m PARAMETRIC YIELD OPTIMIZATION WITH MESH ADAPTIVE DIRECT SEARCH 195 5 Examples and results The proposed algorithm is implemented in Python as part of the PyOPUS library [10]. SPICE OPUS [11] is used as the circuit simulator. The algorithm is parallelized where possible (i.e. evaluation of the m worst-case points in Algorithm 1 and evaluations of a circuit over multiple corners in Algorithm 2). All experiments are performed on a 3.2GHz Intel XEON processor with four cores and eight threads. One thread is reserved for the manager task and the remaining seven threads serve as workers. The proposed approach is tested by sizing two operational transconductance amplifiers (OTA) [12]. Both circuits are sized for a 0.18^m manufacturing process. The Pelgrom model of the device mismatch [1] is used. Global variations are not taken into account. j I—HI |HJ |mp2 Mp3 il—I s© '-L s Jr. r1 1| 1n3 I a TH3T t; 1p1 i—11 ll—i Mp 0» Mn1 Mn2 j-11 j m ä > HJa Mp8 out Mn6 Figure 3. Folded cascode OTA. The second circuit (Figure 3) is a folded cascode OTA (FCOTA) with 11 design parameters, 32 statistical parameters, and two operating parameters. The bias current is set to 5^A. Table 1. Operating parameters. Low High Nominal Tempetarure [° C] 0 100 25 Supply voltage [V] 1.7 2.0 1.8 The ranges and the nominal values of the operating parameters are given in Table 1. All transistors are required to operate in the staturation region at the operating point. This results in two additional requirements for every transistor (i.e. VGS > VT and VDS > VGS - VT). These requirements are enforced in all corners, but they are not subject to the worst-case analysis or yield optimization. Every circuit is first sized at the nominal operating and nominal statistical parameter values (i.e. xS = 0). The resulting design parameters are used as a starting point for Algorithm 1. The target yield is set to 99.87% (fto = 3). Table 2. Results for the Miller OTA optimization. Goal Final WCD Figure 2. Miller OTA. The first circuit (Figure 2) is a simple Miller OTA. The circuit has 13 design parameters (11 transistor channel widths and lengths, one resistance, and one capacitance), 16 statistical parameters (two parameters for every transistor), and two operating parameters (temperature and supply voltage). The bias current (Ibias) is set to 100^A. Area [^m2] < 9000 2117 - Supply current [^A] < 1000 175 > 8 Swing [V] > 1.0 1.21 > 8 Gain [dB] > 60 77.8 >8 UGBW [MHz] > 10 11.0 6.1 Phase margin [°] > 50 56.6 >8 CMRR [dB] > 90 90.1 3.3 PSRR Vdd [dB] > 60 84.9 >8 PSRR Vss [dB] > 60 84.5 >8 Overshoot i [%] < 10 8.4 >8 Overshoot f [%] < 10 9.5 >8 Tset i [MS] < 1 0.784 >8 Tset f [^S] < 1 0.831 >8 Slew rate i [V/^s] > 2 2.02 4.4 Slew rate f [V/^s] > 2 2.01 3.7 The results of the Miller OTA optimization are listed in Table 2. The final optimization result is verified by computing the worst-case distances of the circuit performances. All the worst-case distances are greater than fto implying that the target yield is exceeded. The process of circuit sizing takes 57 minutes. Table 3. Results for the FCOTA optimization. Goal Final WCD Area [^m2] < 2000 1637 Supply current [^A] < 400 63.8 > 8 Offset (low) [mV] > -20 -8.39 7. 1 Offset (high) [mV] < 20 8.56 7. 1 Swing [V] > 0.3 4.09 > 8 Gain [dB] > 70 70.2 4. 2 UGBW [MHz] > 4 4.04 3. 9 Phase margin [°] > 60 61.4 6. 2 CMRR [dB] > 100 126 > 8 PSRR Vdd [dB] > 70 140 > 8 PSRR Vss [dB] > 70 71.0 > 8 Overshoot i [%] < 10 4.8 > 8 Overshoot f [%] < 10 0.34 > 8 Tset i [^s] < 2.5 0.189 > 8 Tset f [MS] < 2.5 0.319 > 8 Slew rate i [V/^s] > 2 6.07 > 8 Slew rate f [V/^s] > 2 4.08 > 8 The results of the FCOTA optimization are listed in Table 3. The process of circuit sizing takes 9.5 minutes. Vdd d Mp1 C R inp D a inn out Mn4 Mn5 Mn1 Mn2 Vdd D Mp5 Mp6 Mp7 inp o a inn Mn5 Mn3 Mn7 Mn8 Vss D 196 BÛRMEN The final result is verified with the worst-case distance computation which confirms that the final yield is greater than the target yield. 6 Conclusion Designing circuits that exhibit a high parametric yield is an important task in the process of the analog integrated circuit design. Computing the yield as well as finding the design parameters that satisfy the minimum yield requirement is an optimization problem. As circuit simulators do not compute sensitivities, the derivatives of the function subject to optimization are not available. Therefore, it makes sense to use derivative-free methods for solving such optimization problems. An automated design methodology is proposed based on a set of corners that represent the operating conditions and manufacturing process variations where the circuit exhibits the worst performance. The corners are computed by solving an optimization problem. The optimal design parameter values are found by solving an optimization problem obtained from the circuit-sizing problem by using a penalty function-based approach. The set of corners is built iteratively by repeatedly solving the two optimization problems. The process stops when all the design requirements are satisfied and there are no new corners found. For each optimization a mesh adaptive direct search optimization algorithm is used. The proposed approach is tested on two analog circuit-sizing problems. The results show that the approach is effective and capable of finding a circuit satisfying the minimum yield requirement. [6] C. Audet, J.E. Dennis Jr., Mesh adaptive direct search algorithms for constrained optimization, SIAM Journal on Optimization, Vol. 17, pp. 188-217, 2006. [7] A.R. Conn, K. Scheinberg, L.N. Vincente, Introduction to Derivative-Free Optimization, SIAM, Philadelphia (PA), 2009. [8] A. BUrmen, J. Olensek, T. Tuma, Mesh adaptive direct search with second directional derivative-based Hessian update, Computational Optimization and Applications, DOI 10.1007/s10589-015-9753-5, April 2015. [9] A. BUrmen, H. Habal, Computing Worst-case performance and yield of analog integrated circuits by means of mesh adaptive direct search, Informacije MIDEM - Journal of Microelectronics, Electronic Components and Materials, Vol. 45, scheduled for publication in issue 2, 2015. [10] A. Burmen Optimizacija vezij s knjižnico PyOPUS, Elektrotehniški vestnik, Vol. 79, pp. 149-152, 2012. [11] A. Burmen, T. Tuma, Circuit Simulation with SPICE OPUS, Theory and Practice, Birkhauser, 2009. [12] R.J. Baker, CMOS Circuit Design, Layout, and Simulation John Wiley & Sons, 2008. Arpad Burmen received his Ph.D. degree in electrical engineering from the Faculty of Electrical Engineering, University of Ljubljana, Slovenia, in 2003. Currently, he is an associate professor at the same faculty. His research interests include continuous and event-driven simulation of circuits and systems, optimization methods and their convergence theory and applications, and algorithms for parallel and distributed computation. He is one of the principal developers of the SPICE OPUS circuit simulator and the PyOPUS design automation library. 7 Acknowledgement The research was co-funded by the Ministry of Education, Science, and Sport (Ministrstvo za Šolstvo, Znanost in Sport) of the Republic of Slovenia through the programme P2-0246 Algorithms and optimization methods in telecommunications. References [1] M.J.M. Pelgrom, A.C.J. Duinmaijer, A.P.G. Welbers, Matching properties of MOS transistors, IEEE J. Solid-State Circuits Vol. 24, pp. 1433-1440, 1989. [2] C. Michael, M. Ismail, Statistical modeling of device mismatch for analog MOS integrated circuits, IEEE Journal of Solid-State Circuits, Vol. 12, pp. 154-166, 1992. [3] J. Bastos, M. Steyaert, A. Pergoot, W. Sansen, Mismatch characterization of submicron MOS transistors, Analog Integrated Circuits and Signal Processing, Vol. 12, pp. 95-106, 1997. [4] A. Burmen, D. Strle, F. Bratkovic, J. Puhan, I. Fajfar, T. Tuma, Automated robust design and optimization of integrated circuits by means of penalty functions, AEU-International Journal of Electronics and Communications, Vol. 57, pp. 47-56, 2003. [5] H. Graeb, Analog Design Centering and S izing, Springer, 2007.