INFORMATICA 4/1980 MICROCOMPUTER BUSES SVSTEM FRANC NOVAK UDK:681.3 (083.7) INSTITUT JOŽEF STEFAN, LJUBUANA The paper revievs some inost popular microcomputer common buses vhieb appeared together with tho generation of 16-bit doviceB. Bua speeiflcations eonaiderably differ frotn each other, Binoe most of them are primarily suited to • certain microprocessor family. Tbe paper deacribes the moet important functional char- acteristicB of the following microcomputer buees: 8-100, VERSAbus, Multibus, TH 990 bus and ZBI bus. A brief 8uamary of conneotor types and card dimeneione for each bus is given as well. MIKRORAČUNALNIŠKA VODILA. Članek podaja pregled mikroračunalniških vodil, kl BO naetala vzporedno z generacijo 16-bitnih mikroprocesorjev. Vodila se aed seboj precej razlikujedo, saj BO V večini primerov "piaana na kožo" ene od mi- kroprocesorskih familij. Članek predstavlja mikroračunalniška aistemska vodila: B-100, VERSAbus, Multibue, TM 990 bus in ZBI bus z ozirom na njihove najpomsm- bnejgo funkoionalne karakteristike. Za vaako vodilo 80 opisani tudi.tipi ko- nektorjev in dimenzije kartic. I. IBTRODUCTION One of the most important features of micro- oomputer aystem design is tbe implementation of tbe system bus. A common bus is a composi- tion of unidirectional or bidirectional lines whieh transfer information and oleotrical pow- er between tbe various components of a micro- computer Byetem. These lines aro characterised from a functional point of view (e.g. address lines, data lines,...)« as «ell as from an e- lectrical point of view (e.g. open collector line, three state line,...)• There are two basic types of funotional ele- ments tbat conneot to the bus: masters and Blaves. A bus master is any module having tbe ability to control tbe bus. It is capable to address bus slaves by generating propor control and addresa signals. A bus master has the capa- bility to tranefer measages to or from tho ad- drossed elave. A bua slave decodes the addresa lines and acts upon tbe command signals from tbe mastera. The overall bebaviour of the eventa on the bua is defined by tbe bus protocol. The last but not least important feature of the bus are its mechanical specifications (e.g. oon- nector types, board size etc). Tba bus struc- . ture is important to the users wben tb.ey intend to upgrade their systems by, say, commercially available memory boards or peripherals. II. MICROCOMFUTEH BUS PR0P0SAL3 In the area of 8-bit microcomputers almost aa many different backplane packaging and funo- tional speoifioations were propoeed aa tbere were microproceseor manufaoturers. Obvioualy, aoine of them gained more popularity than others ( SBC 80, ECORcisor, Z-80 bus, PRO-LOG, to oite Juet a few of them). Still none is the favorit. As the 16-bit devices began to appear on tb« 57 market the same story happened again though witb. a considerably amaller number o£ bus pro- posals. Intel Multibus, Motorola VEKSAbus, TM 990 bus and ZILOG ZBI bus are widely proclaim- ed but tb.ey all tend to be specific to the com- puter they were designed for. In some case3, the design of the bus ie constrained by the fact that compatibility with preceding members of the microprocessor family is provided. VEESAbus and ZBI bus are here outatanding ex- ceptions. They still proride means lor support- ing 8-bit microprocessors but their upper limit is 32 rather than 16-bit data transfer. Despite differences in internal CPU architec- ture, bus protocol o.f any micropi'ocassor systen> exerts similar master - slave i-elations. For example, communication with memory and periph- erals requires similar signals and timing rela- tionsMp. Consequently, a universal bus struc- ture which is independant ot" actual micropro- oessor type should be possible to define. The S-100 bus resulted from the effords to create such "universal" bus. V/ith its specification openly published by the IEEE it could meet most requirements for the present microcomputer sys- tems and ±t had been adopted by many manufactur- ers. Yet, a dravjback is that it tiad been orig- inally designed foi> 8-bit data and 16-bit ad- dress lines. Its proposed exetention to 16-bit data lines has not been widely accepted. In October 1980, the IBEE Gomputer Society pro- posed the 796 Bus Standard vhlch is actually only a sliglit modification of the Multibus and is stated to be "a cooperative industry effort toward establishing a standard for a large num- ber of manufacturers and users of microcomputer modules". The purpose of this paper is not to make an ae- essment oi" advantages and disadvantages of the contenders for the title of "industry standard". Instead, most common feature3 of microprocessor bus proposals are reviewed to acquaint the read- er with their basic design. III. ADDRE3S AND DATA LINES All the above mentioned buses provide raeans for 8 and 16-bit data transfer, but still oonsider- able differences exist in the way to accomplish this. Likawise, the number o£ addresa lines dif- fers from each other resulting in different ad- dressing oapabilities. The data bus of the S-100 bus consists of 16 lines which are grouped as two unidirectional 8-bit buses for byte transfer and as a single bidirectional bus for 16-bit word format. The address bus consists of 16 lines for standard memory addressing (64 k locations), or of 24 lines for extended memory addressing ( 16 M locations ). The Multibus provides 16 bit data bus and 20 bit address bus. The implementation of the 8 and 16-bit data transfer employs a special Swap Byte Buffer which must be included in any 16- bit master or slave in order tc maintain com- patibility with previous 8-bit mastera and slaves. Tb.e 20 address lines allow a maximum of 1 M bytes of memory to be accessed. The VERSAbus provides 16 bit data and 24 bif address lines whioh can both be expanded to 32 lines using the second connector. The TM 990 data bus consists of 16 lines. The 20 address lines are comprised of 16 basic and 4 extended addreas lines. Up to 1 M bytes can be addresaed by means of the raemory mapping techniquo. Tbe most significant difference between the ZBI bus and other buses is in the way of the trans- fer of d.ata and address information. The ZBI bus uses a multiplexed bus Btructure with 52 data or addreas lines. This gives a smaller number of bus interconnections, at the expense of a slight increase in the complexity of the cir- cuits connected by the bus. 32 lines provide mestns to accomodate future 32-bit microprocessors and offer wide addresaing capability. IV. BUS ARBITRATION All 16-bit microprocessors are designed to allow multiprocessing. They have facilities to bandle bus control which can accomodate several bus mas- ters on tho same system, each taking control of the bus .for its own data transfer. The S-100 bus arbitration system uses 4 bus lines for arbiti'ating among 16 temporary masters. In general, one permanent master may exist in the system and it has ths highest arbitration prior- ity. Each temporary master has a unique priority number which it asserts on the arbitration bus afc an appropriate time. A temporary master oan get the control of the bus from th.e permanent master only for an arbitrary number of bus cy- cles. Then it must return the control to the permanent master.•The parallel priority reso- lution is implemented by means of additional logic stored on eaoh master board interfacing to the arbitration lines. There are another 4- lines on tJie bus to dis- able the line drivers of the permanent master making together 8 control lines for the DMA arbitration. In cases where the existence of the permanent master in the system may prov"3 to be ineffi- cient, a dummy raaster may replace it. The dum- my master merely passes the control of tbe bus from one temporary master to anotber. It is especially suitable v/hen a number of processors co-exiat in a single system. The Multibus offers two bus exchange priority techniqu.es: serial and parallel. Serial prior- ity resolution is accomplished with a daisy - chain technique. A relatively small number of masters can be accomodated in this way. Due to the present time hardware limitations only up to 3 masters can be accomodated in a system with bus clock period of 100 ns. In tbe parallel technique, the priority is re- solved by raeans of a priority resolution cir- cuit. This circuit must be externally supplied and its position in the system is not strictly determined by the bus standard. 1£ the parallel technique is used a practical limit of 16 mas- ters in a system is stated. The VERSAbus provides 5 level bus arbitration. Eacb. level can be implemented as a daisy - chain to increase the number of bus masters. The priority is first resolved among the five levels and then within the elements of the daisy - chain of the level which gained the pri- ority. In the TM 990 bus specificaticn the arbitratior soheine is liraited to a single daisy- chain like the Multibua serial resolution. Slmilarly, the ZBI bus employs a eerial daiey - cbain resolution technique and four control lines to enable multiple processors to sbare the bus. Wbile in the previously mentioned bus epec- ificatoins a DMA module uses the same arbitra- tion soheme as otber processor modules in the 8yatem, the ZBI bus makes a distinction: it provides separate daisy - chain for tbe DMA ar- bitration. V. INTEREUPT REQUEST SCHEME The intermpt request scb.eme in the S-100 bus is comprised of an 8-level maskable vectored interrupt system and a non - maskable interrupt which is an optional control input to the bus masters. Tbe eight interrupt request lines are inputs to a bue slave or an interrupt controller whicb maska and prioritizes the requests. As a result it outputs the interrupt request to the permanent master. The Multibus can support bus vectored and non- bus vectored interrupts at tbe same time. Bus vectored interrupta are generated by the slave Priority Interrupt Controllers which transfer the vector addreas to the bus master. The non- bus veotored interrupts are handled on the bus master. A bus slave that requeste the interrupt does not convey interrupt vector address on the bus, it is generated by the interrupt controller on the master. Eight intermpt request lines enable 8-level priority interrupts. To handle interrupts the VEKSAbus provides a 7- level priority control. !The 7 interrupt request lines are of tbe wire-0Red configuration so that each level can be expanded by a daisy - ohain. The VERSAbus accomodates bus vectored interrupts. 15 general purpose vectored interrupts are de- fined in the TM 990 bus each having its own pri- ority level. Tlie interrupts are maskable by the primary master. Interrupts on tbe ZBI signal lines can be imple- mented as maskable or non-maskable, vectored or non-vectored depending on how the CPU is conjfig- ured. 9 interrupt lines organized into 3 inde- pended groups exist on the bus each having its unique priority level. VI. MISCELLANEOUS FUNCTIONS A number of signals and their functions have not been described not to go too much into detailes. Nevertheless, let us review just a few interest- ing features. The decision, if they are worth mentioning is left to the reader. The ZBI bus and the VERSAbus include parity cheok bits for data and address lines, wbile in gen- eral, each bus includea at leaat one generalized error line that indicates that the current oper- ation is producing an error. 59 For the case of power failure, control eignals are provided that indicate that the power is going to fail enabling the system to enter the power fail sequence. The system may etore im- portant data in memory which is powered by the standby power supply. To enhance the system's integrityt clock signal lines are accompanied by their own signal-ground lines on the bačkplane. the different bus specifications. This may be the reason why tbe IEEE wbrks on a processor - independant standard P896 referred as the "future bus". The future bus, if it be- comes the IEEE standard, will operate at, rates over 10 MHz, the arbitration scheme :will; handle up to 64 raasters in a sof isticatedj arbitrat;iori protocol, the interrupt control will ha^idle 1024 priority levels. Another bus design is reported .fromllntel. NUMBER OF CONNECTORS S-100 VERSAbus Multibus TM 990 ZBI bua 1 2 2 1 2 Pl P2 Pl P2 Pl P2 CONMECTOR DESCRIPTION (50/100 pin) : (70/140 pin) : (60/120 pin) : (43/86 pin) : (30/60 pin) (50/100 pin) board edge connecter board edge c. board edge c. board edge c. board edge c» board edge c. : (32/32/32 pln) wirewrap c. : (32/32/32 pin) wirewrap c. CARD DIMENSIONS ' ( in inches ) 5-125x10 9.25x6.5 (reduced size).•., or 9.25x14.5 , V-- 12.00x6.75 ' •..'• :••• 11x7.5 6.3x3.9 (Eurocard) or 6.3x9.2 (Double Euroc.) Table 1 VII-. MECHANICAL SPECIFICATIONS Table 1. summarizeB eome most important mechan- ical specifications concerning the physical de- sign of a bus backplane and the dimensions of the printed circuit boards that plug into the bus interface. Some remarks are necessary: Signals of tiie VERSAbus Pl connector allow tho implomentation of a complete 16-bit device on a reduced size board. The 1'2 conneotor provi- des extension to service future 32-bit devicea. Pl oonnector of the Multibus is the primary connector and P2 is an auxiliary connector. The ZBI system signals are all gathered togeth- er on the Pl connector, the P2 connector is re- served entirely for the user application. VIII. CONCLUSION Standardization of the microcomputer bus is an important element to be considered when micro- oomputer systems are designed. A number of bus etandards have been proposed in the paet. Each microprocessor raaker was solving problems from hia own point of view which resulted also in Developing the new 32-bit laiaroprocessor iAPX 432, new bus itvfcerconnection concepts are an- nounced. The last word has not beensaid yet. IX. LITERATURE 1). F. Taylor, J. Race: Standards for microsys- tems, (Microproc. and Microsystems, vol4,n8) . 2). L.Yencharis:...But the right bus evokes the system's best, (Electronic design, May 1980) 3)t M. Marshall: IEEE readies backplane standard, (Electronics, September 25, 1980) 4). A. Clements: Computer system buses, (Microproc. and niicrosystems, vol 3, no 9) 5). J. Rattner, W. Lattin: Ada determines archi- tocturo of 32-bit microproceaaoi", (Electronics, February 24, 1981) 6). Standard specification for S-100 bus inter- face devices, (Computer, July 1979) 7). L. Bender: ZBI:a system bus for the Z 8000. (Mini Micro Systems, June 1980) 8). VEft3Abus, Multibua, TM 990 bua, (Manuals) 9). Proposed raicrocomputer systera 796 bue stand- ard, (Computer, October 1980)