Professional paper
Informacije
^efMIDEM
A lonrnal of
Journal of Microelectronics, Electronic Components and Materials Vol. 45, No. 1 (2015), 87 - 97
Contour Graph Approach of Micropower Clock Generator Design for Energy Harvesting Charge Pump Circuits
R. Aloulou1,2, J. Armand2, P-O Lucas de Peslouan2, F. Alicalapa2, H. Mnif1, J. D. Lan Sun Luk2 and M. Loulou1
1LETI Lab, University of Sfax, Tunisia
2LE2P Lab, University of La Reunion Saint Denis, Reunion, France
Abstract: This paper presents a novel design methodology of micropower noncritical clock generator for charge pump circuits. Embedded clock generator circuit requires careful attention in terms many issues: topology choices, component sizes, power dissipation and signal voltage values. This paper also presents comparisons and performance optimization of microwatt clock generators using SPICE simulator. Additionally a contour graph approach is developed to find relevant parameters value in order to minimize the power consumption and the chip area. The circuit design was implemented on standard 0.35 ^m Si CMOS process. The active area dimensions are 42 ^m*25 ^m. Consistent results were obtained between experimental results and transient simulations. In comparison to previous papers, under low-voltage constraints, interesting measured circuit consumption was observed: 1.15 ^W from 1 V.
Keywords: Contour curve; clock generator; micropower clock; power consumption; optimization; low power; charge pump; energy harvesting
Metoda grafa obrisa za urni generator majhnih
»-v^	•	••	77*
moci pri črpanju energije z okolja
Izvleček: Članek predstavlja novo metodologijo načrtovanja urnih generatorjev za črpanje energije z okolja. Vgrajeno vezje urnega generatorja zahteva posebno pozornost pri: topologiji, velikosti komponent, porabi energije in napetosti signala. Predstavljena je optimizacija in primerjava urnih generatorjev v SPICE okolju. Za zmanjšanje porabe energije je uprabljena metoda grafa obrisa. Vezje je bilo implementirano v 0.35 ^m Si CMOS tehnologiji z aktivno površino 42 ^m * 25 ^m. V primerjavi s prejšnjimi rešitvami je bila dosežena nizka poraba energije: 1.15 ^W pri napetosti 1 V.
Ključne besede: Graf obrisa; generator ure; poraba energije; energija iz okolice
' Corresponding Author's e-mail: aloulourahma@yahoo.fr
1 Introduction
Energy harvesting is becoming a practical solution to improve battery lifetime in micro-scale electronic systems for wireless sensor applications. Many research papers have been proposed to design an energy harvesting system based on a charge pump circuit [1]. Charge pumps (CPs) are circuits that generate voltages greater than the supply voltage from which they operate. Some of these circuits are based on two anti-phase pumping clocks [2]. For this charge pump circuit operation, low frequency clock generator is actually needed. Clock generator circuits are thus widely-used in CPs
and are an important subpart of these systems [3,4]. In the literature, some papers have been published on their performance, where oscillators are aimed to be used as clock generators [3, 5, and 6]. In the context of energy scavenging, power consumption is a crucial issue [7]. The energetic constraint is also applied to clock generators despite the fact that it is sometimes underplayed or un-optimized. This trend is confirmed by the publications on subthreshold mode circuits [8], in which power consumption is dominated by leakage current Ioff [9, 10] and supply voltages lower than 1 V [7]. Furthermore to keep the cost low, attention should
also be given to the chip size by introducing effective design methods.
This work compares power consumption and performance analysis of different square-wave clock generator topologies. Topologies comparison aim at selecting an appropriate low frequency clock generator topology, under low power constraint, in the energy scavenging context. This comparison is performed under some specific conditions: the energy criterion is more important than noise performance. The operating frequency is in the range of hundreds of megahertz (in accordance with charge pump circuit design concepts for energy harvesting applications [11], from 1 Hz to 100 MHz). Furthermore, the clock signal generator is designed to drive CP switches [4]. In this scheme, its output square signal amplitude should be high enough to have an appropriate voltage gate control of the CP switches. In this work, the minimum voltage level is set to Vt = 0.7 V, as the CP CMOS switches are not operating in subthreshold mode. About the supply voltage, as the clock generator will be associated with a bandgap and a charge pump circuit, the typical value that will be considered is 0.8 V. And finally in this context, the studied topologies are intended for application in highly integrated systems (consuming a reasonable silicon area), using a low-cost 0.35 ^m Si CMOS process.
Many candidates are well-known in the literature: LC circuits, CMOS oscillators and crystal oscillators. Some of them are not suitable for low-cost process integration (crystal oscillators) or rather interesting for high frequency low noise applications. Some others use additional external components. Alternative topologies are interesting for the purpose of this work: the Schmitt trigger circuit, the ring oscillator and the voltage controlled ring oscillator. Some drawbacks are known, but under certain aspects of ring oscillators, they can be exploited. All, these points will be respectively presented in section 2, 3 and 4. Attention will be paid to low power consumption and frequency range in order to select one of these circuits. Section 5, will present the contour graph methodology which was used to optimize the circuit under the constraints (power, frequency, chip area). Then a power consumption comparison is performed for the different clock generator topologies at selected low frequencies. Measurement results are provided in section 6, along with the parasitics effect on power consumption offset and comparison with some publications. Section 7, finally presents the conclusions of this paper.
2 Schmitt trigger clock generator STCG
The circuit depicted in Fig. 1 is known as a multivibrator circuit, astable type. The circuit is configured around an
inverting Schmitt trigger gate and a delay structure (composed of the surrounding components, R and C).
Figure 1: Schmitt Trigger Clock Generator circuit
The oscillation frequency fo is mainly determined by the delay structure as:
/ = j 1
RCIn
highy lo^w
(1)
V,
low
V -V
y high DD
Where, VDD is the power supply voltage. Considering the upper (Vh,gh) and lower (V|ow) switching voltages (usually associated with transistors transconductance ratios), which define the hysteresis of the gate in the transfer curve: the Schmitt trigger's output is a well defined voltage, which is really suitable for noisy signal or signal cleaning functions [12].
Dynamic behavior simulations of STCG circuit have been performed using SPICE simulator and 0.35 ^m Si CMOS process parameters.
The operating frequency range was simulated for different values of the delay structure (t = R.C, Fig. 2).
10"
S?


..... fo: 1.349e+006 .................
.......■■.....
W T =1.2e-4s (R=120Kn,C=1nF) —0—T =9e-5s (R=90Kn,C=1nF) —^■T =6e-4s (R=120Kn,C=5nF) T =5e-7s (R=50Kn,C=10pF)
3	3.5	4	4.5
VDD (V)
Figure 2: Simulated output frequency fo versus supply voltage (VDD) - STCG circuit
10
10
VDD: 3
t= 10
10
10
Over the frequency range of 10 Hz to hundreds of megahertz, fo is inversely proportional to t = R.C. The oscillation frequency range is obviously governed by the RC time-constant.
10"

^^ 10-4
■O- ■ T =9e-5s (R=90Kfl,C=1nF) -^-x =6e-4s (R=120Kfl ,C=5nF) ■*—% =5e-7s (R=50KO,C=10pF)
10
3	3.5	4
VD D (V)
Figure 3: Spice simulated power consumption as a function of the supply voltage VDD - STCG circuit
From the power dissipation point of view, Fig. 3 displays power simulation results as a function of the supply voltage VDD. From this graph, it can be seen that a fall of the supply voltage, lowers the power consumption. Also, it can be deduced that the variation of the power_consumption has a small fluctuation as function of the delay structure t.
Transient results and the theory reveal that the circuit does not work properly for a supply voltage less than 2 V. In fact, the gate hysteresis tends to disappear at this voltage level. At this lowest 2 V voltage, the total power consumption is 20 ^W.
Consequently, and especially in the context of our purpose where a low power and frequency clock generator is required, this drawback (lowest supply voltage=2 V) can represent a major limitation for the use of this topology. In the next section a different topology (inverter based clock generator) is presented.
3 Ring oscillator RO
A ring oscillator (RO) (Fig. 4) consists of an odd number of inverters in a unity gain feedback loop [13]. To achieve oscillation, the circuit must satisfy the Barkhau-sen's criterion which means that the total phase shift and the gain of the feedback loop must be 2n and one respectively [14].
Figure 4: Ring Oscillator circuit and additional C capacitors
To design oscillators whose output frequency ranges from 1 Hz to 100 MHz, a ring structure of three stages is chosen. C capacitors have also been included to lower the output signal frequency to meet the custom specifications of charge pump circuits. Instead of C addition, we could have chosen a greater number of stages. In terms of output frequency value and power consumption, this is not compatible with our application (supply voltage value of 0.8 V and low power circuit) as depicted in Table 1.
Table 1: RO clock generator frequency as a function of VDD and the inverter stage number without capacitors
Vdd (V)	3 stages	5 stages	7 stages
0.8	18.45 MHz	10.54 MHz	7.65 MHz
1	115.5 MHz	63.1 MHz	44.55 MHz
1.5	257 MHz	191 MHz	114.5 MHz
Theoretically, the frequency of the oscillation can be found as:
fo =
1
2 Nt,„
(2)
Where N is an odd number and is the propagation delay of one inverter stage. The delay of each inverter stage will be given by:
VC..
x = —
mv i
-avec Vo =

CONT
CONT
C
dt
(3)
Where, V^ is the voltage signal amplitude, ICONT is a DC control current source (Fig. 4) and C,n the equivalent input capacitor of the following inverter (intentional ad-
2
2.5
4.5
5
dition (C) and MOS transistors parasitics). The expression of the frequency becomes [15]:
f =	(4)
It is known that the delay of each stage is governed by the supply voltage VDD and the capacitors value, C. This dependence can be verified by simulations of the frequency performance and power consumption (Fig. 5 and Fig. 6). These parametric simulations (sweep on C) are performed as a function of VDD.
10"
:: io4
VDD: 1
fo: 2.55e+007
-!-
1 i
1
i	i A....:•■■•♦■••■
^T	A. — 'f : i '■ -
..............^ i, j i ii
0.5 0.6 0.7 0.8
0.9 1 VDD (V)
1.1 1.2 1.3 1.4
Figure 5: Simulated output signal frequency (fo) as a function of the supply voltage VDD and C capacitor value, RO circuit
In Fig. 5, considering the VDD range between 0.5 V and 1.5 V, the output frequency ranges from 10 Hz to 1 GHz. But referring to section 1, the lowest supply is limited to 0.7 V in order to ensure the charge pump correct operation. In the same context, considering the lowest voltage limit, the real performances range from 500 HZ to 1 GHz. Furthermore, taking into account additional circuits which should be included in the global charge pump circuit (bandgap and charge pump circuit), the supply voltage must be greater than 0.8 V and below 1.5 V. In this voltage range, referring to Fig. 5, we can see that suitable capacitor values to generate a 20 kHz signal (at 1V as supply voltage) are in the order of 1.5 x 10-10 F. This can be a drawback for the chip size.
About of power consumption, Fig. 6 reports power simulations as a function of the supply voltage VDD and capacitor C. Power consumption decreases naturally with the reduction of the supply voltage. In contrast, the simulations reveal that the capacitors value C, is not explicitly related to power in this circuit. For purpose of comparison, when the supply voltage value is 1 V and for an output signal of 20 kHz, this circuit has a consumption power of 9 ^W. At the end of this sec-
10
10
0.5
1.5
VDD (V)
Figure 6: Simulated power-VDD curves over a range of capacitor value, RO circuit
tion, it has been remarked that to obtain the required operating frequency range, additional capacity must be included or greater number of stages must be designed. These points are disadvantages for the chip area. Therefore, the next paragraph will discuss a third topology of clock generators.
4 Voltage controlled ring oscillator ^CRO
Since the limitations and drawbacks of the previous topologies the voltage-controlled ring oscillator (VCRO) will be opted to meet the custom performances (frequency, power and area) of the charge pump design. Different schemes can be used for controlling the circuit. Compared to the RO circuit, a voltage-controlled ring oscillator (VCRO) commonly uses variable voltage source to control its oscillation frequency (the possibility to adjust the clock frequency is obviously a strong point). Tun-ability of the VCRO is implemented via a variable resistance in the circuit. Theses resistances are designed using a transmission gate (Nmos-Pmos transistors), where the MOS transistors are controlled by their gate voltage. This topology (Fig. 7) was firstly proposed by Retdian [15] in order to improve the output voltage swing. Compared to Fig. 4, this circuit is also composed of three stages to satisfy some criteria. Among these criteria: the output frequency and the power consumption. Each stage includes one inverter (namely INV, in Fig. 7, consisting of MPINVi and MNINVi transistors) and one transmission gate (namely TG,, made up of MPtg, and MNtg,). The voltage VCONT applied on transmission gates enables the resistance tuning. The result being as expected, a control of the output frequency, which can be given as:
_ 1
_ 2 NC in [Rin + Rtg )	'5)
10
10
10
10
10
10
106
10
10
1.5
Where: R|N is the inverter equivalent resistance, and RTG, the transmission gate equivalent resistance. Cin is the equivalent input capacitor of the following inverter (the sum of the MOS transistors parasitic capacitors).
Figure 7: Voltage Controlled Ring Oscillator circuit, VCRO
5 VCRO performance optimization using contour graph approach : power, frequency and area
5.1 Contour graph approach
The contour graph approach is a good graphical tool for representing spatial relations between two variables. In addition, a contour line or isoline (often, is just called a « contour ») is a curve that joins points of equal values. Plotting these contours forms a map called a contour map.
Hence, considering the VCRO candidate, electrical and geometrical characteristics can be optimized, to find a minimum power dissipation point [16] using this contour graph approach.
In order to apply this approach and evaluate the the power dissipation and frequency behaviors, simulations are performed as a function of VDD, VCONT and W/L transistor ratios.
To go further, once VDD and VCONT have been fixed to their typical value (0.8 V),_concerning the transmission gates and the inverters of VCRO: the W/L transistor ratio (which is assumed to be identical for each electronic sub-function), have an impact on the optimal operation point. Fig. 8, 9, 10 and 11 show their influence on isopower dissipation and isofrequency graphs.
First focusing on MP_TG and MN_TG transistors, frequency performance and power dissipation are studied for a set of values of W/L ratio. Contours of Fig.8 and 9 demonstrate that frequency performance and power dissipation are mainly dependent on MP_TG transistors.
_ 6
ä 4
		i	T---1	1-[— + i	-!—\-!-!-'		-j-
5e	0	6		1	/ /		
Se	0	6			!.1e+007l i i		
	7e	+0	Tö= 06	e+007 1 1 1	fO=ll^e+007 i		
			j............j ie+006...	1............■!"	/		
						i fo=i.3e+	107!
							
		1 + il		^ 1		i i	i
4	5	6
WMP-Tg (Mm)
Figure 8: Isofrequency curves versus TG transistors width (MP_TG, MN_TG), VCRO circuit
7
ä 4
3 .....-"t- A......T

3	4	5	6
WMP-TG (Mm)
Figure 9: Isopower consumption (PT) versus TG transistors width (MP_TG,MN_TG), VCRO circuit
7
IT 6 ^^ 5 i 4
3 2
PT=.
5e-007 i pT=.7ei007
• PT=
T=6e-00?

i +
123456789 WMP-INV (Mm)
Figure 10: Isopower consumption curves versus IN transistors width (MP_INV, MN_INV) - VCRO circuit
Now, regarding the inverters and the effect of W/L transistor ratio: power dissipation and frequency performance are given respectively in Fig. 10 and Fig. 11 for MP INV and MN INV transistors.
9
8
7
5
3
2
2
3
7
8
9
9
6
E
5
2
7
8
9
9
8
It appears that the variation of power dissipation has a rather small fluctuation compared to MP_TG and MN_ TG impact on the power dissipation (Fig. 10). About Fig. 11, MP_INV and MN_INV transistors have roughly the same impact on frequency performance.
Previously, we saw that C capacitors in ring oscillators didn't change power dissipation (Fig. 6). Consequently, it can suggest that inverter transistor dimensions (MP_ INV, MN_INV) mainly contribute to the overall equivalent capacitance.
For the given parameters of transistors, in order, to study the evolution of the power dissipation and frequency characteristics as a function of VDD, VCONT Fig. 12 and 13 show contour graphs representing lines of equal frequency and power (isofrequency and isopower graphs). In these simulations, the points that are located under the line defined by VDD = VCONT, should not be considered, as this means that VDD < VCONT. In this case, additional circuits are needed to generate negative voltages for the TG transistors. That's the reason why we will consider VDD > VCONT.
s
s 4
. i ; ; i fo=J>e+006 !	! ...........^............^...........^............^.......... i fo=5
J 4e+006-

n......3e+006
' 2e+006
4	5	6
WMN-INV(Mm)
Figure 11: Frequency performance versus IN transistors width (MP_INV, MN_INV) - VCRO circuit
About the conclusions of this approach: these curves indicate that power dissipation is dominated by MP_TG transistors (as depicted by the vertical parts). A power optimization method can firstly consist of sizing of MP_ TG transistors, based on energy resources. And secondly the desired frequency performance can be adjusted using the W/L ratios of MP_INV and MN_INV transistors. This methodology can save time for low power and low frequency oscillator with small size devices. In the purpose of our work, the operating frequency of the charge pump is in the range of tens of megahertz. By using this contour graph method (Fig 8, 9, 10, 11), the following sizes were selected to generate the required frequency.
Table 2: Selected CMOS transistors sizes - VCRO (VDD = VCONT = 0.8 V)	DD
Transistors	W/L (^m)
MP_INV	9/0.6
MN_INV	4.5/1.2
MP_TG	3/0.6
MN_TG	1.5/1.2
Concerning the frequency performance (Fig. 12), the output frequency (fo), doesn't depend strongly on VDD as denoted by the vertical parts. Reading the isolines of Fig. 13, power dissipation varies between 0.1 nW and 10 ^W. For a given value of VDD while VCONT is increasing, we note that the power dissipation increases too.
0.4	0.6
1.2	1.4
VCONT (V)
Figure 12: Simulated isofrequency contour graphs (fo) as a function of VDD and VCONT, VCRO circuit
1.4
1.2
Q 1 Q
0.4 0.4
		pt\1e-0	5		
	PTsE1E-0e		VDD		
PT =	1E-07 \				
s^._______	08				
ve-09					
					
					
					
0.8 1 1.2 VCONT (V)
Figure 13: Constant power dissipation contour graphs simulations (PT) as a function of VDD and VCONT, VCRO circuit.
7
ir6
5
2
3
7
8
9
0.8
1.6
1.6
0.8
0.6
0.6
1.4
1.6
In order to operate to a specific frequency fo (which depends on the CP topology) and at the minimum power dissipation, VDD and VCONT should be the lowest with respect to the application requirements. The optimal operating point can be extracted from these curves, which are useful for circuit design. The optimal operating point is the voltages (VDD and VCONT), which give the minimum power dissipation for a desired output frequency.
VDD and VCONT can be chosen independently. But Fig. 14 pictures the impact of the difference between the two voltages: power dissipation as a function of VDD -VCONT for different output frequencies. These results clearly show that the optimal point is achieved when VDD =
VCONT-
1 y	i
!!'!!!!!: vdd-vcont: o.56 üüjü-yrn; üiuh:!!!!:
_ 10 s
0 0.2
0.4	0.6	0.8
(VDD - VCONT) (V)
Figure 14: Power dissipation (PT) as a function of VDD -VCONT for three frequencies, VCRO circuit
5.2 Validation of the approach and comparisons results
In order to evaluate the VCRO performance and the design approach, and for the purpose of comparison with previous clock generators (STCG, RO), the frequency and power performances (Fig 15 and16) have been investigated.
On Fig. 15, the output frequency is plotted as a function of VCONT at a supply voltage of 1 V. For control voltage (VCONT) between 0.1 V and 1 V, this topology achieves a tuning frequency range from 20 Hz to 36.6 MHz. This frequency range is reached using a reasonable silicon area as no additional capacitors are needed
Concerning the power dissipation (Fig. 16) the total power dissipation in CMOS circuits comes from two parts [17]: static and dynamic power.
10
10
10
10
10-
10
10
VCONT: 0.7 fo: 2.39e+006
iiililiii^iliiilili^iiiiiiiii	ililiiilililliiiiiiiii^liliiiiir
VCONT: 0.5 fo: 2e+004
!|!l!IIIIIIIM|!l!l!ll?l!
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VCONT (V)
Figure 15: Output frequency simulation as a function of Vcont,Vdd = 1 V, VCRO circuit
Statics	Dynamic
(6)
Where, Is the total current leakage, a is the activity factor, Cout is the total output switching capacitance and fo the clock frequency. Dynamic dissipation has theoretically been far greater than static power. This issue is also true for this circuit as proved in Fig. 16
10
10
10
105
10
10
10
10
llililiiliiilllililiäiMllllliäliiiililli VCONT: 0;7,, liiHIi
..	To: 2.39e+006
VCONT: 0.5 fo: 2e+004
y
i: VCONT: 0.3
::: fo: 97.7
p
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VCONT (V)
Figure 16: Simulated frequency dependence of power consumption (PT), VCRO
In the same manner (in view of eq6), on Fig. 17, the total simulated power consumption, PT, is reported as a function of VCONT at VDD = 1 V. Dynamic power dissipation increases with high VCONT values. And as in some way Fig. 15 and 17 have shown that VCONT and the output frequency has identical trend, it should be noticed that low VCONT values cannot be used in the frequency range of interest. Thus in the useful range of VCONT (VCONT <0.35 V), dynamic dissipation dominates the total power consumption.
105
5
10
10
10
9
10
10
10
1.2
10'
10
10
10
VCONT: 0.65 PT: 1.4059-007
I
VCONT: 0.5 PT: 1.4389-008
PP
■ -I..........).....
-5..........i.....
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VCONT (V)
Figure 17: Simulated power dissipation (PT) as a function of VCONT, VDD = 1 V, VCRO circuit
For the purpose of comparison, this circuit has a power consumption of 14.38 nW (Fig. 17) at VDD = 1V and VCONT = 0.5 V. In this case the output frequency is 20 kHz.
These data (summarized in Table 3) tend to indicate that the VCRO reaches the lowest power dissipation for the operating ranges under consideration (frequencies, voltages). Indeed, the latter exhibits a typical 14.38 nW power dissipation, one decade below the others.
Table 3: Typical simulated power dissipations of the CMOS clock generators @ 20 kHz
VCRO	RO	STCG
PT = 14.38 nW	Pt = 9 ^W	PT = 20 ^W
6 Experimental results and discussions
In order to verify and validate the system operation for low frequency and low power power clock applications, a three stages voltage controlled ring oscillator was implemented using AMS 0.35 ^m Si CMOS technology. Fig. 18 shows the microphotograph of the circuit. The VCRO occupies a small effective area of 1050 ^m2, where its dimensions are 42 ^m x 25 ^m.
This section also describes the measured results for the power dissipation and output frequency of the VCRO. Fig. 19 compares the simulated and measured power dissipation as a function of VCONT at a supply voltage of 1 V. As seen the measured power dissipation increases with the voltage control as mentioned earlier. The trends are nearly the same. We note, however, an offset between the simulated and measured power consumption. Our analysis of the mismatch, of the circuit and the layout, took us to an assumption:
Figure 18: Die photo of the VCRO circuit using AMS 0.35 ^m Si CMOS technology - active area: 42 ^m x 25 ^m
the effect of parasitics (resistances and capacitances) associated with metal wires, bonding pad and bonding wires. Indeed, in the context of the charge pump circuit, VCRO is not intended to be connected to any lead frame in an individual package. Among the possible parasitics, as we have two output bonding pads, we decided to include two capacitances to the circuit (Fig. 20), as it could change the output frequency and consequently the power consumption. Furthermore, about the interconnecting metal wires: their resistance can be neglected considering their short lengths and actual widths (Fig. 20).
■ " ~ Simulation results ■O" Measurement results
Simulation results with parasitic R,C
10-6
10
0.5 0.6 VCONT (V)
Figure 19: Measured and simulated power consumption as a function of VCONT @VDD = 1 V.
Thus, new simulations were computed with the addition of C capacitors and their series resistors. As pictured in Fig. 19, a good match can be observed be-
-4
10
10
10
0.3
0.4
0.7
0.8
0.9
tween the corrected measurements and prediction given in the previous section.
Table 4: Simulated performances of the VCRO
Figure 20: VCRO and the effect of selected parasitics
The second experiment (Fig. 21) aims at comparing the simulated and measured output frequency as a function of VCONT and the supply voltage. These curves were obtained for VDD ranging from 1 V to 2 V and VCONT from 0.4 V to 0.65 V. Through these curves, we see that the frequency increases with the voltage control and also increases as the supply voltage increases too. Good agreement are observed.
,8 10
nn=
Eilil
Eilil

----simulation results [VClTiL^O.JV)
mreasurement results (VClTiL=l).4V|
......simulation results [VClTiL^0.45V)
X mreasurement results {VCTOL^O.JW)
-simulation results [VCmL=0.5V)
results {VCraL^0.5V)
— ■— simulation results {VCmL^0.6&V) □ mreasurement results {VCmL=0.6tV)
-simulation results {VClTiL=0.6V)
+ mreasurement results {VCmL^O.SV)
-----simulation results [VCTRL=0.65V)
• mreasurement results {VCmL^0.6&V)

"" ^ " I t .......i".......[""""["......i.......i"""

1.4 1.5 VDD (V)
Figure 21: Measured and simulated output frequency
as a function of Vdd and Vcont
A summary of the performances of this circuit is presented in table 4.
To demonstrate the advantages of the proposed design, Table 5 reports performance comparisons between the VCRO circuit and others comparable designs which have been already reported in the literature.
Parameters	Values
Supply voltage	0.4 V-1.6 V
Control voltage range	0.4 V-1.6 V
Frequency range	400 Hz-190 Mhz
Power consumption range	25.23 pW-79.5 ^W
Area of layout	1050 ^m'
Technology	AMS 0.35 ^m CMOS
As observed the VCRO has very low power consumption with the lowest silicon area. A further advantage is that the VCRO circuit can be fully integrated, as it does not require any external components, compared to other circuits presented in Table 5.
Referring to section 5 and table 2, the frequency of oscillation of the VCRO while VDD = 1 V and VCONT = 0.5 V is around 20 kHz. Thus, Fig. 22 shows the transient simulation response for this frequency. In this typical condition, Fig. 23 illustrates the measurement output waveform of the VCRO oscillating at 18.62 kHz and exhibits the good agreement between simulation and experimental waveforms. Voltage level is also suitable for the charge pump CMOS switches control.
Figure 22: Simulated transient voltage of the VCRO, VDD = 1 V, Vcont = 0.5 V (Fosc = 20 kHz)
Table 5: Measured performances comparison with other designs
	[3]	[5]	[6]	[13]	[18]	This work
Supply voltage (V)	0.8	2.5	1.25	1.25	1	1
Power consumption (^W)	0.62	5.9	1120	810	52	1.15
Frequency (Hz)	50E3	34.6E3	6E6	200E3	100E3	20E3
External components	no	yes	yes	no	yes	no
Area (mm')	0.24	0.1	0.14	0.032	0.09	0.01050
Technology(^m, CMOS)	0.35	3	0.18	0.35	0.35	0.35
10
10
10
10
10
10
1.2
1.3
1.6
1.7
1.8 1.9
2
1.1
Figure 23: Measured VCRO output waveform VDD = 1V, VCONT = 0.5 V (18.62 kHz)
7 Conclusions
Through the preceding realizations and analysis, this work has examined power dissipation for three CMOS clock generator circuits. It has shown that the voltage controlled ring oscillator achieves the lowest power consumption for moderate frequency. Its silicon area on the chip is really interesting (1050 ^m2), which is significantly smaller than comparable clock generators. In comparison with others, another strong point was also studied: for the power consumption estimation, na-nowatt values are observed. It can be less than 15 nW.
The simulation results also show that the VCRO exhibits a wide frequency tuning range, with good transient characteristics, both at high and low frequencies. This is usually difficult to obtain from the conventional generators.
Complementary simulations have shown the effect of input voltages (VDD, VCONT) and transistors sizes scaling (W/L ratios), on power and frequency performances. The optimal point is guaranteed when the VDD = VCONT relation is verified. Another important point is that, MP_TG transistors of VCRO, dominate the power dissipation and the frequency performance. From the same complementary simulations, contour graphs were drawn in order to find the optimal voltages and dimensions. These results are valuable information for the design of low power VCRO clock generator circuits.
Finally, to validate this approach, the VCRO circuit has been fabricated using AMS 0.35 ^m Si CMOS technology. Output signal path parasitics has been considered
for the power consumption measurements. A close agreement between simulation and experimental data is obtained, which testify the performances of the VCRO circuit for lower power systems and energy harvesting applications.
Acknowledgment: We gratefully acknowledge the financial support of the structural funds of the European Community, and the Regional Council Reunion Island (Region Reunion), for providing research grants (grant FEDER PRESAGE32933, CARERC project n°33933).
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Arrived: 16. 09 .2014 Accepted: 10. 11. 2014