Elektrotehniški vestnik 85(3): 1-7, 2018 Original scientific paper
FPGA Implementation of a Space Vector Pulse Width Modulation Technique for a Two-Level Inverter
Ahmed Belkheiri1*, Said Aoughellanet1 and Mohammed Belkheiri2
department of electronics, Faculty of Technology, University of Batna 2, Fésdis, Batna, Algeria. 2Laboratory of Telcommunications, Signals and Systems, Université Amar Telidji de Laghouat, Algeria *E-mail: a.belkheiri@lagh-univ.dz
Abstract. The paper presents a design and a hardware implementation of a Space-Vector Pulse-Width Modulation (SPVPWM) IP core. The aim of this work is to benefit from the FPGA component in controlling electric drives and in power-electronic applications. Subsequently, we can expand the libraries of predefined complex functions and circuits for reuse and to speed up the design process of AC control algorithms. The SVPWM generator is fully customizable where the modulation index, carrier frequency, modulating-signal frequency and delay time (dead-time) can be set easily by the user. The proposed SVPWM generator, implemented on cyclone IV ALTERA education board associated with an experimental set-up composed of a three-phase inverter and AC load, works properly, uses a reduced number of logic elements (LE) and is well optimized to be used in open or closed-loop motion-control applications.
Keywords: Logic element, FPGA, three-phase inverter, SVPWM, variable speed.
FPGA izvedba pulzno-širinske modulacije prostorskega vektorja za dvonivojski pretvornik
V prispevku sta predstavljena načrtovanje in strojna izvedba IP-jedra generatorja pulzno-širinske modulacije prostorskega vektorja (SPVPWM) s ciljem izrabe vezja FPGA pri krmiljenju električnih pogonov in aplikacij močne elektronike. S tem razširimo knjižnice ponovno uporabnih vezij in pohitrimo proces razvoja krmilnih algoritmov. Generator SPVPWM je popolnoma prilagodljiv in omogoča nastavitev modulacijskega indeksa, nosilne frekvence, modulacijske frekvence signala in zakasnitve (mrtvih časov). Predlagani SVPWM-generator, ki je izveden na učni razvojni plošči z vezjem Cyclone IV izdelovalca Altera ter povezan na trifazni inverter in izmenično breme, deluje pravilno. Vezje zasede manjše število logičnih elementov (LE) in je dobro optimizirano za odprto- ali zaprtozančni nadzor gibanja.
1 Introduction
Adjustable speed drives (ASD) are the main components in many industrial applications that are used in converting the electrical energy to mechanical energy with a controlled speed. The ASD controller design has been significantly improved due to the development of the two-level inverter driven by a pulse- width modulation (PWM) technique. Among the existing pulse-width modulation algorithms, space- vector pulse-width modulation (SVPWM) is more attractive thanks to its inherent optimized switching that significantly reduces the power switching loss and increases the DC bus voltage utilization.
The SVPWM technique is a kind of a modulation scheme with a superior performance compared to sinus PWM and third harmonic injection PWM for the inverter-control applications. In the conventional SVPWM algorithm, it is always necessary to perform many trigonometric operations and coordinate matrix transformations to determine the sector position of the equivalent voltage space vector. These complex calculations will inevitably produce a large number of calculations, thus reducing the overall processing speed of the digital system and making the control program design more complicated, and hence, occupying more resources and taking a longer time to run. Therefore, from the practical application point of view, it is necessary to overcome the digital implementation complexity using an adequate hardware and to make the conventional SVPWM easily implementable.
Using the FPGA circuit to implement PWM strategies is proposed for the first time in [1] and it has been also used for the ac motor drives or three-phase ac-voltage control systems [2]. Many papers have reported and tried to propose optimized space-vector PWM for open and closed vector control of the AC machines driven by voltage-source inverters. The proposed implementations use a huge amount of resources due to the trigonometric functions, transformations and switching-time complex calculations in a (d-q) reference frame [3],[4],[5]. In order to save the hardware-resource utilization, a simplified strategy is proposed to generate SVPWM
Received 29 September 2017 Accepted 20 March 2018
waveforms eliminating trigonometric function using bus-clamping technique in [6],[7],[8].
Another strategy based on a generalized scalar PWM approach is detailed in [9] by extracting voltage signals based on the pulse-width calculations during rotation of the reference vector instead of calculating the turn-on and turn-off times of the power switches [10],[11].
Chen et al. propose a technique that simplifies the region identification in determining sectors and reduces the total switching frequency of the dual inverter [12],[13].
The main contribution of this paper is implementing an efficient SVPWM on FPGA, to control two-level three- phase inverters for adjustable-speed drives. The modified SVPWM is optimized to have simple digital logic functions for sector selection and a set of arithmetic subtractions and multiplexing to calculate the switching time based on the reference voltage in the (abc) frame rather than using the (a,P) frame. This strategy allows the user to completely avoid the trigonometric calculation, which will eventually reduce both the calculation time and the FPGA logic element utilization compared to the implemented SVPWM in the literature. The proposed SVPWM generator is implemented on a low-cost DE0-nano Altera educational board with a cyclone IV FPGA. The achieved design is proven to work properly. The rest of the paper is organized as follows. Section 2 is devoted to the theory behind the space vector PWM. The digital hardware implementation is detailed in Section 3. Simulations and experimental results are highlighted in Section 4. Finally, in Section 5, some concluding remarks are given.
2 Principle of Space Vector PWM
<
U/2
o
U/2

rQ
Cfi
IM
c
Figure 1. Two level controlled voltage source inverter.
These calculations are performed in an (a,p) complex plane or "space-vector" plane based on the Clarke transformation of the reference three-phase voltage
FT=[va Vb Vc] given by:
K-
_ _ i -	- 3
2-1 -1 0 V3 -V3
' "a ' \VrJ
(2)
According to equations (1) and (2), the eight possible switching states of the power switches will generate eight possible voltages (F, i=0..7) as shown in Table 1.
Table 1. The switching states and inverter output voltages
Sect Sa Sb Sc [»„	vc] [Fta F^] Vi
-1 -1 -1
[0 0 0]ud,
[0 0]Ud(
In order to generate an AC voltage of a desired amplitude and frequency from a fixed DC bus source, the inverter switches are switched on and off using a modulating circuit shown in Fig. 1.
The output phase voltage vector vT=[va vb vc] of a balanced star-connected AC load fed by the voltage-source inverter is expressed by the equation below:
f "a '
1


-1 1 -1
2 2
1 -1 1
22

f "a
de
(1)
where Sp are the upper switches states and (p=a, b, or c) are the phases of the inverter.
SVPWM is inherently a voltage-control scheme that uses the reference voltage space-vector to calculate the optimum switching pattern for the three-phase inverter to ensure that the desired space-vector voltage is obtained.
1 -1 -1
1 1 -1
-1 1 1
1 -1 1
[2 -1]
1-3 3 3 J
0K,
[3 V3]
1-1 2 -11	r-1 1 1
-1 1 -1 [T 3 -K [T
[- 1 1]
L 3 3 3l

-1 -1 1 hr -T-
-1 -1 2
3 3 3 ac
T
1 -2 1 [3 T 3]Udc
[3 Vf!"-
The switching states are almost similar to the "Grey Codes". To change from one state to the other, only one phase-arm changes the state. When the Clarke transformation is performed on eight inverter switching
a
b
0
0
V,
0
2
V-
4
1
u
dc
3
11-2
V-
6
u

dc
3 3 3
V-
2
1-
2
3
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dc
5
c
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1
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5
6
states, it translates into six voltage vectors. e.g Fi|2=|F2|2= |Fi|2=%Udc, i=1..6 but with different angles, as well as two zero vectors Vo and V7 of the zero length. These space vectors are graphically shown in Fig. 2. It can be seen that the adjacent switching state transform to adjacent space vectors in a transformed two-phase (a,p) plane.
The space vector modulation (SVM) can best be explained based on a two-phase representation of Fig. 2.
where Tx and Ty are the on-times of adjacent non-zero vectors Vx, Vy. They are calculated based on projections of two adjacent vectors of an appropriate sector among the six sectors using equations below:

vxa
vy «
Vxfi Vy p
V
vxa
V
"y a
VxP Vy P

(4)
(5)
Figure 2. Principle drawing SVM for a three-phase two level-VSI.
Reference voltage Vr is to be generated by the inverter. First, it is located on one sector i (i=1,..6) defined by two adjacent active vectors Vi and V+i. Then it can be approximated based on a timely switching among (V, Vi+1) and one or two zero vectors. In this case, vector V2 should be applied for a longer time than Vi since Vr is nearer to V2; and the time of the zero vectors should also be applied to reduce the magnitude.
The objective of using the space-vector PWM technique is to approximate reference voltage vector Vr using the eight switching patterns. One simple method of approximation is to generate the average output of the inverter in a small period, Ts, to be the same as that of Vr in the same period.
Usually, the switching times are derived using complex trigonometric calculations which makes the SVPWM implementation inefficient and takes more resources from the digital hardware [4], [5].
The SVPWM controller is designed to drive the inverter to generate desired voltage Vr by projecting the instantaneous transformed voltage in a sector (x) defined by two adjacent vectors (Vx , Vy) expressed during modulation period Ts as:
and Tz= Ts -(Tx +Ty) is the on-time of appropriate zero-vector Vz.
Equation (5) is usually used for a digital implementation of SVPWM in most papers in the literature either for the microcontroller or FPGA, but it is not optimal and uses more recourses and makes the algorithm more complex compared to the simpler Sine PWM. In this paper, a more intelligent implementation of SVPWM is achieved by an intelligent manipulation of equation (5).
3 Digital fpga implementation of SVPWM
Field Programmable Gate Arrays (FPGAs) offer many advantages in the digital implementation of controlers for power-electronic systems. Since the complexity of the SVPWM algorithm is related to a sector selection and the calculation of the switching times, which is huge relatively to reference (a,p) , our idea is to calculate switching times Tx and Ty,using the original frame (abc):
fT
' 1 y
Ts	¡Vxa	Vl	-1	2 -1	-1
Udc	vxp	vyfi\		0	
' "a 1
Vb
(6)
Table 2 gives the conditions for the sector selection in terms of instantaneous desired reference-voltage values Vr in the (abc) frame. The obtained conditions can be transformed to simple logical functions in terms of the line-to-line voltages or difference comparisons (vab=va-vb, Vbc=Vb-Vc and vca vc- va). This reduces and simplifies enormously the calculations of the SVPWM algorithm. A general overview of the SVPWM generator composed of a combinatory logic that determines at the same time active sector Sec i and the timing pattern generator with the Tx Ty Tz timing calculation is based on Figure 3 and Table 2.
^S VXTX + VyTy + VZTZ
(3)
1
T.
y
Table 2. The switching conditions and times for each sector
Switching Conditions
SecI (V100-V110)
va>vb> vc
100|110
Sec II (V110-V010) vb>va> vc
010|110
Sec III (V010-V011) vb>vc> va
010|011
T,
Udc U - "J
Ts fVg-Vc\
(vh - vj
Udc W - "J
											—V N ab dc
1											
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0.1 02 0.3 0.4 0.5
Sec IV (V011-V001) vc>v„> va
011|001
TS (V„ - Va\
Sec V (V001-V101) vc>va> vb
001|101
]j_ivc - va\
U„r W -Vb)
Sec VI (V101-V100) va>vc> vb
101|10
Ts rvc - vb\
U„r (va - vj
Tooo T100 | Tuo \ Tm Tno Figure 3. Switching-time pattern for Sector I.
Figure 4 illustrates the switching times calculated using Table 2 for a normalized balanced three-phase reference voltage on one period simulated using MATLAB software.
Figure 4. Switching times for Balanced three-phase pattern with a 50% modulation depth.
The first column of the table gives conditions on how to determine the sector where the reference space vector is located using only line-to-line voltages . For example, if Vb>Vc>Va , then sector III is selected. It can be used in generating switching patterns of the inverter as shown in Figure 3 for all the sectors (I.. .VI).
3.1 Sector determination and active-time calculation
The switching diagram for sector I is illustrated in Figure 3 and with the same way are attained the same switching equations for other sectors.
Figure 5 presents the digital circuit for sector selection and switching time calculation. The comparators calculating the differences vpq=vp- vq (p=a,b or c and ~q=b,c or a ) give the amplitude of the difference with a sign that gives the result of the comparison, (e.g. if difference vab=va- vb is positive, then flag A is set to 1, else A is reset to 0), and according to Table 2, the digital logic condition for the sector selection is simplified and this in turn will save enormous FPGA resources.
Figure 5. Sector selector and timing of the active vectors.
The differences are also used as an input to two (4:1) multiplexers to select for each sector condition the appropriate switching-on times (Tx and Ty) which simplifies the switching-times calculation to only few operations compared to other modified SVPWM algorithms which use complex trigonometric calculations.
T.
3.2 SVPWM generator
To drive the three-phase switches, SVPWM pulses Sa, Sa and Sb are generated by a comparision with a triangle carrier signal with switching times Ti , Th and Tz calculated in the previous stage, as showen in Figure 6.
Figure 6. SVPWM digital implementation.
This switching strategy is identical for all sectors. The SVPWM generator is controlled by threshold values Th, Ti and next signals logic and the state output is governed by the selected sector logic calculated by the data path of Figure 6.
The SVPWM threshold values required for the PWM pulse generator, Ti =Tx/2 and Th =(Tx +Ty)/2, are calculated as follows:
= (ya - vb)
Ts 2 Udc
Tç
Th = (va-vc)-±-
2Udc
TZ=TS- 2Th
(7)
(8) (9)
The obtained design is optimal and uses few logical and arithmetic operations compared to the modified optimized SVPWM implementations.
4 Simulation and Implementation
Figure 7 shows the hardware set-up constructed at our laboratory to test and validate experimentally the developed PWM techniques. The hardware used for the
digital implementation is an Altera DEO-Nano board. It contains 22K logic elements Cyclone IV FPGA. The Altera Quartus software is used as a development tool (IDE) for editing, compiling, and synthesis of the hardware implemented in the VHDL language.
Figure 7. Experimental hardware set-up.
A general RTL synoptic schematic of the implemented optimized SVPWM modulator is shown in Figure 8.
Figure 8. RTL view of the optimized SVPWM.
After a successful synthesis of the design, a report is generated by IDE which summarises, shows, and saves of the used recourses (Figure 9).
Flow Status Quartus Prime Version Revision Name Top-level Entity Name Family Device
Timing Models Total logic elements
Total combinational functions Dedicated logic registers Total registers Total pins Total virtual pins Total memory bits Embedded Multiplier 9-bit elements Total PLLs
Successful - Sun Jan 15 16:18:55 2017
15.1.0 Build 185 10/21/2015 SJ Lite Edition
modif_SVPWM
mtxlSVPWM
Cyclone IV E
EP4CE22E22C7
Final
903
903
18
CD
Figure 9. Compiler flow summary of optimized SVPWM.
The simulation results, presented in Figures 10 and 11 show a functional simulation for one period of a three phase balanced AC reference voltage.
Figure 10. Global simulation results of the SVPWM generator. Figure 13. Generated switching pulses for Sector 6.
Figure 11. Generated switching for Sector I (V100-V110)
Figure 12 presentes a zoomed area of a switching period for Sector I.
Figure 14. Zoomed results for one sector of the SVPWM generator.
A high-resolution (Hi-Res) mode in digital scope is used to filter out the difference between two phase patterns switches (Sa-Sb) shown in Figure 15. The obtained curve is a sinusoidal voltage of the reference voltage at the desired 50 Hz frequency.
Figure 12. Zoomed area for one sample time of the SVPWM generator.
The experimental real-time SVPWM patterns generated by the FPGA board and visualised by a digital scope are highlighted in Figures 13 and 14 for Sector VI.
Figure 15. Experimental results of three filtered line-to-neutral output voltages (Sa-Sb).
5 Conclusion
This paper presented the design and implementation of an optimized SVPWM generator using FPGA. This PWM modulator can be used in many inverter control applications for AC drives. To design such module on FPGA, a novel approach is introduced in order to reduce the number of used logic elements (LEs) compared to previous designs [15], [16], [17]. The modified SVPWM is optimized so as to have simple digital logic functions for sector selection and a few sets of arithmetic subtractions and multiplexing to calculate the switching times. This strategy overcomes the trigonometric shortcomings of the conventional SVPWM algorithm. Experimental results confirm that the proposed SVPWM scheme works properly for the AC-voltage generation.
References
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[5]	Mauricio Tonelli, Pedro Battaiotto and Maria I. Valla, FPGA implementation of an universal space vector modulator, IECON'Ol The 27th Annual Conference of the IEEE Industrial Electronics Society, 2001, pp. 1172-1177.
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[15]	S Mazumdar & K Ray (1988) A Microcomputer Controlled Drive Signal Generator for 3-Phase Sinusoidal Pulse-Width Modulated Inverters, IETE Technical Review, 5:5, 211-219, DOI:10.1080/02564602.1988.11438293
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Ahmed Belkheiri received his engineering degree in electronics and instrumentation from the University of Laghouat in 1998. He obtained his magister degree in the IC design and control from the University of Hadj Lakhdar Batna in 2005. He is preparing his PhD thesis on the subject of different PWM techniques for AC drive control. Since 2007 he has been teaching in the Department of Electrical Engineering at the University of Amar Telidji- Laghouat. Email: a.belkheiri@,lagh-univ.dz
Said Aoughellanet obtained his engineering degree in electrical engineering in 1990 and his magister degree in automatic control in 1992. He received his PhD degree in electronics/control from the University of Ferhat Abbas, Setif, in 2006. Since 2005, he has been an associate professor at the Department of Electronics, University of Hadj Lakhdar - Batna. His research interests include robotic trajectory tracking, power inverter and speed variator control using FPGA. Email: asunibat@yahoo.fr
Mohammed Belkheiri obtained his engineer degree in electrical engineering from the University of Boumerdes in 2000, and his magister degree in robotics and automatic control from the Military Polytechnic School of Algiers in 2002. He received his PhD degree in automatic control from the Ecole Nationale Polytechnique d'Alger in 2008. He is currently working as a professor in the electrical engineering department at the University of Laghouat.. His research interests include nonlinear, adaptive and intelligent neural networks control of electromechanical systems and robotics. Email: m.belkheiri@lagh-univ.dz