VERTICAL SILICON-ON-NOTHING FET: SUBTHRESHOLD SLOPE CALCULATION USING COMPACT CAPACITANCE MODEL B. Sviličič1, V. Jovanovic2, T. Suligoj3 1Faculty of Maritime Studies, University of Rijeka, Rijeka, Croatia 2ECTM-DIMES, Delft University of Technology, The Netherlands 3Faculty of Electrical Engineering and Computing, University of Zagreb, Croatia Key words: Silicon-on-Nothing, fully-depleted MOSFET, vertical SONFET, subthreshold slope, compact model Abstract: The subthreshold slope model of the Vertical Silicon-on-Nothing FET, extracted from the compact capacitance model, has been developed. For short-channel effects modeling the voltage-doping transformation is used. The analytical model is verified by comparison to the two-dimensional numerical device simulator, MEDICI, over a wide range of different device structures. Good agreement is obtained for channel lengths down to 50 nm. Vertikalni SONFET: modeliranje podpragovne tokovne karakteristike Kjučne besede: SONFET, vertikalni SONFET, naklon podpragovne tokovne karakteristike, modeliranje Izvleček: Razvili smo model podpragovne tokovne karakteristike vertikalnega tranzistorja SONFET ( Silicon-on-nothing FET ). Analitični model smo preverili s primerjavo rezultatov dobljenih z dvodimenzionalno simulacijo s programom MEDICI. Dobili smo dobro ujemanje izračunanih in izmerjenih vrednosti za dolžine kanala navzdol do 50nm. 1 Introduction The scaling of conventional CMOS is approaching technological limits /1/, and the need for replacement device architecture is growing. A possible alternative is the Silicon-on-Nothing (SON) technology /2/, where the epitaxial process is used for the formation of the sacrificial SiGe layer and top Si layer for the active device part. The sacrificial SiGe region is later removed below transistor channel and replaced by an insulating material, resulting in quasi-SOI structure in the active region. However, the SON MOSFET (SONFET) transistors are processed on bulk Si wafers with reverse biased source and drain junctions to the substrate. This eliminates one of the major advantages of standard SOI technologies, which is the reduction of parasitic capacitances. The SON technology can also be transferred to SOI substrate, but with considerable increase in process complexity. The Vertical Fully-Depleted SONFET (VFD SONFET) is developed as a further evolution of the lateral SONFET /3, 4, 5/. The channel length of the vertical SONFET is defined by the molecular-beam epitaxy (MBE), allowing the channel-length reduction into the sub-30 nm region without the need for high-resolution lithography. Furthermore, standard bulk region underneath the buried oxide is eliminated (Fig. 1.). The absence of the transistor bulk is a unique property of the VFD SONFET, not present in either bulk or SOI CMOS. The subthreshold slope value is one of the key issues for deep-submicrometer devices, with the target value of 60 mV/dec at temperature of 300 K. In this paper, we give an analytical solution for the VFD SONFET subthreshold slope based on the compact capacitive model in subthreshold region. The voltage-doping transformation (VDT) is used for short-channel effects modeling and the solutions are verified in comparison to the results of two-dimensional device simulator. 2 Modelling 2.1 Capacitive model in subthreshold region The analytical solution for subthreshold slope is based on the capacitive model in subthreshold region (Fig. 2.). The compact capacitive component model for the VFD SONFET operating in accumulation, depletion and inversion condition is presented in /6/. Intrinsic capacities include the capacitance of the depleted silicon body Csi,d, gate oxide capacitance CGox=kGoxLeii/tGox, and buried oxide capacitance CboX: ^BOX ~ ^ 1 + (1) I-Si channel D N+ ^^GOX BOX G S N+ P substrate Fig. 1. (a) VFD SONFET structure cross-section, (b) VFD SONFET structure close-up. Fig. 2. Capacitive model of the VFD SONFET in the subthreshold region. The buried oxide capacitance Cbox of the VFD SONFET has specific, two-dimensional properties and its analytical Fig. 3. Equivalent capacitive circuit of the VFD SONFET in the subthreshold region. relation is given with an approximation by perpendicular planes. For the effective channel lengths that are tBOX < Leff/2 analytical relation is given: -BOX In 1+ '■BOX '^BOX , (2) Overlap, fringe and source/drain depletion capacitances are also included in Fig. 2, but do not have significant influence on the subthreshold slope. Equivalent capacitive circuit of the VFD SONFET in the subthreshold region is shown on the Fig. 3. Applying the Ohms law at each node, we calculate the relation between the front-gate surface potential (interface gate-oxide/Si-film) and the back-gate surface potential Ys2 (interface Si-Film/BOX) /Fig. 1 (b)/: ^aox y (3) = C„ Q 2C BOX y + C (4) where Qsi,d=-qNAtsi is the depletion charge, VFB1 = VTln(NGNA/ni2) is the top-gate flat-band voltage, VFB2=VTln(Ns-DNA/ni2) is the back-gate flat-band voltage, and Vd and Vs are drain and source voltages, respectively. With source voltage being zero (Vs=0), the following relations can be used: Vd+Vs=Vd=Vd-Vs=Vds. From the equivalent capacitive circuit, the analytical solution for the gate voltage VG is extracted: 1 + -jr^-^ ^ Caox^su 1 1 -+- (5) (-GOX (pShd + ) CßOX (f-SId + ^(-BOX ) 2.2 Two-Dimensional Effects: Voltage Doping Transformation An elegant and compact solution for two-dimensional model is offered by the concept of Voltage-Doping Transformation (VDT) /7/. VDT enables to account for 2D-effects into quasi 1D-analysis of the VFD SONFET. According to this concept, the influence of the lateral field initiated by the junctions is equivalent to a reduction in the effective channel area doping. The effective doping in channel area: . p 2V' A A j2 'ikf Where (6) (7) where Vds is the drain-source voltage, '^bi=VTln(Ns.DNA/ ni2) is the built-in potential. The back-gate surface potential Ys2 is given: qNJsiLeff (8) ^BOX The silicon body capacitance with short channel effects (VDT) taken into account is therefore: '"Si.d - -:rr. -- (9) As the subthreshold slope is defined in the regime before the onset of the strong inversion, the silicon body capacitance C''si,d will be evaluated for the front gate surface potential: (10) where y^b=VTln(NA/n) is the difference between Fermi level and intrinsic level. 2.3 Subthreshold slope model Using the definition for the subthreshold slope as the gate voltage variation needed for the change of one decade in the drain current /8/ and applying the gate voltage solution (5) and the VDT approximation (6-10), the subthresh-old slope follows as: dlog/^ ' ' q d^,, = ln(lO> kT 1 + ^aox k^si.d + 2 ^Box ) (11) The complex influence of the VFD SONFET parameters are combined in a simple form of (11) with second term in the bracket being responsible for the difference from the ideal S value of 60 mV/dec at 300 K. The scaling tendencies are clear from the capacitance ratio, where Cgox should be increased and C*si,d and Cbox decreased to approach the ideal value. 3 Calculation and simulation results In order to verify the accuracy of the analytical model for the subthreshold slope, the calculated results are compared to a two-dimensional numerical device simulator, MEDICI /9/. Concentration dependent model for the low-field carrier mobility and the velocity saturation mobility model at high parallel electric field were used. Band-gap narrowing in silicon and polysilicon, Shockley-Read-Hall recombination and Auger recombination are taken into account. The gate current was modeled by the Lucky-electron gate current model and the simulation temperature was 300 K. The simulator does not include quantum effects. Focus of this paper is the device subthreshold characteristics where the quantum effects are less pronounced and the drift-diffusion model can be considered accurate. The calculated and simulated subthreshold slope values plotted against effective channel-lengths Leu are shown in Fig. 4. for different: (a) gate oxide thickness tGox, (b) gate dielectric kGox, (c) BOX dielectric kBox, and (d) BOX thickness tBox. The examined devices take advantage of the fully-depleted structure and have an effectively undoped channel for higher mobility. The range of effective channel-lengths investigated was between 288 nm - long channel case, and 22 nm - very short-channel. The simulated structures in each plot varied only in the effective channel-length with other dimensions and technological parameters kept the same. For the effective channel lengths down to 100 nm, subthreshold values are close to ideal values of approximately 60 mV/dec. Agreements between the values obtained by the numerical simulations and analytical model are within 2 mV/dec (3%) for the channel lengths down to 50 nm. For shorter channel lengths (<50 nm) the deviation of our model is mainly due to the rough VDT approximation of the effective doping in channel area N'a and thus the calculation of the silicon body capacitance C'si.d. As the channel length is reduced the influence of the last term in relation (11) becomes higher and more accurate modeling of C'si.d is necessarry. The subthreshold slope can be improved by increasing the value of the gate oxide capacitance Cgox, or by decreasing the value of the buried oxide capacitance Cbox. If the gate oxide thickness tGox is scaled down /Fig. 4. (a)/ or the material with higher dielectric constant kGox is used for the gate oxide /Fig. 4. (b)/ the characteristics show expected improvements. The case of material with the lower dielectric constant kBox used for the buried oxide /Fig. 4. (c)/ also improves the subthreshold slope, as well as thinner buried oxide thickness tBox /Fig. 4. (d)/. 4 Conclusions The subthreshold slope model extracted from the compact capacitance model of the VFD SONFET has been demonstrated. It has been shown that the developed model has high accuracy for channel lengths down to 50 nm and can be extended even further with improvement of the voltage-doping transformation, which is used to account for short-channel effects. With the simple processing of the VFD SONFET, devices with very short gates can be fabricated and the presented model used for the prediction of the subthreshold behavior. The specific, two-dimensional 150 O aj > C a tyj 'o I 100 - 50 A'^=10 cm r= 300 K G |l o" cm"' N^^ = 1 o" cm"' ♦ m Medici ■ 'lei ■■ 1 nm 1 nm ♦ Medici ^^^^ 4 nm --- ■ 'iel 4 nm 0 50 1 00 1 50 200 250 300 EfTective Cliaiuiel Length [mn] (a) Fig. 4. Comparison of subthreshoid siope vaiues against effective channel lengths obtained by MEDICI simulations and analytical model for different: (a) toox, (b) koox, (c) Kbox, (d) tBox. K=k/so. characteristics of the VFD SONFET structure are accurately described in the model and combined in a simple relation for the subthreshold slope. This offers clear insight into influences of different parts of the structure and can be used to estimate the performance of scaled devices. ACKNOWLEDGMENTS The authors would like to thank Petar Biljanovic for support and suggestions. This work was supported in part by the Croatian Ministry of Science, Education and Sports (scientific projects 036-0982904-1642 and 036 -0361566 - 1567). REFERENCES /1/ B. Sviličič, A. Kraš, "CMOS Technology: Challenges for Future Development", Journal Pomorstvo, November 2006. /2/ M. Jurczak, T. Skotnicki, M. Paoli, B. Tormen, J. Martins, J. L. Regolini, D. Dutartre, P. Ribot, D. Lenoble, R. Pantel, S. Mon-fray, "Silicon-on-Nothing (SON) - an Innovative Process for Advanced CMOS", IEEE Trans. on Electron Devices, vol. 47, p. 2179, 2000. /3/ P. E. Thompson, G. Jernigan, J. Schulze, I. Eisele, T. Suligoj, "Vertical SiGe-based Silicon-on-Nothing (SON) technology for sub-30nm MOS devices", Materials Science in Semiconductor Processing 8, pp. 51 -57, 2005. /4/ I. Radinkovič, V. Jovanovic, T. Suligoj, J. Schulze, I. Eisele, G. Jernigan, and P.E. Thompson, "Scaling Properties of Vertical Silicon-on-Nothing (SON) MOSFETs", MIPRO, 2004. /5/ V. Jovanovic, T. Suligoj, J. Schulze, I. Eisele, G. Jernigan, and P.E. Thompson, "Characteristics of 30 nm Long Vertical Silicon-on-Nothing (SON) MOSFET", MIPRO, 2005. /6/ B. Sviličič, V. Jovanovic, T. Suligoj, "Vertical Silicon-on-Nothing FET: Capacitance-Voltage Compact Modeling", MIPRO, 2007. /7/ T. Skotnicki, G. Merckel, T. Pedron, "The Voltage-Doping Transformation: A New Approach to the Modeling of MOSFET Short-Channel Effects", IEEE Trans. Electron Devices, vol. 9, no. 3, pp. 109-112, March 1988. /8/ B. Sviličic, V. Jovanovic, T. Suligoj, "Vertical Silicon-on-Nothing FET: Analytical Model of Subthreshold Slope", MIDEM 2007, 2007. /9/ Synopsys, Inc., Taurus Medici, Two-Dimensional Device Simulation Program, Version x-2005.10-0, 2005. B. Sviličič, Faculty of Maritime Studies, University of Rijeka, Študentska ulica 2, 51000 Rijeka, Croatia Phone: +385 (0)51 338 411, Fax: +385 (0)51 336 755, E mail: sviiicic@pfri.hr V. Jovanovič, ECTM-DIMES, Delft University of Technology, The Netherlands T. Suligoj Faculty of Electrical Engineering and Computing, University of Zagreb, Croatia