Review scientific paper Original scientific paper 4 2 1 2 3 © MIDEM Society 5 49 ISSN 0352-9045 Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 1(2021), March 2021 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 51, številka 1(2021), Marec 2021 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 1-2021 Journal of Microelectronics, Electronic Components and Materials VOLUME 51, NO. 1(177), LJUBLJANA, MARCH 2021 | LETNIK 51, NO. 1(177), LJUBLJANA, MAREC 2021 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2020. All rights reserved. | Revija izhaja trimesecno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale – Društvo MIDEM. Copyright © 2020. Vse pravice pridržane. Editor in Chief | Glavni in odgovorni urednik Marko Topic, University of Ljubljana (UL), Faculty of Electrical Engineering, Slovenia Editor of Electronic Edition | Urednik elektronske izdaje Kristijan Brecl, UL, Faculty of Electrical Engineering, Slovenia Associate Editors | Odgovorni podrocni uredniki Vanja Ambrožic, UL, Faculty of Electrical Engineering, Slovenia Arpad Bürmen, UL, Faculty of Electrical Engineering, Slovenia Danjela Kušcer Hrovatin, Jožef Stefan Institute, Slovenia Matija Pirc, UL, Faculty of Electrical Engineering, Slovenia Franc Smole, UL, Faculty of Electrical Engineering, Slovenia Matjaž Vidmar, UL, Faculty of Electrical Engineering, Slovenia Editorial Board | Uredniški odbor Mohamed Akil, ESIEE PARIS, France Giuseppe Buja, University of Padova, Italy Gian-Franco Dalla Betta, University of Trento, Italy Martyn Fice, University College London, United Kingdom Ciprian Iliescu, Institute of Bioengineering and Nanotechnology, A*STAR, Singapore Marc Lethiecq, University of Tours, France Teresa Orlowska-Kowalska, Wroclaw University of Technology, Poland Luca Palmieri, University of Padova, Italy Goran Stojanovic, University of Novi Sad, Serbia International Advisory Board | Casopisni svet Janez Trontelj, UL, Faculty of Electrical Engineering, Slovenia - Chairman Cor Claeys, IMEC, Leuven, Belgium Denis Ðonlagic, University of Maribor, Faculty of Elec. Eng. and Computer Science, Slovenia Zvonko Fazarinc, CIS, Stanford University, Stanford, USA Leszek J. Golonka, Technical University Wroclaw, Wroclaw, Poland Jean-Marie Haussonne, EIC-LUSAC, Octeville, France Barbara Malic, Jožef Stefan Institute, Slovenia Miran Mozetic, Jožef Stefan Institute, Slovenia Stane Pejovnik, UL, Faculty of Chemistry and Chemical Technology, Slovenia Giorgio Pignatel, University of Perugia, Italy Giovanni Soncini, University of Trento, Trento, Italy Iztok Šorli, MIKROIKS d.o.o., Ljubljana, Slovenia Hong Wang, Xi´an Jiaotong University, China Headquarters | Naslov uredništva Uredništvo Informacije MIDEM MIDEM pri MIKROIKS Stegne 11, 1521 Ljubljana, Slovenia T. +386 (0)1 513 37 68 F. + 386 (0)1 513 37 71 E. info@midem-drustvo.si www.midem-drustvo.si Annual subscription rate is 160 EUR, separate issue is 40 EUR. MIDEM members and Society sponsors receive current issues for free. Scientific Council for Technical Sciences of Slovenian Research Agency has recognized Informacije MIDEM as scientific Journal for microelectronics, electronic components and materials. Publishing of the Journal is cofi­nanced by Slovenian Research Agency and by Society sponsors. Scientific and professional papers published in the journal are indexed and abstracted in COBISS and INSPEC databases. The Journal is indexed by ISI® for Sci Search®, Research Alert® and Material Science Citation Index™. | Letna narocnina je 160 EUR, cena posamezne številke pa 40 EUR. Clani in sponzorji MIDEM prejemajo posamezne številke brezplacno. Znanstveni svet za tehnicne vede je podal pozitivno mnenje o reviji kot znanstveno-strokovni reviji za mikroelektroniko, elektronske sestavne dele in materiale. Izdajo revije sofinancirajo ARRS in sponzorji društva. Znanstveno-strokovne prispevke objavljene v Informacijah MIDEM zajemamo v podatkovne baze COBISS in INSPEC. Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madic Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina placana pri pošti 1102 Ljubljana Journal of Microelectronics, Electronic Components and Materials vol. 51, No. 1(2021) Content | Vsebina 3 25 49 63 73 85 Review scientific papers B. Pecar, D. Resnik, M. Možek, D. Vrtacnik: Microfluidics: a review J. Štremfelj, F. Smole: Nanotechnology and Nanoscience – From Past Breakthroughs to Future Prospects Original scientific papers K. Arunachalam, M. Perumalsamy, A. Ramasamy: Multi-Port Memory Design in Quantum Cellular Automata Using Logical Crossing H. Ercan, S. A. Tekin: A Low-Voltage Current Mirror for Transconductance Amplifiers M. Kovacic: Effect of Dipole Position and Orientation on Light Extraction for Red OLEDs on Periodically Corrugated Substrate - FEM Simulations Study N. Roongmuanpha, W. Tangsrirat: Practical Floating Capacitance Multiplier Implementation with Commercially Available IC LT1228s Front page: Wearable integrated microdosing system for transdermal drug delivery (D. Vrtacnik) Pregledni znanstveni clanki B. Pecar, D. Resnik, M. Možek, D. Vrtacnik: Mikrofluidika: pregled podrocja J. Štremfelj, F. Smole: Nanotehnologija in nanoznanost – od preteklih dosežkov do obetov za prihodnost Izvirni znanstveni clanki K. Arunachalam, M. Perumalsamy, A. Ramasamy: Vecvhodni spominski dizajn kvantnih celicnih avtomatov z uporabo logicnega križanja H. Ercan, S. A. Tekin: Nizkonapetostno tokovno zrcalo za transkonduktancne ojacevalnike M. Kovacic: Vpliv Pozicije in Orientacije Dipola na Izstop Svetlobe Rdecih OLED na Periodicno Teksturiranem Substratu – FEM Simulacijska Obravnava N. Roongmuanpha, W. Tangsrirat: Prakticna uporaba množilnika plavajoce kapacitivnosti s komercialnim IC LT1228s Naslovnica: Integrirani mikrodozirni sistem za cezkožni vnos ucinkovin z rezervoarjem, mikrocrpalko in poljem votlih silicijevih mikroigel (D. Vrtacnik) Editorial | Uvodnik Dear reader, Another year is around, a special year that we will all remember. It was a year of covid-19 that continues to affect our lives and limit our freedom. For our journal it was a year of celebration, since we published the 50th volume. Thanks to open access all papers are accessible in WoS, Scopus or DOAJ by a single mouse click. We sincerely hope that the open-access papers will help us in wider dissemination and larger readership. In 2020 we received more than 150 manuscripts, out of which only 16 have been accepted for publication so far, while 45 were out of scope and 75 manuscripts were rejected. The success rate remains low (close to 10% in 2020) primarily because we receive many manuscripts that do not meet the quality and originality that we aim at. Citation metrics with JCR IF-2019=0.340, SNIP-2019=0.353 and CiteScore-2019=0,90 is an important performance indicator. In 2020 we published 24 original scientific papers and I sincerely thank all reviewers and Editorial Board Members for their valuable contribution to the journal. As a part of your success in science and engineering we commit ourselves to continue serving you and look forward to receiving your future manuscript(s) on our submission page (http://ojs.midem-drustvo.si/). Stay safe and healthy! Prof. Marko Topic Editor-in-Chief 31 March 2021 https://doi.org/10.33180/InfMIDEM2021.101 Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 1(2021), 3 – 23 Microfluidics: a review Borut Pecar, Drago Resnik, Matej Možek, Danilo Vrtacnik University of Ljubljana, Faculty of Electrical Engineering, Laboratory of Microsensor Structures and Electronics, Ljubljana, Slovenia Abstract: Microfluidics technologies have become a powerful tool in life science research laboratories over the past three decades. This review discusses three important segments of the field from origins and current status to future prospective: a) materials and microfabrication technologies from the field, b) research and development of essential microfluidic components and c) integration of components into complex microfluidic systems that will, according to some forecasts, play a key role in improving the quality of life for future generations. The most sophisticated microfluidic systems developed by now are Point-of-Care systems, that are based on Lab-on-Chip technologies. As these subfields are very extensive and go beyond the scope of this review, some carefully chosen additional review papers are provided. Keywords: microfluidics; materials; technologies; micropumps; flowmeters; microneedles; fuel steam reformers; microdosing systems; LOC; POC Mikrofluidika: pregled podrocja Izvlecek: Mikrofluidne tehnologije so v zadnjih treh desetletjih postale nepogrešljivo orodje sodobne znanosti. Pregledni clanek pokriva tri pomembne segmente podrocja: a) materiale in tehnologije za izdelavo mikrofluidnih naprav, b) raziskave in razvoj osnovnih mikrofluidnih komponent in c) integracijo komponent v kompleksne mikrofluidne sisteme, ki bodo po napovedi mnogih imeli kljucno vlogo pri zagotavljanju višje kakovosti življenja prihodnjih generacij. Med najnaprednejše mikrofluidne sisteme uvršcamo sisteme za hitro analizo na samem mestu odvzema vzorca, ki temeljijo na tehnologijah »laboratorija na cipu«. Ker podrocja teh sistemov presegajo obseg tega dela, smo podali nekaj dodatnih skrbno izbranih preglednih clankov s podrocij. Kljucne besede: Mikrofluidika; materiali; tehnologije; mikrocrpalke; merilniki pretoka; mikroigle; mikroprocesorji goriva; mikrodozirni sistemi; LOC; POC * Corresponding Author’s e-mail: borut.pecar@fe.uni-lj.si 1 Introduction Since Richard Feynman’s thought-provoking 1959 speech “There’s Plenty of Room at the Bottom”, human­ity has witnessed the most rapid technology devel­opment in its history—the miniaturization of devices [1]. Microelectronics was one of the most significant enabling technology of the last century. Until recently, the development of miniaturized transducer and flu­idic devices lagged behind this miniaturization trend in microelectronics. In the late 1970s, silicon technology was extended to 3-D machining of mechanical micro­devices, which later came to be known as microelec­tromechanical systems (MEMS) [2]. The development of microvalves, micropumps and microflow sensors in the late 1980s dominated the early stage of microflu­idics. Since then, microfluidics is rapidly emerging as a breakthrough technology that finds applications in di­verse fields ranging from biology, chemistry, pharmacy, biomedicine to information technology and optics [3]. Microfluidics can be defined as the science and tech­nology of manipulating small amount of fluids in chan­nels with dimensions of tens to hundreds of microm­eters [4]. Due to their small scale, microfluidic devices have advantages over conventional devices. Among the advantageous properties are, large surface area to volume ratio, which lowers the diffusional distances dramatically and very low reagent consumption [4]. Consequently, they can enhance the reaction efficien­cy, reduce the analysis time, simplify procedures and provide highly portable systems [5]. Furthermore, they can be easy to use, cheap to fabricate and disposable [6]. The purpose of this review is to give a broad overview of the field, summarizing recent advances in materials and microfabrication technologies in relation to the field, addressing the essential microfluidic components and outlining the integration of components into wide variety of miniature-sophisticated systems capable of performing even the most demanding tasks. The re­mainder of the review paper is organized as follows: Section 2 covers relevant materials and technologies for microfluidic applications. Correspondingly, silicon, glass and polymer materials will be addressed. Focus will be on precedent research activities in the field of reactive and deep reactive ion etching of silicon, dry and wet etching of glass and polymers micromachin­ing. Since most microfluidic devices require bonding of substrates with additional functional layers to create enclosed volumes, various bonding processes such as silicon-silicon, silicon-glass and thermoplastic–polydi­methylsiloxane bonding will be reviewed. Section 3 is devoted to microfluidic components. First, an overview of micropumps, microvalves and micro­actuators will be given. Regarding micropump inte­gration into modern polydimethylsiloxane (PDMS) microfluidic systems that require miniaturization and autonomy, focus in this subsection will be on PDMS elastomeric micropumps, especially on microthrottle pumps and peristaltic micropumps. Moreover, addi­tional micropump functionalities such as bidirectional pumping and low pulsating flow will be discussed. Sec­ond, flowmeters for microfluidic applications will be outlined. Various flowmeter measurement principles and reported functional devices will be summarized. Focus will be on thermal mass microflowmeters, which have been fabricated on a wide variety of substrates. Here, past efforts which led to improvements of flow­meters sensitivity and response time, will be reviewed. Third, heaters, coolers and temperature sensors for mi­crofluidic platforms will be addressed. Temperature is a critical parameter in managing many physical, chemi­cal and biological microfluidic applications therefore many interesting approaches to this issue have been proposed. Fourth, overview of microneedles will be made. The microneedles are essential in microfluidic systems for transdermal drug delivery applications. They have been made from various materials using different fabrication processes and were applied us­ing many approaches to enhance the drug delivery through the skin. Section 4 deals with microfluidic systems, where mi­crofluidic components discussed in Section 3 are inte­grated and functionally interconnected into advanced microfluidic platforms. Such systems can execute even the most demanding tasks required by the modern sci­ence. Here, several most representative microfluidics systems will be addressed, starting with micro fuel re­formers, more specific with methanol steam reformers, which convert methanol solution into a hydrogen rich gas needed for fuel cells to generate electricity. Many different approaches related to this field and which have been reported in the last sixteen years and greatly im­proved conversing efficiency, will be reviewed. Tempera­ture control and fuel supply for micro fuel reformers will be also addressed from the microfluidic aspect. Next, microdosing systems for drug delivery, which typically comprises several integrated microfluidic components such as micropumps, microfluidic channels, reservoirs and microneedle arrays, will be suggested. In this sub­section, innovative bubble-type, shape memory alloy and other non-mechanical microdosing systems will also be tackled. At the end of the Section 4, Lab-on-Chip (LOC) and Point-of-Care (POC) systems, which are the most sophisticated microfluidic systems developed by now, will be described. As these subfields are very exten­sive and go beyond the scope of this review, we will pro­vide some additional carefully chosen review papers in conjunction with foodborne pathogens detection, drug development, stem cell analysis, cardiovascular disease prevention, infectious disease diagnostics etc. Few ex­amples of successful transformations of LOC technolo­gies into actual POC devices will follow. Our conclusions are drawn in the final Section 5. 2 Materials and technologies for microfluidic applications Microfluidic devices originate from microelectronics fabrication sector [7]. Silicon has been most frequently used as the base substrate material for fabrication of microfluidic devices in the past. However, silicon sub­strate is relatively expensive and optically opaque at certain wavelengths, limiting its applications in optical detection. To combat these shortcomings, glass and polymer materials have been introduced into micro­fluidic devices [7]. Polymer materials in microfluidics include polymethylmethacrylate (PMMA), polystyrene (PS), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene (PE) and PDMS. Amongst these polymer materials, PDMS has been one of the most widely used materials for fabricating microfluidic de­vices due to its flexibility in moulding and stamping, optical transparency and biocompatibility [8]. The literature on microfabrication techniques for mi­crofluidic applications shows a variety of approaches. Silicon microfabrication is a process that involves the removal of silicon material using wet chemical or dry plasma etching processes such as reactive ion etch­ing (RIE) or deep reactive ion etching (DRIE) in order to create 3-D silicon or non-silicon microstructures for microfluidic devices [9]. An excellent overview of tech­niques involved in advanced microfabrication of silicon was written by Resnik et al. [10]. RIE has limitations in producing deep vertical silicon structures and is more often used for etching thin inorganic and organic lay­ers. To overcome these limitations, Vrtacnik et al. [11] studied and optimized RIE of deep silicon microchan­nels for microfluidic applications. Optimal set of etch­ing parameters resulted in high silicon etching rate (2 µm/min), good anisotropy close to 90°, lateral undercut less than 6% and surface roughness of less than 1 µm. DRIE process was first introduced by Bosch in the mid-nineties and commercialized by several equipment manufactures. DRIE is capable of forming vertically smooth sidewalls at high etch rate (>10 µm min-1) [12]. An improved DRIE process for ultra high aspect ratio silicon trenches with reduced undercut was reported by Owen et al. [13]. By ramping process pressure, etch power and switching time, authors were able to produce 5.7 µm trenches with an aspect ratio of 70. Giang et al. [14] reported microfabrication of shallow concave pits or deep spherical cavities in PDMS using DRIE silicon molds. Effect of DRIE process parameters on the surface mor­phology and mechanical performance of silicon struc­tures were studied by Chen et al. [15]. Authors designed and performed a set of experiments to fully characterize surface morphology and mechanical behavior of silicon samples produced with different DRIE operating condi­tions. Similarly, Vrtacnik et al. [16] performed optimiza­tion of Bosch process for DRIE silicon microstructures. After optimization, directional Si etching resulted in etch rate of 3.0 µm min-1, profile angle close to 90°, roughness of sidewalls less than 150 nm and aspect ratio higher than 10 (see test pillar structures in Fig. 1). Figure 1: SEM image of test Si pillar structures fabri­cated by optimized DRIE etching. Source: Vrtacnik et al. [16]. For glass microfabrication, three major groups of tech­niques are used: mechanical treatment, dry and wet etching. Mechanical treatments include traditional drilling, ultrasonic drilling, electrochemical discharge and powder blasting. The dry etching technique of Py­rex glass using SF6 was reported by Li et al. [17]. Authors fabricated small through holes in Pyrex glass wafers in­tended for electrical feed-throughs. The disadvantage of glass etching by DRIE was relatively low etching rate, which extended etching time to 10 hours. Wet etching of glass is the most common method and was reported by Stjernström and Roeraade [18]. In this work, capil­lary electrophoretic chips were fabricated in glass us­ing photoresist as the mask layer. Excellent review on wet etching of glass for microfluidics was given by Ili­escu [19]. For polymers micromachining, soft lithography [20], hot embossing [21], injection molding [22], casting [23], laser micromachining [24] and milling [25] are the most commonly applied. Most microfluidic devices require bonding of substrates to create enclosed volumes for fluid handling. There­fore, various bonding processes have been developed in the last thirty years to mutually bond silicon, glass and polymer layers. Direct silicon wafer-to-wafer bond­ing without the use of intermediate adhesive layer was employed by Thompson et al. [26]. To heat silicon wa­fers above 1000 °C before they were brought into con­tact, electromagnetic induction was applied. Typical power consumption was in the range of 900 to 1300 W for silicon wafers with the diameter values between 75 and 100 mm. Low temperature direct bonding of sili­con and silicon dioxide by surface activation method was investigated by Takagi et al. [27]. Neutralized high-energy Ar beam etching (FAB 110, Atom Tech, UK) was used to create a clean surface which had strong bond­ing ability. The specimens were brought in contact and bonded in vacuum. Modified process for low tempera­ture direct silicon bonding was reported by Quenzer and Benecke [28]. After a hydrophilic pretreatment, a diluted solution of sodium silicate in water was spun onto one of the two surfaces and the two wafers were brought into contact. Resnik et al. [29,30] studied di­rect bonding of (111) and (100) oriented silicon wafers performed in the range of temperatures from 80 to 400 °C in nitrogen, oxygen and low vacuum atmosphere. Authors found that bond strengthening in nitrogen ambient exhibited about 25% higher tensile strength compared to bonding performed in vacuum or oxygen. The combination of glass and silicon is a common choice for fabrication of microfluidic systems. Glass can be bonded to silicon with fusion bonding process or anodic bonding process. Fusion bonding process as applied by Xiao et al. [31] comprises thorough sili­con wafers cleaning during which Si–O–Si bonds of the native oxide on the silicon surface.The Si–O–Si bonds on the glass surface are cleaved by the attack of OH- and H+ ions. The new Si–OH groups on wafer surfaces are formed after the silicon and glass wafers are put together face to face in a clean room at room temperature. Resnik et al. [32,33] focused on issues ac­companied with defect free anodic bonding of multi­layer glass-Si-glass microfluidic structures. Pyrex 7740 and Borofloat 33 glass wafers were bonded to bare Si and Si/SiO2 terminated structures in the tempera­ture range 350-400 °C in the air ambient under applied anodic voltages between 800-1200 V. Authors concluded that appropriate configuration of bonding electrodes was mandatory to avoid debonding effects in multi­layer bonding process. Thermoplastic–polydimethylsiloxane assemblies in the field of microfluidics gained popularity in the last ten years [34]. Many strategies for plastic–PDMS bonding have been previously reported, such as sol–gel coating approach, chemical gluing approach and organofunc­tional silanes approach [35, 36]. First approach requires a multiple coating procedures as well as a complex technology. Second approach creates chemically robust amine–epoxy bonds at the interface at room tempera­ture, however, two silane-coupling reagents are required and both surfaces had to be oxidized prior to chemical modification. Third approach requires only one coupling agent. In this approach, the most widely used organo­functional silane is 3-amino propyltriethoxysilane (APT­ES), aminosilane frequently employed in covalent bond­ing of organic films to metal oxides [37]. Pecar et al. [38] studied, optimized and applied two room-temperature bonding processes for thermoplastic - PDMS polymer covalent bonding based on organofunctional silanes APTES and amine-PDMS linker (Fig. 2). Both bonding processes were applied on piezoelectric micropumps where glass substrate was replaced by thermoplastic substrate. Water initiated the hydrolysis of covalent bonds established via the modified APTES bonding process while micropumps employing amine-PDMS linker exhibited no deterioration in their perfor­mance after eight weeks of continuous operation. 3 Microfluidic components 3.1 Micropumps The most often encountered components in microflu­idic systems are micropumps [39]. They are incorporat­ed into the system separately as discrete components or integrated into the microfluidic platform. Division of micropumps based on Krutzch classification [40] is shown in Fig.3. Micropumps employing displacement principle ex­ert pressure forces on the working fluid through one or more moving boundaries, while the onesemploy­ing dynamic principle add energy to the working fluid in a manner that increases either its momentum or its pressure. First, reciprocating micropumps require valves for its operation. Passive valves operate based on the pressure gradient, while active valves require outside actuation. In 1988, van Linte et al. [41] intro­duced diaphragm passive check valve. Seven years latter, Carrozza et al. reported ball valve [42]. Each ball valve consisted of a cylindrical chamber connected to a hemispherical chamber, which contained a mobile ball. First cantilever flap was reported by Koch et al. in 1998 [43]. For this flap, deep boron diffusion together with KOH etching was employed. Recently, Pecar et al. [44] proposed venous-valves micropump with valves that mimic the operation of biological venous valves. Next, reciprocating micropumps require an actuator to perform pumping function. For this purpose, piezo­electric, electrostatic, electromagnetic, shape memory alloy and pneumatic or thermopneumatic actuators have been applied. Piezoelectric actuation with lead zirconate titanate (PZT) has been widely utilized for mi­cropump actuation due to small size, low power con­sumption, absence of electromagnetic interference and relatively low fabrication costs [45]. An effective method for reducing the excitation signal amplitudes in piezoelectric micropumps might be the use of high­ly efficient piezoelectric materials. The microcylinder pumps employing piezoelectric actuators based on relaxor-ferroelectric 0.57Pb(Sc1/2Nb1/2)O3–0.43PbTiO3 (PSN–43PT) was reported by Pecar et al. [46]. The per­formance results indicate that PSN–43PT is a promising material for high performance portable, wearable, or implantable micropump applications, where operation amplitude has to be kept low for reasons of safety and smaller plus more economic driver circuits. A special subgroup of displacement micropumps are pumps without check valves (fixed geometry, throt­tle, peristaltic). Rectifying effect is accomplished (a) by geometrically asymmetric channels or structures such as diffusers [47], Tesla valves [48] or oscillating sharp-edge structures [49] shown in Fig. 4, (b) by principle of peristaltics or (c) by use of throttle rectifying elements. Over the last decade, PDMS has become virtually the default material for forming microfluidic devices due to its simplicity of casting and bonding to the glass substrate [50]. Regarding micropump integration into modern PDMS microfluidic systems that are required to be miniature and autonomous, micropumps fabri­cated on PDMS elastomer are considered as the most appropriate. Incorporation of PDMS micropumps into microfluidic systems can be found widely in the recent literature. Wang et al. [51] proposed a check valve mi­cropump for implantable drug delivery application. A magnetic nanoparticle-PDMS composite membrane is actuated in a magnetic field to release a drug. For the same application, Gadad et al. [52] reported a dual-chamber valveless PDMS micropump. It produced 1.7 ml min-1 of water flowrate at excitation frequency of 14.8 Hz. Kawun et all. [53] reported a thin PDMS noz­zle/diffuser micropump for biomedical applications. The pump comprised a cast PDMS body, a spin coated PDMS membrane and commercial silicone tubing, all bonded together with PDMS. The pump produced a peak flowrate of 135 µl min-1 and a maximum back­pressure of 2.5 mbar at excitation frequency of 12 Hz and duty cycle of 25%. Chien et al. [54] proposed a ball valve PDMS/PC micropump on LOC microfluidic devic­es. It comprised a pair of ball valves implemented by confining a micro-ball within nozzle. Micropump ex­hibited maximum flowrate of 389 ml min-1 and a maxi­mum backpressure of 41.5 mbar. Regarding advanced microfluidic systems that require additional pumping capabilities and functionalities, several solutions were recently proposed. In 2018, Ye et al. [55] reported a PDMS check valve improvement for piezoelectric PDMS pumps. Authors achieved a con­siderable increase in the micropump flowrate perfor­mance by adding a blocking edge over conventional polydimethylsiloxane (PDMS) check valve. Generally, micropumps drive the fluid in only one direction. How­ever, bidirectional capability is an important feature in the development of chemical analysis especially in the fluid handling application such as mixing, circulation and metering [56]. For instance, in a chemical analysis, to mix two chemical compounds, a single directional flow micropump needs an additional active rotational mechanism to create turbulent flow in mixing process. With the bidirectional flow functionality, the microflu­idic system can be made in more efficient and com­pact structure, which merits from reducing the chemi­cal analysis time and complexity. Recently, a research group from Malysia [57] reported a PDMS bidirectional flow dual-chamber micropump for LOC applications. Authors implemented a dispersing depth between the microchannel chamber and inlet/outlet channel in or­der to achieve a bidirectional flow. For microfluidic systems where steady, low pulsating flow is required, a PDMS micropump system with ad­ditional PDMS fluidic capacitor was proposed [58]. Two single pneumatic micropumps connected in paral­lel exhibited maximum flowrate of 496 µl min-1. It was shown, that the PDMS structure with its elastic me­chanical properties smoothened pulsating flow with a smoothing factor of 0.6. In addition, Gidde and Pawar [59] addressed PDMS material properties and their in­fluence on PDMS micropumps performance. One sub-group of micropumps that does not employ check-valves are peristaltic micropumps. Conventional piezoelectric peristaltic micropumps comprise a series of sequentially actuated segments that deform fluidic channel on the principle of peristalsis to induce a net flow. The first piezoelectric peristaltic micropump with three piezoelectric actuators was reported by Smits in 1990 [60]. In 2003, Berg et al. [61] reported first peristal­tic micropump with two piezoelectric actuators. Here, an established mechanical traveling wave was induced by a proper signal phasing of two actuation sequences. Such provoked flow-rates were comparable to three-stage peristaltic micropumps. A two-stage micropump was patented in 2010 (U.S. 20100059127 A1). A first pi­ezoelectric peristaltic micropump with a single piezo­electric actuator was reported by Pecar et al. [62]. The fabricated prototypes featured high water / air flowrate performance (up to 0.24 ml min-1/up to 0.84 ml min-1) and backpressure performance (up to 360 mbar/up to 80 mbar). Furthermore, bubble tolerance and self-priming capability have been proved, together with valve regime of operation that enables sealing of the fluidic path when appropriate dc voltage was applied. Another sub-group of micropumps that does not em­ploy check-valves are throttle micropumps [63]. Their main advantage is high tolerance to clogging caused by mechanical particles or aggregates in the pumping medium, omitting the need for filters, which introduce significant pressure drop and increase system com­plexity. Furthermore, incomplete closing of rectifying elements (throttling) prevents damage to sensitive bio­logical samples. Compared to peristaltic micropumps, microthrottle pumps exhibit superior backpressure and flowrate performance. A novel design of a strip-type microthrottle pump with a rectangular actuator geometry was proposed by Pecar et al. [64], with more efficient chip surface consumption compared to ex­isting micropumps with circular actuators. Measured characteristics proved expected micropump opera­tion, achieving maximal flow-rate 0.43 mL min-1 and maximal backpressure 12.4 kPa at 300 V excitation. In 2014, Pecar et al. [65] introduced a novel concept of microthrottle pump, named “microcylinder pump”. Improved version of microcylinder pump was embed­ded in professional housing (see Fig. 5). Novel concept offers numerous advantages over conventional micro­throttle design including self-priming ability, high level of bubble tolerance, inhibition of the cavitation occur­rence and valve regime of operation. 3.2 Flowmeters Flowmeters are prerequisite for proper operation of a wide range of microfluidics devices. Four measurement principles are frequently employed in these devices, namely thermal dilution in a flow stream, transit time measurement of a tracer injected into the flow, pres­sure difference measurement across a restriction and force measurement on an element placed in the stream [66]. Figure 5: Piezoelectric microcylinder pump in a profes­sional housing. Wang et al. [67] demonstrated an electrolytic-bubble-based approach. Authors measured pressure differ­ence (and thus flow rate) in real time by simultaneously generating two gas bubbles electrochemically along a channel. Nezhard et al. [68] fabricated PDMS microcan­tilever flow sensor suitable for integration in LOC. The author’s attention was focused on a high aspect ratio microcantilever, which was fabricated using a multilay­er PDMS fabrication process. The device was capable of measuring flowrates as low as 35 µL min-1. Amnache et al. [69] reported microflowmeter for moderate flow­rates of gases based on a differential pressure meas­urement. It consisted of a microfabricated silicon–glass rectangular micro-orifice plate and two pressure sen­sors. Richter et al. [70] studied microflowmeter based on the micromachined electrohydrodynamic injection pump. Method is based on the measurement of the ion transit time between two grids. Another unique ap­proach was demonstrated by Accoto et al. [71]. Their PDMS microflowmeter for closed-loop management of biological samples detected the streaming poten­tial associated with the liquid flow by means of inter­face between polymeric surfaces and polar liquids and yielded a linear response. Nie et al. [72] reported mi­croflowmeter which operated in the range of 30–250 nl min-1 for water. The principle was based on determining the evaporation rate of the liquid via reading the number of wetted pore array structures in a microfluidic system, through which continuous evaporation took place. Thermal detection principles are widely used for air and gas flow sensors. An excellent state-of-the-art review in the field of thermal mass flowmeters was given by van Oudheusden [73] with the references therein. Typically, thermal mass flowmeter comprises a heating element which creates a local temperature increase and sens­ing elements that aim to measure the distortion in the temperature profile along the channel as induced by the fluid flow [74]. Several Si-based thermal flow sen­sors are currently available for measuring gas and liq­uid flowrates [75-77]. To enhance the device sensitiv­ity and to improve corresponding response time, heat dissipation to the substrate should be minimized [78]. Due to the high thermal conductivity of the silicon substrate, various schemes have been implemented in order to achieve the thermal isolation of the sens­ing elements, such as freestanding structures, vacuum cavities and formation of porous silicon, or thin silicon nitride membranes [78]. Baek et al. [79] reported a vac­uum-isolated thermal microflowmeter for in vivo drug delivery. Flowmeter used an arsenic-doped polysili­con heater/sensor, supported on dielectric membrane over the flow channel. Heater/sensor was capped by a vacuum-sealed microchamber to minimize heating of the surrounding structure and maximize heating effi­ciency. To provide highly effective thermal isolation of the heating/sensing elements without the need for above­mentioned thermal insulation approaches and addi­tional MEMS fabrication processes, attempts have been made to substitute silicon substrate with organic ma­terials such as  epoxy-based negative photoresist SU8 [79], polyimide [80, 81], Kapton® [82] and parylene [83]. Pecar et al. [84] proposed thermal microflowmeter for microfluidic applications where a PDMS elastomer was employed as heat insulative substrate between heater/sensor elements (Fig. 6). Device is suitable for integra­tion on common microfluidic platform with additional PDMS fluidic components. 3.3 Heaters, coolers and temperature sensors for microfluidic platforms Modern microfluidic systems require integration of multiple functions within a compact platform. One of such functionalities is the control of temperature, either in terms of profile or accessible range [85]. The temperature is a critical parameter in managing many physical, chemical and biological microfluidic applica­tions such as Polymerase Chain Reaction (PCR), Electro­phoresis (TGF), digital microfluidics, mixing and protein crystallization. The most commonly employed heating or cooling technologies exploit Peltier element, micro­waves, pre-heated liquids, integrated wires or lasers, chemical reactions and Joule heating. Matsu et al. [86] reported application of temperature gradient concentrator in a PDMS/glass hybrid microflu­idic chip. By the combination of a temperature gradi­ent along a microchannel using two Peltie elements, an applied electric field, and a buffer with a temperature-dependent ionic strength, Oregon Green 488 carbox­ylic acid was concentrated approximately 30 times as high as the initial concentration. Kempitiya et al. [87] explored the potential of microwave heating for appli­cations requiring parallel deoxyribonucleic acid (DNA) amplification platforms. For this purpose, authors de­livered microwave power at 6 GHz to the chamber via copper transmission line in a microstrip configuration. Temperatures up to 72 °C were achieved with less than 400 mW power consumption. An approach by using preheated and precooled liquids to generate a linear temperature gradient across a series of samples was employed by Mao et al. [88]. The three channel device (see Fig. 7 ) comprises a sandwich of glass and PDMS layers. Hot and cold fluids were introduced through the brass tubing using standard water bath circulators. The advantages of optical heating with laser are absence of the electric connections and the heating locations are more controllable comparing to the resistive elec­trodes. Optical approach was employed by Zhang et al. [89]. They used continuous wave laser induced heat to substitute microvalves and micropumps in microfluidic platform. Authors demonstrated effective blocking of microfluidic channels and bi directional pumping of fluid at a flow rate of 7.2–28.8 µl h-1. The interesting approach to heating and cooling in mi­crofluidics, especially in PCR, was proposed by Guijt et al. [90]. In that work, chemical and physical processes were employed to locally regulate temperature. Cool­ing and heating of the microchannel was achieved by evaporation of acetone (endothermic process) and by dissolution of concentrated sulfuric acid in water (exo­thermic process), respectively. Figure 7: Three-channel device using preheated and precooled liquids by Mao et al. [88]. Reprinted with per­mission from [88]. Copyright (2019) American Chemical Society. Regarding Joule heating, Mavraki et al. [91] reported low cost microfluidic device with integrated micro­heaters on a thin flexible polymeric substrate suitable to perform DNA amplification on a chip. The heating/sensing elements were formed on the Cu layer on the Pyralux substrate. Electrical measurements proved the functionality of the microheaters both as temperature sensors and thermal elements. Selva et al. [92] demon­strated Joule heating with electrical resistors that were fabricated by evaporating chromium (15 nm) and gold (150 nm) on the glass wafer. By applying improved op­timization algorithms, the shape of resistors was opti­mized to generate high-temperature gradients with a linear temperature profile. Hserh et al. [93] proposed a new approach to increase the temperature uniform­ity inside a microthermal cycler, especially for PCR, by using new array-type microheaters with active com­pensation units. In this study, platinum was used as material for the microheaters and the temperature sen­sors. Resnik et al. [94] reported thin film Ti/Pt heaters and integrated temperature sensors on a Si microflu­idic platform (Fig. 8). Heaters and sensors were fabri­cated by the combination of DC sputtering, lift-off process and thermal annealing of the deposited layers. Heater was able to provide vaporization of input liquid between 120 and 150 .C. Integrated Pt temperature sensors exhibited a typical TCR of 2200 ± 100 ppm/°C when annealed at 700 °C and proved stable during the prolonged operation. 3.4 Microneedle arrays Microneedles are essential in microfluidic systems for drug delivery application. They are used for delivering drug through the transdermal route and for overcoming the limitations of conventional drug delivery approaches [95].  Figure 8: fabricated microfluidic platform with the me­andered microchannel on the rear side (left) and a Ti/Pt heater and sensors on the front side (right) in PTFE housing. Microneedles differ in design and composition. Cur­rently, four distinct types of microneedles exist [96]: (a) solid microneedles often used to pretreat the skin prior to the administration of bioactives; (b) drug-coated sol­id microneedles for drug dissolution in the skin; (c) hol­low microneedles for drug injections; and (d) dissolving microneedles prepared from a polymer in which the drug or vaccine is embedded in the polymer matrix for the controlled or rapid release in the skin. In the early period microneedles used for drug delivery were made from silicon wafers through deep reactive ion etching and photolithography [97, 98]. Chen et al. [99] and Lin and Pisano [100] reported silicon microneedles with biodegradable tips and 6 mm-long silicon micronee­dles for localized chemical analysis, respectively. In the last fifteen years, various titanium [101], stainless steel [102], glass, ceramics [103] and polymeric [104-106] mi­croneedles were introduced. Since the diffusion of substances through the skin lay­ers is a gradual process, microneedles systems use vari­ous approaches to enhance the drug delivery through the skin. Common methods practice electroporation, iontophoresis, sonophoresis [107], use of chemical en­hancers [108], high velocity jet injection, ablation, tape stripping, vibratory, or impact assisted approaches [109]. Resnik et al. [110] reported investigation of skin penetration efficacy by a silicon microneedle array. When impact assisted penetration of microneedle ar­ray was applied instead of incremental increase of ap­plied force, a significant impedance reduction of up to 50% on animal skin and 95% on human skin was ob­tained, which was a strong evidence of successful skin penetration. Several publications have appeared in recent years documenting many successful microneedle arrays ap­plications. In recent study, Deng et al. [111] for the first time evaluated the ability of solid silicon micronee­dle array for punching holes to deliver cholesterol-modified housekeeping gene (GAPDH) siRNA to the mouse ear. Such development of siRNA therapies has significant potential for the treatment of skin condi­tions (alopecia, allergic skin diseases, hyperpigmenta­tion, psoriasis, skin cancer, pachyonychia congenital) caused by aberrant gene expression. In 2020, Kim et al. [112] delivered coronaviruses-S1 subunit vaccines by dissolving microneedle array. MERS-S1 subunit vac­cines elicited strong and long-lasting antigen-specific antibody responses in mice, implyingthat it is a prom­ising immunization strategy against coronavirus infec­tion. For diabetic patients, insulin delivery using hollow microneedle array is very desirable. In experimental study of in vivo insulin delivery conducted by Resnik et al. [113], two types of fast-acting insulin were used to provide evidence of efficient delivery by hollow mi­croneedle array to a human subject (Fig. 9). Results of in vivo insulin delivery proved successful infusion of fast-acting insulin as shown by blood analyses. Recently, a new cell transplantation method to inject donor cells into tissues to treat certain diseases using an array of ultrathin microneedles was reported by Iliescu et al. [114]. Here, an array of silicon microneedles was suc­cessfully employed to inject fluorescently labeled Mar­din–Darby canine kidney cells into rat liver tissue. Figure 9: SEM image of hollow Si microneedles array fabricated by DRIE etching (a) and assembled microin­jection device with 100 microneedles (b) view from the rear side, showing fluidic connection, distribution cav­ity and through holes. Source: Resnik et al. [113]. 4 Microfluidic systems 4.1 Micro fuel reformers With the rapid advancement in technology, everyday application of electronic devices such as laptops, cell phones, music players and other portable devices has become inevitable. Li-ion batteries are good options for providing the required energy for such devices. However, they require time-consuming recharging and are generally difficult to be recycled [115]. In contrast, liquid hydrocarbon fuels contains enormous energy per volume and weight compared to the best existing batteries, refueling is more convenient than recharging and recyclable fuel cartridges are more environmental­ly friendly. From the above reasons, various approaches were proposed to convert liquid hydrocarbon fuels to electrical power at micro-scale, such as using miniature gas turbine generators, fuel cells, thermo electric gen­erators, a thermophotovoltaic generator and a thermi­onic generator [116]. Among them, a miniature hydro­gen fuel cell system combined with a microfluidic fuel reformer seems one of promising candidates to power mobile devices. Microfluidics technologies enabled fabrication of catalyst coated microchannels with large surface area to volume ratio, which greatly increased fuel conversion efficiency. Methanol is one of the best choices for the hydrogen production since it is a liquid at room temperature and can be easily stored in small cartridges premixed with water. In 2004, Pacific Northwest National Laboratory devel­oped a micro integrated methanol reformer, which was equipped with a microcombustor, an evaporator and a CO methanizer [117]. It was small enough for port­able electronics but limited to 3.55 ml min-1 hydrogen production. Kamura et al. [118] reported a miniaturized methanol reformer with Cu/ZnO/Al2O3 catalyst-based microreactor shown in Fig. 10. The microreactor (25 × 17 × 1.3 mm3) was constructed from glass and silicon substrates. The use of the high-performance catalyst allowed for higher hydrogen production rates than us­ing a commercial Cu/ZnO catalyst. The microreactor was demonstrated to be capable maintaining a hydro­gen production rate suitable for powering 1 W-class devices. Hsueh et al. [119] presented a numerical investigation of the transport phenomena and performance of a plate methanol steam micro-reformer with serpentine flow field as a function of wall temperature, fuel ratio and Reynolds number. Jeong et al. [120] studied hydro­gen production by steam reforming of methanol  over Cu/Zn-based catalysts. Among the catalysts tested, Cu/ZnO/ZrO2/Al2O3 exhibited the highest methanol conversion and the lowest CO concentration in the outlet gas. Figure 10: Individual glass wafers of MEMS methanol reformer heated by decomposition of hydrogen perox­ide. Source: Kim et al. [121]. Kim et al. [121] proposed micro methanol reformer with a heat source. The micro system consists of the metha­nol steam-reforming reactor, the hydrogen peroxide catalytic decomposition reactor and a heat exchanger between the two reactors. Catalyst loaded supports were inserted in the cavity made on the glass wafer. The total hydrogen production rate was 23.5 ml min-1. This amount of hydrogen can produce 1.5 W of power on a typical proton-exchange membrane fuel cells. To improve the energy conversion of a micro-chan­nel reactor, Mei et al. [122] proposed and fabricated an innovative microchannel catalyst support with a micro-porous surface. Results showed that the microchannel catalyst support with micro-porous and non-porous sur­faces had a hydrogen production rate of 18.07 ml min-1 and 9.65 m min-1, respectively at 573 K under the inlet flowrate of 30 µl min-1. Huang et al. [123] studied the fractal channel pattern design and the gradient catalyst layer in relation to their effects on the performance of a methanol micro steam reformer. Compared to a uniform catalyst layer, the fractal design effectively increased the conversion ratio by 8.5% and decrease CO by 11% when the inlet liquid flow rate was fixed at 1.0 cc min-1. Recently, Sarafraz et al. [124] conducted series of experi­ments for the hydrogen production via steam reforming of methanol with Cu–SiO2 porous catalyst coated on the internal walls of a micro-reactor with parallel micro-passages. Wang et al. [125] proposed a partial oxidation methanol micro reformer with finger-shaped channels for low operating temperature and high conversing effi­ciency. Micro reformer supplied hydrogen to fuel cells by generating 2.23 J min-1 for 80% H2 utilization and 60% fuel cell efficiency at 2 ml min-1 of supplied reactant gas. Figure 11: Si based micro catalytic methanol–oxy­gen combustor with thin film nanostructured Pt/CeO2 catalyst in microchannels. To maintain the required reactions taking place in micro reformer unit, a micro combustor is commonly employed. The most convenient approach is to uti­lize the same energy source (methanol) for steam re­forming process and for catalytic combustion. In this case the methanol–air or methanol–oxygen mixture should be provided for combusting process. Corre­spondingly, Resnik et al. [126] studied Si based micro catalytic methanol–oxygen combustor with thin film nanostructured Pt/CeO2 catalyst (Fig. 11). The goal of the study was to reduce the catalyst load and to maxi­mize the catalyst effectiveness through better mass transfer by implementing of the new high performance mesoporous Pt/CeO2 catalyst with multiple layer depo­sition method and by the proposed micro combustor design. For proper operation of methanol fuel microreactor, precise temperature control and uninterrupted fuel supply is mandatory. Temperature control of metha­nol fuel microreactor for hydrogen production was re­ported by Peruško et al. [127]. The temperature control was achieved by on-off control with an adjustable hys­teresis. The heater actuation circuit comprised a boost converter, controlled by pulse width modulated signal from the microcontroller. The output of the boost con­verter was applied to the platinum (Pt) heater in the microreactor evaporation stage. To pump the fuel into microreformer, a fuel supply system is required. Pecar et al. [128] proposed a low cost, energy efficient flow-generator for hydrogen production in microreactors. The proposed approach is energy efficient and suit­able for implementation into a compact hybrid device, small enough to fit on microreactor housing. 4.2 Micro dosing systems for drug delivery A typical microdosing system comprises micropump, microsensor, microfluidic channel, reservoir and elec­tronics. It is mainly aimed at serious chronic diseases, such as diabetes, melancholia, malignant lymphoma, etc., or abrupt life threats, such as heart attack, stroke, septicaemia etc. [129]. With the automatic dosing sys­tem, the patients are protected from sudden death or irregular/incorrect taking medicine. Microdosing sys­tems are fabricated using bio-compatibile materials such as poly methyl methacrylate, poly-pimethylsilox­ane, SU-8 photo resist, or parylene C [129].  Bubble-type and other non-mechanical microdos­ing systems need no physical actuation components but its effectiveness, due to long time delay and slow response, are much devalued [129]. Bohm et el. [130] proposed a closed-loop controlled micromachined dosing system for accurate manipulation of liquids in microsystems down to the nanoliter range via ex­panding electrochemically generated gas bubbles. Another solution was described by Reynaerts et al. [131]. An implantable drug-delivery system based on shape memory alloy micro-actuation was based on a precisely controlled discontinuous release from a pres­surized reservoir by using a shape memory actuated microwave system. One dose can be controlled with accuracy up to 5 µl. However, shape memory alloys dosing systems suffer from a relatively low flowrate and insufficient bio-compatibility [129]. A microdosing de­vice comprising a dosing chamber, dispensing opening and vibration unit was patented by Koerner et al. [132]. Vibration unit was connected to at least one boundary surface of the dosing chamber. Consequently, bound­ary surface oscillated for the purpose of a dispensing operation. A plastic micro drug delivery system was successfully demonstrated by Ianchulev et al. [133], utilizing the principle of osmosis without any electri­cal power consumption. The system had an osmotic microactuator and a polydimethylsiloxane (PDMS) mi­crofluidic cover compartment consisting of a reservoir, a microfluidic channel and a delivery port. Induced osmotic pressure could extend up to 25 MPa to over­come possible blockages caused by cells or tissues dur­ing drug delivery operations. Than et al. [134] reported a strategy using an eye patch equipped with an array of detachable microneedles. Microneedles penetrated the ocular surface tissue, and served as implanted mi­croreservoirs for controlled drug delivery. System com­prised micro-seized membrane in sealed microfluidic reservoir, piezoelectric microcylinder pump and array of hollow Si microneedles. Biocompatible components were covalently bonded to each other to form a com­pact wearable system. Complete emptying of 590 µl sealed reservoir needed suction pressure of less than 50 millibars which minimized power consumption that is crucial for long device autonomy. Figure 12: Wearable integrated microdosing system for transdermal drug delivery by Vrtacnik et al. [136,137]. Kabata et al. [135] fabricated insulin pump using the volume change of hydrogen bubbles and conducted experiments using rats. To monitor the blood glu­cose level, a glucose sensor was employed. Recently, Vrtacnik et al. [136, 137] proposed and patented wear­able integrated microdosing system with a micronee­dle array for transdermal drug delivery (Fig. 12). 4.3 Lab-on-Chip and Point-of-Care systems One of the main objectives of microfluidic technolo­gies is to provide a total solution, from sample input to display of the analyzed results [138]. Complete ana­lytical protocols, from sample pretreatment through to sample and reagent manipulation, separation, reaction and detection can be performed automatically on well-designed and integrated miniaturized devices such as LOC systems. LOC devices are a subset of MEMS devices and often indicated by “Micro Total Analysis Systems” (µTAS) as well [139]. LOC devices comprise microchan­nels, integrated pumps, electrodes, valves, sensors and electronics to perform required tasks [140]. The term “Lab on Chip” was probably first used [141] by Moser et al. from Technical University Vienna [142] to describe the miniaturized thin film glutamate and glutamine bi­osensors developed by them. Research on LOC focuses on several applications including human diagnostics, DNA analysis and synthesis of chemicals [140]. The miniaturization of biochemical operations normally handled in a laboratory has numerous advantages, such as cost efficiency, parallelization, ergonomics, di­agnostic speed and sensitivity. LOC systems offer advantages for pathogen, toxin and virus detection. A review by Yoon et al. [143] summa­rized the requirements of LOCs for foodborne patho­gens detection and gave an overview on immunoassay and PCR-based LOC biosensors. A review by Weigl et al. [144] highlights LOCs for drug development, advances in LOC technology for flow-injection analysis, electro­kinesis, cell manipulation, proteomics, sample pre­conditioning, immunoassays, electrospray ionization mass spectrometry, and polymerase chain reaction. Overview on LOC technologies for stem cell analysis was presented by Ertl et al. [145]. Authors focused on the advantages of the microfluidic devices to over­come most of the challenges associated with stem cell identification, expansion and differentiation. Por et al. [146] focused on the latest developments in environ­mental LOC monitoring devices and provided future perspectives to overcome the challenges using print­ing technologies. Wu et al. [147] made a short review on LOC platforms for detection of cardiovascular dis­ease and cancer biomarkers. Ai et al. [148] summarized recent progress in LOCs for pharmaceutical analysis and pharmacological/toxicological tests. Authors gave insight into the challenges and possible breakthrough of Pharm-LOCs development. POC diagnostic systems are instruments that can rap­idly provide in vitro diagnostic results by non-trained personnel at a patient site, in the physician’s office, in the field, at home, in an ambulance, or in a hospi­tal [149]. There has been a growing need to provide diagnostic results at the point of care, for prompt treat­ment of acute diseases such as acute myocardial infarc­tion and for home-care diagnostics such as diabetes monitoring. In many ways, the features of microfluidics and LOC technologies are a natural fit for POC diagnos­tics devices [150]. Bringing the LOC technology to life through POC devices is a challenging task. So far, there have been only a few successes in the transformation of LOC technology to the actual POC devices with a real life application [151]. A review of POC diagnostic sys­tems using microfluidic LOC technologies was recently given by Sia at al.[152]. This review covers advances in POC technologies, commercially available POC diag­nostic systems and microfluidic LOC technologies. Park et al. [153] summarized advances in microfluidic PCR for POC infectious disease diagnostics. In this review, authors discussed practical issues and perspectives related to implementing microfluidic PCR technolo­gies into infectious disease diagnostics. Further on, in recent years, paper-based microfluidics has emerged as a multiplexable POC platform [154]. Paper-based microfluidics is considered a low-cost, lightweight, and disposable technology [155].  A review on paper-based microfluidic POC diagnostic devices was given by Yeti­sen et al. [156], covering fabrication of paper-based microfluidic devices, functionalization of microfluidic components and quantitative readouts via handheld devices and camera phones. Examples of successful transformations of the LOC technologies into an actual POC devices are encourag­ing. Ahn et al. [157] demonstrated a disposable plastic biochip incorporating smart passive microfluidics with embedded on-chip power sources and integrated bio­sensor array for applications in clinical diagnostics and POC testing. Neuzil et al. [158] demonstrated a high performance polymerase chain reaction system in port­able LOC for POC. Sun et al. [159] designed, fabricated, and tested miniature 96 sample ELISA-LOC for immuno­logical detection of Staphylococcal Enterotoxin B. Their simple POC system is useful for carrying out various immunological assays and other complex medical assays without a laboratory. Upaassana et al. [160] re­ported highly sensitive LOC immunoassay for protein biomarker that causes lung inflammation (see Fig. 13). Authors drastically reduced analysis time to about 30 min as opposed to hours in conventional methods. Recently, several authors demonstrated an integrated POC solution for noninvasive diagnosis and therapy monitoring of heart failure patients [161]. KardiaPOC™ is an easy to use portable device with a disposable LOC for the rapid, accurate, non-invasive and simultaneous quantitative assessment of four heart failure related biomarkers from saliva samples. Figure 13: Schematic diagram of the highly sensitive LOC for POC immunoassay for protein biomarker that causes lung inflammation by Upaassana et al. [160]. On-chip reservoirs store assay reagents. Air gaps iso­late reagents and prevent mixing while in storage and during the assay. Reprinted with permission from [160]. Copyright (2019) American Chemical Society. 5 Conclusions: Future perspective of the field The field of microfluidics has grown into a mature tech­nology capable of producing the most complex micro­fluidics systems that push the boundaries of today’s scientific and technological advances. Many challenges still lie ahead, but the main challenge remains how to translate a wide variety of successful microfluidic con­cepts from laboratory prototypes to robust end-user products in order to be more accessible. Many fabrica­tion processes currently employed in laboratory envi­ronment, including manually performed PDMS soft lithography techniques, are inappropriate for mass pro­duction of microfluidic devices due to speed and cost concerns. There is a need to overcome these limitations in the future. Advances in bioinspired smart materials are leading to next-generation fabrication technolo­gies for microfluidic devices such as 4-D printing, which adds a time dimension to the conventional 3-D print­ing and offer the capability to control size, shape and structure post-manufacture [162]. With the continuous development of novel fabrication technologies includ­ing 4-D printing, it is expected that the future micro­fluidic devices, will be less expensive, more integrated, more customizable and will incorporate a higher level of quality control [163]. Given the current state of the field, we can expect that future advances, particularly in POC systems, will have a transformative impact on the global health care system, which will improve the quality of life especially for elder people and people in developing countries [164]. Some exciting futuristic as­pects for the field of microfluidics was given by Tian et al. [165] as follows: »Microfluidics will provide autonomous distributed monitors for public health and surveillance for biothreats. The aging population will use health kits to provide preventive medicine. Medical checkups will be performed daily. Healthcare costs will be reduced due to the availability of microfluidics instruments. Chronic disease patients will possess home diagnostics systems and high risk patients (e.g. post surgical) will enjoy the comfort of being at home knowing that LOC de­vices will be monitoring risks of infection, blood clots, etc. Microfluidic devices will increase the efficacy and safety of medical treatments by assisting in the pre­scription and administration of drugs. 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Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 Figure 4: Acoustic streaming phenomenon around the tip of a tilted oscillating sharp-edge structure in acou­stofluidic pumping device actuated by piezoelectric transducer. Source: Huang et al. [49]. Figure 3: Division of micropumps based on Krutzch classification [40] where throttle and peristaltic pumps were additionally assigned to “valves” category. B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 Figure 6: Thermal microflowmeter for microfluidic ap­plications and piezoelectric micropump on common substrate by Pecar et al. [84]. PDMS elastomer is em­ployed as heat insulative substrate between heater/sensor elements. B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 B. Pecar et al.; Informacije Midem, Vol. 51, No. 1(2021), 3 – 23 Copyright © 2021 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 1(2021), 25 – 48 https://doi.org/10.33180/InfMIDEM2021.102 Nanotechnology and Nanoscience – From Past Breakthroughs to Future Prospects Jernej Štremfelj, Franc Smole University of Ljubljana, Faculty of Electrical Engineering, Ljubljana, Slovenia Abstract: Nanoscience and nanotechnology are already improving our lives in numerous ways. The aim of this paper is to give an insight into the vast array of their potential future uses, as well as current applications, and present the major breakthroughs, which made their development possible. A special section is reserved for the development in the field of microelectronics, which is facing numerous challenges due to the downsizing of devices to the nanometre level. Current situation in microelectronics industry and predictions for the next few years are presented. Furthermore, the use of nanotechnology and future prospects in the fields of medicine, energetics, environmental protection and transport are described. A significant part of this paper is devoted to the field of electronics and information technology, where some potential nanotechnological solutions for the challenges of microelectronics are implied. The use of carbon nanotubes in logic circuits and memory applications is presented. The basic principle of single-electron transistor is also described. Basic concepts of the use of spintronics in magnetoresistive random access memory (MRAM) structures are explained. Memristor is also presented as an important future prospect. In the last part, the investments in nanotechnology and nanoscience under the funding programmes of European Union are presented, followed by some predictions of these fields’ future development. However, the review paper focuses only on positive effects of the use of nanotechnology, and thus does not discuss its possible negative impact on public health and environment. Keywords: nanotechnology; nanoscience; microelectronics; carbon nanotubes; quantum dots Nanotehnologija in nanoznanost – od preteklih dosežkov do obetov za prihodnost Izvlecek: Nanoznanost in nanotehnologija že izboljšujeta naše življenje na razlicne nacine. Namen clanka je podati vpogled v širok nabor potencialnih podrocij njune uporabe tako v današnjem casu, kot tudi v prihodnosti in predstaviti pomembnejša odkritja, ki so omogocila razvoj tega podrocja. Posebno poglavje je namenjeno razvoju na podrocju mikroelektronike, ki se zaradi manjšanja dimenzij na nanometrski nivo sooca s številnimi izzivi. Predstavljena je trenutna situacija v mikroelektronski industriji in obeti za naslednjih nekaj let. V nadaljevanju je predstavljena uporaba nanotehnologije in obeti za prihodnost na podrocjih medicine, energetike, varovanja okolja in transporta. Pomemben del clanka je namenjen podrocju elektronike in informacijskih tehnologij, kjer so predstavljene nekatere potencialne nanotehnološke rešitve za izzive mikroelektronike. Predstavljena je uporabnost ogljikovih nanocevk v logicnih vezjih in pomnilniških strukturah. Razloženo je osnovno delovanje enoelektronskega tranzistorja. Podani so koncepti uporabe spintronike v pomnilniških strukturah MRAM (magnetoresistive random access memory), kot pomemben obet za prihodnost pa je predstavljen tudi memristor. V zadnjem delu so navedena sredstva, ki jih Evropska Unija v okviru svojih programov financiranja namenja za razvoj nanotehnologije in nanoznanosti. Navedenih je tudi nekaj napovedi glede razvoja opisanih podrocij v prihodnosti. V clanku so predstavljeni le pozitivni vplivi uporabe nanotehnologije, medtem ko analiza morebitnih negativnih vplivov na okolje in zdravje ljudi ni vkljucena. Kljucne besede: nanotehnologija; nanoznanost; mikroelektronika; ogljikove nanocevke; kvantne pike * Corresponding Author’s e-mail: js8675@student.uni-lj.si 1 Introduction Nanotechnology focuses on developing materials, structures and systems by manipulating matter on the 1-100 nm scale [1], [2]. However, the final objective does not necessarily have to be nanodimensional. It is of most importance that new properties, which occur at the nanometre scale are being taken advantage of [1]. The role of nanoscience is to pave the way for nano­technology by studying those phenomena [2]. The fact is that the nanometre world behaves a little differently as one would expect based on one’s visible and also micrometre world experience. Physical, mechanical, chemical, electrical and numerous other properties of particles are being completely changed as quantum ef­fects begin to rule their behaviour [1], [3]. Those effects are studied by an important branch of modern physics, called quantum mechanics, which was developed after the year 1900 [1]. One of the fascinating results of quantum effects at the nanoscale is that the particle properties are chang­ing with its dimensions. Therefore, material properties can be fine-tuned by changing the size of the particles. Thus, they can for example be labelled with fluorescent colours, which is useful for their identification [3]. An interesting example, which illustrates those unique properties is gold. A metal, which typically has a dis­tinctive yellow colour, occurs as red or purple at the nanoscopic scale (Fig. 1). The reason for this phenom­enon is that the movement of electrons is confined at the nanoscale dimensions, which gives golden nano­particles a different light response, compared to bigger particles. Their small dimensions and special optical properties make them increasingly useful in medicine. They are being accumulated selectively in cancer cells, which allows precise laser destruction of tumour, with­out harming healthy cells [3]. Figure 1: Light response of gold nanoparticles with different diameters. Reprinted with modification (crop­ping) from [4]. Copyright 2016-2020 Phornano Holding GmbH. Another quantum effect that is completely contradic­tory with the laws of classical physics is quantum tun­nelling through a potential barrier [3], [1]. In 1981, a scanning tunnelling microscope was invented on its basis and brought a Nobel Prize in physics to its inven­tors [5], [6]. All of the aforesaid examples certainly give us an ex­planation why developers in many completely differ­ent areas of modern technology strive for miniaturisa­tion. A simple thought experiment, which is depicted in Fig. 2, leads to additional arguments. Let us imagine a 1 cm3 cube. Its surface area is therefore 6 cm2. If we divide it into 1000 smaller cubes with 1 mm3 volume, we get a total surface area of 6000 mm2 or 60 cm2. If we continue with this procedure to the nanometre scale, we get 1021 cubes with volume of 1 nm3 and surface area of 6 nm2 each. By adding their surface areas, we get an astonishing value of 6 km2. Therefore, smaller particles have exceptionally large active surface area compared to their volume. Consequentially, there is more area for contact between particles, which in­creases their reactivity [3]. Figure 2: Increase in total surface area, achieved by diminishing particle size. Reprinted from [3]. Licensed under CC BY 3.0 license. 2 Microelectronics However, when speaking about decreasing dimen­sions, especially electronic engineers firstly think about the famous Moore’s law. Most electronic devices are downsizing especially due to their better functional­ity and compactness, and not because of fascinating nanodimensional phenomena. In addition, the devices are becoming cheaper with more chips being made on one silicon wafer. This development is made possible by downscaling of the basic components of integrated circuits – the transistors. The discovery of this element can be counted as the beginning of the microelectronic industry. This achievement was accomplished in 1947 in Bell Laboratories by William Shockley, John Bardeen and Walter H. Brattein, who were awarded Nobel Prize in physics, nine years later [1], [7]. Although the first transistor was a point-contact tran­sistor (Fig. 3), it represented a basis for the develop­ment of the first germanium bipolar transistor, based on two pn-junctions, which was conceived in year 1948 by Shockley and fabricated in 1950. Four years later, Gordon Teal from Texas Instruments made the first silicon version [9]. Next big breakthrough hap­pened in year 1958, when Jack Kilby realised integra­tion of elements on the same germanium substrate (Fig. 4.c). In 1959, Robert Noyce integrated also the connections, this time on a silicon substrate, and therefore laid the foundations for integrated circuit development [10]. In the same year, Dawon Kahng and Martin John Attala made the first metal-oxide semiconductor field-effect transistor (MOSFET) by growing a silicon dioxide (SiO2) layer on silicon wafer (Fig. 4.b) [11]. This was the first compact transistor, whose structure made possible the miniaturisation to the dimensions, used in today’s complementary met­al-oxide semiconductor (CMOS) integrated circuits [12]. The mentioned inventions are presented in Table 1 in chronological order. Two of them are also depict­ed in Fig. 4, which shows the progress in the design principles of electronic components and integrated circuits through years. Table 1: Important inventions, which made possible the development of microelectronics industry Inventor Year Discovery W. Shockley, J. Bardeen, W. H. Brattein 1947 First transistor W. Shockley, G. Teal, M. Sparks 1950 First germanium bipolar transistor G. Teal 1954 First silicon bipolar transistor J. Kilby 1958 Integration of elements on germanium substrate R. Noyce 1959 Integration of elements and connections on silicon substrate D. Kahng, M. J. Attala 1959 First MOSFET In 1965, Gordon E. Moore predicted that the number of components per integrated circuit would double every year in his article for the journal »Electronics« [19]. In 1975, he modified his assumption a bit, and predicted doubling approximately every two years [20]. 45 years later, we can conclude that his predictions were correct, which can be observed in Fig. 5. Achieving predicted miniaturisation became the driving force of microelec­tronics development. In the middle of the 1980s, the minimal gate length of the MOSFET reached 1 µm, whereas at the turn of the millennium the typical dimensions were already at around 150 nm [21]. In 2005, the 65 nm technology was introduced, five years later the main manufacturers al­ready produced chips in the 32 nm technology [1]. At this point, it is necessary to stress that inconsistencies between technology node names and actual transistor dimensions occurred through the years. The dimen­sions, stated in technology node name, are a conse­quence of International Technology Roadmap for Sem­iconductors (ITRS) [22] and its successor International Roadmap for Devices and Systems (IRDS) guidelines [23], which predict the development in this field for the next fifteen years. Until the mid-1990s, the technology node dimensions were consistent with the gate length of MOSFETs [24], while today they do not correspond to any of actual dimensions, but only reflect the gener­al technology progress [25]. That being the case, the In­tel’s 250 nm technology transistors had gate length of 200 nm, while its 180 nm technology transistors from a year later only 130 nm. The trend of more aggressive gate length scaling lasted to the year 2007, when Intel reached the gate length of 25 nm with its 45 nm tech­nology node. At that time, the gate length downscaling stalled for few years [26]. Miniaturisation to such small dimensions brought numerous disadvantages, which more than ten years ago indicated that CMOS technol­ogy would not be able to achieve further progress only by downsizing planar transistors. The MOSFET channel dimensions had decreased to such an extent that the voltage applied between the drain and the source be­gan to cause significant subthreshold leakage, which in­creased static power consumption in CMOS circuits. As a solution, the first three-dimensional (3D) MOSFET – fin field-effect transistor (FinFET) entered mass production in 2011, within the 22 nm technology node [27]. Figure 6: Visualisation of FinFET. Reprinted from [28]. Copyright 2010-2020 Samsung. In this type of transistor, depicted in Fig. 6, the channel is vertically raised above the substrate and surrounded with the gate on three sides, which limits the men­tioned current leakage. However, FinFET also has its disadvantages. By planar transistors, the channel width can be flexibly determined in order to achieve the de­sired current capabilities. Higher width-to-length ratio results in higher transistor current at certain gate-to-source voltage in the saturation region. It also brings higher transconductance of the transistor, which gives higher ratio between changes in drain current and gate-to-source voltage. By FinFET, the effective channel width cannot be so unrestrictedly set. It is equivalent to (1) where hfin denotes the channel height and wfin rep­resents the channel width. The height is limited with manufacturing process, while changing the width-to-height ratio is undesirable due to the worsening of characteristics. That issue was solved by developing FinFET with multiple fin structures [1]. This version of FinFET is also being used in the latest 5 nm technology [30], whose mass production was started by Taiwan Semiconductor Manufacturing Company (TSMC) and Samsung in 2020 [31]. Nevertheless, the way for the mass production is paved by prior research and development, which at the same time give us a look into the future prospects. On that basis, it is assumed that FinFET is soon going to be replaced with new solutions. The developers found additional room for improvement in the fact that Fin­FET’s bottom side was still connected to the body of the silicon, which meant that the subthreshold leakage could be further reduced. The idea was realised by the development of a transistor with the gate surrounding the channel on all sides – gate all-around field-effect transistor (GAAFET) [27]. The result of GAAFET development was firstly a transis­tor with the channel region in the shape of a very nar­row nanowire. However, the small channel dimensions did not provide sufficient currents and consequentially switching speeds, which was soon solved by stacking nanowires on the top of each other (Fig. 7 – GAAFET). Unfortunately, this approach also brought several limi­tations. Similar as by FinFET, the stack’s height was lim­ited. Furthermore, additional nanowires increased the device’s capacitance and thus slowed the transistor’s switching speed. Another downside was the complex manufacturing of very narrow nanowires, which could lead to structure irregularities [27]. The discussed problems were diminished by devel­oping a transistor with nanosheets (Fig. 7 – MBCFET), which is, according to Samsung, going to be used in the 3 nm technology, whose mass production is predicted to begin in the next years [32]. This is an improved ver­sion of the aforementioned GAAFET, with stacked thin sheets of silicon instead of nanowires. Thus, the effec­tive channel width is increased, while the leakage cur­rent is still limited. Moreover, the variable sheet width enables the channel width flexibility, which is not the case by FinFET [27]. Figure 7: Evolution of Samsung’s field-effect transis­tors. Reprinted from [33]. Copyright 2010-2020 Sam­sung. With all the described improvements, the validity of the Moore’s law, whose end has been foreseen by many, certainly extended for at least a decade. None­theless, all mentioned solutions are still based on the elementary version of silicon MOSFET, where the pho­tolithography with all its limitations remains the main technological process. The main problem regarding photolithography is that at the nanoscale dimensions, the diffraction of light causes significant random manufacturing variations, which can result in unpre­dictable behaviour of elements [1]. Nevertheless, we are witnessing a fast development also in this field. In the second half of 2019, the extreme ultraviolet li­thography (EUVL) at 13,5 nm wavelength succeeded the deep ultraviolet lithography using excimer argon fluoride (ArF) laser at 193 nm wavelength, in mass production of some 7 nm technology integrated cir­cuits [34], [1]. Despite the promising predictions of us­ing even shorter wavelengths, which could be made possible by the development of beyond extreme ul­traviolet lithography (BEUVL) [35], it is quite probable that downscaling, using only lithography processes will soon come to an end. Another issue, brought by small dimensions of integrat­ed circuits and high transistor density, is cooling. One of its consequences is the stall of the processor frequency, which has not significantly improved for approximately a decade and remains below 4 GHz in most cases. A po­tential solution for the near future is in using other, more efficient semiconductor materials as silicon, for example indium-gallium arsenide (InGaAs) [27]. Regardless of all foregoing solutions, it is inevitable that electronics industry is going to face essential changes in the future. It will be necessary to find alternatives to the CMOS technology, which are most likely going to be based on the aforementioned nanodimensional phenomena. Downscaling brought the dimensions al­most to the atomic level and consequently gave us a completely different perspective of future technologi­cal development. New approaches to the mentioned problems, using new materials are being researched. Many studies already focus on the self-assembly of na­nostructures on the atomic level [1]. 3 Atoms The idea of manipulating single atoms stirred already the imagination of ancient Greek philosophers. In the fifth century before Christ, philosophers Democritus and Leucippus, who were also the founders of the Greek philosophical school of atomism [36], stated that everything was composed of atomos (Greek word for “unbreakable”), which were indivisible. They claimed that those particles were solid and homogenous but varied in size, shape and weight. Between them, there was only empty space. Later on, their ideas came in for criticism and disapproval from other philosophers and were also considered atheistic by Christians [37]. Scientific establishing of the atomic theory began in the 17. century, when British scientist Robert Boyle proved the inverse relationship between the pressure of a gas and its volume, which is known as Boyle’s law. The pres­sure in a container of gas is a consequence of the atoms’ collisions with the container walls, which are more sig­nificant at a smaller volume of container. At the end of the 18. century, a French chemist Joseph Louis Proust empirically discovered that the ratio between different elements in a chemical compound always remains the same, without being affected by the way of its prepara­tion, which is consistent with the Democritus’ concept of indivisibility. His theory was later expanded by John Dalton, who figured out that the molecules consisted of fixed number of different atoms and therefore laid the foundations for the modern atomic theory [37]. In the 19. century, the question arose, what are the at­oms composed of. Joseph John Thomson was one of the scientists, who tried to answer it. He experimented with a closed glass tube with almost no air inside. With high voltage applied across two metal electrodes in it, he produced a visible ray and found out that the ray deflected in presence of electric or magnetic field. On the basis of the deflection and magnetic field measure­ments, he concluded that the particles in this ray were significantly lighter than atoms. In addition, he ob­served that they were attracted by positive charge and repelled by negative, which indicated their negative charge. He got similar results when using electrodes of other metals, which lead him to a conclusion, that these particles were present in all atoms [38]. Therefore, he showed that the atoms were not indivisible and proved the existence of electrons [39]. In 1904, he proposed a model of atom, depicted on Fig. 8.a, where the elec­trons were embedded in positively charged mass, mak­ing the atom electrically neutral. Next important break­through in studying electrons’ properties was achieved in 1909 by Robert Andrews Millikan, who found out the value of charge and mass of a single electron. However, the form of the atoms, especially the positively charged part, was still not properly explained [38]. The inaccuracy of by then proposed atom models was proved by Ernest Rutherford in 1911, even though he initially tried to confirm their correctness. He, Hans Geiger and Ernest Madsen conducted an experiment where they directed a beam of positively charged alpha particles to thin gold foil and observed their deflection. Assuming the Thomson’s model, which implied distri­bution of positive charge over the entire atom, was cor­rect, they expected little or no deflection of particles. However, whereas most of the particles really passed through the foil without any deflection, some of them were significantly diverted. On that basis, Rutherford concluded that most of the atom’s volume consisted of empty space, whereas at the centre of atom, there was a small, positively charged nucleus. He proposed a new model of atom, depicted on Fig. 8.b, with the elec­trons orbiting around the nucleus [38], [39]. Later, he discovered that all elements’ nuclei contained hydro­gen nuclei – positively charged subatomic particles. He named them protons [38]. In 1913, Niels Bohr found out that the movement of the electrons in orbits with arbitrary radii, as proposed in Rutherford’s model, was unstable. According to the classical physics, electrons would emit electromagnetic radiation when orbiting and consequently lose energy. Therefore, their orbits’ radii would diminish, so they would spiral towards the nucleus. Based on the find­ings of Max Planck and Albert Einstein, who postulated that the energy of radiation could have only discrete values, Bohr stated that the angular momentum of the electron was also quantised. Due to the quantisation, the orbits had fixed radii and energies. In order to jump to another orbit, the electron had to emit or absorb the energy equal to the difference of two orbits’ energies [44]. The Bohr’s model of atom is depicted on Fig. 8.c. However, the Bohr’s theory did not prove to be entirely correct. His model was based on the hydrogen atom, and could not explain the emitted spectrum of atoms with more electrons. Even hydrogen’s spectrum was not adequately explained with Bohr’s energy levels. Its individual spectral lines proved to be divided into more, closely spaced ones, which showed the exist­ence of additional energy states [44], [45]. In the early 1920s, the scientists started to develop a theory, where the matter was assumed to have both particle and wave characteristics. In 1923, Louis Victor de Broglie stated that the electrons should also be con­sidered that way [44]. In 1926, Erwin Schrödinger developed an equation, which represented the foundation of the quantum mechanics. It described the form of wave functions, whose values at a given point of time and space gave the information about the probability of the particle, being at that point. He applied and also successfully solved it for the hydrogen atom [46], [47]. Therefore, he proposed the quantum mechanical model of atom (Fig. 8.d), where the electrons were treated as waves. Instead of the exact location of an electron, only the probability of the electron, being in a given region could be determined [48]. The Schrödinger’s model of atom is still accepted as the most accurate one [39]. Nevertheless, the structure of atomic nucleus was not yet entirely understood. It was known that it contained protons, but its mass indicated the existence of addi­tional building blocks [49]. In 1932, James Chadwick observed the reaction between alpha particles and be­ryllium atoms. Neutrally charged particles with approx­imate mass of proton were emitted. These particles were named neutrons [50]. This finding also explained the existence of isotopes – chemically indistinguish­able atoms with different atomic masses, discovered by Frederick Soddy about twenty years before. The isotopes of a same element have different number of neutrons and consequentially different atomic masses, whereas their chemical properties remain the same, because of the same number of protons [38], [51]. Another quantum phenomenon that is important for understanding the atom’s structure is the electron spin. It was experimentally discovered by Otto Stern and Walther Gerlach in 1922. They directed a beam of electrically neutral silver atoms through an inhomoge­neous magnetic field. On the basis of the classical phys­ics and the assumption that the electrons would act as magnetic dipoles, they expected that the atoms would be deflected in different directions, based on the mag­netic dipole moments’ orientations, giving a random and continuous distribution on the screen. However, the atoms were deflected only in two directions. That result clearly indicated that electrons could exhibit only two possible, antiparallel orientations, which could not be explained by classical physics. The reason for that result was in the electron spin, which could have two possible values. Up and down [48], [1]. Three years after the abovementioned experiment, Wolfgang Ernst Pauli discovered that only two elec­trons could be located in the same orbital or energy level. In addition, they had to have the opposite spin. Hence, the electrons repel each other not only because of the charge, but also due to the parallel spins [1]. Another interesting empirical discovery was made by Friedrich Hund, who found out that the electrons in ground state always occupy the maximum number of empty orbitals. Therefore, if more energetically equiva­lent orbitals are available, they occupy the empty ones, rather than join an electron in a half-occupied orbital. Such arrangement of electrons is more stable [1]. Since that time, our understanding of the atomic world improved even more. However, the described transition from classical mechanics to quantum me­chanics, which crucially influenced the atomic theory, represents one of the most important advances in the history of physics. All the mentioned findings made many achievements of the nanotechnology possible. The electron spins can for example be used as qubits in quantum computing. The electron and also nuclear spin of phosphorus donor in silicon proved highly ap­propriate for such use [52], [53], [54]. 4 A half century of nanotechnology The outstanding potential of the abovementioned possibilities fascinated an American physicist Richard Feynman in the 1950s. His prophetic speech »There’s Plenty of Room at the Bottom«, which he held at the annual banquet of the American Physical Society in 1959, could be counted as the beginning of the his­tory of nanotechnology. Therein, he pointed out that the technology process miniaturisation to the atomic level was completely realisable according to the laws of physics and predicted that future technology was going to be based on rearranging the atoms as de­sired. He talked about the bottom-up approach, which represented an alternative to the top-down approach, which has been driving the miniaturisation in the field of microelectronics, according to the Moore’s law, for many more years. Feynman motivated the audience with numerous challenges, like for example writing the entire Encyclopaedia Britannica on a pinhead, or mak­ing an electrical motor, smaller than 0.256 cm3 and also offered a pair of 1000 $ prizes. Some of the challenges were already realised in months after the speech, which made it clear that his predictions were going to come true even sooner than he expected [37]. The term »nanotechnology« was first used in 1974 by a Japanese scientist Norio Taniguchi in a paper about the technological concepts on the nanometre level. He stated that atoms and molecules with the dimensions of 0.1-0.2 nm are the smallest particles in the process­ing of materials. In addition, he defined the separation, consolidation and deformation of materials by single atoms or molecules as a main part of the nanotechnol­ogy [55]. A very important breakthrough in further nanotech­nology and nanoscience development was achieved in 1981 by the scientists of the company International Business Machines (IBM) Zürich, who invented the aforementioned scanning tunnelling microscope [5]. Five years later, the atomic force microscope was in­vented in the same company and became the most important tool for observing and manipulating mate­rial on the atomic level [56]. In the following years, the increasingly efficient computing systems enabled pro­gressively demanding simulations, which, alongside with the experimental work, lead to fast development. In 1989, another scientific team from IBM managed to align 35 atoms of xenon in the form of letters »IBM« (Fig. 9) [57]. Figure 9: Thirty-five xenon atoms, arranged in the form of “IBM”. Image originally created by IBM Corporation. Another very important discovery had been made four years before by scientists Robert F. Curl, Harold W. Kroto and Richard E. Smalley, who discovered the carbon al­lotrope – buckminsterfullerene (C60) [58]. As a conse­quence, special structures of fullerene – the carbon nanotubes (CNTs) were discovered in 1991 [59]. Figure 10: Visualisation of a CNT. Reprinted from [60]. Copyright 2000-2020 Dreamstime. A structure of a CNT can be imagined as a graphene sheet, rolled into a hollow cylinder, as shown in Fig. 10. The carbon atoms are connected by sigma (s) bonds, which are the strongest type of covalent chemical bonds. This makes CNTs the strongest fibres. Topologi­cal defects in their structure, like pentagons and hepta­gons, embedded in the hexagonal lattice, enable their termination, as well as formation of joints and toroidal or spiral shaped nanotubes. In addition to the mechan­ical ones, they also have outstanding electrical, chemi­cal, optical, magnetic and thermal properties. Their di­ameter varies between 0.4 nm and 3 nm for single-wall CNTs or up to 100 nm for outer walls of multi-wall CNTs. They can be metallic or semiconducting. Researches have shown their potential as sensors, actuators, bat­teries, fuel cells, capacitors and field-emission devices, which makes them one of the most promising materi­als in the field of nanotechnology [1]. The studies of semiconductor nanocrystals also lead to the development of quantum dots [61]. These are small, in most cases semiconductor structures, with the dimensions that are comparable or smaller than the Fermi wavelength, which is around a nanometre for metals and few dozen nanometres for semiconductors. Therefore, the movement of electrons is restricted in all three dimensions, which results in discrete energy states of electrons that completely change the material properties (Fig. 11) [1]. What is more, the small dimensions bring higher re­activity to the material, because of more atoms on the surface, which can interact with the environment. Quantum dots can be used as charge islands in the cir­cuits based on the Coulomb blockade [1]. Additionally, their exceptional optical properties make them poten­tially useful in lasers, photodetectors [63], displays [64], solar cells [65] and also as biological markers. The re­turn of excited electrons to the ground state produces light emission. Therefore, by making sure that for ex­ample a semiconductor quantum dot stops on a cancer cell and is appropriately illuminated, a tumour can be detected [1]. In the 1990s, the progress of nanotechnology contin­ued at an increasingly high rate. In 1992, nanostruc­tured catalytic materials MCM-41 and MCM-48 were discovered. They are still being heavily used in refining crude oil and also in medicine [66], [67]. Seven years later, Lee and Ho from American university Cornell managed to assemble molecules of Cu(CO), Fe(CO), Cu(CO)2 and Fe(CO)2 from individual iron (Fe) and copper (Cu) atoms and carbon oxide (CO) mol­ecules, by using a scanning tunnelling microscope [68]. In the same year, Chad Mirkin invented dip-pen nano­lithography and so introduced one of the alternatives to the before described photolithography. As the name suggests, the material is deposited on the surface by an atomic force microscope tip, similarly as by writing with a pen on the paper (Fig. 12) [69]. Therefore, a mask is not necessary, which is a crucial benefit [1]. In the following years, nanotechnological solutions started to make their way to commercial products. Scratch-resistant car bumpers, antibacterial socks, faster-recharging batteries, electronic devices with improved displays and similar products began to ap­pear. The scientific achievements in this field were also increasingly frequent [67]. In 2003, the scientists at Rice University developed gold nanoshells, which at the right dimensions absorb near-infrared light and can therefore be used for discovery, diagnosis and also treatment of breast cancer [70], [67]. Two years later, Barish, Rothemund and Winfree from the California Institute of Technology made deoxyribo­nucleic (DNA) crystals that perform operations of copy­ing and counting by self-assembling and hence dem­onstrated the potential of algorithmic self-assembly for being used in creating complex nanoscale patterns [71]. Self-assembly of smaller components into larger and more complex ones due to intermolecular forces, similar as in nature, became one of the most promis­ing fields of research in nanotechnology [1]. In 2010, Seeman and his team from New York University made a 3D self-assembling DNA structure, whose construc­tion can be programmed by putting small cohesive se­quences on ends of the patterns [72]. Another unique achievement was made by IBM in the same year. Using a nanometre-sized silicon tip, they created a 3D relief world map with the dimensions of 22 µm by 11 µm in two minutes and twenty-three sec­onds [73], [74]. Considering the fact that bottom-up approach is in general slower than its top-down coun­terpart, achieving such manufacturing speed is very important. Thus, this achievement confirmed the great potential of such technological procedures. During the described development, most of the lead­ing industrial countries established the organisations committed to the progress of nanotechnology, where study of nanodimensional material properties in order to develop new processes and appliances, which in the end also bring economic results, remains the main re­search objective. Moreover, the education in this field and the awareness of the nanotechnology’s impact on public health and security are becoming increasingly important [75], [76], [77], [78]. 5 Nanotechnology and nanoscience today and tomorrow Nowadays, nanotechnology is a part of our lives, which is reflected on many different areas. Alongside with na­noscience, it plays a key role in the development and revolutionary improvements in electronics, informa­tion technology, medicine, energetics, transport, envi­ronmental remediation and generally our everyday life. The expectations of future development are also very promising [79]. 5.1 Everyday life Numerous commercial products for everyday use, which are based on the use of nanomaterials are al­ready available. Thin nanoparticle films on glasses, windows, computer screens and other surfaces make those surfaces water and dust repellent, anti-reflective, ultraviolet or infrared light-resistant, scratch-resistant or even electrically conductive [79]. Smart textiles with many nanosensors, which react to the stimuli from the environment and the human body are being devel­oped [80], [81]. Nanoparticles are being added to the materials for tennis rackets, bicycles, helmets and car parts and are therefore making them lighter, stronger and more flexible. Nanostructures are also used in de­greasers, stain removers and air purifiers. Another field of their use is personal care. Nanoparticles of titanium dioxide (TiO2) and zinc oxide (ZnO) have been used in sunscreens for years [79], [82]. 5.2 Medicine Nanotechnology is being increasingly used in modern medicine. Its contribution to the new solutions for dis­ease prevention, diagnosis and treatment is of great importance. It is enabling the development of better diagnostic tools, which are crucial for early disease di­agnoses, which increase the probability of successful treatment [79]. A promising example are the already mentioned gold nanoparticles with their unique physi­cal properties, which can be used as probes for detec­tion of specific nucleic acids sequences [83] and are also applicable to the most sophisticated photother­mal cancer therapy methods [84]. In addition, they can serve as a tool for cancer imaging [85], [86]. Nano­technology also has an enormous potential for treat­ment and diagnosis of atherosclerosis. High density lipoprotein (HDL) mimicking nanoparticles have been designed and are expected to have similar properties to native HDL, also known as »good cholesterol«, which removes cholesterol from atherosclerotic plaques [87]. Nanotechnology is also enabling the establishment of more effective drug delivery methods for the treatment of ophthalmological, pulmonary and cardiovascular diseases along with cancer therapy, where nanoscale delivery carriers are targeted directly to the cancer cell, improving the treatment efficiency and reducing side effects [88]. Bone and nerve tissue engineering also represent promising fields of research. It is possible to compose nanomaterials which are able to mimic the architecture of natural bone [89]. Nanoparticles have been also applied to many virus detection methods. A promising technique has recently been reported to detect severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2), which causes coronavirus disease 19 (COVID-19). They are also suitable for targeted vaccine delivery to mucosal and alveolar structures [90], which could serve as an alternative to parenteral vaccine ad­ministration [91]. 5.3 Energetics Nanotechnology is changing the field of traditional, as well as alternative energy sources. Numerous solutions for low loss energy generation and distribution with less of a negative environmental impact are being re­searched [79]. Nanocatalysts are improving the efficiency of many conversion processes in petroleum processing indus­tries [92]. Moreover, car fuel consumption can be re­duced by adding metallic nanoparticles to fuel, which ensure more efficient combustion [93]. Already de­scribed CNTs have proved effective as a low-tempera­ture adsorbents for carbon dioxide (CO2) capture from power plant flue gas [94]. CNT fibres also have a future potential to be used in electrical wiring. By controlled assembly of CNTs, material with excellent electrical conductivity could be produced [95]. In addition, im­proved materials for wind turbine blades are also be­ing developed using CNTs, which enable production of more durable and more efficient blades [96]. Na­notechnology is utilised also in the new photovoltaic solutions, where perovskite solar cells with their high efficiency and low cost represent a promising future prospect. They can also be utilised in tandem solar cells (Fig. 13), which possess a higher power conversion ef­ficiency potential than single-junction solar cells [97]. Different principles, including the utility of colloidal quantum dots are also being developed for thermo­electric generators, which can be used in converting waste heat into electrical power [98]. 5.4 Environmental protection In addition to the mentioned energy efficiency im­provements, nanotechnology also offers other possi­bilities, which can lead to better environmental protec­tion. Advancements are being achieved in detecting and removing the contaminants from different sub­stances [79]. Water purification is one of the most common exam­ples where nanomaterials can be utilised, improving existing remediation technologies [100]. Another ex­ample is water desalination with a single-layer mo­lybdenum disulphide (MoS2) nanopore, which can ef­fectively reject ions, allowing water flux that is two to five orders of magnitude greater comparing to other known nanoporous membranes [101]. Nanotechnolo­gy based techniques, using nanoscale zero-valent iron, CNTs and other nanomaterials are being developed for oil removal, which can contribute to future improve­ments of oil spill remediation [102]. Toxic gases in the ambient air can also be removed, exploiting adsorption properties of CNTs and gold nanoparticles [100]. CNTs can also be utilised in biosensors with fast responses and high sensitivity due to their electrical conductiv­ity, which is highly dependent on the concentration of certain gas molecules [1]. Fig. 14 depicts a FET-based CNT sensor structure. 5.5 Transport Nanotechnology offers various possibilities for improv­ing the existing technologies for automotive industry. With its capability to preserve lighter and stronger body parts and therefore enhance safety and fuel ef­ficiency, it can be incorporated in various parts of the vehicle. Coating with nanoparticles can improve the durability of paint and make it more scratch-resistant. In addition, ultra-thin hydrophobic layers of aluminium oxide on the mirrors significantly reduce the light re­flection. Moreover, nanoparticles of aluminium oxide can improve the tire durability when added to the rub­ber composite. Aluminium nanomaterials also have the potential to reduce friction of the engine cylinder walls, and therefore improve the engine efficiency [104]. Na­no-composite materials are also very promising in the field of aviation. CNT reinforced polymer (CNRP) can be incorporated in airframes, as an alternative to conven­tional aluminium. Study of O’Donnell and Smith [105] showed, that a decrease in airframe structural mass of 10,07% on average, as a consequence of using CNRP, resulted in decreased fuel consumption of 11,2%. Composite materials, reinforced with CNTs could also reduce icing effects [104]. Furthermore, nanotechnol­ogy also enables the progress in materials used for maritime transport. A study was made, where material with nanostructured titanium dioxide (TiO2) polymer coating proved to have higher corrosion resistance in seawater [106]. Alongside with all abovementioned improvements and future prospects, the transport engineering is also predicted to utilize nanotechnological solutions in future [107]. Nanostructure modification of materi­als should enhance their performance [108]. Nanopar­ticles represent one of the key technologies available for self-healing asphalt pavement design [109]. Highly sensitive nanosensors could also be embedded in con­crete and asphalt materials and therefore be used for the monitoring of road infrastructures [110]. 5.6 Electronics and information technology As already described, an astonishing progress has been made in electronics during the last fifty years. However, the miniaturisation has also brought many aforemen­tioned issues, which do not allow further development of CMOS technology only by downscaling planar sili­con MOSFETs. Consequently, new approaches are be­ing developed by using different materials, where the special nanodimensional characteristics play a signifi­cant role. Despite the fact that silicon technology is still far from being replaced, the breakthroughs in nano­technology clearly indicate that the development in the field of electronics is not going to stagnate soon [1]. 5.6.1 Carbon nanotubes As much as in other fields, CNTs also represent a prom­ising prospect in electronics. Similar as in the silicon technology, the p-type and n-type nanotube together form an element with semiconducting properties. Like­wise, a structure with the properties similar to those of heterojunction diode can be formed using a p-type semiconductor nanotube and a metal nanotube. If such a structure is placed on a silicon dioxide substrate with a gate contact, an element, similar to the junction field effect transistor (JFET) is formed. First experimen­tal versions of CNT field effect transistors (CNTFET) were introduced in 1998. Metal contacts were placed on the layer of oxide, which was deposited on the sili­con gate. Then, a CNT, which served as a channel, was grown between the metal electrodes by chemical va­pour deposition (Fig. 15). Researches have shown that by increasing gate voltage, the Schottky-barrier on the metal-nanotube junctions is being decreased, thus in­creasing the current [1]. Figure 15: Structure of CNTFET with a channel length of 18 nm, constructed by Infineon in 2004. Reprinted from [111]. Copyright 1999 - 2020 Infineon Technolo­gies AG. The design of CNTFET electrical circuits is quite similar to conventional technologies. The capability of creating both p-type and n-type nanotubes enables the design of CMOS-like circuits, identical to those in the silicon technology, which are known to be the most energy ef­ficient. Extraordinary properties of CNTs represent the main advantage of CNTFETs over conventional MOS­FETs. Clock frequencies up to 1 THz could be reached in the future due to their high carrier mobility [1]. With their energy efficiency and extremely small dimensions, those transistors represent one of the most perspective candidates for the successor of silicon-based technol­ogy. Nevertheless, the development of such transistors is facing numerous problems. Firstly, it is impossible to synthesise only semiconducting nanotubes. To achieve that, the diameter and chirality of CNTs would have to be precisely controlled. Thus, every CNT synthesis re­sults in a certain percentage of metallic CNTs, whose conductance cannot be sufficiently modulated by the gate of CNTFET. Secondly, CNTs bundle together into random structures during wafer fabrication, which re­sults in CNTFET failure. Thirdly, the conventional CMOS technology demands the fabrication of transistors with precisely controlled and tuneable properties, which is a severe issue by CNTFETs [112]. In 2013, Shulaker et al. in [113] demonstrated a miniature one-bit computer, made from 178 CNTFETs, whereas in 2019 they intro­duced a 16-bit microprocessor, comprising more than 14000 CNTFETs. During its development, they evolved new techniques of circuit design for significantly de­creasing the effect of metallic CNTs. Moreover, they developed an efficient process for removing undesir­able CNT bundles on the wafer, using special adhesive promoters and solvents [112]. They predict that CNTs in combination with the silicon-based technology could become a part of the integrated circuits production in few years [114]. The CNTs are also very promising in the field of data storage. Nano random access memory (NRAM) struc­tures, whose cells comprise of hundreds of CNTs, po­sitioned between two electrodes, are being devel­oped. Depending on the voltage on the electrodes, nanotubes connect or disconnect from each other (Fig. 16), which reflects in changed resistance, represent­ing a logical one or zero. One of the main advantages of NRAM is the non-volatility of CNTs, caused by mo­lecular binding forces, which keep them connected or separated without any voltage applied. NRAM is pro­jected to retain data for more than 300 years at 300 °C. Furthermore, by stacking the layers of memory cells on top of each other, very high data storage density could be achieved in the future [115]. CNTs can also be utilised as light sources in optoelec­tronics. Under certain circumstances, electrons and holes can enter the CNT simultaneously from the op­posite sides. When they meet, a recombination occurs, where the electron jumps from the conduction to the valence band, releasing the energy in the form of light. Another promising future area of usage are the ultra-thin computer screens, which are based on the field electron emission of the CNTs and are expected to be very energy efficient with better brightness and longer life span [1]. 5.6.2 Quantum dots Quantum dots also possess many potential applica­tions in electronics. Besides of those using the light emission of electron, which returns to the ground state, there are also other possibilities for their utilization. Quantum dot is a part of single-electron transistor. That is a structure, where the electrons are tunnelling between either source or drain and the quantum dot in between. The amount of energy needed for the tunnel­ling to take place is tuned by the third electrode – the gate, which is capacitively coupled to the quantum dot island (Fig. 17) [117]. Figure 17: Schematic visualisation of a single-electron transistor. Reprinted from [118]. Visualisation is in the public domain. Tunnelling of the electrons, which results in electrical current, is due to the Coulomb blockade possible only when appropriate combination of voltages is applied to the gate terminal and between drain and source electrodes (Fig. 18). Thus, the switching operation of the transistor is enabled at very low power consump­tion, which represents a potential for the future of logi­cal circuits. Coulomb blockade can be observed only at small enough dimensions, which result in small ca­pacitances between the quantum dot and the source or drain electrode. In this case, when the potential dif­ference between for example the source and quantum dot is too small, the tunnelling is not possible due to negative change in energy, stored in electric field be­tween the electrodes, which would occur by the trans­fer of an electron. However, this is valid only at tem­perature of 0 K. At higher temperatures, the Coulomb blockade is observable when the mentioned change in energy is larger than the thermal energy. Therefore, at room temperature, a quantum dot must be in size of few nanometres at most [1]. Figure 18: Stability diagram of single electron transis­tor. Shadowed areas depict the combinations of volt­ages, where tunnelling is not possible. Ug represents drain-to-source voltage, whereas UG represents gate voltage. U1 equals to , where q denotes elementa­ry charge and CG is the capacitance between gate elec­trode and quantum dot. When UG equals to odd mul­tiples of U1, the Coulomb blockade does not exist [1]. Apart from the challenges, associated with manufac­turing the quantum dots in so small dimensions, the effect of random background charge also represents a problem. Impurities with trapped charge in the insu­lating oxide can lead to logic errors in the single-elec­tron logic circuits or their unreliable operation. What is more, the transfer characteristics of single-electron transistor have more peaks and thus more voltages where tunnelling can occur. Consequently, the poten­tial single-electron logic circuits are going to be sensi­tive to noise and voltage drift [1]. However, the features of single-electron transistors make them usable in su­persensitive electrometers, infrared radiation detectors and also memory devices [119]. 5.6.3 Spintronics Another field, which offers promising possibilities for advancement, especially in data storage technolo­gies, is spintronics. That is a fairly new discipline, which deals with manipulation of the electron’s spin in order to code, store, transfer and process the information. By using the spin of electron instead of its charge, many improvements could be made in the field of electron­ics [1]. One of the most promising applications of the principles of spintronics is magnetoresistive random access memory (MRAM), based on the magnetoresist­ance effect, where the resistance of material, in this case a ferromagnetic, is being changed in the pres­ence of magnetic field [120]. The ability of movement of electrons in a ferromagnetic material depends on their spin orientation in relation to the material mag­netisation. Electrons with spin orientation parallel to the magnetisation move unlimitedly, in contrary to the electrons with antiparallel spin orientation, who thus feel higher resistance [1]. Utilizing this property, a spin valve was designed, which served as a basis for the first storage element in MRAM. It consisted of two ferromagnetic layers with a non-magnetic conductive layer in between. One of the ferromagnetic layers had an antiferromagnetic layer in its proximity, which made it fairly insensitive to the applied magnetic field. This ferromagnetic layer was therefore called “pinned” or “fixed” layer, while the other one was “free”, because its magnetisation could be changed. Therefore, a par­allel or antiparallel magnetisation of layers could be achieved [120]. By parallel magnetisation, electrons with particular spin orientation felt low resistance in both layers, whereas the other ones felt high resistance in both layers. By antiparallel magnetisation, electrons of each spin orientation felt high resistance in one of the layers. With the current of both groups of electrons being independent of each other, the equivalent resist­ance was higher by antiparallel magnetisation, as de­picted in Fig. 19. Hence, data could be stored by affect­ing the free layer magnetisation [1]. A big breakthrough was made in the late 1980s, when the spin valve based structures were discovered, whose resistance changed for up to 80% due to the ap­plied magnetic field. This was called giant magnetore­sistance (GMR) [1]. However, the practical GMR, which could be used in MRAM has remained too low to pro­duce a sufficient voltage difference between the high and low resistance states [120]. As an improvement, the magnetic tunnel junction (MTJ) structures, using tunnel magnetoresistance (TMR), were developed. TMR structures are similar to GMR, except they have a very thin insulator film between the ferromagnetic lay­ers instead of a non-magnetic layer. Therefore, the elec­trons can tunnel through the insulating film, where the probability of tunnelling is higher by parallel magneti­sation, resulting in lower resistance. The values of the resistance change based on TMR have already achieved 100-200% in MRAM devices, which produces a signifi­cant voltage difference between logic states. The basic principle of writing in MRAM is based on applying a magnetic field to appropriate cell, which switches the magnetisation in free layer. MRAM archi­tecture consists of word and bit lines, which are or­thogonal to each other (Fig. 20). The magnetic field is strong enough to alter the magnetisation in a data cell only when the current flows through both correspond­ing lines, which allows the addressing of each cell sepa­rately [1], [120]. However, at smaller cell dimensions, higher switching field and consequently higher current is necessary, which limits the scalability of field-assisted MRAM to about 90 nm. As a solution, spin transfer torque (STT) MRAM was introduced, where the switching of mag­netisation was induced by a current, flowing through the device (Fig. 21). If the magnetisation needs to be switched from antiparallel to parallel, the electrons are sent from a pinned layer to free layer. In the pinned lay­er, the electrons with a spin in the opposite direction to magnetisation get scattered and the others pass to the free layer. There, the spin angular momentum exerts a torque on the magnetisation, resulting in its switching to parallel direction. In order to achieve switching from parallel to antiparallel magnetisation, the current must flow in the opposite direction. In this case, the electrons flow from the free to pinned layer. The electrons with spin orientation antiparallel to magnetisation get scat­tered back to the free layer, where they cause a switch to antiparallel magnetisation. STT MRAM allows scaling to smaller dimensions than MRAM with magnetic field-based writing [120]. Figure 20: Schematic representation of conventional MRAM architecture, where magnetisation of free layer is set by applying sufficient magnetic field to the cell. To achieve that, current must flow through both corre­sponding word line and bit line. Reprinted from [120]. Licensed under CC BY-NC-ND 4.0 license. Figure 21: STT MRAM cell and its writing principle. Re­printed from [120]. Licensed under CC BY-NC-ND 4.0 license. One of the main advantages of MRAM in general is its non-volatility, which is achieved by retentivity of fer­romagnetic materials. Nevertheless, to achieve long lasting data retention, sufficient thermal stability of MTJ must be provided. By the in-plane MTJs, where the magnetisation of ferromagnetic layers is in the film plane (Fig. 22), this is hardly achievable for the cells with diameter less than 60 nm. Therefore, the MTJs with perpendicular magnetisation (pMTJ) are being increas­ingly researched [120]. Moreover, the critical switching current density, at which the magnetisation direction in free layer is rotated by the STT effect, can be con­siderably reduced, using pMTJ [122]. Thus, MRAMs with perpendicular magnetisation are considered to replace in-plane ones in the near future [120]. With all the mentioned attributes, STT MRAM is consid­ered as a perfect candidate for future memory applica­tions. However, the issue of a relatively high switching current and consequently high energy consumption will have to be solved in order to launch MRAM suc­cessfully into the computer memory market [123]. Figure 22: MTJ with in-plane and perpendicular mag­netisation, where k represents width-to-length ratio of MTJ. By in-plane magnetisation, MTJs must have ellipti­cal shape in order to prevent the formation of vortex magnetisation in the films, which is another downside of in-plane MTJs regarding scalability [120]. Reprinted with modification (cropping) from [124]. Licensed un­der CC BY 4.0 license. 5.6.4 Memristor When talking about the potential future data storage solutions, it is appropriate to mention memristor. This is an element, which was theoretically described in the 1970s by Leon Chua and in its essence represents a relation between the electric charge and magnetic flux. Chua came to a conclusion that memristor there­fore represents the fourth fundamental component of electrical circuits, alongside with the capacitor, resistor and inductor. The main property of memristor is that its resistance is being changed by the current, which flows through it. It is very important that this resistance retains its value after the current is shut down, which means that memristor can be used as a non-volatile memory device, whose high or low resistance repre­sents one bit of information [1]. Physical realisation of memristor had not taken place until 2008, when the company Hewlett Packard (HP) in­troduced an element with allegedly memristive prop­erties. It was made of a thin layer of titanium dioxide (TiO2), embedded between two platinum (Pt) elec­trodes. A part of TiO2 layer was oxygen deficient and therefore acted as an electrically conductive doped semiconductor due to the oxygen vacancies, which acted as dopants. The other part was not conductive. With external voltage applied, positively charged va­cancies moved in the direction of electric field. When the vacancies drifted towards the opposite Pt elec­trode, the conductive channels were created at some point, switching the device on. When they drifted away, the channels were dispersed and the electronic barrier was recovered, switching the device off [125], [1]. De­scribed memristive effects are highly dependent on the device’s dimensions. They are remarkably more sig­nificant at the nanometre scale, which explains the fact that memristor was not physically realised before the immense progress in the field of nanotechnology [1]. The discussions are common, whether the mentioned realisation actually is a memristor, as described by Leon Chua, or it just exhibits some similar characteristics. De­spite the fact that both the justification of memristor as the fourth fundamental electrical component and the actual realisation of theoretically proposed mem­ristive properties are on shaky grounds, the memristor certainly represents a big promise in data storage, logic circuits and neural networks [1]. Several different types of memristive devices have been proposed so far, for example redox-based, ferroelectric, multiferroic and spin-based memristors [126]. In 2017, Samardžic et al. presented a multiferroic multilayer memristor, composed of BaTiO3/NiFe2O4/BaTiO3 thin films, deposited on platinised silicon wafers by spin-coating. Bottom electrode was therefore platinum, whereas the upper one was golden. The investigated memristor proved to have typical current-voltage char­acteristics in the form of pinched hysteresis loop, which was symmetric and repeatable for the voltage ampli­tudes of ±10 V. Two conducting mechanisms were identified. Fowler-Nordheim tunnelling for the applied voltages above 5 V and thermionic emission for lower voltages and higher temperatures [126]. In 2019, Lu et al. demonstrated purely electronic memristors, fabri­cated from amorphous silicon, doped with oxygen or nitrogen and embedded between metal electrodes. Such memristive devices could be easily integrated into conventional silicon technology, which is one of their main advantages [127]. Memristors have also found their way to biological computing. In 2020, Fu et al. presented a diffusive memristor, made of protein nanowires of the bacterium Geobacter sulfurreducens, functioning at low, biological voltages (40-100 mV) [128]. Diffusive memristors spontaneously relax back to non-conductive state, after the bias voltage for switch­ing to conductive state is removed [129]. Hence, they enable emulations in short and long-term memory synapses, artificial neurons and neural networks [128], [129]. The artificial neuron, constructed with diffusive protein-nanowire memristors achieved similar tempo­ral integration as biological neurons [128]. Various ways of memristors’ utilisation have been intro­duced in the past few years. Memristor crossbar arrays with potential applications in non-volatile memory, logic circuits and neuromorphic computing systems have been proposed and realised [130]. Two nanometre feature size memristor crossbar arrays with a single-lay­er density comparable to information density achieved with state-of-the-art flash memory devices were re­alised in 2018. Such structures represent a promising solution for power efficient information storage and processing [131]. Multi-bit memristive devices, which possess more than two distinctive resistance states, have also been proposed. In 2015, a microscale TiO2 based memristor with silver and indium tin oxide elec­trodes was made and proved to have quantised con­ductance steps that were integer multiples of elemen­tary conductance [132]. Two years later, memory cells with up to 6.5 bits information storage and long-lasting data retention have been developed [133]. Memristors with large number of conducting states could be very useful in artificial neural networks. Several researches have been made in this field. Graphene based non-volatile memristive synapses were introduced recently, with more than 16 arbitrarily programmable conduct­ance states [134]. 5.7 Funding of nanotechnology Nanotechnology and nanoscience are becoming in­creasingly important driving forces for the modern world’s development. It is estimated that governments worldwide invested over $67 billion in nanotechnol­ogy research between years 2000 and 2015. They also represent a significant part of European Union’s (EU) research funding programmes. Under the Seventh Framework Programme (FP7), €2.56 billion was de­voted for the projects in the fields of nanotechnology and nanoscience between years 2007 and 2011, mostly coming through the “Nanosciences, Nanotechnolo­gies, Materials & new Production Technologies (NMP)” scheme [135]. Between 2014 and September of 2020, €56.4 billion was earmarked for the projects of Horizon 2020, EU research and innovation funding programme [136]. Under that programme, an estimated total budg­et of €1.77 billion was devoted only for the programme part “Nanotechnologies, Advanced Materials, Biotech­nology and Advanced Manufacturing and Processing” between years 2018 and 2020 [137]. There are also other initiatives in the field of nanotechnology, funded under the same programme. One of them is Graphene Flagship with planned budget of €1 billion, which was initiated in 2013 and is still in progress [138]. The same budget is predicted for the Quantum Technologies Flagship initiative, which started in 2018 and supports quantum technologies research in Europe [139]. The funding of these initiatives will be continued by the programme Horizon Europe, which will span from 2021 to 2027 and have a budget of around €100 billion [140]. It is therefore reasonable to expect that the research in the fields of nanoscience and nanotechnologies is go­ing to be increasingly funded by the EU in future. 5.8 A look to the future With such financial support, we can expect an im­mense progress in these fields in next years. New so­lutions will have to be found in order to continue the development of the electronics’ industry, according to the Moore’s law. CNTFETs certainly have a potential to succeed the silicon based technology. However, the complete transition to CNTFETs is not likely to happen in the near future, due to the many manufacturing dif­ficulties. We will more probably face gradual changes, in the form of incorporating CNTs as parts of the silicon based circuits, which could already happen in the pre­sent decade [114]. Nevertheless, the silicon transistors with nanosheets are yet to come into mass produc­tion in the next technology nodes, which implies that silicon will not be replaced very soon. In addition, it is more likely that it will be succeeded by more efficient, for example III-V semiconductors, before the CNTs play a significant role [27]. Most probably, the future elec­tronic circuits will firstly be designed using combina­tions of mentioned materials. Besides new materials and transistor types, different design and manufacturing principles could also con­tribute to the progress in the field of electronics. An in­teresting example is wafer-scale processing, where the whole silicon wafer is used for production of a single chip. This approach can be useful in designing high-performance computers, which execute computation­ally demanding tasks, like training deep artificial neu­ral networks. A very large number of processor cores and memory units can therefore be integrated on a single chip, which significantly increases communica­tion bandwidth and decreases processing times [141]. In 2019, a computer systems company Cerebras intro­duced a chip, measuring 46.255 mm2, with more than 1.2 trillion transistors and 400,000 cores, using TSMC’s 16 nm fabrication technology [142], [143]. In 2020, they announced a second generation of the chip, which comprised 850,000 artificial intelligence optimised cores and 2.6 trillion transistors, using TSMC’s 7 nm technology [144]. Another field, which will importantly benefit from the progress of the nanotechnology is medicine. Promis­ing methods are being developed for early diagnosing of different diseases, including certain types of can­cer and diabetes, by detecting biomarkers in human breath [135], [145]. Furthermore, graphene quantum dots have shown the potential to treat the Parkinson’s as well as Alzheimer’s disease, which could change the life of millions of people in the future [146], [147], [148]. Targeted drug delivery with the use of nanoparticles is also a promising field, which will provide less invasive treatment, especially for cancer patients [135]. One of the most perspective areas of nanotechnology in gen­eral, the self-assembly of structures, will also affect the field of medicine, in terms of self-repair mechanisms. Methods are being developed, where the nanostruc­tured scaffolds are used to direct the growth of cardiac, bone and skin tissues [135]. Self-assembly will certainly represent a future revolu­tion in many areas of technology. Assembling of mole­cules in particular structure without external interven­tion is an essential tool, which makes the bottom-up fabrication possible. It will enable the development of CNT based electronic devices and also be increas­ingly used in energy and environmental remediation applications. Low cost and highly efficient perovskite solar cells with self-assembled monolayers are already being developed, contributing to the progress of this perspective solar technology [149]. 6 Conclusions Considering all the above, it is clear that nanotechnol­ogy and nanoscience are going to affect our lives in the future. In this review paper, only positive effects of this field are presented. However, numerous questions are being set about the negative impacts of nanotechnol­ogy on health and also about its ethics. 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Licenced under CC BY-SA 3.0. Author: David Forbes; b) First MOSFET, fabricated in Bell Laboratories in 1959. Reprinted from [14]. Copyright 2021 Nokia; c) First integrated circuit, fabricated in Fairchild Semiconductor in 1959. Reprinted from [15]; d) uA741 operational amplifier, made by Fairchild Semiconductor in 1969. Reprinted with modification (cropping) from [16]. Licenced under CC BY-SA 4.0. Author: Jay Philippbar; e) Die image of Intel A80386DX-20 32-bit microprocessor, introduced in 1987. The integrated circuit consisted of 275000 transistors [17]. Reprinted from [18]. Licenced under CC BY-SA 3.0. J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 Figure 5: Number of transistors per integrated circuit between years 1971 and 2018. Reprinted with modification (cropping) from [29]. Licensed under CC-BY-SA 4.0 license. Author: Max Roser J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 Figure 8: a) Thomson’s atomic model, called also “The plum pudding model”. Reprinted from [40]. Licenced under CC BY-SA 4.0.; b) Rutherford’s atomic model. Reprinted from [41]. Licenced under CC BY-SA 3.0.; c) Bohr’s atomic model. Reprinted from [42]. Licenced under CC BY-SA 3.0.; d) Schrödinger’s atomic model, called also “The quantum mechani­cal model” or “Wave model”. Reprinted from [43]. Licenced under Pixabay License. J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 Figure 11: Diagram of density of states for different forms of semiconductors. Discrete energy states can be observed in case of quantum dots. Reprinted from [62]. Licensed under CC BY-NC-SA 3.0 license. J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 Figure 12: Writing principle of dip-pen nanolithogra­phy. From [69]. Reprinted with permission from AAAS. J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 Figure 13: Structure of a perovskite-silicon tandem solar cell. Reprinted from [99]. Licensed under CC BY-NC 3.0 li­cense. J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 Figure 14: CNT gas sensor. Reprinted with modifica­tion (cropping) from [103]. Licensed under CC BY 3.0 license. J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 Figure 16: Working principle of NRAM. Data is stored by connecting or disconnecting CNTs between the electrodes. Reprinted with modification (cropping) from [116]. Copyright 2020 Nantero.com. J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 Figure 19: Resistive model of spin valve. Reprinted from [121]. Licensed under CC BY-SA 3.0 license. J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 J. Štremfelj et al.; Informacije Midem, Vol. 51, No. 1(2021), 25 – 48 Copyright © 2021 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 1(2021), 49 – 61 https://doi.org/10.33180/InfMIDEM2021.103 Multi-Port Memory Design in Quantum Cellular Automata Using Logical Crossing Kamaraj Arunachalam1, Marichamy Perumalsamy2, Abirami Ramasamy1 1Mepco Schlenk Engineering College, Department of ECE, Sivakasi 2P.S.R Engineering College, Department of ECE, Sivakasi. Abstract: Memory and its data communication play a vital role in deciding the performance of a Processor. In order to obtain a high performance computing machine, memory access has to be equally faster. In this paper, Dual port memory with Set/Reset is designed using Majority Voter in Quantum-dot Cellular Automata (QCA). Dual port memory consists of basic functional blocks such as 2 to 4 decoder, Control Logic Block (CLB), Address Checker Block (ACB), Memory Cell (MC), Data Router block and Input/Output block. These functional units are constructed using the 3-input majority voters. QCA is one of the recent technologies for the design of nanometer level digital components. The functionality of Dual Port Memory has been simulated and verified in QCADesigner 2.0.3. A novel crossover method called Logical Crossing is utilized to improve the area of the proposed design. The logical crossing does the data transmission with the support of proper Clock zone assignment. The logical crossing based QCA layouts are optimized in terms of area and number of cell counts. It is observed that 29.81%, 18.27%, 8.32%, 11.57% and 3.69% are the percentage of improvement in the number of cells in Decoder, ACB, CLB, Data Router and Memory Cell respectively. Also, 25.71%, 16.83%, 8.62%, 4.74% and 3.73% of improvement is achieved in the area for Decoder, ACB, CLB, Data Router and Memory Cell respectively. In addition to that the proposed Dual port memory using logical crossing attains improvement in the area by 8.26%; that is made possible due to the 8.65% reduction in the number of cells required for its construction. Moreover, the quantum circuits of the RAM are obtained using the RCViewer+ tool. The quantum cost, constant inputs, the number of gates, garbage output and total cost are estimated as 285, 67, 57, 50 and 516 respectively. Keywords: Dual Port memory; Logical Crossing; Number of Cells; Total Cost Vecvhodni spominski dizajn kvantnih celicnih avtomatov z uporabo logicnega križanja Izvlecek: Ucinkovitost procesorja je odvisna od spomina in podatkovne komunikacije. Clanek opisuje dvovhodni spomin s set/reset z uporabo vecinskega volivca v kvantnem celicnem avtomatu (QCA). Dvovhodni spomin je sestavljen iz osnovnih funkcijskih blokov, kot so: 2-4 dekoder, controlni logicni blok (CLB),blok preverjanja naslovov (ACB), spomiska celica (MC), podatkovni usmerjevalni blok in vhodno izhodni blok. Te funkcionalne enote s zgrajene z uporabo trovhodnih vecinskih volilcev. Funkcionalnost je bila simulirana in preverjena v QCADesigner 2.0.3. Uporabljena je nova metoda logicnega križanja, ki opravlja prenos podatkov s podporo pravilne ure. Izboljšave v številu celic v dekoderju, ACB, CLB, usmerjevalniku in spomiski celici zanšajo 29.81%, 18.27%, 8.32%, 11.57% in 3.69% in izboljšavi v površini dekoderja, ACB, CLB, usmerjevalnika in spomiske celice v višini 25.71%, 16.83%, 8.62%, 4.74% in 3.73%. Skupna površina je manjša za 8.26%. Kvantna vezja RAM so narejena v RCViever+ orodju. Kljucne besede: dvovhodni spomin; logicno križanje; število celic; strošek * Corresponding Author’s e-mail: kamarajvlsi@gmail.com 1 Introduction In a processor, the memory plays a critical role in de­ciding the performance of computation. The main characteristics of RAM are Reliability, Availability and Maintainability. The computation speed depends upon the design of memory architecture and the speed of communication. The communication speed indirectly depends on the architectural design of memory. The improvement in architectural design increases the per­formance of the system. In CMOS (Complementary Metal Oxide Semiconduc­tor), the memory architecture has nearly reached its saturation point. There comes a need for technological improvement at this moment, which can be achieved through the realization of digital structures in nanom­eter quantum cellular automata (QCA) [1]. QCA is a fast, ultra-low power and provides high packing density compared to other emerging nanotechnologies [1]. Further, the performance of the QCA can be enhanced by incorporating novel architectures. Generally, copla­nar (single layer) and multilayer crossing is adopted in QCA wiring. However, usage of Multilayer architecture consumes less area and exhibits higher performance compared to coplanar wiring [2]. Logical Crossing is a new kind of wire crossing that exhibits a better perfor­mance than its predecessors. [3]. Two kinds of memory architectures can be realized in QCA. They are (1) line based and (2) loop based memo­ry. In line-based memory, the four QCA clocking signals are used for storing the values in the cell; whereas the loop-based structure maintains the data using feed­back in the circuit [1, 4]. The line-based method is very simple, but the reliability is questionable. While the loop-based method has better reliability and it is real­ized using multiplexer logic and latches [5]. The remaining parts of the paper are organized as fol­lows; Section 2 explains the definitions of performance measures. Section 3 discusses the outcomes of the RAM related literature reviews. Section 4 deals with the novel logical crossing for interconnections in QCA. Section 5 elaborates on the proposed RAM design and its QCA realization. The simulation results obtained are discussed in Section 6. Finally, the paper is concluded with suggestions for future research. 2 Preliminaries performance metrics 2.1 Quantum Cost The Quantum Cost of a circuit is defined as the total number of elementary quantum gates (primitive gates) that are needed to realize a given function [6]. The quantum cost of reversible preliminary gates such as Feynman, Toffoli and Fredkin gates are 1, 5 and 5 re­spectively [6]. 2.2 Garbage Output Garbage Output is defined as the number of unused outputs of the reversible circuit. Based on the require­ment, these outputs are introduced to maintain the property of reversibility in the circuit [7]. 2.3 Constant Input Constant Input is a predefined input (Logic ‘0’ or ‘1’) in order to obtain the desired output function from the reversible gate. The input is kept constant at either ‘0’ or ‘1’ during the entire computation. 2.4 Logical Calculations It is defined as the number of NOT (.), AND (ß) and XOR (a) operations that are required to obtain a desirable output function in reversible logic [8]. It indicates the hardware complexity of the circuit. 2.5 Number of Gates It is the total number of gates required to realize the desired function. It is measured from the circuit’s input to its output. 2.6 Total Cost It is a sum of the Quantum Cost, Constant Input, Gar­bage output and Number of Gates. 2.7 QCA Due to the increasing growth of electronic tools, pa­rameters such as speed, area, processing power, energy consumption and density in the design of these tools are highly important [9]. In this regard, new technolo­gies and designs are always being presented to resolve the disadvantages and make necessary improvements. One of the proposed technologies that try to advance in the digital electronics industry is quantum cellular automata (QCA) nanotechnology. This technology, which progresses constantly, has higher speed, densi­ty; also consumes far lower area and energy compared to the existing technologies [10]. In QCA technology, there can be two types of cells, which are 45°and 90°cells. A QCA cell contains four quantum dots that are located in the square corners. The electrons occupy the two corners of the QCA cell diagonally. A QCA wire can be designed simply by plac­ing QCA cells next to each other. The length of the QCA wires should not be high since it leads to signal drop and can cause trouble in the circuit operation. Once the polarization of a QCA cell is fixed, the encoded binary information is transferred to the adjacent cells [11]. The three input majority gate and inverters are the basic structures of QCA circuits. Designing this gate is difficult in other technologies, but in this technology, the five QCA cells are arranged in a way to generate the majority gate. According to the structure and equation of three input majority gate, it is observed that the AND and OR gates can be constructed based on two inputs by inserting a fixed value into one of the three input cells (logical one for OR and logical zero for AND) [12]. 2.8 QCA Clocking Every QCA based circuit requires a clocking mecha­nism for synchronization, flow control management, and provision of power to stimulate a circuit. This syn­chronization process is performed through QCA Clock­ing [13] as shown in Fig.1. The clocking of QCA can be accomplished by controlling the potential barriers be­tween adjacent quantum dots. Figure 1: QCA Clocking (4 Clock Zones) In QCA, the data flow path is based on the path along which the clocking phase increases [14]. It must be noticed that clocking phases should increase in turn unless the circuit does not function as expected. The control of data flow is one of the specific characteristics of QCA. This inherent characteristic helps designers in developing more optimized novel structures for digital circuits [15]. 3 Related works in RAM Timing of the clocking zones requires two additional clocks to implement a four step process for read­ing/writing data to the memory in line based parallel memory [16]. The parallel hybrid memory architecture reduces the area and latency. The area, number of in­terconnection and latency can be improved by proper QCA layout [17]. Various kinds of RAM architectures are presented and their performances are analyzed in terms of number of cells, area, number of clocks and cell delay as shown in Table 1. Then the best and worst-case performanc­es are identified based on the latency and area of the presented layout design [5]. Set/Reset signals are intro­duced in the recent RAM cell designs. The inclusion of Set/Reset does not increase the number of gates [18], but the number of gates is reduced in [19] through op­timum realization. The number of QCA cells increases when the RAM layout is realized using regular clock zones with Latches (D or SR), but it reduces the clock latency [20]. The number of QCA cells, area, the number of gates and latency of RAM are reduced with the usage of 3-input and 5-input majority gate [19] in the archi­tecture. Also, the removal of coplanar wires (crossover) [20, 21] and the effective layout arrangement of QCA cells make it a robust and noise free design [18, 19]. Initially, single port RAM is designed using SR/D Latch with Loop-based concept in QCA. The performance is improved by incorporating the 5-input majority gate and efficient layout design. But, the present-day pro­cessors are expecting RAM with multiple ports and high capacity. So recently, a 4×4 RAM is designed with two ports using majority voters in QCA [22, 23]. The major objective of this RAM design is to avoid cross­ings in the entire layout [22]. But, multilayer crossing is adopted in [23] to reduce the number of cells and area. 3.1 Limitations of the existing design From the above analysis of the existing RAM designs, the following observations are made, - Single port memory is designed with or without crossover in [19-21]. - No array type architecture is presented so far ex­cept in [22, 23]. - Coplanar and multilayer crossings are used in [20, 21 and 23]. - In order to overcome the limitations of the exist­ing designs, a Multiport 4×4 RAM is proposed in this paper, which is being realized in the QCA lay­out using Logical Crossing. 4 Logical crossing Two major wire crossing techniques are popularly used in QCA data transmission: coplanar and multilayer. Each of them has its own advantages and disadvantages as shown in Table 2 [3, 24]. In order to combine the advantages of both methods, a new wire crossing technique is introduced in [3] named Logical Crossing. In logical crossing, the data are trans­mitted to adjacent cells by operating them with clock signals shifted in phase by 180º clock phase. When two cells are in locked and locking stages, the Coulomb re­pulsion between them makes the data transmission possible. In other clock zones, the data transmission does not occur. The detailed clock zone information for data transfer in QCA is shown in Table 3. Hence the cells in the hold and relax phase can cross each other without polarization effect. The diagram­matical view of data transmission in coplanar, multi­layer and logical crossing are shown in Fig.2 and their corresponding QCA simulation waveforms are shown in Fig. 3. It is observed that the Logical Crossing uses Clock Zone 0 & 2 to pass Input A & B and Clock Zone 1 & 3 to transfer Input A & C to output. The logical crossing method is used to construct XOR function [3], 2×1 multiplexer [25], Full Adder [26] and complex logical functions [24]. The incorporation of logical crossing in all these references reduces the number of cells and area in the QCA layout. 5 Proposed dual port RAM design In dual port memory, a user can access two memory locations at a time. A data conflict may occur when two users access (among them at least one is write opera­tion) the same location at same time. The data conflicts can be avoided if one of the ports signal is stalled by delaying it. But this demands for additional buffers in QCA to introduce delay. So, to overcome this problem a priority-based dual port memory architecture is pro­posed. Fig.4. shows the proposed architecture.. Dual port memory architecture consists of decoder block, Address Checker Block (ACB), Control Logic Block (CLB), Data Router Block (DRB), Macro Memory Cell (MC) as shown in Fig. 5 (a to e). The decoder pro­vides the address to the two ports (Port A and Port B). ACB checks the address of the two ports (i.e. to check whether the address of the two ports is the same). CLB generates the priority for the two ports, if Port A has higher priority, it accesses that memory cell first; fol­lowed by Port B. DRB provides the write/read operation (Data Route) to the two ports. Memory cell stores the single bit and it performs write/read operations. 5.1 Decoder In dual port memory, two memory cells are selected at the same time for write/read operation. So, two de­coders are used to generate the addresses for both the ports as shown in Fig.5a. The decoders are used to gen­erate a ‘row select’ signal for addressing an appropriate memory array which is shown in Table 4. Table 4: Truth Table of Decoder A B A’B’ A’B AB’ AB 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 5.2 Address Checker Block (ACB) The addresses of the two decoders are compared to check whether they are similar or not. If the output of Address Checker Block (ACB) as shown in Fig.5b, X is ‘1’ then addresses of the ports are same. Table 5 shows the operational output of ACB, where DiR and DiL represent the right and left decoder outputs respectively. If D0R and D0L have logic ‘1’ the output is logic ‘1’. Similarly, all inputs logic is performed. The ACB works on a priority basis. Table 5: Truth Table of ACB D0R D1R D2R D3R D0L D1L D2L D3L X 1 X X X 1 X X X 1 X 1 X X X 1 X X 1 X X 1 X X X 1 X 1 X X X 1 X X X 1 1 0 0 0 0 0 0 0 0 0 5.3 Control Logic Block (CLB) The control logic block (CLB) has inputs of Data Router signals of two ports and a control input. CLB produces the priorities as well as the Data Router for both ports. If the addresses are different, no conflict occurs at all. So, after the ACB block, if the addresses are unmatched, the control logic block simply passes the same Data Router data for both ports as supplied to the input lines of this block. For the same addresses, outputs will be chosen based on the control input (S0) as per Table 6. Table 6: Truth table for CLB priority calculation Inputs Outputs S0 Address Port A Address Port B WRA WRB X P1 P2 0 01 01 0 0 1 0 0 0 01 01 0 1 1 0 1 0 01 01 1 0 1 1 0 0 01 01 1 1 1 1 1 1 10 10 0 0 1 0 0 1 10 10 0 1 1 0 1 1 10 10 1 0 1 1 0 1 10 10 1 1 1 1 1 0 10 11 0 0 0 0 0 0 10 11 0 1 0 0 1 0 10 11 1 0 0 1 0 0 10 11 1 1 0 1 1 1 10 11 0 0 0 0 0 1 10 11 0 1 0 0 1 1 10 11 1 0 0 1 0 1 10 11 1 1 0 1 1 If the addresses are same and X is logic ‘1’, S0 is the con­flict resolver, WRA and WRB have logic ‘0’ then the prior­ity outputs P1 and P2 are logic ‘0’. The priority and the port for write/read A/B is selected based on the address port and WR signal. In order to remove the conflicts, the conflict resolve factor (0 or 1) is used. When the same memory location is selected for both ports with at least one operation is write operation, then the priority of the two ports must be different. These priorities also work as the final write/read signals as shown in the fol­lowing equations 1 to 4. B1 and B2 can be defined by the following functions. (1) (2) Therefore, conflict resolver functions as the write/read signals which satisfies all the following conditions (ac­cess of the same or different memory location), (3) (4) Where, P1, P2 are the priority of port A and port B re­spectively. 5.4 Data Router Priority generated in the CLB is used as the Data Router for ports A & B. At any point of time, one row is selected for port A/port B, for the intended operation. Hence, the Data Rout­er and the address lines have to be combined as shown in Fig.5d. In Table 7, di is the left address decoder while Di is the right address decoder, Pi is Port A/B and RSi is memory ar­ray i for write/read operation. If the same memory location is selected for both the ports, then the write/read signal of the prior port is selected. Output signals RS1, RS2, RS3, and RS4 are the Data Router signals for four rows. 5.5 Memory Cell The memory architecture used in [27, 28] is modified according to dual port mode as shown in Fig. 5e. The stored data are constantly updated inside the memory loop until both the write/read and row select wires of the same port are enabled. If the row select is enabled and the write/read is logic ‘0’, then the current memory value inside the loop is forwarded to the output. The data input of the prior port is considered as the input line of the memory cell. In Table 8, WRi and RSi are the write and the read operation of Port A and B, respec­tively. 5.6 I/O Operation There are individual data inputs for each port. The se­lected input port data are forwarded to the Memory cell or data are transferred to the output port based on the CLB control signals. The operation is performed us­ing AND-OR combinational logic. 6 Results and discussions The above discussed dual port memory components are realized in quantum cellular automata (QCA) us­ing logical crossing as shown in Fig.6 (a to e). It shows the QCA realization of Decoder, ACB, CLB, Data Router and Memory cell using Logical crossing based crosso­ver. QCADesigner 2.0.3 [29] is used for this QCA layout design. The simulation waveforms of the individual modules of the RAM are shown in Fig.7. The simulation waveforms confirm the functional verification of the proposed RAM design. In Fig.7, the sample input and output simulation waveforms are shown, in which, for each module, one of the possible inputs and outputs is highlighted on the waveform and its logical value is represented on the right side. Table 9: Comparison of Memory Cell implementation in QCA S. No. Memory Cell References Number of Cells 1. [21] 158 2. [20] with D Latch 132 3. [18] 109 4. [20] with SR Latch 100 5. [19] 88 6. Proposed 77 The QCA layout of individual modules of dual port RAM is realized using the logical crossing. The AND, OR and NOT are the basic logic units of the functional blocks of RAM. These logic units are constructed using 3-in­put majority voter and they are incorporated to build the decoder, ACB, CLB, Data Router and Memory cell. The interconnections between them are introduced by logical crossing, which has a positive impact on the performance measures. In [18-20], memory cell structure alone is implemented in QCA using multilayer/coplanar architecture. In [20], the inherent QCA capability is used to derive the Latch function. From Table 9, it is observed that the logical crossing in memory cell design reduces the required number of cells. When observing the logical crossing realization in Table 10, the inverter realization has 20% area reduction. In the decoder, the number of cells needed for providing interconnections is reduced by 39%. The decoder area is reduced by 29.81% compared to existing designs. The area reduction in the decoder is mostly due to the results of the area reduction of the ACB (up to 18.27%). Similarly, the control logic block has an 8.32% smaller area due to logical crossing. The AND and OR gates are the only logical elements in CLB, where the area is not reduced with logical crossing. Hence, the area reduction was possible only in the in­terconnections for CLB. Data router is a combination of CLB and ACB (for which the area is already reduced). This has a positive effect on the construction of data router resulting in area reduction up to 11.27%. The number of cells required for wire connections in the proposed methodology has been reduced significantly. The realization of memory cell leads to a small area re­duction of 3.42%. The area occupied by the 4×4 memo­ry array is reduced by 3.69%. The complete architecture of the RAM is obtained by combining all the individual modules, which results in a 12.35% area reduction com­pared to the existing designs due to the use of the logi­cal crossing. Hence, the overall area reduction of 8.65% is achieved for RAM. Upon summarizing the obtained results, the functional units are integrated together to construct the 4×4 Dual Port RAM. In addition to that, it is observed from Table 11 that the reduction of number of cells in the RAM layout has been up to 8.26%. The quantum circuit of the functional modules of RAM is obtained from Toffoli-Fredkin Code (.tfc) using RCViewer+ software [30]. In Fig.8, logic ‘1’ and ‘0’ denote the constant inputs and ‘G’ refers to garbage output. Here, Toffoli and Fredkin primitive gates are used to construct the RAM and their quantum cost is 5 [6]. The quantum cost of RAM is the sum of the quantum cost of the primitive gates used in the circuit. The quantum cost, constant input, number of gates and garbage out­put are listed in Table 12. From Table 12, the total cost of RAM is 516, which is the sum of quantum cost (285), number of constant inputs (67), number of gates (57) and number of garbage out­puts (50). The number of logical calculations show the hardware complexity of the circuits. 7 Conclusion and future work Quantum Cellular Automata is a low-power technology compared to present-day CMOS technology. In this pa­per, various functional blocks of Dual port memory such as 2 to 4 decoder, Control Logic Block (CLB), Address checker block (ACB), Data Router block and 4×4 mem­ory cell block are designed using majority voters. The design unit consists of basic logic gates such as AND, OR, Inverter and connecting wires. All the functional mod­ules are realized in the QCA layout with Logical Crossing. In Logical crossing method, the alternate clock signals are used to control the flow of data transmission rather than orientation and multiple layers for crossover. It has a positive impact on the cell count and reduces the area. In comparison to the best published results from re­cent literature, it is worth mentioning that the num­ber of cells is reduced by 29.81% (Decoder), 18.27% (ACB), 8.32% (CLB), 11.57% (Data Router) and 3.69% (Memory Cell) in the proposed work. Also, the area of the aforementioned blocks is reduced by 25.71%, 16.83%, 8.62%, 4.74% and 3.73%, respectively. In addi­tion to that, the proposed logical crossing based com­plete Dual port memory achieves an improvement of 8.26% in area and 8.65% in number of cells. Moreover, the quantum cost, the number of constant inputs, the number of gates, the number of garbage output and the total cost are 285, 67, 57, 50 and 516 respectively. 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A.Kamaraj and P.Marichamy, “Area Optimized Nano-Metric Level Dual Port Memory Design In QCA”, Journal of Adv Research in Dynamical & Con­trol Systems, Vol. 11, No.07, 2019, https://www.jardcs.org/abstract.php?id=2997. https://waluslab.ece.ubc.ca/qcadesigner/ http://webhome.cs.uvic.ca/~dmaslov/. Arrived: 06. 04. 2020 Accepted: 29. 01. 2021 K. Arunachalam et al.; Informacije Midem, Vol. 51, No. 1(2021), 49 – 61 K. Arunachalam et al.; Informacije Midem, Vol. 51, No. 1(2021), 49 – 61 Table 1: Comparison of RAM Designs present in the Literatures RAM Design Crossover No. of Ports Latch Basic Building Blocks Set / Reset Number of Gates Number of Clock Cells Area (µm2) Latency 1×4 [21] Coplanar (Loop Based) Single Port Memory Cell D 3-input Majority Voter & not Gate No 8 (6+2) 158 0.16 2 1×1 [20] SR No 8 (6+2) 144 0.18 1 D 6 (5+1) 132 0.21 1 1×1 [18] No Crossover D FF Yes 8 (6+2) 109 0.13 1.75 1×1 [19] D 5-input Majority Voter Yes 4 88 0.08 1.5 4×4 [22] Dual Port Memory Cell - 3-input Majority Voter Yes 6 40 0.048 0.75 4×4 [23] Multilayer - Yes - - - - K. Arunachalam et al.; Informacije Midem, Vol. 51, No. 1(2021), 49 – 61 Table 2: Comparison of Wire Crossing Methods Wire crossing technique Advantages Disadvantages Coplanar 1. Single Layer. 2. Lower number of cells. 3. No additional layers and cells. 4. No noise interference. 1. Need additional space between (45º deg.) cells. 2. Decreased energy separation between the ground state and the first excited state. 3. Performance decreases (high operating temperature, resistance to entropy and switching time). Multilayer 1. No need to rotate the cells. 2. Good energy transformation. 3. Good performance (fast switching and high entropy). 1. Noise problem between intersection cells in the crossover area. 2. Number of layers, crossover and vertical cells are increased. Table 3: Data Transfer in QCA Clock Zones State of Cells Action & Data Transmission Two adjacent clock cells (Clock Zone 1 & 3, Clock 2 & 4) Locked and Locking stages pair. Coulomb repulsion. Data transmission is per­formed within two cells. Other Clock Zones Pairs Locked and Relaxing stages. Data transmission does not operate between two cells. Locking and Relaxed stages. Locking and Relaxing Stages. Locked and Relaxed stages pair. Coulomb repulsion. Data transmission is not per­formed without any interference. K. Arunachalam et al.; Informacije Midem, Vol. 51, No. 1(2021), 49 – 61 a) a. Coplanar Crossing b) Figure 3: Simulation of Wire Crossing Methods in QCA, a) Multilayer Crossing and b) Logical Crossing. b. Multilayer Crossing c. Logical Crossing Figure 2: Wire Crossing Methods in QCA K. Arunachalam et al.; Informacije Midem, Vol. 51, No. 1(2021), 49 – 61 a. Decoder b. Address checker block Figure 4: Block diagram of priority based Dual Port Memory. c. Control logic block d. Data router e. Memory cell Figure 5: Block diagram of individual modules of Dual Port Memory a) Decoder b) Address Checker Block c) Control Logic Block d) Data Router and e) Memory cell. K. Arunachalam et al.; Informacije Midem, Vol. 51, No. 1(2021), 49 – 61 Table 7: Truth table for Data Router a b d3 d2 d1 d0 A B D3 D2 D1 D0 P1 P2 RS0 RS1 RS2 RS3 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 K. Arunachalam et al.; Informacije Midem, Vol. 51, No. 1(2021), 49 – 61 Table 8: Truth table of memory cell for Dual port memory P1 P2 Data input WRA RSA WRB RSB Output A Output B Port A Port B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 0 1 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 K. Arunachalam et al.; Informacije Midem, Vol. 51, No. 1(2021), 49 – 61 a) a. 2 to 4 Decoder b) c) b. Address checker block d) c. Control logic block e) d. Data router Figure 7: QCA Simulation of Dual Port RAM a) Decoder b) Address Checker Block and c) Control Logic Block d) Data Router and e) Memory cell. e. Memory Cell Figure 6: QCA Realization of Dual port memory blocks K. Arunachalam et al.; Informacije Midem, Vol. 51, No. 1(2021), 49 – 61 Table 10: Comparison of Dual Port Memory Compo­nents of RAM Type and Num­ber of functional units Existing [22] Proposed (Logical Cross­ing) % of Improvement w.r.t. [22] Number of Cells Wires Total Number of Cells Wires Total Number of Cells Wires Total AND - 5 0 5 5 0 5 0 0 0 OR - 5 0 5 5 0 5 0 0 0 NOT   5 0 5 4 0 4 20 0 20 Decoder 4 AND, 2 NOT 30 74 104 28 45 73 6.67 39.19 29.81 ACB 2 Decoders, 4 AND, 1 OR 233 194 427 171 178 349 26.61 8.25 18.27 CLB 8 AND, 2 OR 477 328 805 421 317 738 11.74 3.35 8.32 Data Router Signal 2 Decoders, 1 CLB, 2 ACB, 8 AND, 2 OR 1917 530 2447 1676 488 2164 12.57 7.92 11.57 Memory Cell (MC) 3 NOT, 10 AND, 3 OR 80 300 380 77 290 367 3.75 3.33 3.42 4×4 MC 16  MC 1520 650 2170 1468 622 2090 3.42 4.31 3.69 Complete architecture 2 Decoders, Data Router, 4×4 MC, CLB, ACB 13620 11892 25512 12882 10423 23305 5.42 12.35 8.65 Table 11: Area comparison of Dual Port Memory Modules of Dual Port Memory Area occupied by %of improvement w.r.t. [22] Existing layout [22] Proposed (Logical crossing) 2:4 Decoder 0.14 0.104 25.71% Address checker block 1.01 0.84 16.83% Control logic block 2.32 2.12 8.62% Data Router 2.74 2.61 4.74% Memory cell 0.51 0.491 3.73% Total 6.72 6.165 8.26% Table 12: Performance of Dual Port RAM Modules of Dual Port Memory Number of Primitive Gates Quantum Cost Constant Input Number of Gates Garbage Output Logical Calculations Total Cost Toffoli Fredkin 2:4 Decoder 4 2 30 8 6 4 54 ACB 4 3 35 7 7 12 68 CLB 10 4 70 18 14 12 128 Data Router 12 - 60 12 12 10 106 Memory cell 15 3 90 22 18 12 160 Total 45 12 285 67 57 50 516 Where a is XOR, ß is AND, . is NOT gate functions K. Arunachalam et al.; Informacije Midem, Vol. 51, No. 1(2021), 49 – 61 c. Control Logic Block b. Address Checker Block a. Decoder e. Memory Cell d. Data Router Figure 8: Quantum Equivalent Circuit of Dual Port RAM K. Arunachalam et al.; Informacije Midem, Vol. 51, No. 1(2021), 49 – 61 K. Arunachalam et al.; Informacije Midem, Vol. 51, No. 1(2021), 49 – 61 Copyright © 2021 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 1(2021), 63 – 71 https://doi.org/10.33180/InfMIDEM2021.104 A Low-Voltage Current Mirror for Transconductance Amplifiers Hamdi Ercan1, Sezai Alper Tekin2 1Erciyes University, Department of Avionics, Kayseri, Turkey 2Erciyes University, Department of Industrial Design Engineering, Kayseri, Turkey Abstract: In this study, a low-voltage current mirror to use in differential pairs as an active load is introduced. The proposed current mirror which can operate at ±0.5 V has high output impedance and low input impedance. The proposed structure employs the principle of voltage level-shifting for PMOS transistors. The voltage level-shifting operation has been achieved by using the bulk voltage at this structure. Spice simulations also justify this current mirror’s outstanding performance with a bandwidth of 11 GHz using an external capacitor at an input current of 200 µA. Keywords: PMOS level shifter; low-voltage; current mirror; current-mode; differential pair; bulk voltage Nizkonapetostno tokovno zrcalo za transkonduktancne ojacevalnike Izvlecek: Clanek predstavlja nizkonapetostno zrcalo za uporabo kot aktivno breme v diferencialnih parih. Predlagano zrcalo obratuje pri napetosti ±0.5 V in ima visoko vhodno nizko izhodno impedanco. Struktura uporablja princip premikanja napetostnega nivoja pri PMOS tranzistorjih. Odlicna ucinkovitost je bila pokazana tudi s SPICE simulacijami pri pasovni širini 11 GHz, z uporabo zunanjega kondenzatorja pri vhodnem toku 200 µA. Kljucne besede: PMOS premikanja nivoja; nizka napetost; tokovno zrcalo; tokovni nacin; diferencialen par * Corresponding Author’s e-mail: hamdiercan@erciyes.edu.tr; 1 Introduction Nowadays, integrated circuit design has concentrated on a circuit with low-voltage operation, low-power dis­sipation, wide bandwidth and minimum area require­ments. A growing need has emerged associated with low-voltage analog circuit design. The demand for cir­cuits operating at low voltage has increased due to the need for low power dissipation. The low-voltage and low-power designs have increased operation time be­tween the battery recharging cycle and have utilized a smaller or lighter-weight battery. Numerous low volt­age applications have been proposed earlier [1,2]. Con­sidering several technologies such as bipolar junction transistor (BJT), metal-oxide-semiconductor (MOS) and bipolar complementary MOS (BiCMOS), the CMOS technology has played a crucial role in the develop­ment of low power circuit for diverse applications. The current mirror has been known as a circuit having two terminals whose output current is independent of the output voltage and depends only on the input cur­rent. These circuits copying the current carry out a sig­nificant function for active elements such as Op-Amp, OTA, current conveyor etc. The low-voltage current mir­ror has been used in a lot of active elements designed with low-power. The performance parameters of cur­rent mirrors like active elements parameters contain linearity, power dissipation, minimum supply voltage requirement, input and output resistance in these ap­plications. At the same time, many active elements in­clude differential pairs designed using PMOS current mirror as an active load [3-6]. The low-voltage opera­tion of the active elements has been restricted because these current mirrors have high input voltage. A low voltage level shifter-based current mirror has been presented in Ref. [7] for current sensor application. Ac­cording to this study, the bandwidth of the circuit was a few tens of MHz. Though this current mirror can be used in low voltage design, the level shifter approach has been designed using only the NMOS current mir­ror. The threshold voltage of the PMOS transistor is always higher than that of the NMOS. Thus, the circuit presented in Ref. [7] cannot be obtained using a PMOS transistor. However, this case has been resolved by us­ing the proposed circuit. In the present study, a low-voltage PMOS current mir­ror employing voltage level-shifting principle has been introduced. The voltage level-shifting operation has been achieved by using bulk voltage in this structure. The circuit utilizes a voltage level shifter at the input port to achieve the high input voltage swing capability. Thus, it can operate with low power supply voltage and low input /low output voltage requirements. Addition­ally, the proposed structure as an active load has been used in the transconductance amplifier. 2 Conventional PMOS current mirror A conventional PMOS current mirror (CM) circuit is shown in Figure 1. Transistor M1 has been used as a di­ode and the input current copied to output has been compelled to pump by the input voltage. Figure 1: A conventional PMOS current mirror. Transistor M1 shown in Figure 1, operates in satura­tion mode. Besides, the input impedance of the CM depends on the transconductance (gm) of the M1. The input voltage of the circuit can be written as below: (1) where kp =µpCox is the conduction factor, VTHP is the threshold voltage for PMOS transistor, VDD represents the supply voltage. Also, W and L are the effective tran­sistor width and length. The output voltage require­ment of the CM can be given as (2) where VDS,sat is drain-to-source voltage for relevant tran­sistors in the saturation region. One of the drawbacks of the conventional PMOS CM is that input voltage is always greater than the threshold voltage, being a cru­cial parameter for low-voltage application. The other disadvantage is the low output impedance. Therefore, using this structure is inconvenient in the low voltage. By using the proposed approach, these challenges have been met. 3 PMOS level-shifter current mirror Figure 2 indicates the PMOS level-shifted current mir­ror (PMOS LSCM) circuit for low-voltage applications [8]. Transistors M1 and M2 are operated in the saturated region (VSD > VSG - VTHP) in this circuit. Where VSD and VSG are the source-drain voltage and the source-gate voltage for M1 and M2, respectively. Additionally, VTHP is the threshold voltage for M1 and M2. Nevertheless, the most convenient mode is the operation of M3 in sub-threshold region (VGS3 < VTHN). Where VGS3 is the gate-source voltage for M3 and VTHN is the threshold voltage for M3. Also, M1 operates in sub-threshold region for low input currents and saturation region for high input currents [9,10]. Figure 2: PMOS level-shifter current mirror. Threshold voltage can be defined by [11] (3) where VTHN is the threshold voltage for M3, VTHO is the zero-VBS value of the threshold voltage, .F is the surface inversion potential of silicon, . is the body effect pa­rameter and VBS (Vbulk-VS) is the bulk-source voltage. VBS represents the bulk-source voltage for M3. As shown in Figure 2, transistor M3 has been used for shifting the voltage level at the drain terminal of M1. The high value of the biasing current forces M3 to operate in the satu­ration region. According to these results, the relation between the voltages can be written as below (4) where VSG1 and VGS3 are the gate-to-source voltage of the relevant transistors. The equations describing the operation in saturation and sub-threshold regions, re­spectively are (5.a) (5.b) where ID1 and ID3 are the drain currents of transistors M1 and M3, respectively. Besides, kp =µnCox is the transcon­ductance parameter of the PMOS transistor, UT is the thermal voltage and ID03 is the saturation current. Also, ID03 and n are the process- dependent constants. From Equation (5), the VSG1 and VGS3 can be obtained as (6.a) (6.b) The input voltage of LSCM can be written as below (7) by using Equations (5) and (6). For low voltage opera­tion, VTHN > |VTHP| and Iin > Ib1 is required. This condition related to threshold voltages is arranged when the bulk-source voltage of the M3 is negative value using the bulk voltage (Vbulk) as shown in Equation (3). The output voltage necessity for the proposed PMOS LSCM is given by (8) 4 Proposed low-voltage PMOS current mirror structure The low-voltage PMOS current mirror (LVCM) structure is shown in Figure 3. Figure 3: Low-voltage PMOS current mirror. The input voltage for the proposed CM is given by (9) From Equation (3), it can be seen that the threshold volt­age can be increased by using the bulk-source voltage for M3 and M6. Hence, it should be indicated that this condition for the PMOS transistor can achieve level-shifting operation. If Figure 3 is analyzed, it can be seen that VSG1 > VGS3 and VSG4 > VGS6 because there is a relation­ship between voltages as VTHN > VTHP. This condition is ar­ranged when the bulk-source voltage of the M5 and M6 is negative value as seen in Equation (3). Also, the input voltage of the CM shown in Figure 3 can be written as (10) where kp =µnCox is the transconductance parameter of the PMOS transistor, UT is the thermal voltage and ID03, ID06 is the saturation current. Also, ID03, ID06 and n are the process- dependent constants. The maximum output voltage requirement for the proposed CM is given by (11) Input and output impedances of the proposed circuit can be defined as (12.a) (12.b) The proposed LVCM is shown in Figure 4. The transis­tors M7 and M8 have been added for biasing. Figure 4: Enhanced low-voltage PMOS current mirror. If the M3 and M6 are considered identical, the biasing current Ib1 can be given as (13) ID07 is the saturation current. Also, ID07 and n are the pro­cess-dependent constants. Ib2 can be defined as similar to Ib1. It can be seen that these currents are always low. Thus, the M3 and M6 operate in the sub-threshold re­gion. Also, using an external capacitance (C) shown in Figure 4 decreases effective input capacitance. Figure 5 (a) indicates the conventional transconduct­ance amplifier circuit. Figure 5 (b) indicates the pro­posed transconductance amplifier circuit for use in low voltage applications. The drain resistance as a load is used in the transcon­ductance amplifier. Replacing the drain resistance with a current mirror as an active load results in much higher voltage gain [11]. The proposed LVCM as an active load can be used in the transconductance amplifier shown in Figure 5 (b). Transconductance can be expressed as (14) Here, it can be determined as Gm ˜ gm = gm9 = gm10. Where V1, V2 are the input voltages, I0 is the output cur­rent, gm9 and gm10 are the transconductances of transis­tors M9 and M10, respectively. W/L is the aspect ratio of the transistors using for differential pair. The bulk for differential pair is connected to drain in Figure 5 (b). Body bias is used to dynamically adjust the threshold voltage (VTH) of a CMOS transistor. The polarity of the body bias for M9 and M10 is positive values. This situa­tion causes a decrease in the value of VTH for M9 and M10. The bulk-connected structure is suitable for low voltage applications. Also, the current IB is the biasing current for the differential pair. A low-voltage transcon­ductance amplifier has been used in many active ele­ments designed with low-power such as Op-Amp, OTA and current conveyor [1-4]. Thus, these active elements have gained operating capability at the low-voltage by using the proposed circuit. 5 Simulation results The current mirror circuits (Figs. 1, 2, and 4) were simu­lated for TSMC 0.13 µm technology. The aspect ratios of the transistors are given in Table 1. Table 1: The aspect ratio of the transistors. Transistor M1–M4 M5, M6 M7, M8 M9, M10 M11, M12 W/L (µm) 30/0.26 20/0.26 0.26/0.26 2/1 40/0.26 All the circuit operations have been simulated for the supply voltage ±0.5 V. Currents Ib1 and Ib2 are selected as 20 nA. Also, Vbulk is equal to -0.5V (VSS). Comparison of current/voltage characteristics of the current mirrors is illustrated in Figure 6. Vin is the input voltage for LVCM is shown in Figure 3. The value of Vin is taken as 0 V. The I / V characteristic shown in Figure 6 is obtained by changing the supply voltage between 0 mV and 600 mV. It is clearly shown that the supply voltage of the pro­posed LVCM requires the lowest value of the supply voltage compared to any other structures. Therefore, the proposed circuit is suitable for low voltage applica­tions. The current transfer characteristic exhibits linear behavior as depicted in Figure 7. However, deviation from linearity occurs for larger value of currents. The percentage gain error (Iout / Iin) of the proposed cir­cuit is approximately 0.3 % for Iin=200 µA as displayed in Figure 8. Whereas, the percentage gain error (Iout / Iin) of the PMOS LSCM and conventional CM are 0.6 % and 0.9 % for Iin=200 µA, respectively. Figure 8: Current tracking errors of various CMs. The I-V characteristics of the proposed LVCM at differ­ent input currents are illustrated in Figure 9. The out­put current swing of the LVCM is almost independent on VDD for low output current values. The value of Vout is taken as 0 V (Vout = 0 V). Considering the output cur­rent of the proposed LVCM it can be operated at 0.5 V as shown in Figure 9. Figure 9: I-V characteristics of the proposed LVCM. The frequency responses of the current mirrors are in­dicated in Figure 10. Figure 10: Comparison of the bandwidth of various CMs. There is an improvement in the bandwidth when a capacitance (C) is used and the bandwidth is found to be 11 GHz. It is shown that the bandwidth reduces to 5 GHz when the C is not used in the design. It is seen that as the capacity value increases, the bandwidth in­creases. Also, the capacitance (C) has a value of 100 pF. The bandwidth of the PMOS LSCM and conventional CM are 0.24 GHz and 17.2 GHz, respectively. The capacitance (C) has a value of 100 pF for 11 GHz shown in Figure 11. As the capacitance value decreas­es, the bandwidth decreases. The bandwidth can be sacrificed to obtain the lower value of capacitance. The temperature effect on gain-bandwidth perfor­mance of the LVCM is depicted in Figure 12. Figure 12: The temperature effect on Gain-Bandwidth performance of the LVCM. The current gain is about equal to 0.35 dB for 75 °C as shown in Figure 12. Although higher temperature in­creases the gain of the LVCM the increase is tolerable. The LVCM exhibits temperature-dependent bandwidth characteristics depending on transistors M3 and M6 op­erates in sub-threshold region as shown in Figure 3. The Monte Carlo analysis which is repeated for 30 times is illustrated in Figure 13. Figure 13: Monte Carlo analysis for Current Gain. Figure 13 justifies that current gain value has still stable under 20 % random variations in threshold voltages of the transistors. Figure 13 indicates the good perfor­mance of the proposed circuit versus mismatches. Performance comparison of the aforementioned cur­rent mirrors is depicted in Table 2. Table 2: Performance comparison of the CMs. Parameter PMOS CM Level Shifter CM Proposed LVCM Power dissipation (µW) 3 dB BW, Iout / Iin (GHz) Vin (mV) Rin (K.) Rout (K.) Gain error, Iout / Iin (%) 177 17.2 512 2.56 69.5 0.9 67.7 0.24 470 2.35 99.3 0.6 56.6 11 392 1.96 130 0.3 for supply voltage = ±0.5 V and input current Iin = 200 µA When the performance parameters of the CMs are in­vestigated, it is clearly shown that the proposed struc­ture has a lot of advantages compared with the others. Significantly, the proposed circuit’s input resistance is much lower than the others, and it is seen that the sug­gested LVCM’s low input voltage is one of the critical advantages. Also, the gain error belonging to currents (Iout / Iin) of the proposed circuit is reasonable compared to the other circuits. The low-voltage transconductance amplifier used the LVCM and the conventional transconductance ampli­fier is shown in Figure 5. These circuits were simulated for TSMC 0.13 µm technology. The aspect ratios of the transistors are given in Table 1. The relation between input difference voltage and out­put current of the transconductance amplifiers is de­picted in Figure 14. Also, the supply voltage has been chosen as ±0.5 V for both amplifiers. The value of IB shown in Figure 5 is chosen as 50 µA. Figure 14: I / V characteristic of the transconductance amplifiers (input difference voltage versus output current) Conventional transconductance amplifier has not ex­hibited good performance at low voltage. The circuit has not strictly operated at ±0.5 V for the negative values of the output current. It is shown that the pro­posed circuit is more suitable than the other circuit for low voltage applications. However, a conventional transconductance amplifier can only be operated on minimum supply voltage with ±0.65 V, while the pro­posed circuit can be employed for lower voltage. Figure 15 indicates the power consumptions of the proposed and conventional transconductance ampli­fiers for different biasing currents (IB). Figure 15: Total power dissipation versus biasing cur­rents for circuits. As seen in Figure 15, the presented circuit consumes lower power than the conventional circuit for diverse biasing currents. The proposed circuit consumes 70 µW for 50 µA of biasing current. Hence, the suggested cir­cuit is suitable for low-power applications. The frequency performance of the transconductance amplifiers is illustrated in Figure 16. Figure 16: The frequency response of the transcon­ductance amplifiers. Frequency responses of the transconductance (gm) value for the proposed and conventional circuits are indicated in Figure 16, which gives a bandwidth (-3dB) of 398.8 MHz and 581.1 MHz, respectively. The total harmonic distortion (THD) is evaluated for in­put voltage with different amplitudes for a biasing cur­rent of 50 µA, as shown in Figure 17. Figure 17: THD (%) versus input voltage (at a frequen­cy of 1 MHz) for the proposed circuit. The fundamental frequency (1st harmonic) has been specified and THD has been calculated via the PSpice program. The third harmonic provides the most im­portant contribution to the total harmonic distortion of the circuit. The THD has a value of about 0.94% for 250 mVP-P. It is shown that THD obtained according to the different peak-to-peak input voltages are reason­able values. 6 Conclusion A low-voltage current mirror circuit employing the volt­age level-shifting principle is demonstrated for use in differential pair as an active load. The proposed current mirror operates at ±0.5 V and its bandwidth is about 11 GHz. Also, it consumes 56.6 µW power. The proposed circuit exhibits better performance than the other CMs called PMOS CM and level shifter CM. It is undeniable that the simulation results confirm the validity of the theory and demonstrate the usage of the LVCM in elec­tronic applications. Also, the proposed transconduct­ance amplifier using LVCM has been compared to the conventional one. The proposed transconductance amplifier’s bandwidth is about 581.1 MHz. It consumes 70 µW power. Finally, such a current mirror is appropri­ate for low-voltage applications, resulting in increas­ing threshold voltage. Hereafter, the suggested PMOS current mirror would be operated even at lower supply voltages if the threshold voltages could be decreased. 7 Conflict of interest The authors declare no conflict of interest. 8 References 1. S. Chatterjee, Y. Tsividis, and P. Kinget, “Ultra-low voltage analog integrated circuits,” IEICE Trans. Electron., vol. E89-C, no. 6, pp.673–680, 2006, https://www.doi.org/10.1093/ietele/e89-c.6.673. 2. S.A. Tekin, H. Ercan, and M. Alçi, “Novel low volt­age CMOS current controlled floating resistor us­ingdifferential pair,” Radioengineering, vol. 22, no. 2, pp. 428-433, 2013, https://dx.doi.org/10.13164/re 3. H. Ercan, “A linear current-controlled floating neg­ative resistor,” Informacije MIDEM Journal of Micro­electronics, Electronic Components and Materials, vol.43, no.4, pp.222–227, 2013. 4. S.A. Tekin, “Voltage summing current conveyor (VSCC) for oscillator and summing amplifier ap­plications,” Informacije MIDEM Journal of Micro­electronics, Electronic Components and Materials, vol. 44, no. 2, pp. 159–167, 2014. 5. K. K. Abdalla, D. R. Bhaskar and R. Senani, “A re­view of the evolution of current-mode circuits and techniques and various modern analog cir­cuit building blocks,” Nature & Science, vol. 10, no. 10, pp. 1–13, 2012, https://www.doi.org/ 10.7537/marsnsj101012.01 6. K. Monfaredi, H. Faraji Baghtash, “An Extremely Low-Voltage and High-Compliance Current Mir­ror” Circuits Syst Signal Process, vol. 39, pp. 30–53, 2020, https://doi.org/10.1007/s00034-019-01175-1. 7. J. Ramirez-Angulo, “Low voltage current mirrors for built-in current sensors”, IEEE International Sympo­sium on Circuits and Systems ISCAS ‘94, vol. 5, 1994, pp .673–680, https://www.doi.org/ 10.1109/ISCAS.1994.409429. 8. H. Ercan, S.A. Tekin, and M. Alçi, “Low-voltage low-power multifunction current-controlled con­veyor,” International Journal of Electronics, vol. 102, no. 3, pp. 444–461, 2015, https://doi.org/10.1080/00207217.2014.897382. 9. S.S. Rajput, and S.S. Jamuar, “A current mirror for low voltage, high performance analog circuits,” Analog Integrated Circuits and Signal Processing, vol. 36, no. 3, pp.221–233, 2003, https://doi.org/10.1023/A:1024718421282. 10. S. Yan, and E. Sanchez-Sinencio. “Low voltage analog circuit design techniques: A tutorial,” IEICE Transactions on Fundamentals of Electronics, Com­munications and Computer Sciences, vol.83, no.2, pp. 179–196, 2000. 11. A. S. Sedra and K. C. Smith, Microelectronic Cir­cuits, Revised Edition, Oxford University Press, New York, 2007. Arrived: 11. 01. 2021 Accepted: 01. 04. 2021 H. Ercan et al.; Informacije Midem, Vol. 51, No. 1(2021), 63 – 71 H. Ercan et al.; Informacije Midem, Vol. 51, No. 1(2021), 63 – 71 H. Ercan et al.; Informacije Midem, Vol. 51, No. 1(2021), 63 – 71 H. Ercan et al.; Informacije Midem, Vol. 51, No. 1(2021), 63 – 71 a) Figure 6: Comparison of I / V characteristics of various CMs. b) Figure 5: Transconductance amplifiers a) conventional, b) proposed. Figure 7: Current transfer characteristics of proposed LVCM. H. Ercan et al.; Informacije Midem, Vol. 51, No. 1(2021), 63 – 71 Figure 11: Variation of the bandwidth with external capacitor H. Ercan et al.; Informacije Midem, Vol. 51, No. 1(2021), 63 – 71 H. Ercan et al.; Informacije Midem, Vol. 51, No. 1(2021), 63 – 71 H. Ercan et al.; Informacije Midem, Vol. 51, No. 1(2021), 63 – 71 Copyright © 2021 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 1(2021), 73 – 84 https://doi.org/10.33180/InfMIDEM2021.105 Effect of Dipole Position and Orientation on Light Extraction for Red OLEDs on Periodically Corrugated Substrate - FEM Simulations Study Milan Kovacic University of Ljubljana, Faculty of Electrical Engineering, Ljubljana, Slovenia Abstract: One of the main efficiency-limiting factors for organic light-emitting diodes (OLEDs) is poor light extraction, which typically reaches only 20% (in best cases up to 30%) in flat standard devices. Optical modeling and simulations play an important role in improving light extraction and optimizing outcoupling efficiency. Using FEM modeling approach, the effect of dipole positions and orientations for red OLEDs on periodically corrugated substrate is evaluated and used to enhance the outcoupling efficiency. It is shown that with only 3 carefully selected dipole positions, the outcoupling efficiency over the whole area can be predicted with very reasonable accuracy, which greatly reduces the number of simulations required. The presented modelling approach is used for optimization of the sine texture as a substrate corrugation structure. OLEDs with optimized simulated texture show a relative improvement of light outcoupling from the thin film stack to the substrate by more than 25% compared to the flat plane devices. Keywords: OLED; outcoupling; finite element method; optical modelling Vpliv Pozicije in Orientacije Dipola na Izstop Svetlobe Rdecih OLED na Periodicno Teksturiranem Substratu – FEM Simulacijska Obravnava Izvlecek: Eden izmed glavnih dejavnikov, ki omejujejo ucinkovitost organskih svetlecih diod (OLED), je nizka stopnja ucinkovitosti izstopa svetlobe, ki pri standardnih napravah dosega le okoli 20% (v najboljših primerih pa do 30%). Opticno modeliranje in simulacije igrajo pomembno vlogo pri izboljšanju izstopa svetlobe in optimizaciji opticnega izkoristka. Z uporabo FEM modeliranja se ovrednoti ucinek položaja in usmeritve dipolov za rdeco OLED na periodicno teksturiranem substratu, ki se uporablja za povecanje ucinkovitosti izstopa svetlobe. Pokaže se, da je mogoce s samo 3 skrbno izbranimi položaji dipola, z dobro natancnostjo napovedati ucinkovitost izstopa na celotnem obmocju, kar mocno zmanjša število zahtevanih simulacij. Predstavljeni FEM pristop se uporabi za optimizacijo sinusne teksture kot strukture teksturiranega substrata. OLED z optimizirano simulirano teksturo kažejo relativno vec kot 25% izboljšanje ucinkovitosti izstopa svetlobe iz tankoplastne strukture v substrat v primerjavi s plošcatimi napravami. Kljucne besede: OLED; izstop svetlobe; metoda koncnih elementov; opticno modeliranje * Corresponding Author’s e-mail: milan.kovacic@fe.uni-lj.si 1 Introduction Organic light-emitting diodes (OLEDs) have in recent years achieved a commercial widespread in display technology, especially in mobile and television dis­plays. OLEDs are also very promising for general indoor and outdoor lighting, due to low cost, high efficiency, and high color quality. OLEDs can be fabricated as a large area sources on rigid or flexible substrates, can be made transparent for application on windows, all of which is important in lighting and architecture design [1]–[5]. OLEDs based on phosphorescent [6] and more recently on thermally activated delayed fluorescence emitters [7], [8] have already achieved internal efficien­cies close to 100%. On the other hand, highest EQEs for typical flat plane devices reaches only 20-30%, which is due to high optical losses resulting in poor light out­coupling efficiency [9]. Optical losses in OLEDs can be divided into three main groups. First are substrate losses due to total internal reflection (TIR) on the substrate/air interface, where light gets captured inside the thick substrate. Second are waveguide losses, that happen due to TIR at or­ganic (transparent contact)/substrate interface, where light gets waveguided and eventually absorbed. Third part are losses due to coupling of light to surface plas­mon polaritons (SPP) at organic/metallic interfaces. Minor losses are also due to parasitic absorption in lay­ers [10]. There has been a lot of research and proposed solutions to improve the light outcoupling, see for ex­ample recent reviews [11], [12]. Especially on reducing the substrate losses, highly efficient solutions already exist, like attaching a half-sphere, different micro-texturing [13]–[17] and others [18], [19]. On the other hand, solutions to waveguide and SPP losses exists, like micro-lens arrays [20], introducing scattering par­ticles [21], corrugations [22], [23] and others [24], [25], but remain less researched and non-optimized. This is mainly because internal solutions are more challeng­ing to fabricate and to integrate with OLED thin film stack, without having negative impact on electrical ef­ficiency [26]. With this in mind, optical modelling and simulations play an important role in improving out­coupling efficiency, to predict optimal solutions prior to complicated fabrication process, to test only most promising ones. Simulations of light emission from thin film stacks with internal outcoupling solutions (e.g. tex­turization, corrugations, scattering particles) requires more advanced modelling approaches, compared to flat-plane devices. In this paper, finite element method (FEM [27]) opti­cal modelling is utilized to research effects of a corru­gated substrate, which introduces internal textures in the OLED device structure itself. The aim is improved outcoupling of light into the substrate. In particular the focus is on investigation of different positions and ori­entations of emitting dipoles on outcoupling efficiency for red OLED on periodically corrugated substrate. FEM modelling approach, describing main considerations when simulating OLEDs, is explained. Presented model is used to analyze how number and position of simu­lated dipoles affect the simulated outcoupling accu­racy. In addition, it is shown that in the analyzed cases already 3 specifically positioned dipoles in the simula­tion domain are sufficient to get good prediction of trends for outcoupling efficiency. Moreover, outcou­pling efficiency and outcoupling trends of differently oriented dipoles for different positions on corrugated substrate are evaluated. 2 OLED Modelling The outcoupling of light in OLEDs, which is the focus of this paper, can be presented by combined opto-electri­cal parameter called external quantum efficiency (EQE), which defines the ratio between the number of pho­tons reaching the far field as useful light to the num­ber of injected charge carriers. EQE is calculated using equation (1), where . is electrical efficiency defined as ratio between the number of radiative recombination in emission layer and the number of injected charge carriers, is normalized electroluminescent spec­trum of emission material, is outcoupling effi­ciency of generated light into far field and is effective radiative efficiency. (1) where (2) determines the ratio between radiative and non-radiative recombination. is the intrinsic ra­diative efficiency of the emitter and is the Purcell factor, defined as a ratio between total emitted light at the source location and total emitted light in infinitive homogeneous medium. Using optical simulations, also employed in this work, wavelength dependent outcou­pling efficiency of generated light and wave­length dependent Purcell factor are calculated, and with these and by using equations (1) and (2), EQE as a primary optical data can be calculated. 2.1 Modelling of light in thin film OLED stack In OLEDs light is generated in the emission layer (EML) inside a thin film structure (e.g., see thin film structure used in this paper – Figure 1(a)) by electrolumines­cence emission of emitter material molecules. As sizes of these molecules are much smaller (few nanometers) than emission light wavelength (visible light), these can be treated as differently oriented point dipole sources [28]. The dipoles have specific predefined emission spectrum (determined by the molecule type) and angular intensity distribution and polarization of light according to the orientation in the layered system. Dipoles can in general have any arbitrarily orientation which can be represented by three perpendicular di­pole components, two horizontally (x-y) and one verti­cally (z) oriented according to the selected global coor­dinate system. In case of flat plane OLEDs, orientation of dipoles in the plane of layered system (x-y) plays no direct role on outcoupling efficiency itself (it can af­fect angular distribution of light) and is in most cases treated as isotopically oriented [29], thus only ratio be­tween vertical and horizontal dipoles is considered. To describe general orientation of all emitting dipoles in the system, an anisotropy coefficient a is introduced, which is defined as the ratio between the vertical di­pole component towards all three dipole components. Anisotropy coefficient a = 1/3 meaning isotropic ori­entation of dipoles, while a < 1/3 indicates preferential horizontal orientation of dipoles and a > 1/3, preferen­tial orientation of vertical dipoles. Simulation of flat plane devices can be quickly and effi­ciently done by decomposing the dipole emission into set of plane waves which are then transferred through the thin film stack by using transfer matrix method (TMM). In case of large external corrugations or other textures, TMM can be coupled with geometrical optics for complete device simulations [16], [17]. On the other hand, modelling and simulation of nano­textured, corrugated or by introducing other disrup­tion in horizontal directions (e.g., scattering particles) requires more advanced approach. For the modelling of nanostructured thin-film structure we use 3D optical simulator COMSOL Multiphysics [30], which is based on a finite element method. We choose FEM due to advantages over other methods (RCWA FDTD) due to possibility of better discretization with higher order approximation of field inside the element, fairly straightforward definition of material properties (dielectrics and metals) and boundary conditions (e.g. absorbing, symmetry), ability to handle complex 3-D geometry and especially delivery of steady-state so­lutions in frequency (wavelength) instead of time do­main (e.g. FDTD). Using FEM, an arbitrarily oriented dipole source can be placed anywhere inside the structure and its steady state can be simulated. As each dipole need to be treated as individual source in laterally large structure (incoherent relation between different dipoles), there is a problem how to set the boundary conditions of simulation domain to avoid coherent connections between different dipoles. This presents one of the main challenges in rigorous simulations of OLEDs, re­quiring special modelling approaches to be taken. For example, regular periodicity boundary conditions that significantly reduce the simulation domain to a single unit cell or less, cannot be used here, as imply coherent connections between sources in periodically repeated unit cells. One solution would be to put a single dipole source in a laterally large structure with dimensions large enough to take into account all effects taking place far away from the source with multiple simula­tions for each different dipole position and orientation [31]. Main drawback is the required size of the model, as propagation lengths can be very large, thus lateral sizes of at least 40 mm and more away from the source would be necessary to include majority of the effects. Such large models would require huge amount of com­putational power (especially limiting is the computer memory) and are thus not really feasible. Alternative method is the usage of the so-called Flo­quet transform method [32], [33] (FTM). FTM highly re­duces memory requirements as it enables simulations of a single period (geometry) with individual source anywhere in the basic cell by using the Floquet trans­form to decompose non-periodic dipole source to a linear superposition of Bloch periodic terms. Details on the method itself can be found in [32]. Drawback of this approach is that it requires large number of simula­tions for accurate results (many Bloch periodic terms). Numerous simulations are required due to application of different phases for in/out going waves at the edge of domain, required to cancel unwanted coherence be­tween dipoles from neighboring domains. With paral­lelization this can be tolerable and FTM is also used for simulations in this work. When constructing FEM model with FTM, we need to consider some specifics that we will describe in the fol­lowing. Simulation domain needs to contain at least one, but multiple (integer) periods can also be used. On top (vertical dimension) unbounded areas that are stretching to infinity (e.g. glass, air), need to be trun­cated using open boundaries, absorbing all incident light with zero reflectivity. Open boundaries like per­fectly matching layer (PML) or absorbing boundary conditions (ABC) are applied here. An important aspect is also the distance between open boundary and thin film stack. If the boundary is too close to the stack, pos­sible coupling of evanescent waves to the boundary can happen influencing the simulation accuracy, on the other hand if the boundary is too far away, this can result in larger domain, requiring more computational power, elongating the simulation time. Here a rule of thumb is applied that the minimal distance between boundary and thin film stack is around 1~1.5 * simu­lated wavelength. In lateral directions where perio­dicity is applied, 2 pairs of periodic Floquet boundary conditions are used. For periodic boundary conditions, special care needs to be taken when meshing, as mesh shape and size needs to be identical on both repeating sides, otherwise large errors can happen. For the rest of the device, meshing of the structure with general rule of thumb can be used, with 8-10 elements per distance of effective wavelength. It needs to be mentioned that by using FTM (or other FEM method) angular intensity distribution (AID) of emitted light of OLED device in the far-field cannot be gained directly, only the total outcoupling efficiency and the Purcell factor can be calculated directly. For far field AID calculation, a reciprocity principle [34], [35] can be employed, that enables to calculate AID as a consequence of any single dipole (or continuous spa­tial emission by multiple dipoles) at any position in the OLED stack. For each plane wave entering from outside under specific angle of incidence, it can be recalculated (by knowing E field (simulations) at the dipole(s) loca­tion) how this dipole contributes to emission into this specific angle in the far field. Extending simulations to multiple incident angles (both zenith and azimuth), AID in the far field for all simulated incident angles can be gained. This approach can only access modes that reach the far field medium (glass, air), while all other modes are inaccessible, giving only partial data. For to­tal evaluation, reciprocity principle for calculating AID and FTM for calculating outcoupling efficiency and Pur­cell factor, could be used as complementary methods, enabling simulations of device with thin and optically thick layers as well as nano and micro-sized textures or other outcoupling solutions. 2.2 Corrugated OLED structure description and model In this contribution the focus is only on thin film stack and optical properties connected with it. In simulations glass substrate is treated as half infinitive, this is from ex­perimental point similarly as by attaching a large glass hemisphere on top of the substrate, that enables extrac­tion of almost all light that reaches the substrate. By this, losses due to TIR at substrate/air interface are excluded and additional back reflections into the thin film stack are neglected, thus only waveguide and SPP losses are included. Due to this, outcoupling efficiency through entire paper is considered for light reaching the sub­strate and consequently air by using a glass hemisphere (ignoring minimal losses at glass hemisphere/air inter­face). We focus on standard red bottom emitting OLED [10], [16], with high electrical efficiency . = 1 and intrin­sic radiative efficiency = 0.7. Simulated stack, with layer thicknesses marked, is presented in Figure 1(a). Emission layer (EML), where light is generated, is sand­wiched between two blocking layers (for electrons - EBL and holes - HBL), and two transport layers (for electrons - ETL and holes HTL), that ensure high recombination rate in EML. Contacts are realized by opaque Ag cathode and a transparent indium tin oxide (ITO) anode. In our simu­lation model, EBL, HBL and EML were joined into single EML layer, to avoid very thin layers that can be very prob­lematic to mesh and add unnecessary complexity to the device. This can be justified due to very similar optical properties of these layers so only minimal difference is expected. Emission dipoles are positioned at EML/HBL interface, as majority of recombination events occurs in vicinity of HBL, due to higher hole conductivity of EML. Entire thin film stack is deposited on top of a flat or sine textured substrate. A sinusoidal texture is selected as it is commonly used and can be experimentally fabricated on e.g. silicon or glass master by e-beam or other etch­ing techniques. Additionally, selected sine texture ex­hibits smooth morphology without any abrupt changes, minimizing possibility of introducing electrical defects. All results in this contribution are related to this texture shape. When layers are deposited on top of a textured sub­strate, they experience layer growth which is a combi­nation of conformal and isotropic growth [36]. In this case a more conformal growth (linear combination of both 0.3*isotropic + 0.7*conformal) was used, which is the most common growth ratio in many amorphous materials. Actual layer growth as used in model can be seen in Figure 1(b). In EML a continuous homogenous spatial emission in the emission layer is assumed, i.e. an uninterrupted distribution of dipoles across the entire emission layer. With laterally symmetrical textures, such as the 2D sine texture in this case – Figure 1 (b), an advantage of the symmetry of the structure can be taken and only di­poles on a smaller area can be simulated. In this case, this means that by considering dipoles on only 1/8 of the period (see Figure 1 (b) with red dots indicating di­pole positions), the coverage of emission sources over the entire period and thus structure can be described. On the other hand, for non-symmetrical textures (e.g. saw profile or random) all possible locations of dipoles need to be considered. In the case of the sine texture, 15 dipoles positioned at constant distances from each other within the 1/8 of the texture were used, with the aim to consider as many possible positions of the di­poles on the texture, including extreme positions (e.g. on top and bottom of the texture). The numbering of the dipoles starts with no. 1 at the bottom (minimum) of the texture and ends at the top (maximum) with no. 15. Other dipole positions and corresponding number markings can be read from Figure 2(a) (top view of the dipole area, which can be linked to Figure 1(b)). It must also be taken into account that not all dipole po­sitions, once extended to the whole period, make the same contribution to the total outcoupling efficiency, as some dipoles represent larger area than others - see Figure 2(a) (weighing factors for entire period marked with x-times) and Figure 2 (b-d). For example, area cor­responding to dipole at location 15 (also 1) when ex­tended to the whole period represent the same area as a dipole at location 7 (8 or 11) before extension, re­sulting in 8-times lower contribution for dipole at lo­cation 15 (or 1) than for dipole at location 7 (8 or 11). To compensate for this, an additional weighting factors are added to each simulated dipole according to the represented area in the whole structure - see weight­ing factors in brackets in Figure 2(a), next to the dipole number. The orientation of the dipole is defined by its dipole moment direction, which for horizontally oriented di­poles points in the x, y plane and for vertically oriented dipoles in ±z direction according to the globally de­fined coordinate system and not according to the tex­ture surface normal. For vertically oriented dipoles, this direction is uniquely defined in ±z direction. While for two horizontally oriented dipoles the orientation in the x, y plane is in general free, only with the requirement of 90 degrees between them. Due to introduced sym­metry in used model, the orientation is defined in the initial simulation domain (1/8 of the period), where two horizontally oriented dipoles are differentiated as hori­zontally oriented - 1, where dipole moment direction points in ±x-direction, and as horizontally oriented - 2, where dipole moment direction points in ±y-direction- see Figure 2 (b-d). Looking at the symmetry, extension over the texture diagonal leads to a change of dipole moment direction by 90 degrees in a defined coordi­nate system. As our definition of dipole orientation is defined on the starting 1/8 of the structure, even though the dipole moment is rotated by 90 degrees, the orientation with respect to the structure remains the same and is still treated as the same orientation as defined in the original 1/8 of the period. For details on the orientation of dipoles over the entire period, see Figure 2 (b-d). 3 Results 3.1 Flat plane device To verify the presented FEM model, a simple device with a flat plane is simulated and results are compared (see Figure 3) with an internally developed TMM model which has been derived theoretically and verified ex­perimentally [16]. Two orientations of dipoles are considered separately in this case: horizontally oriented-1 (identical results have been obtained for the horizontally oriented-2 in case of flat device) and vertically oriented (along z axis). In Figure 3(a) simulation results are presented for the outcoupling efficiency - and in Figure 3(b) the Purcell factor - F(.) (see definitions in Eq. 1). For both horizontally and vertically oriented dipoles very good agreement between the results can be observed, espe­cially for the outcoupling efficiency. On the other hand, some differences in the Purcell factor can be seen, but the deviations from the correct results are small and should even decrease with texturization due to multi­ple random scattering events, resulting in reduced un­wanted coherence between random scattering events resulting dipoles (boundary conditions). 3.2 OLED on corrugated substrate - effect of dipole location and orientation FEM model is used to analyze optical properties, with the focus on light outcoupling of the red OLED thin-film stack deposited on a sine textured substrate with a period P = 800 nm and different height ranging from 0 (flat) to 400 nm (see definition of P and h in Figure 1). The effect of dipole positions and heights on outcou­pling efficiency is analyzed. Results are presented for wavelength of 612 nm, that corresponds to the emis­sion spectrum peak presented in Figure 3(a). First, the focus is on how dipole positions and orienta­tions influence light outcoupling for different heights of the sine texture. For this, simulations of outcoupling ef­ficiency for each of 15 dipoles individually for all three orientations and with different heights (0-400 nm) of the texture were carried out. Results of the simulations are presented in Figure 4(a-c), where lines represent outcou­pling to substrate for each dipole individually and the crosses with dashed lines present weighted average of all 15 dipoles, which is actually the result corresponding to situation when all dipoles were included in calcula­tion at once. Since the dipoles are not coupled in a co­herent manner, such averaging can be carried out. First observation from the results plotted in Figure 4 (a-c) is a high spread of results depending on the position of the dipole, indicating high influence of dipole posi­tion on the outcoupling efficiency. It has to be noted that global orientation of dipoles in one orientation set (e.g., horizontally oriented -1) remains the same inde­pendent of the dipole position. Differences are increas­ing with increasing texture height. This is expected, as the differences in actual vertical positions of dipoles are larger for the textures with higher h. Differences in outcoupling efficiencies between specific dipole loca­tions can also be very high, especially for horizontal orientations, with absolute differences between mini­mum and maximum value above 10% for horizontal dipoles and even above 25% for vertical dipoles at tex­ture height of 400 nm. For a visual presentation of the effect of dipole loca­tion for the three different orientations, outcoupling efficiencies are compared again for OLED structure with the sine texture with P = 800, h = 250 (max. out­coupling with a = 0.24). The outcoupling efficiency ac­cording to the dipoles position on one quarter of the sine texture is shown in Figure 5. For both horizontal orientations, the highest outcoupling efficiency can be observed for the dipoles which are located on top of the texture, while outcoupling starts to decrease when moving towards the lower positions, again it slightly increases at the lower end. For horizontal-1, a high outcoupling at the ridge can be observed, while for horizontal-2 at the same position no such increase can be observed. With vertically oriented dipoles, in contrast to both horizontally oriented dipoles, a mini­mal outcoupling efficiency is achieved at the top end of the texture, which increases towards the middle of the texture, while outcoupling decreases again at the minimum. The outcoupling efficiency seems to follow the inclination on the texture. For horizontal dipoles a lower outcoupling at higher inclinations (separately in x or y direction for horizontal-1 and horizontal-2) is gained. While with vertical dipoles at higher inclina­tions a higher outcoupling efficiency is observed. This would indicate, as a highly simplified approximation, that textures with less steep features are required for an optimal outcoupling with horizontally oriented di­poles, while for vertically oriented dipoles exactly the opposite is required, i.e. textures with steeper features, indicating that the final outcoupling efficiency is a compromise between both scenarios. The optimal tex­ture would also change with the general orientation of the dipoles, since a different texture would be optimal if there would be more vertically oriented dipoles or more horizontally oriented dipoles. Ultimately, the out­coupling cannot only be related to the inclination of the texture, as there are a number of other effects, such as the actual texture shape, the emission wavelength, the thin-film structure, all of which are specific to each individual OLED design, but these findings can serve as guidelines for further research. In addition, the mixture of many optical effects, with a high dependency not only on the shape and size of the texture but also on the emitting dipole positions and orientations, shows the importance of optical modeling and simulations for the planning, optimization and analysis of optimal optical solutions for achieving the highest outcoupling of individual OLED design. 3.3 Effect of number of dipoles used in simulations To evaluate how much each outcoupling efficiency at each dipole position differs from weighted average, in Figure 6 total relative deviation from weighted aver­age is presented, calculated as abs(( )- ) / ), where i is the number of the dipole (1-15), and summed over all texture heights. A high spread of deviations between all dipole posi­tions is observed. What can also be clearly observed is the difference in the deviations at the same positions but different orientations, which indicates that the de­viation is not only location-dependent but also strong­ly orientation-dependent. For example, dipoles at po­sition 3 show high deviations for horizontally-1 and vertically oriented dipoles, but very low deviations for horizontally – 2 oriented dipoles. Overall, the smallest deviations for all three orientations can be observed for dipoles at position 8 and 11. Investigation on what is the minimal number of dipoles and what are their locations to approach the results obtained in simulations using 15 dipole locations were done. The first choice would be to take a single dipole position, preferably the dipole at position 8, which gen­erally shows the least deviation from the averaged total data. On the other hand, a single dipole position would theoretically allow us to hit a special location where the results would differ significantly from all others (e.g., constructive or destructive coherence, etc.), so that mul­tiple dipole positions would be preferable. To compare the outcoupling trends, in Figure 4 (d, e, f) the outcou­pling for a single dipole at location 8 as the dipole with the smallest total deviation from the weighted average, the combination of the dipoles at locations 8 and 11 as two of the dipoles with the smallest deviation from the weighted average, special case of the combination of dipoles at the locations 7, 8, 11 as the combination of dipoles which are most represented on the geom­etry, and which are also at center locations, and at the end the combination of dipoles at the locations 6, 8, 13 which show the best agreement with the weighted av­erage over 15 dipole locations are shown. Interestingly, the most representative combination of dipoles was the combination of dipoles at locations 6, 8 and 13, which are also located at central locations but are more widely spread than the dipoles at sites 7, 8 and 11 – see Figure 2. This combination of dipole locations follows weighted data for 15 dipole locations very well. It should be noted that even by simulating a single dipole at location 8 or a combination of other dipole locations, as shown in Figure 4 (d, e, f), a good agreement with general trends is obtained, albeit with an over- or under- estimation of the actual outcoupling efficiency. These results show that even by simulating a smaller number of carefully se­lected dipole locations, it is possible to predict outcou­pling trends, which greatly reduces the simulation time, although for the most accurate data, as many dipole po­sitions as possible would have to be included in the sim­ulations. On the other hand, it must also be mentioned that not every dipole location or even the combination of two or three dipole locations with the wrong selec­tion (e.g. dipoles at extreme points, symmetry, e.g. no. 1, 5, 15) leads to good results. Not only can these results differ significantly from the actual data, they can also lead to false trends. In Figure 4(d, e, f), vertical lines rep­resenting the maximum and minimum output values at each texture height are added, showing high deviations from the actual weighted average, and also different trends for both horizontally oriented dipoles, with maxi­mum output at much higher heights (250 - 300 nm) of the texture than with weighted average (150 - 200 nm). Therefore, three carefully selected dipole positions, pref­erably in the middle and wide spread, are necessary for a good adaptation to several dipole positions. It should be noted that this study was performed for sine shaped textures, while for other texture shapes other combina­tions of dipole positions may be more suitable and need to be investigated separately. 3.4 Simulation improvements of outcoupling efficiency due to substrate corrugation So far only each individual dipole by position and ori­entation was evaluated, without commenting on the improvement of the outcoupling as a whole. From the presented results it can be observed that with increasing height of the texture outcoupling efficiency also increas­es and reaches a maximum for horizontally -1 oriented dipoles at the height of 150 nm and for horizontally - 2 oriented dipoles at 200 nm, whereas with even higher heights of the texture outcoupling starts to decrease. For vertically oriented dipoles, the outcoupling efficiency in­creases with increasing texture height and saturates at heights above 300 nm Thus, the optimal height depends on the actual orientation of the dipoles, with which the ratio between the individual contributions can be deter­mined, that will influence the final output. The actual ori­entation of the emitter material molecules on corrugat­ed substrates may also differ from that on flat substrates and must be determined and taken into account. The advantage of modelling, where outcoupling efficiency of light is calculated for each orientation separately, is the simple and straightforward possibility to recalcu­late the final outcoupling to the actual distribution of the dipole orientations without additional simulations by simply weighing each contribution. If we assume for this case that the general orientation of the dipoles does not change (a = 0.24) when deposited on corrugated substrates, the highest EQE ( ) for glass substrate (or for air by using a glass hemisphere) of 47.7% at a texture height of 250 nm can be found, which is more than 25% higher than for flat plane device with 37.6% EQE – see Figure 7(b), indicating a high potential of sine corrugated substrates for the outcoupling of light from the OLED thin film structure. Moreover, added is outcoupling efficiency as calculated by using only 3 di­pole locations (6, 8, 13), to show almost perfect match­ing with the simulation results for 15 locations used. In addition, the comparison of the Purcell factor between flat and textured structure (Figure 7(a)) displays only a minimal difference, indicating that texturing does not have a major impact on the microcavity in this case. It needs to be noted, that optimal texture height of h = 250 nm for P = 800 nm, was determined for a single wavelength at emission peak of 612 nm, while if wave­lengths over entire emission spectrum would be in­cluded in the optimization process, possibly different height would result in best outcoupling efficiency, thus further optimization would need to be employed. 4 Conclusions A modeling approach based on FEM was presented to research effects of dipole position and orientation on the outcoupling efficiency of red OLED devices with periodically corrugated substrates. High devia­tions from the averaged outcoupling efficiency for in­dividual positions and orientations of emitter dipoles were revealed, although it is shown that even with a smaller number (three) of carefully selected dipole po­sitions the outcoupling over the wide area of sinusoi­dal texture height with very reasonable accuracy can be predicted and the number of required simulations reduced by a factor of 5. For an optimal texture, out­coupling tendencies corresponding to texture inclina­tion are shown, with opposite effects for horizontally and vertically oriented dipoles. This shows how impor­tant it is to optimize the outcoupling solutions for each specific OLED design, especially for dipole orientation. Finally, a possible 25% improvement in EQE (improved outcoupling efficiency) is shown, over flat plane de­vices by using a sine textured substrate with a period of 800 nm and a height of 250 nm, with the possibility of additional improvements. Modeling and simulations show a high potential for further design and optimiza­tion of future outcoupling solutions. 5 Acknowledgments The author shows appreciation to M. Topic and J. Krc for their valuable suggestions, advices and support in writ­ing this paper. The author acknowledges the financial support from the Slovenian Research Agency (P2-0197 and J2-1727). 6 Conflict of interest Author declares no conflict of interest. 7 References 1. Y. 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Sever et al., “Combined model of non-confor­mal layer growth for accurate optical simulation of thin-film silicon solar cells,” Solar Energy Materi­als and Solar Cells, vol. 119, pp. 59–66, Dec. 2013, https://doi.org/10.1016/j.solmat.2013.05.016. Arrived: 11.11.2020 Accepted: 16.03.2021 M. Kovacic.; Informacije Midem, Vol. 51, No. 1(2021), 73 – 84 M. Kovacic.; Informacije Midem, Vol. 51, No. 1(2021), 73 – 84 M. Kovacic.; Informacije Midem, Vol. 51, No. 1(2021), 73 – 84 a) b) Figure 1: a.) Thin film stack of a standard red bottom emitting OLED on a corrugated glass substrate. b) Po­sition of dipoles on a corrugated substrate (red dots shown on 1/8th of the period area only)– snapshot from Comsol simulator M. Kovacic.; Informacije Midem, Vol. 51, No. 1(2021), 73 – 84 Figure 2: a.) Top view of dipole numbering on top of 1/8 of sine texture with weights factors in brackets. b-d.) Top view of sine textures, with marked dipole posi­tions (red dots shown on 1/8th of the period area only) and arrows showing dipole orientations as defined and used in simulations. The three analyzed situations with respect to dipole orientations are denoted with horizontally – 1 (b), horizontally – 2 (c) and vertically (d) oriented dipoles. M. Kovacic.; Informacije Midem, Vol. 51, No. 1(2021), 73 – 84 a) b) Figure 3: Comparison between two simulation mod­els of a flat plane OLED. Symbols and lines represent results obtained with the TMM method and the FEM model, respectively. a) Outcoupling efficiency (Light extraction to substrate), b) Purcell factor. M. Kovacic.; Informacije Midem, Vol. 51, No. 1(2021), 73 – 84 a) b) c) d) e) f) Figure 4: Outcoupling efficiency (to glass substrate) for each individual dipole according to its position on texture for different heights of the texture. a) Horizontally - 1 oriented dipoles, b) Horizontally - 2 oriented dipoles and c) Verti­cally oriented dipoles. d), e), f) - comparison between weighted average of all dipole positions taken into account and specifically selected ones. Added are maximum deviations for both higher and lower outcoupling efficiency. d) for horizontally - 1 oriented, e) horizontally - 2 oriented and f) vertically oriented dipoles. M. Kovacic.; Informacije Midem, Vol. 51, No. 1(2021), 73 – 84 Figure 6: Total relative deviation from weighted aver­age for each dipole and orientation. a) b) c) Figure 5: Outcoupling efficiency (color) for different dipole locations on top of a texture (P = 800, h = 250) for a) horizontally - 1, b) horizontally - 2 and c) vertically oriented dipoles. See Figure 2 for dipole orientation. M. Kovacic.; Informacije Midem, Vol. 51, No. 1(2021), 73 – 84 a) b) Figure 7: Comparison of simulation results for flat plane OLED and OLED on textured substrate with P = 800 and h = 250 nm. Anisotropy of a = 0.24 is consid­ered for both cases. Added are simulations results for only 3 dipole positions (6, 8, 13). a) Purcell factor – aver­aged over multiple positions; b) outcoupling efficiency and EQE to glass substrate (to air by using a glass hemi­sphere) M. Kovacic.; Informacije Midem, Vol. 51, No. 1(2021), 73 – 84 M. Kovacic.; Informacije Midem, Vol. 51, No. 1(2021), 73 – 84 M. Kovacic.; Informacije Midem, Vol. 51, No. 1(2021), 73 – 84 Copyright © 2021 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 1(2021), 85 – 94 https://doi.org/10.33180/InfMIDEM2021.106 Practical Floating Capacitance Multiplier Implementation with Commercially Available IC LT1228s Natchanai Roongmuanpha, Worapong Tangsrirat* School of Engineering, King Mongkut’s Institute of Technology Ladkrabang (KMITL), Bangkok, Thailand Abstract: A practical realization of a tunable floating capacitance multiplier using commercially available integrated circuits, namely LT1228 is proposed. The synthetic capacitor utilizes only two IC LT1228s along with two passive components (one resistor and one capacitor). The capacitance multiplication factor is electronically controllable through the transconductance gain of the LT1228. The effects of non-ideal transfer gains and parasitic elements of the LT1228 on the circuit performance have been evaluated in detail. The applicability of the proposed floating capacitance multiplier as a second-order band-pass filter is also presented. The claimed theory is verified by several PSPICE simulations and experimental test results. Keywords: capacitance multiplier; impedance simulation circuit; commercially available integrated circuit; electronically tunable Prakticna uporaba množilnika plavajoce kapacitivnosti s komercialnim IC LT1228s Izvlecek: Predstavljena je prakticna uporaba nastavljivega množilnika plavajoce kapacitivnosti z uporabo komercialnega integriranega vezja LT1228. Sinteticen kondenzator uporablja le dva IC LT1228 in dva pasivna elementa (upor in kondenzator). Faktor množenja je elektronsko nastavljiv s transkonduktancnim ojacenjem LT1228. Natancno so opredeljeni prenosi neidealnih ojacenj parazitnih elementov. Uporabnost množilnika je prikazana na pasovnem filtru drugega reda. Teorija je verificirana v PSPICE simulatorju in z eksperimentalnimi testi. Kljucne besede: kapacitetni množilnik; impedancno simulacijsko vezje; komercialno integrirano vezje; elektronska nastavljivost * Corresponding Author’s e-mail: drworapong@gmail.com 1 Introduction It is well known that the capacitance multiplier is a significant electronic block in the fabrication of high capacitance values in integrated circuit (IC) technol­ogy [1]-[2]. This is due to the large-value capacitors re­quiring a large silicon area on the IC chip. To overcome this limiting problem, the capacitance multiplier circuit which performs the multiplication of small capacitance values can be very useful [3]-[4]. Therefore, the design of capacitance multiplier circuits becomes an essen­tial research issue in the area of analog ICs. Over the years, there are various floating capacitance multiplier circuits reported by several researchers employing nu­merous versatile active elements [5]-[13]. However, careful observation of the topologies reported in these references reveals that they still suffer from one or more of the following restrictions: 1. They contain three or more active components [5]-[6], [10], [12], which enlarge the area on the chip, and relatively high power dissipation. 2. They need to employ more than two passive components [7], [9]-[10]. 3. They are unavailable in commercial IC form [6]-[9], [11]-[12], which cannot be practically imple­mented using already existing readily available ICs. 4. They lack the electronic adjustability for the ca­pacitance multiplying factor [7], [9]-[10]. The in­ternal tuning feature would be desirable for mod­ern mixed-signal systems. 5. They use different types of active components for their implementations [5], [12]-[13]. The attention aim of this work is, therefore, to design a floating and tunable capacitance multiplier using already existing commercially available ICs, namely LT1228 [14]. The LT1228 structure internally consists of an operational transconductance amplifier (OTA) and a current feedback operational amplifier (CFOA) in the same IC package. Thus, it may be noted that LT1228 has now become a popular commercial IC for design­ing several types of analog signal processing circuits and applications [15]-[20]. Two LT1228s and two passive components, i.e. one resistor and one capacitor, are em­ployed in this design. The capacitance scaling factor of the simulated circuit can be altered through the tunable transconductance gains of the LT1228s and/or the resis­tor in the circuit. A careful non-ideality analysis for the proposed capacitance multiplier circuit is investigated in detail. The second-order RLC band-pass filter imple­mented with the proposed tunable active capacitance simulator is given as an application. To verify the work­ability of the proposed circuit, it has been simulated in the PSPICE program using macro-model of IC LT1228, and also experimentally tested in a laboratory using commercially available IC namely LT1228s. 2 Circuit description 2.1 Commercially available IC LT1228 The LT1228 is a commercially available IC manufactured by Linear Technology Corporation [14]. The LT1228 in­ternal circuit, which has the properties of both the op­erational transconductance amplifier (OTA) and the cur­rent feedback operational amplifier (CFOA), is shown in Fig.1(a). The OTA provides an electronic gain control with a differential voltage-to-current converter, whose transconductance gain (gm) depends on an external bias current, while the CFOA is implemented to drive load low-impedance loads with excellent linearity at high fre­quencies. The circuit representation block of the LT1228 and its equivalent circuit are given in Fig.1(b) and 1(c), re­spectively. In ideal operation, the function of the LT1228 can be described by the following matrix relation: (1) In equation (1), ROL is the transresistance gain of the LT1228, which is ideally considered to be infinite. The gm-parameter of this IC can be adaptable electronically with the help of the external bias current IB and the ex­pression is given by: (2) Figure 1: Commercially available IC LT1228: (a) pack­age information; (b) electrical symbol; (c) equivalent circuit 2.2 Proposed floating capacitance multiplier design The schematic diagram of the proposed floating ca­pacitance multiplier circuit is given in Fig.2(a). It is com­posed of only two LT1228s, one resistor, and one capac­itor. The equivalent circuit for the proposed capacitor implementation of Fig.2(a) is shown in Fig.2(b). Assum­ing that the matching condition of gm = gm1 = gm2 is sat­isfied, routing circuit analysis shows that the equivalent input impedance looking between ports v1 and v2 of the proposed circuit in Fig.2(a) can be obtained as: (3) It is obvious that the proposed circuit of Fig.2(a) im­plements a floating tunable lossless capacitance with equivalent capacitance being given by: (4) where K = gmR1 represents the capacitance multiplica­tion factor. The relation in (4) reveals that the capaci­tance magnification with a large multiplication factor is easily feasible by appropriate choosing gm and/or R1. Also from equation (2), the electronic tuning capabil­ity of the proposed design is evident through the bias currents of the LT1228s. It should be further noted here that two transconductance gains for this implementa­tion need to be equal. This can be done easily by using simple current mirror to supply equal external bias cur­rents to the two LT1228s. (a) (b) Figure 2: Proposed floating capacitance multiplier im­plementation: (a) circuit diagram; (b) ideal equivalent impedance 2.3 Non-ideality performance analysis Consider the non-ideal transfer gains of the LT1228, the characteristic of the LT1228 given in equation (1) can be re-described by the following matrix equation: (5) In above equation, a = (1 – egm) and ß = (1 – ev), where |egm | << 1 and |ev | << 1 are the transconductance track­ing error and the voltage transfer error, respectively. Therefore, an analysis of the simulator given Fig.2(a) with the consideration of these parasitic gains gives the following expression for the equivalent input im­pedance looking into port 1 and ground as: (6) It is obvious that the parasitic gains a1 and ß1 directly deviate the value of the working capacitance C1. To compensate for this, it can be governed by tuning the appropriate value for the gm1R1 product. On the other hand, the non-ideal equivalent impedance looking into port 2 and ground can be approximately found as: (7) From equation (7), due to the LT1228 non-ideal gains, there is an extra undesired parallel resistance (R'ex) ap­pearing in parallel with the non-ideal equivalent ca­pacitance. The non-ideal equivalent circuit for this case can then be represented as in Fig.3, where C'eq2 = (R1C1ß2)(gm2a2) and R'ex = 1/(ß2-1)(gm2a2). Since a typical value of R'ex is of the order of hundreds of k., the para­sitic elements C'eq2 and R'ex introduce an extra pole at low frequency, which restricts the operating frequency range of the circuit. This effect on the frequency re­sponse of Z'eq2 will be shown in the following section. Figure 3: Non-ideal equivalent input impedance Z'eq2. In practice, if the parasitic impedances at the corre­sponding LT1228 terminals are taken into account, then the practical circuit model of the LT1228 can be drawn in Fig.4. At terminals p, n and z, there are the parasitic resistances Rp, Rn, and Rz appearing respectively in par­allel with the parasitic capacitances Cp, Cn, and Cz. Their impedance values are theoretically equal to infinity. On the other hand, the parasitic resistance Rx appears in se­ries at terminal x. By considering v2 = 0, the impedance of the designed capacitor with the consideration of the parasitic element effects can be given by: (8) where ROLi , Rxi , Rzi, and Czi (i = 1, 2) are the parasitic ele­ments ROL, Rx, Rz, and Cz of the i-th LT1228, respectively. For practical realization, ROL1 and Rz1 are typically very large, yielding ROL1 >> Rx1 and Rz1 >> 1. Therefore, an equivalent capacitance C"eq1 . (gm1R1C1 - Cz1) is obtained from equation (8). It is further mentioned that there is not any additional parasitic pole and zero due to the parasitic elements, and the operating frequency limita­tion can be expressed as: f = min [1/2p(gm1R1C1 – Cz1)]. Figure 4: Practical LT1228 model with parasitic ele­ments. By defining v1 = 0 and conducting relevant analyses, we can obtain the following expression for the non-ideal impedance seen between terminal 2 and ground as: (9) ) where R"2 = Rn1//Rp2//Rz2 and C"2 = Cn1+Cp2+Cz2. In equa­tion (9), the negative terms exhibit non-ideal behavior of the proposed capacitance simulator by introducing a parallel resistive effect. Since ROL2 >> Rx2 and R"2 >> 1, then equation (9) reduces to (10) The consideration of the above effect implies that in the frequency range of f = min [1/2p(gm2R1C1 - C"2)], and the inequality gm2R1C1 << C"2, the simulator operates practically as an expected ideal capacitance multiplier. 3 Computer simulation validation To verify our proposed design, the circuit in Fig.2(a) has been simulated in PSPICE program using the macro-model parameters for the LT1228 provided by Linear Technology Corporation [14], with DC supply voltages of ±5 V. In simulations, the component values are taken as: R1 = 1 k., C1 = 50 pF and IB = IB1 = IB2 = 200 µA. From equation (2), the transconductance gains are calculat­ed as: gm = gm1 = gm2 = 2 mA/V. Also, from the relation in (4), the capacitance multiplication factor, and the simulated equivalent capacitance are calculated as: K = 2 and Ceq = 0.1 nF, respectively. The simulation results for input signals vid and iin of the proposed capacitance multiplier are given in Fig.5, when a 1-MHz sinusoidal signal of an amplitude 50 mV (peak) was applied as an input signal. The phase difference between vid and iin was observed to be 86.77° leading, as against the theoretical value of 90°. The corresponding frequency responses are also given in Fig.6. The total power con­sumption is measured to be 0.12 W when v1 and v2 are kept grounded. Figure 5: Simulation results for vid and iin of the pro­posed floating capacitance multiplier circuit in Fig.2(a). In order to evaluate the impact of the unwanted para­sitic resistance R'ex the frequency responses of the non-ideal equivalent impedance Z'eq2 (Z'eq2 = v2/i2) when v1 =0 are depicted in Fig.7. It is observed that, at low fre­quency range between 1 kHz and 20 kHz, R'ex mainly causes drop of the magnitude response of the Z'eq2 and also some deviates in phase response as depicted. However, some circuit techniques which reduce the parasitic impedance effects can be applied in the pro­posed capacitance multiplier circuit to improve the fre­quency performance [21]-[23]. Figure 6: Expected and simulated frequency responses of the proposed floating capacitance multiplier circuit in Fig.2(a). Figure 7: Frequency responses of the non-ideal equiv­alent input impedance Z'eq2 in Fig.3. The adjustability of the proposed capacitance multi­plier circuit is assessed by tuning the capacitance mul­tiplication factor (K = gmR1), and also shown in Fig.8. Variations of Ceq against gm and R1 are demonstrated as examples. The Ceq tuning with gm (varied from 0.1 mA/V to 10 mA/V) while keeping R1 constant at 20 k. is shown in Fig.8(a), whereas the results in Fig.8(b) are obtained by setting gm fixed at 10 mA/V and varying R1 from 0.5 k. to 20 k.. It is evident from the results that the simulated capacitance value Ceq can enhance up to approximately 200 times with the maximum error in all cases less than 10%. Fig.9 shows the temperature analysis results of the pro­posed capacitance multiplier circuit in Fig.2(a), where the ambient temperature is changed from 0°C to 100°C in the step of 20°C. From Fig.9, the simulation results demonstrate that the magnitude response has deviat­ed with a variation of -8% ~ +22% over the temperature range of 0°C to 100°C. (a) (b) Figure 8: Variation of Ceq with the multiplication factor (K = gmR1): (a) gm = 0.1 mA/V to 10 mA/V (IB = 10 µA to 1000 µA) and R1 = 20 k.; (b) gm = 10 mA/V (IB = 1000 µA) and R1 = 0.5 k. to 20 k. Figure 9: Temperature analysis results of the proposed floating capacitance multiplier circuit in Fig.2(a). 4 Experimental Evaluation In the experimental evaluation, the availability of the proposed floating capacitance multiplier circuit in Fig.2(a) has been verified in the laboratory using off-shelf IC’s LT1228 [14] under ±5V supply voltages. All experimental measurements were performed through Keysight EDU-X 1002G oscilloscope and HP4395A im­pedance analyzer. To perform the experimental test, the components used have been: gm = 2 mA/V (IB = 200 µA), R1 = 1 k., and C1 = 50 pF, yielding Ceq = 0.1 nF. Fig.10 shows the measured input waveforms vid and iin of the proposed circuit in Fig.2(a), when the input sig­nal is 100 mV peak-to-peak at 1 MHz. The phase shift between vid and iin obtained from this experiment is measured as 86.8°. The corresponding frequency re­sponses of the equivalent input impedance Zeq are also represented in Fig.11. It appears from Figs.10 and 11 that the proposed circuit behaves as a lossless capaci­tor as expected. Figure 10: Measured time-domain behavior of the pro­posed floating capacitance multiplier circuit in Fig.2(a). So as to survey the electronic tunability of the capaci­tance multiplier circuit, the measured magnitude and phase responses with three different values of gm (i.e. gm = 0.5 mA/V, 3 mA/V, and 5 mA/V) are shown in Fig.12. These results were obtained by taking R1 = 1 k. and C1 = 50 pF. This tuning process leads to obtain K = 0.5, 3 and 5 (Ceq = 25 pF, 0.15 nF, and 0.25 nF), respectively. On the other hand, the magnitude-frequency respons­es of Zeq for different values of R1 are depicted in Fig.13. In Fig.13, setting gm = 1 mA/V and C1 = 50 pF, and differ­ent values for R1 as 5 k., 10 k. and 20 k., results in the theoretical equivalent capacitances of Ceq = 0.25 nF, 0.5 nF, and 1 nF, respectively. 5 Illustrative application In this section, illustrative applicability of the proposed floating capacitance multiplier given in Fig.2(a) has been considered. It may be utilized in the implementa­tion of the second-order RLC voltage-mode band-pass (BP) filter as shown in Fig.14. The transfer function of the filter can be given by: (11) The center frequency (.c) and the quality factor (Q) are respectively expressed below: (12) and (13) As an example for the circuit simulation, the following passive and active components were chosen as: RBP = 3.3 k., LBP = 1 mH, and Ceq = 0.1 nF (gm = 2 mA/V, R1 = 1 k., and C1 = 50 pF). The ideal and simulated frequency responses of the filter in Fig.14 are exhibited in Fig.15, in which the calculated and simulated values of fc are found to be 503 kHz and 509 kHz, respectively. The simulated frequency characteristics are in good agree­ment with the predicted responses, thereby confirm­ing the practical utility of the proposed capacitance multiplier circuit. The corresponding frequency spec­trum of the output voltage (vout) of the BP filter is also recorded in Fig.16, where the total harmonic distortion (THD) values observed is well within 1.17%. Figure 14: Second-order RLC voltage-mode BP filter implemented with Ceq from Fig.2(a). Figure 15: Expected and simulated frequency charac­teristics of the BP filter in Fig.14. Figure 16: Output frequency spectrum of vout. Finally, in order to inspect random deviations of the BP filter center frequency due to the process and mis­match variations, Monte-Carlo analysis simulation has been evaluated with the same given parameters that resulted in the frequency characteristic of Fig.15. The simulations were performed 200 times with a 5% Gaussian deviation of relevant gm, R1, and C1. The his­togram of the center frequency is shown in Fig.17. Ac­cording to statistical analysis results, the mean value is at 522 kHz with a standard deviation of 9.4 kHz, cor­responding to 1.8% deviation from the nominal value. 6 Conclusive Discussion This work is an attempt to present a practical realiza­tion of the tunable floating capacitance multiplier cir­cuit using a commercially available IC LT1228. The syn­thetic capacitance simulator is constructed with two LT1228s, one resistor, and one capacitor. The electronic tuning feature of the simulated floating capacitor can be achieved by means of external bias currents of the IC LT1228s. The communication further discusses a second-order RLC voltage-mode band-pass filter to validate the applicability of the proposed capacitor simulation. PSPICE simulation and experimental re­sults of the commercially available IC LT1228 are also included to demonstrate the convincing characteristics of the proposed circuit and its practical significance. Figure 17: Monte-Carlo analysis results showing the deviation in the standard deviations of the BP filter center frequency. 7 Acknowledgment This work was supported by King Mongkut’s Institute of Technology Ladkrabang. 8 Conflict of interest The authors confirm that this article content has no conflict of interest. 9 References 1. S. Pennisi, “CMOS multiplier for grounded capa­citors”, Electron. Lett., vol.38, no.15, pp.765-766, 2002 https://doi.org/10.1049/el:20020517 2. M. A. Al-Absi, E. S. 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Lett., vol.30, no.5, pp.377-378, Mar.1994. https://doi.org/10.1049/el:19940302 22. F. Sequin and A. Fabre, “New second-generation current conveyor with reduced parasitic resist­ance and bandpass filter application”, IEEE Trans.Circuits Syst.I: Fundam. Theory Appl., vol.48, no.6, pp.781-785, Jun.2001. https://doi.org/10.1109/81.928161 23. G. Feeri, N. C. Guerrini, and M. Diqual, “CCII-based floating inductance simulator with compensated series resistance”, Electron. Lett., vol.39, no.22, pp.1560-1562, Oct.2003. https://doi.org/10.1049/el:20031046 Arrived: 27. 02. 2021 Accepted: 01 .04. 2021 N. Roongmuanpha et al.; Informacije Midem, Vol. 51, No. 1(2021), 85 – 94 (a) (b) (c) N. Roongmuanpha et al.; Informacije Midem, Vol. 51, No. 1(2021), 85 – 94 N. Roongmuanpha et al.; Informacije Midem, Vol. 51, No. 1(2021), 85 – 94 N. Roongmuanpha et al.; Informacije Midem, Vol. 51, No. 1(2021), 85 – 94 N. Roongmuanpha et al.; Informacije Midem, Vol. 51, No. 1(2021), 85 – 94 (a) (b) Figure 11: Measured frequency behavior of the pro­posed floating capacitance multiplier circuit in Fig.2(a). (a) magnitude behavior (|Zeq|); (b) phase behavior (.Zeq) N. Roongmuanpha et al.; Informacije Midem, Vol. 51, No. 1(2021), 85 – 94 Magnitude response Phase response (a) Magnitude response Phase response (b) Magnitude response Phase response (c) Figure 12: Measured frequency responses of Zeq for different gm.(a) gm = 0.5 mA/V (K = 0.5, Ceq = 25 pF); (b) gm = 3 mA/V (K = 3, Ceq = 0.15 nF); (c) gm = 5 mA/V (K = 5, Ceq = 0.25 nF) N. Roongmuanpha et al.; Informacije Midem, Vol. 51, No. 1(2021), 85 – 94 (a) (b) (c) Figure 13: Measured magnitude-frequency responses of Zeq for different R1(a) R1 = 5 k. (K = 5, Ceq = 0.25 nF); (b) R1 = 10 k. (K = 10, Ceq = 0.5 nF); (c) R1 = 20 k. (K = 20, Ceq = 1 nF) N. Roongmuanpha et al.; Informacije Midem, Vol. 51, No. 1(2021), 85 – 94 N. Roongmuanpha et al.; Informacije Midem, Vol. 51, No. 1(2021), 85 – 94 Copyright © 2021 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Boards of MIDEM Society | Organi društva MIDEM MIDEM Executive Board | Izvršilni odbor MIDEM President of the MIDEM Society | Predsednik društva MIDEM Prof. Dr. Barbara Malic, Jožef Stefan Institute, Ljubljana, Slovenia Vice-presidents | Podpredsednika Prof. Dr. Janez Krc, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Dr. Iztok Šorli, Mikroiks d.o.o., Ljubljana, Slovenia Secretary | Tajnik Olga Zakrajšek, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia MIDEM Executive Board Members | Clani izvršilnega odbora MIDEM Prof. Dr. Slavko Bernik, Jožef Stefan Institute, Slovenia Izr. Prof. Dr. Miha Cekada, Jožef Stefan Institute, Ljubljana, Slovenia Prof. DDr. Denis Ðonlagic, UM, Faculty of Electrical Engineering and Computer Science, Maribor, Slovenia Prof. Dr. Leszek J. Golonka, Technical University, Wroclaw, Poljska Prof. Dr. Vera Gradišnik, Tehnicki fakultet Sveucilišta u Rijeci, Rijeka, Croatia Mag. Leopold Knez, Iskra TELA, d.d., Ljubljana, Slovenia Mag. Mitja Koprivšek, ETI Elektroelementi, Izlake, Slovenia Doc. Dr. Gregor Primc, Jožef Stefan Institute, Ljubljana, Slovenia Prof. Dr. Janez Trontelj, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Doc. Dr. Hana Uršic Nemevšek, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Danilo Vrtacnik, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Supervisory Board | Nadzorni odbor Prof. Dr. Franc Smole, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Prof. Dr. Drago Strle, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Igor Pompe, retired Court of honour | Castno razsodišce Darko Belavic, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Miloš Komac, retired Dr. Hana Uršic Nemevšek, Jožef Stefan Institute, Ljubljana, Slovenia Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials ISSN 0352-9045 Publisher / Založnik: MIDEM Society / Društvo MIDEM Society for Microelectronics, Electronic Components and Materials, Ljubljana, Slovenia Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale, Ljubljana, Slovenija www.midem-drustvo.si