Elektrotehniski vestnik 78(5): 298-303, 2011 English edition Mobility Modeling in a p-MOSFET under Uniaxial Stress Amit Chaudhry, Sonu Sangwan and Jatindra Nath Roy University Institute of Engineering and Technology, Panjab University, Chandigarh, India E-mail: amit_chaudhry01 @yahoo.com Abstract. A semi analytical model describing the bulk mobility for holes in strained-p-Si layers as a function of applied uniaxial strain applied at the gate has been developed in this paper. The uniaxial tensile stress has been applied externally through the silicon nitride cap layer. The effects of uniaxial stress are understood on all the three components of mobility i.e. phonon, columbic and surface roughness mobility. The results show that the hole mobility is a strong rising function of applied uniaxial strain. Flatband voltage, Depletion Charge density, Inversion charge density, Energy gap and Effective surface electric field have been analytically modeled. There is a sharp increase in the vertical electric field and inversion charge density and decrease in the energy gap, depletion charge density and the flatband voltage when the uniaxial stress is applied. The hole mobility results have also been compared with the experimentally reported results and show good agreement. The results have also been compared with the electron mobility under the same conditions. Keywords: mobility, strained-si, model, experimental. 1 Introduction CMOS technology has contributed significantly to the microelectronics industry thus playing an important role in the overall development of all the countries. The performance and density of a CMOS chip can be improved through device scaling which is inevitable as also propounded by Moore law which says that the transistor density on a CMOS chip doubles approximately after every one and a half years [1]. Continuing with the Moore law, the gate length of the MOSFET will eventually shrink to 10 nm in 2015 [2]. Seeing the trend of down scaling, continuous improvements in the VLSI MOSFET device models are required so that the exact behavior of deep sub-micron and nanometer scaled MOSFETs can be described with accuracy. The reduction in carrier mobility is a major cause of drain current degradation. But as we scale down the MOSFET, carrier mobility decreases due to the high vertical electric fields in the substrate. This reduces the speed of the device. To control these effects, strained silicon technology has evolved in the past few years as a replacement to silicon in substrate. on of extremely scaled down devices. The scaling down of both p-MOSFETs and n-MOSFETs has been taking place for their use in Complementary Metal Oxide Semiconductor (CMOS) technology. Very less attention has been given to the modeling process of p-MOSFET mainly because of the complex band structure of the valence band. Due to this reason, the hole inversion layers have not been studied and that too under uniaxial strain analytically. Various models/experiments have been developed in the past several years for the mobility estimation of the stressed silicon p-MOSFETs. Shifren et al [3] have experimentally and numerically shown the increase in the hole mobility on (100) oriented wafers. Uchida et al [4] have numerically evaluated the hole mobility in PMOS structures using k.p technique. Shuo et al [5] have experimentally found the hole mobility using uniaxial additive stress. Gaubert et al [6] have computed the hole mobility on (110) fabricated oriented wafers. It would be appropriate to say here that there is a strong requirement of an analytical model which is simple and can be easily embedded into SPICE and largely accurate. An attempt has been made in this paper to semi analytically model the hole mobility under the condition of applied uniaxial strain at the gate. 2 Strain Effect on Mobility The deposition of a silicon nitride cap layer over the metal gate produces a uniaxial tensile strain. This is shown in Fig. 1. The strain is a very useful parameter in devices as carrier mobility significantly increases due to the altering of the silicon band structure. The alteration of band structure in the channel layer provides lower Figure 1.Cross-sectional view of uniaxial stressed-bulk-Si MOSFET. effective mass and also suppresses intervalley scattering which is a prime cause of enhancement of carrier mobility and the drive current. Due to strain the valence bands split up into three sub bands. These are heavy hole, light hole and spin orbit hole sub bands as shown in Fig. 2. Figure 2. Energy band splitting due to uniaxial strain in silicon valence bands. Due to strain, the effective mass of holes in the direction of flow of charge decreases and hence the mobility increases. Mathematically, carrier mobility is ji= q x/m* (1) Figure 3. Percentage decrease in energy bandgap ((Egs-Eg)/Eg)xl00 with the applied strain (%) for uniaxial strained silicon MOSFETs at room temperature. 3 Modeling of Hole Mobility Hole mobility is a very important parameter in the overall MOSFET modeling process. This is because parameters like drain current and hence trans-conductance strongly depend on mobility. There are three major scattering mechanisms that affect a MOSFET's inversion layer carrier mobility given below. 3.1 Phonon scattering due to lattice vibrations Phonon scattering is due to the lattice vibrations. The scattering rate is taken from [7]. The main problem is the calculation of the electric field at the oxide/silicon interface. Some of the parameters have been empirically modified to take the effect of uniaxial strain in the mobility calculations. The modified phonon scattering mobility is taken by modifying a to a(e) and P to P (e) by introducing the applied strain dependence: 1/x = scattering rate, m* = Effective hole mass. The mobility is directly related to the carrier velocity v and applied external electric field E as shown by: v = ¡j K (2) It can be seen that increasing the carrier mobility increases the velocity, which is directly proportional to the switching speed of the device and the drain current. The bandgap of the silicon material falls as the uniaxial strain is applied as shown in Fig. 3. VVh = I^Phßß(e) 1 + sa 0.2 a(e) (3) IxphB — 500 cm2/Vs E0 = 3x 104 V/cm a(e) = 1 + 1.28 xe- 0.16 x e2 /?0) = 1 + 1.02 xe-O.Sxe2 EeffS is effective vertical electric field from the substrate to the oxide and "e" is the applied perpendicular tensile uniaxial strain. 3.2 Surface roughness scattering due to the microscopic roughness of the Si-Si02 interface The microscopic roughness at the surface of oxide/silicon interface causes a decrease in hole mobility due to scattering from the surface too. Moreover, the electric fields increasing due to the massive downscaling of the technology tend to pull the holes towards the interface further. The modified empirical formula for the surface roughness is obtained from [7] is given by modifying the 5 parameter to 5(e) by introducing the strain dependence. The strain dependence has been done to accurately match the experimental results in the presence of uniaxial stress. M-.s?* (S(e)lO1 »effs (4) ô(e) = ô0 + 3e - 1.2e2 50 = 1.6 rise in vertical electric field is attributed to the fact that the more number of charge carriers will be available at a given electric field as compared to the conventional MOSFETs. Figure 4. Percentage increase in surface electric field with applied strain at room temperature with a gate to source voltage of -3V. 3.3 Coulomb scattering due to impurity scattering 4.1 Depletion Charge Density The coulomb mobility from [5] as: (5) C = 70 x 10"7 Ns = Qinv/q, Nsis electron density. Na is doping concentration (cm-3) The total mobility of the electrons is calculated as follows from the mathiessen's rule: HTotal 1~ |4ph 1 + |4sr 1 + |4c 1 (6) 4 Effective Surface Electric Field First parameter in solving equations (3)-(5) is the surface electric field. The total charge density in the substrate (due to both inversion region and depletion region) is given by the Gauss law, and hence the surface electric field is found as: Eeffs — Ol X Qinv + Qdep)/£0 (7) r| = 1/3= correction in inversion charge density in (100) surface. Qinv is the inversion charge density, Qdepi is the depletion charge density, ssi is the relative permittivity of silicon substrate and s0 is the air permittivity. The below given Fig. 4 explains the dependence of the percentage rise in effective electric field with the applied strain at -3V gate voltage. The The depletion charge density is given by solving Poisson Equation in the substrate in depletion region. Qdep = ~V2£o £siqNa(f)s (8) The below given Fig. 5 explains the dependence of the percentage fall in depletion charge density with applied uniaxial strain. This shows that the inversion layer will form at a lower gate voltage, thus reducing the overall threshold voltage of the MOSFET. Figure 5 Percentage decrease in depletion charge with applied strain at room temperature for uniaxial strain silicon MOSFETs. 4.2 Inversion Charge Density The inversion charge density is given by Qinv = Cox(-Vgs + Vths) (9) The below given Fig. 6 explains the dependence of the percentage rise in inversion charge density with applied uniaxial strain. This is due to the large decrease in the energy gap due to the applied strain, which forms the inversion layer fast. Figure 6. Percentage increase in inversion charge with applied strain at room temperature with a gate voltage of -3V. Vthsis a uniaxial strained threshold voltage given by Qdep Vths = v, -A, _ fbs Vss r (10) The flatband voltage Vfbs is given by Vfbs = {4>m ~ fa +ae3+Tq- 0/s)} " (Qo/Cox) (11) Xsis the electron affinity at the silicon substrate side and is increased due to decrease in energy gap, 0ss = 2