ISSN 0352-9045 Journal of Microelectronics, Electronic Components and Materials Vol. 52, No. 2(2022), June 2022 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 52, številka 2(2022), Junij 2022 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 2-2022 Journal of Microelectronics, Electronic Components and Materials VOLUME 52, NO. 2(182), LJUBLJANA, JUNE 2022 | LETNIK 52, NO. 2(182), LJUBLJANA, JUNIJ 2022 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2022. All rights reserved. | Revija izhaja trimesečno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale – Društvo MIDEM. Copyright © 2022. Vse pravice pridržane. Editor in Chief | Glavni in odgovorni urednik Marko Topič, University of Ljubljana (UL), Faculty of Electrical Engineering, Slovenia Editor of Electronic Edition | Urednik elektronske izdaje Kristijan Brecl, UL, Faculty of Electrical Engineering, Slovenia Associate Editors | Odgovorni področni uredniki Vanja Ambrožič, UL, Faculty of Electrical Engineering, Slovenia Arpad Bürmen, UL, Faculty of Electrical Engineering, Slovenia Danjela Kuščer Hrovatin, Jožef Stefan Institute, Slovenia Matija Pirc, UL, Faculty of Electrical Engineering, Slovenia Franc Smole, UL, Faculty of Electrical Engineering, Slovenia Matjaž Vidmar, UL, Faculty of Electrical Engineering, Slovenia Editorial Board | Uredniški odbor Mohamed Akil, ESIEE PARIS, France Giuseppe Buja, University of Padova, Italy Gian-Franco Dalla Betta, University of Trento, Italy Martyn Fice, University College London, United Kingdom Ciprian Iliescu, Institute of Bioengineering and Nanotechnology, A*STAR, Singapore Marc Lethiecq, University of Tours, France Teresa Orlowska-Kowalska, Wroclaw University of Technology, Poland Luca Palmieri, University of Padova, Italy Goran Stojanović, University of Novi Sad, Serbia International Advisory Board | Časopisni svet Janez Trontelj, UL, Faculty of Electrical Engineering, Slovenia - Chairman Cor Claeys, IMEC, Leuven, Belgium Denis Đonlagić, University of Maribor, Faculty of Elec. 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Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madić Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana 68 Journal of Microelectronics, Electronic Components and Materials vol. 52, No. 2(2022) Content | Vsebina Original scientific papers Izvirni znanstveni članki G. N. Pandurengan, V. Krishnasamy, J. S. M. Ali, D. Almakhles: Five-Level Transformerless Common Ground Type Inverter with Reduced Device Count 71 G. N. Pandurengan, V. Krishnasamy, J. S. M. Ali, D. Almakhles: Petstopenjski pretvornik brez transformatorja s skupno ozemljitvijo in manjšim številom naprav Y. Wang, X. Su, X. Jin, H. Yang, Z. Zhou: Design, Fabrication and Measurement of LDNMOSSCR Devices with Appropriate ESD Protection Window for 18V HV CDMOS Process 83 Y. Wang, X. Su, X. Jin, H. Yang, Z. Zhou: Načrtovanje, izdelava in merjenje naprav LDNMOSSCR z ustreznim zaščitnim oknom ESD za 18V HV proces CDMOSI K. Arunachalam, M. Perumalsamy: Programmable implementation of timearea-efficient Elliptic Curve Cryptography for entity authentication 89 K. Arunachalam, M. Perumalsamy: Programirljivo izvajanje časovno učinkovite kriptografije eliptičnih krivulj za avtentikacijo entitet R. Mishra, G. R. Mishra, S. O. Mishra , M. Faseehuddin: Electronically Tunable Mixed Mode Universal Filter Employing Grounded Passive Components 105 R. Mishra, G. R. Mishra, S. O. Mishra , M. Faseehuddin: Elektronsko nastavljiv univerzalni filter mešanega načina z ozemljenimi pasivnimi komponentami Ž. Šmelcer, A. Sešek: A Low Distortion Audio Amplifier 117 Ž. Šmelcer, A. Sešek: Avdio ojačevalnik z nizkim popačenjem J. Balent, F. Smole, M. Topič, J. Krč: Analysis of effects of dangling-bond defects in doped a-Si:H layers in heterojunction silicon solar cells with different electron affinities of ITO contacts 129 J. Balent, F. Smole, M. Topič, J. Krč: Numerična analiza učinkov defektov bingljajočih vezi v dopiranih plasteh iz a-Si:H v heterospojnih silicijevih sončnih celicah s kontakti ITO z različnimi elektronskimi afinitetami Announcement and Call for Papers: 57th International Conference on Microelectronics, Devices and Materials With the Workshop on Energy Harvesting: Materials and Applications 143 Napoved in vabilo k udeležbi: 57. mednarodna konferenca o mikroelektroniki, napravah in materialih z delavnico o zbiranju energije: materiali in uporaba Front page: Physical realization of a low distortion audio amplifter (Ž. Šmelcer et al.) Naslovnica: Fizična izvedba avdio ojačevalnika z nizkim popačenjem (Ž. Šmelcer et al.) 69 70 Original scientific paper https://doi.org/10.33180/InfMIDEM2022.201 Journal of Microelectronics, Electronic Components and Materials Vol. 52, No. 2(2022), 71 – 82 Five-Level Transformerless Common Ground Type Inverter with Reduced Device Count Gopinath Narayanan Pandurengan1, Vijayakumar Krishnasamy1, Jagabar Sathik Mohamed Ali2, Dhafer Almakhles2 Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology University, Kattankulathur, Tamil Nadu, India 2 Energy Lab, College of Engineering, Prince Sultan University, Riyadh, Saudi Arabia 1 Abstract: In recent days, the transformerless grid-connected PV inverter is paid more attention due to its compactness and high efficiency with low cost. This paper presents a new five-level transformerless switched capacitor type inverter with a reduced number of power components. The proposed topology has a lower number of power components with a common ground connection between the negative terminal of the input side and load that eliminates the leakage current. The switched capacitors do not require any sensors for their balancing. The different modes of operation and control of the PWM technique are discussed. The proposed topology is compared with recent transformerless inverters, and the advantages of the proposed topology are highlighted. The simulation and experimental results are presented. The prototype hardware setup is built for 1.2 kW and has the simulated maximum efficiency of 96.4%. The performance of the proposed topology is measured by applying various load and modulation index variations. Keywords: Common ground; Leakage current; Multilevel inverter; Transformerless inverter; Switched capacitor Petstopenjski pretvornik brez transformatorja s skupno ozemljitvijo in manjšim številom naprav Izvleček: V zadnjih dneh se zaradi kompaktnosti in visoke učinkovitosti ob nizkih stroških več pozornosti namenja breztransformatorskim PV pretvornikom, ki so priključeni na omrežje. V tem članku je predstavljen nov petstopenjski breztransformatorski razsmernik s stikalnim kondenzatorjem z zmanjšanim številom močnostnih komponent. Predlagana topologija ima manjše število močnostnih komponent s skupno ozemljitveno povezavo med negativno sponko vhodne strani in bremenom, ki odpravlja uhajalni tok. Preklopni kondenzatorji ne potrebujejo senzorjev za uravnoteženje. Obravnavani so različni načini delovanja in krmilne tehnike PWM. Predlagana topologija je primerjana z novejšimi breztransformatorskimi pretvorniki, poudarjene pa so tudi prednosti predlagane topologije. Predstavljeni so simulacijski in eksperimentalni rezultati. Prototipna strojna oprema je izdelana za 1,2 kW in ima simulirano največjo učinkovitost 96,4 %. Učinkovitost predlagane topologije je izmerjena z različnimi spremembami obremenitve in modulacijskega indeksa. Ključne besede: skupna zemlja; uhajalni tok; večnivojski razsmernik; breztransformatorski razsmernik; preklopni kondenzator * Corresponding Author’s e-mail: mjsathik@ieee.org 1 Introduction makes the photovoltaic system a more attractive and promising renewable energy source. Such a photovoltaic system with grid integration can be done generally through galvanic isolation, which is transformer-based and non-galvanic isolation which is a transformerless The PV system is a more promising renewable energy source because of no greenhouse gases, pollution-free, clean, return on investment, and emission-free. Various advantages like reliability, the noiseless operation How to cite: G N.. Pandurengan et al., “Five-Level Transformerless Common Ground Type Inverter with Reduced Device Count", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 52, No. 2(2022), pp. 71–82 71 G N.. Pandurengan et al.; Informacije Midem, Vol. 52, No. 2(2022), 71 – 82 based method [1]. The high-frequency transformer on the DC side and line transformers on the AC side ensures safer operation in the existing system. But the use of transformer leads to decrease in efficiency, more weight, high cost and power losses, need regular maintenance and bulky size. To overcome the drawbacks of transformer-based galvanic isolation, transformerless inverter topologies are developed. The transformerless inverters offer high efficiency, compactness, and low leakage current. However, the power quality concern, output voltage distortion and safety due to the leakage current, isolation capabilities are the main predicament in grid-connected transformerless inverter-based PV systems. Many types of transformerless inverters have been developed to reduce the leakage current [2]. The MLI inverter proposed in [3] has the ability of self-voltage balancing and boosting for the grid-connected renewable energy system. The source of leakage current is a common-mode voltage which can be minimized by proper selection of switching sequence. Parasitic capacitance i.e., stray capacitance is usually appearing between photovoltaic panels negative terminal and neutral side of the grid. In a non-galvanic i.e., transformerless inverters a direct ground current path is developed between the PV and grid grounds. The variable high-frequency common mode voltage (CMV) of the inverter where it can be clamped between the null of ac grid and the parasitic capacitor of the PV arrays negative terminal excites the resonant circuit formed by parasitic capacitor and inverter filer inductor, which produces leakage current. By connecting negative terminal of PV side and neutral of grid side, the CMV will be cancelled out since the parasitic capacitance is clamped to ground potential. Hence, the leakage current can be eliminated [5]. The CMV can be maintained constantly through PWM controlling techniques, decoupling the photovoltaic and grid to reduce the leakage current. There are some methods to mitigate the leakage current. plete elimination of leakage current is not achieved by decoupling methods due to its dc bus utilization limit. A switched-capacitor inverter with a common ground type is presented in [11]. The switched capacitor acts as a virtual dc-link, and this is charging in the positive half cycle and discharging at the negative half cycle. A simple peak current controller controls the output current. A common ground type topology with flying capacitor leg plus a half-bridge cell is presented in [12], gives superior performance in terms of harmonic distortion, thus allowing filter reduction. The multilevel transformerless half-bridge topology is presented in [13]. This topology can inject reactive power into the grid, thereby making it low voltage ride-through capability LVRT. A virtual dc bus concept with feedforward space vector modulation technique is presented in [14]. The modulation strategy decouples the output variables from voltage capacitor oscillations, thus providing a low output current THD, and this is independent of the size of dc capacitors. Asymmetrical T-type common ground transformerless inverter is proposed in [15]. The EMI filter design and the modulation scheme allow the reduction of leakage current with high efficiency. Various methods have been introduced to minimize the leakage current in transformerless inverters. The common ground transformerless inverter topologies are efficiently eliminating the leakage current [5], [11], [14]. Although common ground transformerless inverters have numerous benefits, they also have certain drawbacks, such as the requirement for additional protection circuits due to high inrush current and the discontinuous nature of input current. This article proposes a new six switch one diode five-level 6S-1D-5L transformerless inverter topology with a common ground. The Suppressing the leakage current problem is possible with the grid neutral terminal’s direct connection with the negative PV terminal. This direct connection of grid neutral and PV negative terminal called common ground type transformerless inverters results in zero leakage current. Many topologies have been proposed to minimize the leakage current value. Still, each having has disadvantages like the higher switch count, the high voltage stress on the capacitor and the larger size of the capacitor [6]. The topology developed [7] has four topological variants with high dc-bus utilization and constant total common-mode voltage. By providing the DC and AC decoupling in inverter circuit will reduce the leakage current. A new DC decoupling inverter topology with less power components is proposed to reduce leakage current [9]. However, the com- Figure 1: Circuit diagram of proposed 6S-1D-5L Topology. 72 G N.. Pandurengan et al.; Informacije Midem, Vol. 52, No. 2(2022), 71 – 82 Table 2: Voltage stress of switches proposed topology has significant advantages like low capacitor voltage stress and low power device. Levels 2 Description and its operating principle Vin 0.5 Vin 0 -0.5 Vin -Vin 2.1 Description of 6S-1D-5L inverter topology The power circuit of the proposed 5L-Inverter topology is shown in Fig. 1. The proposed topology comprises six switches (S1, S2, S3, S4, S5, and S6), two capacitors C1 & C2 and one diode D for five-level voltage output. The voltage rating of the capacitors C1 and C2 are 0.5vin and vin, respectively. The C1 and C2 are charging in the positive half cycle and discharging in the negative half cycle. The negative terminal of the load is directly connected to the dc source negative terminal, which is called common ground. Levels Vin 0.5 Vin 0 -0.5 Vin -Vin Vin 0.5 Vin 0 -0.5 Vin -Vin S1 IL1 0 0 0 0 S2 IL- IL1 IL 0 0 0 Switches S3 S4 IL1 0 IL2 0 0 IL3 IL4 0 0 IL5 S5 0 IL2 0 IL4 0 S6 0 0 0 IL4 IL5 Level 2 :(V0 = 0.5Vin): The switches S2, S3 and S5 are switched ON to generate the output voltage of V0 = 0.5Vin. The respective level is shown in Fig. 2b. In this operating level, the capacitors C1 and C2 are charged to 0.5Vin and Vin. Level 3:(V0= 0): The switches S2, and S4 are ON. The output voltage in this level is V0 = 0. The respective level is shown in Fig. 2c. Level 4: (V0 = -0.5Vin) The switches S3, S5 and S6 are switched ON to generate the output voltage of V0 = -0.5Vin. The respective level is shown in Fig. 2d. In this operating level, the capacitor C1 is discharged. Level 5: (V0 = -Vin): The switches S4 and S6 are switched ON to generate the output voltage of V0 = -Vin. The respective level is shown in Fig. 2e. In this operating level, the capacitor C2 is discharged. Table 1: Operating levels of the proposed topology. S6 0 0 0 1 1 S6 1 1 1 0 0 Table 3: Current stress of switches Different switching Levels (Level 1 to Level 5) that generate five levels of the output voltage waveform of the proposed inverter and the switching sequence are listed in Table 1. The analysis of voltage stress and current stress of all the switches is summarized and shown in Table 2 and Table 3. The switch S1 blocks the sum of the voltage across the C1 and dc source voltage, and this S1 has to withstand the maximum voltage, i.e., 1.5 Vin. The maximum current flow through the switch S3. During the positive half cycle, the C2 capacitor is connected in parallel to dc source through switch S3, and it draws more charging current. Conducting Switches S2 S3 S4 S5 1 1 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 0 1 0 S5 0.5 0 0 0 0.5 Level 1: (V0 = Vin): During this level of operation, the switches S1, S2 and S3 are switched ON. The capacitor C2 is charged during this output voltage level. The respective level is shown in Fig. 2a. 2.2 Description of 6S-1D-5L inverter topology S1 1 0 0 0 0 S2 0 0 0 1 1 The blue line and red line in Fig. 2 indicate the current flow from source to load and vice versa. A few highlights of the new 6S-1D-5L inverter are, The proposed topology has few power components. The capacitors voltages are self-balanced and do ot require any additional sensors. The number of ON-state switches is less. Maximum voltage stress across the switch is equal to 1.5Vin. Total capacitor voltage stress is reduced. No leakage currents. Levels S1 0 0.5 0 1.5 1.5 Switches S3 S4 0 1 0 0.5 0.5 0 0 0.5 1 0 FCs Status C1 C2 ↑ ↑ ↑ ↑ ↓ ↓ 3 PWM Modulation technique Several modulation schemes have been developed to generate stepped output voltage levels in MLIs. The 73 G N.. Pandurengan et al.; Informacije Midem, Vol. 52, No. 2(2022), 71 – 82 pulse width modulation technique is classified as a low-frequency switching scheme and a high-frequency switching scheme based on the switching frequency. The multi-carrier level-shifted pulse width modulation technique is one of the familiar modulation methods. For the proposed 6S-1D-5L inverter topology, alternate phase opposition disposition pulse width modulation (APOD-PWM) has been employed, which is shown in Fig. 3a. The carrier signals Vc are compared with a sinusoidal reference signal Vref to generate gate signals. For the proposed inverter topology, the alternate phase opposition disposition pulse width modulation employs four carrier signals, two on the positive side and two on the negative side, compared with the sinusoidal reference signal Vref. The logic scheme to generate the gate S2 = A1 + A2 S 3 = A2 + A4A5 ' (4) Vref 2 × Vc , Vo = M × Vin (5) S5 = A 4 (6) 4 Power loss analysis The equivalent circuit of the proposed 6S-1D-5L topology is shown in Fig. 4a. The equivalent circuit is derived by replacing the switches and capacitors with their equivalent internal resistances. In the equivalent circuit Rsr, Resr, RL and Rd indicate the internal resistance of individual switch, the resistance of the capacitor, the resistance of the load, and the diode resistance. (1) 4.1 Conduction loss The logical expression for the gating signals is expressed as: S1 = A 3 S 4 = A1 + A5 S6 = A2 A3 '+ A4 A5 ' (7) pulses for switches are shown in Fig. 3b. The modulation index is an important factor that supports to control of the load voltage, and it is defined as: MI = (3) The conduction losses are calculated by multiplying the on-state voltage drop of the switch and the conduction current. The total conduction losses have been calculated with pure resistive load at a steady state. All (2) Figure 2: Switching levels of proposed inverter topology. 74 G N.. Pandurengan et al.; Informacije Midem, Vol. 52, No. 2(2022), 71 – 82 From equivalent circuit of Fig. 4d: (a) VC1 IdischargingC1 = R esr + 3R sr (10) From equivalent circuit of Fig. 4e: VC2 IdischargingC2 = (11) R esr + 2R sr By applying Kirchhoff’s voltage law and Kirchhoff’s current law to equivalent circuits of Fig. 4(b-e), the instantaneous value of conduction losses can be calculated using as follows: (b) 2 ) ( ) = 2R sr (IL1 ) + (R sr + R esr ) Icharging P = R sr (Idc ) + (R esr + R d ) Icharging C1 2 C2 2 ( P (12) 2 (13) 2 +(2R sr + R esr ) (IL2 ) Figure 3: Modulation Technique (a) APOD PWM methods and (b) Logic Diagram P C3 ( = (R esr + 3R sr ) Idischarging 2 ) (14) Where I discharging represents the capacitor C1 discharging current. working levels of the proposed topology are considered and its equivalent circuit is shown in Fig. 4(b-e) to calculate the maximum conduction loss. Pure resistive loading condition is considered because there should not exist any auxiliary current path between load current and output voltage to facilitate the charging of capacitors. Therefore, the resistive loading condition is considered the worst condition for calculating losses in switched capacitor-based multi-level inverters [8]. From equivalent circuit of Fig. 4b during V0=Vin: P C4 ( = (R esr + 2R sr ) Idischarging 2 ) (15) Where I discharging represents the capacitor C2 discharging current. The average conduction loss for one complete cycle of output voltage waveform is calculated by using related time interval. From Fig. 5, the time interval for Vin, 0.5Vin, -0.5Vin and -Vin is (t3-t2), (t2-t1), (t7-t6), and(t8-t7). By using the calculated instantaneous conduction loss, the average value of conduction loss is calculated as: Idc = Icharging + IL1 (8) Where IL1 is the load current during V0=Vin. From equivalent circuit of Fig. 4c during V0=0.5Vin: 2 P '= P C1 Idc = Icharging + IL2 (9) (t −t ); P'C2 = T2 PC2 (t2 −t1) Tf 0 C1 3 2 f0 2 P '= P C3 Where IL2 is the load current during V0=Vin. 2 t −t ; P' = P t −t C4 Tf 0 C3 7 6 Tf 0 C4 8 7 ( ) Figure 4: Equivalent circuit (a) Proposed circuit (b) Vo = Vin (c) Vo = 0.5Vin (d) Vo = - 0.5Vin (e) Vo = - Vin 75 ( ) G N.. Pandurengan et al.; Informacije Midem, Vol. 52, No. 2(2022), 71 – 82 The total conduction loss can be calculated using (16): P = P ' + P' C C1 C2 + P' + P' C4 C3 Where , Non is the number of turn ON switches, and Noff is the number of turns OFF switches during one fundamental cycle. (16) 4.3 Capacitor Ripple Loss PC1, PC2, PC3, and PC4 are instantaneous values of conduction losses and P’C1, P’C2, P’C3, P’C4 are average values of conduction losses over one complete cycle. The difference between capacitor voltage and the input voltage results in capacitor ripple losses [8], [10]. The capacitor ripple voltage is calculated using the equation (22): 4.2 Switching loss The switching of semiconducting devices during turnon and turn-off transitions are termed switching losses. The switching losses can be obtained by integrating the voltage and the current on the particular switching period. Here the switching losses can be calculated using linear polynomial approximation. ΔVc = i Ton ∫ V(t) × I(t) dt ∫ i (t) dt Pripple = (17) f × C × (∆VC )2 2 0 = Ton  ∫ 0 T  Vswon × Ton    – I (T-T )  on  dt  ×  1    Ton    ∆VC1 = (18) Ip C1 × fsw  π   cos  − θ  − sin θ  π× f × C2   3   ∆VC 2 = Where Vswon is the on-state voltage on the switch, I1 is the current through the switch after turning on, Ton is the turn-on time of the semiconductor switch. 4.4 Inductor Loss Toff (19) 0 = ∫ 0 = (20) Vswoff × I2 × Toff 6 2 (iL ) (26) Pcore = kf α Vcl Bλ (27) PL = Pcu + Pcore (28) The total loss is estimated as follows (26): Using fundamental frequency switching method, the total switching loss is estimated using (21): Pswitch = f ×(Non Eon + Noff Eoff ) (25) Where RL is the inductor’s series resistance, f is the frequency, Vcl is the core volume, and B is the flux density. K, α, λ are constants which depends on the core material. The inductor loss is expressed as: Toff  T   – I1 (T-Toff )    ×   dt Vswoff × Toff   Toff   (24) R L Pcu = V(t) × I(t)dt (23) In inductors, the total losses are depending on two losses a) copper loss and b) iron losses. For the output filter inductor, the loses are expressed as [14]: The energy dissipated during turn off period of a semiconductor switch is: ∫ I pm × I1 × Ton V = swon 6 Eoff = (22) Where Ci is the capacitance value, i(t) is the current flowing through the capacitors. Hence, from the longest discharge duration capacitors, the capacitor ripple loss over a cycle is calculated as: The energy dissipated during turn-on period of a semiconductor switch is: Eon = 1 Ci PLoss = P + Pswitch + Pripple + PL C (21) The overall efficiency is estimated as follows (27): 76 (29) G N.. Pandurengan et al.; Informacije Midem, Vol. 52, No. 2(2022), 71 – 82 η = Pout Pout + PLoss (30) The proposed topology’s efficiency without the output filter inductor is 96%. When the output filter inductor is considered, the efficiency is reduced to 95.43%. 5 Design considerations of passive elements Figure 5: Typical 5 level waveform The charge of capacitor C2 during its longest discharging period is expressed as: The voltage balancing of passive elements is important in switched-capacitor inverter topologies. The proposed new topology formed using flying capacitor C1 and switched capacitor C2. The capacitors C1 and C2 are charged to half of the input voltage (0.5Vin) and the full (Vin) input voltage. Since the capacitor C2 is charged and discharged using a series-parallel technique, it does not require any separate voltage balancing method. Unlike C2, capacitor C1 is charged and discharged during (+0.5Vin ) and (-0.5Vin) output voltage waveform. The capacitor C1 currents only during ±0.5Vin, and the ner charge of capacitor C1 over a fundamental period is expressed as [16]:    2V − Vin  Q =  C1  T C1, net  Z   Tfo 4 QC2 = 2 × Ip ∆VC1 × fsw Tfo 4 ; ; T fo 12 T fo 6 ≤ T ≤ ≤ β ≤ Vin RL dt (35) From the above equation the optimum value of capacitor C2 is calculated as: C2,mx ≥ π 3 × RL × k × ω (36) Similarly, for resistive-inductive loading the load current is expressed as: IL = Ipm sin(ωt − θ) (32) (37) Using (37) in (34) the capacitance of capacitors C2 is written as: Tfo 4 QC2 = 2 × ∫ Tfo 6 T fo 6 T fo ∫ Tfo 6 (31) As shown in Fig. 5, the longest discharge period of C2 occurs from t3 to t2.Where t1, t2, t3 are Tfo/12,Tfo/6, Tfo/4 which are expressed from fundamental time period Tfo. At R-load during steady state operation the load current flow is given as:  Vin   2 I L (t ) =  V  in (34) By substituting the equation (33) in (34), Under steady-state conditions the voltage across C1 will equal 0.5Vin. From (28), the total charge of the capacitor C1 will be zero in a given fundamental cycle, and it is achieved without any supplementary voltage balancing methods. Regarding the sizing of the capacitor C1, the required parameters are, allowable voltage ripple ΔVC1, switching frequency fsw, peak value of load current. From this C1 is calculated as [18]: C1 = IL (t) dt Tfo 6 QC2 = 2 × ∫ (33) 4 77 Ipm sin(ωt − θ) dt (38) G N.. Pandurengan et al.; Informacije Midem, Vol. 52, No. 2(2022), 71 – 82 (a) Tfo 4 QC2 = 2 × Ipm ∫ (sin ωt × cos θ − cos ωt × sin θ) dt Tfo 6   ωT      ωT QC2 = 2 × Ipm ×  cos  fo − θ − cos  fo − θ  4     6   π   QC2 = 2 × Ipm × cos  − θ − sin θ    3  (39) (b) From (39), a maximum value of capacitances for C2 can be calculated as: C2,mx =  π   ×  cos  − θ − sin θ   ω × k × Vin   3  2Ipm (40) Where Ipm is maximum load current, k is the ripple factor. Fig. 6(a-c) shows the graph between optimum value of capacitance with different load values, different frequencies, and different phase angles. The ripple factor of k=0.01, 0.05 and 0.1 and ω=100π has been taken for calculating the optimum value of capacitances. (c) Fig. 6b shows the graph between optimum value of capacitance C2 and frequency. This graph is plotted by considering the load resistance of 200 Ω. Fig. 6c is the graph plotted for different phase angles of θ with allowable voltage ripple of 0.05 and 0.1, Ipm = 8 A, Vin = 400V, f =50 Hz and ω = 100π at fundamental frequency. It is seen from the Fig. 6c that, as the phase angle increases the capacitance decreases. Figure 6: Variation of optimal capacitance versus (a) RL (resistive load) (b) frequency (Hz) (c) phase angle θ Figure 7: Simulation outputs of proposed 6S-1D-5L inverter topology for 1.2 kW 78 G N.. Pandurengan et al.; Informacije Midem, Vol. 52, No. 2(2022), 71 – 82 to reducing the power components’ life, and higher current rating devices are needed and source able to supply high current. To reduce this inrush current soft charging is used, as shown in Fig. 10. A small inductor with a value of 30 µH is inserted in the capacitor charging loop. In the case of capacitor C1, it doesn’t require because the capacitor is connected series with the load during the charging state. The soft charging path will be provided as long as the RLC circuit operates under damping conditions [17]. Initially, the output results are observed for the pure resistive load with the value of R=100 Ω, and the corresponding voltage and current waveform of load and capacitors are shown in Fig. 11a. Most of the inverters operate in inductive load, so it is necessary to test the proposed topology in resistive and inductive loading conditions. So, the proposed topology is tested with a load value of R=50Ω, L=50 mH and measured. It confirms that the proposed topology can perform for any inductive load, as shown in Fig. 11b. Here worth mentioning that the voltage across the capacitors VC1 and VC2 are not disturbed for inductive load shown in Fig. 11b. The step input variation shown in Fig. 11c confirms that the proposed topology can generate the 5L during the sudden input variation, as shown in Fig. 11c. The load will not be constant, and it is dynamic. So, the load variations are applied by changing from R=100 Ω & R=50 Ω to L=100 mH and the corresponding waveform shown in Fig. 11d. Further, the modulation index is another important factor in an inverter, and it is worth indicating the performance of the proposed topology with the variations of the modulation index. Varying MI=0.5, MI=0.8 and MI=1 test the effect of the modulation index and the corresponding waveforms are shown in Fig. 11e. Hence, the experimental results are confirmed that the proposed topology can operate in any loading conditions. Finally, the proposed topology simulation and measured efficiency are shown in Fig. 12 for different output power. The maximum efficiency is achieved at low output power and low in high output power. 6 Simulation and experimental results 6.1 Simulation results The operation of the proposed 6S-1D-5L inverter topology is examined for generating five-level output voltage using MATLAB/Simulink environment. The parameters used for the simulation and values of components used in the proposed inverter topology is tabulated in Table 4. While using alternate high-frequency phase opposition disposition pulse width modulation schemes with R=100 Ω, the load current is observed as 4 A. The load voltage and current waveforms for the RL-Load of R=50 Ω & L=100 mH are shown in Fig. 7a and Fig. 7b respectively. During RL-load, the voltage and current of the switches S2 and S1 are obtained and shown in Fig. 7(c-f ). Table 4: Simulation and Experimental Parameters. Parameters Input Voltage Capacitor C1 Capacitor C2 Output Voltage RL Load Simulation Experimental 400 V 200 V / 1700 200 V / 2200 µF / µF LGU2D222MELC 400 V / 1700 450 V / 1700 µF / µF PG6DI 400 V R=100 Ω and R= 50 Ω & L= 100 mH Switching frequency Digital Controller Gate Drive Circuit IGBT Switch 5 kHz - TMS320 F28379D TLP 250 SKM75GB063D 6.2 Experimental results A laboratory prototype was developed to validate the performance of the proposed topology. The Semikron IGBT switches SKM75GB063D with TLP250 driver circuits were used to develop the 1200 W prototype, as shown in Fig. 9. The Texas Instruments TMS320F28379D were used to generate the gating pulses with a switching frequency of 5 kHz. The direct parallel connection of dc source and capacitors increases the charging current, also called inrush current. This inrush current leads 7 Comparative Study To evaluate the merits and demerits of the proposed 6S-1D-5L topology, the proposed topology is compared with recent inverter topologies, and it is given in Table 5. Figure 8: Simulation power loss for various output power (a) 500 W (b) 700 W (c) 1000 W and (d) 1200 W 79 G N.. Pandurengan et al.; Informacije Midem, Vol. 52, No. 2(2022), 71 – 82 Figure 12: The efficiency of simulation versus hardware result The comparison is made by considering significant features such as NS –Number of switches, NDR-Number of driver circuits, NC-Number of capacitors, ND-Number of diodes, TSV (p.u)-Total standing voltage in per unit, G-Gain, VStress– Maximum voltage stress, VStress / G, MCS- Maximum number of conducting switches, CGT-Common ground type, LC-Leakage Current, PT- Total Power, η=efficiency. It is observed that the proposed topology has a minimum number of switching components and gate driver units than the topologies mentioned [3], [5], [10], [14]-[15]. The topology [11] offers the same TSV (p.u) as that of the proposed 6S-1D-5L inverter topology, but the voltage stress of the topology is very high than the proposed topology. On comparing with the tabulated topologies in the comparative study, it is clear that the proposed topology has the least total standing voltages TSV (p.u) except topologies [12], [14] but the volt- Figure 9: Photograph of prototype hardware setup Figure 10: Proposed circuit topology with soft charging inductor Figure 11: Experimental results of proposed 6S-1D-5L topology (a) for R-Load, (b) for RL load, (c) for step input change, (d) for R to RL load variations and (e) Modulation variation from 1 to 0.8 to 0.5 80 G N.. Pandurengan et al.; Informacije Midem, Vol. 52, No. 2(2022), 71 – 82 Table 4: Comparative study with other multilevel inverter topologies Top NS NDR NC ND [3] [5] [7] [10] [11] [12] [13] [14] [15] [19] [20] Pro 9 8 8 7 7 6 6 7 6 7 6 6 9 6 8 7 6 6 6 7 6 6 6 6 1 3 2 2 2 3 3 3 2 3 3 2 0 0 1 4 2 1 0 0 2 1 2 1 TSV (p.u.) 9 6.5 12 9 6 5 8 5 10 7 5 6 G 1:2 1:1 1:1 1:2 1:2 1:1 1:1 1:1 1:1 1:2 1:2 1:1 Capacitor Voltage 2Vin Vin 0.5Vin Vin Vin Vin Vin Vin 0.5Vin 2Vin 2Vin Vin VStress 1 1.5 2 2 4 1 1 1 1.5 2 2 1.5 age stress across the capacitor is very low in the proposed topology which reduces the cost of the inverter. With better TSV (p.u) than other topologies, the proposed topology uses fewer switches. Even with better TSV (p.u) of topology [14], the maximum number of conducting switches is more. On comparing with the topologies [7], [11], the ratio of voltage stress to gain (VStress /G) of the proposed topology is less. Also, with reference to the comparison Table 5, except for the topology [11], [ 15] the proposed topology has a smaller number of maximum conducting states than the others. The topology presented in [19] proposes a common ground structure which generates 3L. Despite the usage of two capacitors, the number of ac voltage levels is still three. Also, voltage across one of the capacitors is twice the input voltage. In [20], common ground structure with boosting ability is proposed. But it requires flying capacitor with two times the input supply and also the maximum stress across the switch is equal to twice the input supply. Also, the proposed topology offers high efficiency at low output power. VStress /G 0.5 1.5 2 1 2 1 1 1 1.5 1 1 1.5 MCS CGT LC /PT /η% 5 3 4 4 2 3 3 4 2 3 3 3 No Yes No No Yes Yes Yes Yes No Yes Yes Yes NA / 2kW / 97.91 Zero / 500W / 97.1 NA / 500W / 96.8 NA / 600W / 96.8 Zero / 600W / 98.1 Near Zero / 1.2kW / 95.8 Zero / 1kW / 97 Zero / 500W / 96.4 NA / 400W /97.8 Zero/750W/98.1 Zero / 510W/98.1 Zero / 1.2kW / 95.43 filter inductor, the efficiency is 95.43% which has a good agreement with simulation efficiency of 96.4%. 9 Acknowledgements The authors express their gratitude to the SRM Institute of Science and Technology Kattankulathur, Campus 603203, India and Renewable Energy Laboratory (REL), College of Engineering, Prince Sultan University, Riyadh 11586, Saudi Arabia, for financial and technical knowledge transfer. The authors would like to acknowledge the support of Prince Sultan University for paying the Article Processing Fee (APC). 10 Conflict of interest Authors declaring conflict interest 8 Conclusion 11 References A new transformerless inverter for low power applications is presented in this paper. The proposed topology used two capacitors, and the negative terminal of theload and dc source have a common connection, as discussed. The capacitors voltage is balanced without any additional sensors, and the same is verified in both simulation and experimental results. The output results are discussed, confirming that the proposed topology is suitable for dynamic load variation and modulation index changes. Further, the PLECS analyses the power loss and the various power loss for different output power and the same output power, the measured efficiency is presented. The measured efficiency for the 1.2 kW is 96% without output filter inductor. When including output 1. 2. 3. 81 W. Li, Y. Gu, H. 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Arrived: 01. 09. 2021 Accepted: 07. 03. 2022 82 Original scientific paper https://doi.org/10.33180/InfMIDEM2022.202 Journal of Microelectronics, Electronic Components and Materials Vol. 52, No. 2(2022), 83 – 88 Design, Fabrication and Measurement of LDNMOS-SCR Devices with Appropriate ESD Protection Window for 18V HV CDMOS Process Yang Wang1,3, Xuebing Su1,3*, Xiangliang Jin2,3, Hongjiao Yang1,3, Zijie Zhou1,3 School of Physics and Optoelectronics, Xiangtan University, Xiangtan, Hunan, China; School of Physics and Electronics, Hunan Normal University, Changsha, Hunan, China; 3 Hunan Engineering Laboratory for Microelectronics, Optoelectronics and System on A Chip, Xiangtan, Hunan, China 1 2 Abstract: Lateral Double Diffused MOSFET (LDMOS) embedded Silicon Controlled Rectifier (SCR) is a normal way to improve the Electro-Static Discharge (ESD) robustness for smart power technologies, but it doesn’t always have the proper ESD window for a given application. In this paper, LDNMOS-SCR of four variants structures have been investigated based on a high-voltage (HV) 0.5μm 18V HV CDMOS process with 2D device simulation and silicon verification. Transmission Line Pulse (TLP) testing results demonstrated that those devices successfully elevate the second breakdown current It2 from original 1.146A to above 3A; source isolated device has a lower trigger voltage Vt1 (45.79V) than source non-isolated devices; the holding voltage Vh of the four devices is related to their structure, and their holding current Ih are all above 800mA, which is big enough to ensure the latch-up immunity under ESD stresses in HV applications. The device with its source isolated from PSUB is the suitable ESD protection device for HV 18V CDMOS technology owning to its strong ESD robustness, low Vt1, small on-resistance Ron and sufficiently big Ih. Keywords: ESD window; LDMOS embedded SCR; TCAD device simulation; TLP Načrtovanje, izdelava in merjenje naprav LDNMOSSCR z ustreznim zaščitnim oknom ESD za 18V HV proces CDMOSI Izvleček: Vgrajeni silicijev usmernik z dvojno lateralno difundiranim MOSFET (LDMOS) je običajen način za izboljšanje odpornosti proti elektrostatičnim razelektritvam (ESD) pri pametnih energetskih tehnologijah, vendar nima vedno ustreznega okna ESD za določeno aplikacijo. V tem članku so bile raziskane štiri različice struktur LDNMOS-SCR na osnovi visokonapetostnega (HV) 0,5μm 18V HV CDMOS procesa z 2D simulacijo naprave. Rezultati testiranja TLP (Transmission Line Pulse) so pokazali, da te naprave uspešno povečajo drugi prebojni tok It2 s prvotnih 1,146A na več kot 3A; izvorno izolirana naprava ima nižjo prožilno napetost Vt1 (45,79V) kot izvorno neizolirane naprave; držalna napetost Vh vseh štirih naprav je povezana z njihovo strukturo, njihov držalni tok Ih pa je nad 800 mA, kar je dovolj veliko za zagotovitev odpornosti na zaklepanje pri obremenitvah ESD v HV aplikacijah. Naprava z izvorom, izoliranim od PSUB, je primerna naprava za zaščito pred ESD za HV 18V tehnologijo CDMOS zaradi svoje močne odpornosti proti ESD, nizke Vt1, majhne upornosti Ron in dovolj velikega Ih. Ključne besede: Okno ESD; vgrajeni SCR LDMOS; simulacija naprave TCAD; TLP * Corresponding Author’s e-mail: wangyang@xtu.edu.cn How to cite: Y. Wang et al., “Design, Fabrication and Measurement of LDNMOS-SCR Devices with Appropriate ESD Protection Window for 18V HV CDMOS Process", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 52, No. 2(2022), pp. 83–88 83 Y. Wang et al.; Informacije Midem, Vol. 52, No. 2(2022), 83 – 88 cathode region. Whatever discharge routing it goes, the avalanche breakdown junction is still at the NWD/ PW junction. The equivalent circuit of Type I is shown in Figure 3. The embedded SCR is composed of a vertical p-n-p BJT and a lateral n-p-n BJT to form a 2-terminal/4 layer PNPN (P+/NWD/PW/N+) structure. 1 Introduction LDMOS power transistors have been commonly used as output driver and ESD protection device simultaneously in the smart power technologies [1-3]. However, the HV LDMOS doesn’t have high ESD robustness after entering its snapback breakdown region. Such device exhibits random and unconstrained failures during the snapback breakdown before reaching its intrinsic limitation [4-7]. LDMOS embedded SCR is a normal way to improve the ESD robustness in high voltage technology. Several works have been done to kinds of LDMOSSCR for smart power application. Wang discussed ESD charateristics about LDMOS-SCR device including its working mechanism, latchup immunity simulation, and response time analyses, etc [8]. Chang proposed the impact of technology layers and layout parameters on the LDMOS-SCR devices robustness [9]. Ker put forward a modified LDMOS-SCR achieving high holding voltage with the aid of RC detection circuit [10]. Lee found that a P+ strip inserted into drain region can improve the ESD failure threshold of embedded SCR LDMOS device [11]. Some other novel structures and their performance were studied for different application purposes in [12-16]. The main difference of the other three LDNMOS-SCR devices from Type I device in Figure 2 is that the source of LDNMOS is not isolated from PSUB by NWD. Hence, the avalanche breakdown of those devices could occur either at the NWD/PSUB junction or at the NWD/ PW junction. Among those three types non-isolated LDNMOS-SCR, Type III and Type IV have an additional NW surrounded P+&N+ or P+ only at the anode, which will influence their holding voltage (Vh). The equivalent circuit for device Type II, Type III and Type IV is drawn in their cross-sectional view. Although the different anode structures result in the different resistance between the b-e junctions of vertical PNP transistor, the working mechanism of all the LDNMOS-SCR devices is identical. Bulk FOX FOX P+ The purpose of this paper is to design a robust ESD protection device with an appropriate ESD window for 18V HV CDMOS technology with respect to traditional gate-grounded LDNMOS (GG-LDNMOS). Four types LDNMOS-SCR are considered in this paper, and the testing devices are fabricated in a 0.5μm 18V HV CDMOS technology. Their ESD characteristics are evaluated by two dimensional (2D) device simulation and transmission line pulse (TLP) measurement. Drain Source Gate PW N+ FOX N+ RPW NWD PSUB Figure 1: Cross-sectional views of conventional GGLDNMOS device. 3 TLP testing result and discusions 2 LDNMOS-SCR Devices and working mechanism The above four devices are fabricated as one-finger device with device width of 50μm. The ESD characteristics measurement is performed on the Thermo Celestron I transmission line pulse (TLP) system. It applied a current pulse to the device with a rise time of 10ns, a pluse width of 100ns, and the current stress level increasing continuously until the device failed. The leakage current is measured after each TLP zapping with 19.8V DC voltage on their anode. Once the leakage current is above ~1μA, it is considered that the device under test is failure. The TLP IV curves for LDNMOS with embedded SCR are shown in Figure 4, and corresponding TLP data is summarized in Table 1. TLP measurement data of one-finger traditional GG-LDNMOS with the same device width is also listed in this table for comparison. The cross-sectional view of conventional GG-LDNMOS is shown in Figure 1. Four types LDNMOS embedded SCR are designed based on the LDNMOS. As shown in Figure 2(a) is the structure for type I device, a P+ diffusion in conjunction with N+ diffusion is added in the deep N well (NWD) to serve as anode of the embedded SCR. The N+ region used as original drain electrode of LDNMOS shrinks its lateral dimension and is let alone with no voltage applying to it. Thus, there will be two discharge ways in the modified structure. One path for ESD current discharging is LDNMOS, it should pass through the NWD resistor named Rdrain between the floating drain and anode. The other way is through the embedded SCR, the way is composed by P+ diffusion in the anode region, NWD, PW, N+ diffusion in the It is apparent in Figure 4 that the source isolated LDNMOS-SCR (Type I) has a lower trigger voltage, which 84 Y. Wang et al.; Informacije Midem, Vol. 52, No. 2(2022), 83 – 88 (a) Cathode FOX P+ FOX N+ 8.5μm FOX N+ Rs2 RPW PW HV applications. Their leakage current is remained at 7~9nA before hard failure, hence, they don’t bring considerable impact on the protected core circuit in normal condition. Anode NWD P+ Rdrain FOX N+ RNWD Rs1 PSUB (b) Cathode FOX P+ Anode FOX FOX N+ N+ 10μm Rs2 PW FOX FOX P+ N+ Rdrain RPW RNWD Rs1 NWD PSUB (c) Cathode FOX P+ PW N+ Anode FOX FOX 13.5μm N+ Rdrain Rs2 FOX FOX P+ N+ RPW RNW Figure 4: TLP I-V plots for four types LDNMOS embedded SCR with the same device width of 50 μm. NW Rs1 NWD 3.1 Trigger characteristics PSUB (d) Cathode FOX PW P+ Anode FOX FOX 13.5μm N+ Rdrain Rs2 N+ FOX P+ N+ The trigger voltage of Type I LDNMOS-SCR with its source isolated from PSUB is 45.79V, which is much small-er than that of other three source non-isolated LDNMOS-SCR devices. The different NWD location should take responsibility for the different Vt1. A two dimensional (2D) device simulation is performed on a TCAD platform to discover the root cause. Type II is a typical source non-isolated LDNMOS-SCR, whose source is not enveloped by NWD, thus, only Type I and Type II devices are simulated with a 10V voltage applied on their anode electrode. The simulated junction, depletion layer and electric field distribution for those two devices are demonstrated in Figure 5. The red heavy line in the 2D device structure is the edge of depletion layer, the thickness of depletion layer across NWD/PW junction under the poly silicon of Type I is 1.6μm, which is narrower than that of Type II (2.7μm). As the voltage applied on anode is the same, the device with narrower depletion layer will have a stronger electric field. This is proved in Figure 5 that the electric field equal strength line of Type I is denser than that of Type II at this location. Hence, Type I inclines to breakdown more easily than Type II, and a bigger avalanche breakdown voltage is needed for Type II to switch on. Therefore, Type II owns a Vt1 of 68.78V, which is larger than Type I source isolated LDNMOS-SCR. FOX RNW RPW NW Rs1 RNWD NWD PSUB Figure 2: Cross-sectional views of four kind LDNMOSSCR devices. (a) Type I; (b) type II; (c) type III; (d) type IV. Anode RNWD Vertical PNP NWD Rdrain Rs2 Rs1 Lateral NPN LDNMOS PW RPW Cathode Figure 3: Equivalent circuit of Type I LDNMOS with embedded SCR. can be triggered into its snapback region earlier. The holding voltages are below 18V, however, they have a relatively high holding current above 800 mA, which ensures the latch-up immunity under ESD stresses in 85 Y. Wang et al.; Informacije Midem, Vol. 52, No. 2(2022), 83 – 88 Table 1: TLP measured data for conventional GG-LDNMOS and four kind LDNMOS-SCR devices with the same finger width of 50 micrometers. Device Name GG-LDNMOS Type I Type II Type III Type IV 3.2 Holding characteristics The Vh of four types LDNMOS-SCR are 4.83V, 7.03V, 8.37V and 7.08V, respectively. The holding voltage difference is result from the anode structure. Formula of Vh can be derived from SCR equivalent schematic in Figure 3, Vt1(V) Vh(V) Ih(A) It2 (A) Efficiency Spacing (mA/μm2) (μm) 46.909 8.161 0.907 1.146 0.459 / 45.794 4.825 0.864 3.169 1.884 8.5 68.780 7.029 1.332 3.292 2.480 10.0 69.450 8.368 1.311 3.167 1.735 13.5 69.554 7.082 1.379 3.399 2.086 13.5 Vh ≈ Vec− PNP + (Vbe− NPN / RPW + I be− NPN ) × Rs1 + Vbe− NPN = Vec− PNP + Vbe− NPN (1 + Rs1 / RPW ) + I be− NPN × Rs1 (1) = Vce− NPN + Vbe− PNP (1 + Rs 2 / RNWD ) + I be− PNP × Rs 2 The DC breakdown voltage (BVD) of the LDNMOS device in the core circuit is 43.5V in our CDMOS technology, and Type I LDNMOS-SCR has the lowest Vt1 among the four investigated devices, which is only several volts bigger than BVD. And its Vt1 is closest to the trigger voltage of conventional GG-LDNMOS used for ESD protection at I/O pad. Thus, Type I will be the optimal choice in view of transient Vt1 measured by TLP. The spacing between anode P+ and cathode N+ called SCR length of Type I, Type II, Type III, Type IV are 8.5μm, 10μm, 13.5μm and 13.5μm, respectively. The wider the spacing is, the bigger the parasitic resistance Rs1 and Rs2 are. And it can be concluded from (e.g. Eq. (1)) that device with bigger Rs1 and Rs2 will obtain a lager Vh. Thus, the holding voltage relationship of Type I, Type II, Type III is Vh-Type I< Vh-Type II< Vh-Type III. However, there is an exception that Type III and Type IV have the same anode to cathode space, but Vh of Type IV is smaller than that of Type III. This is because the P+ & N+ diffusion regions at the anode of the Type III device are surrounded by NW, so the RNWD in (e.g. Eq. (1)) is replaced by RNW. While the Type IV device is partly replaced by RNW, as only the P+ diffusion area is sur-rounded by the NW. For the doping concentration of NW is higher than NWD, therefore, the RNWD term in (e.g. Eq. (1)) of Type IV device is larger than Type III, so Type IV has a smaller Vh than Type III. It is noted that Vh of all those LDNMOS-SCR devices are below 18V circuit operation voltage, however, the holding current (Ih) of them is all above 800mA, which is big enough for those devices to immune from latch-up at normal operation in HV applica-tions [17-18]. (a) (b) 3.3 ESD robustness and turn-on resistance characteristics Table 1 shows that the second breakdown current It2 of four devices are all above 3A, which is much higher than that of the traditional GG-LDNMOS of 1.146A. Thus, the ESD robustness of LDNMOS is indeed increased by adding a SCR path in it. Among those devices, Type IV has the highest second breakdown current of 3.399A, but for its bigger SCR length (13.5μm), it ocuppies larger chip area. The device has the biggest current discharge effciency is Type II, its current discharge per unit area is 2.48mA/μm2, thus, it is an optional device when chip area minimization is taken into consideration. Figure 5: Junction location, depletion layer and electric field (V/cm) distribution in (a) Type I source isolated LDNMOS-SCR and (b) Type II source non-isolated LDNMOS-SCR by DC simulation with anode electrode voltage of 10V. The on-resistance (Ron) of devices is indicated by the slope of their I-V curves after snapback. The Ron versus TLP current after snapback and before second breakdown is derived from TLP testing data of those devices and shown in Figure 6. The turn-on resistances differ 86 Y. Wang et al.; Informacije Midem, Vol. 52, No. 2(2022), 83 – 88 from each other for different device structures, Type II & Type IV have the relatively low Ron, Type I has the minimum turn-on resistance, which means ESD current is more easily to discharge through it. It is also noted that the device that has a larger holding voltage owns a bigger Ron. And it has a trend that Ron decreases a little at first, and then increasing apparently as the TLP current growing around ~2.5A. This is because that a bigger current results in a higher lattice temperature, and the carrier mobility will index decrease as the lattice temperature increasing [19]. Thus, Ron increases dramatically until the second breakdown occurs. 5 Acknowledgments This work is supported by National Natural Science Foundation of China (Grant No. 61774129, 61827812), by Excellent youth funding of Hunan Provincial Education Department (Grant No. 19B557), by Technology Program of Changsha (Grant No. kh2201084) and by Degree & Postgraduate Education Reform Project of Hunan Province (QL20210141). 6 Conflict of interest We declare that we do not have any commercial or associative interest that represents a conflict of interest inconnection with the work submitted. 7 References 1. Figure 6: Turn-on resistance Ron of four types LDNMOS-SCR in their snapback region. 2. 4 Conclusions 3. Four types LDNMOS-SCR ESD protection device have been fabricated in a 0.5μm 18V HV CDMOS process and measured by TLP to examine their ESD windows. The key parameters obtained in TLP I-V curves are compared and discussed. 1) The Type I source isolated device has a lower Vt1 due to the thinner depletion layer than the non-isolated LDNMOS-SCR. The Vh of the four devices is determined by the anode to cathode SCR spacing and anode structure, and their Ih is big enough to immune from latchup issue. Further, the second breakdown current It2 of those four devices is much higher than that of traditional GG-LDNMOS, which improve the ESD robustness greatly. 4. 5. 2) From the analysis in section 3, it leads us to conclude that Type I is the appropriate device used for HV 18V ESD protection owning to its low Vt1 and small Ron. Type II will be prior to other two non-isolated LDNMOS-SCR for its high discharge efficiency and relatively low resistance, it can be used to protect circuits with even higher operation voltage. 6. 87 R. K. Williams, M. N. Darwish, R. A. Blanchard, R. Siemieniec, P. Rutter and Y. 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Arrived: 22. 04. 2022 Accepted: 14. 05. 2022 88 Original scientific paper https://doi.org/10.33180/InfMIDEM2022.203 Journal of Microelectronics, Electronic Components and Materials Vol. 52, No. 2(2022), 89 – 103 Programmable implementation of time-areaefficient Elliptic Curve Cryptography for entity authentication Kamaraj Arunachalam1, Marichamy Perumalsamy2 Department of ECE, Mepco Schlenk Engineering College, Sivakasi, India Department of ECE, PSR Engineering College, Sivakasi, India 1 2 Abstract: The rise of wireless technologies, communications and devices, has resulted in the demand for effective security with low hardware requirements and high speed. Among the various cryptographic algorithms, the Elliptic Curve Cryptography (ECC) provides an attractive solution for this demand. In this paper, the Remote Keyless system (RKE) Authentication process using the ECC is implemented in Field Programmable Gate Array (FPGA). The designed ECC processor supports 256-bit point multiplication and point addition on the Koblitz curve secp256k1. The scalar multiplication is performed with the faster multiplier Urdhva Tiryagbhyam (UT). Additionally, pipelining is incorporated in order to speed up the multiplication process of the processor. The proposed ECC processor performs single point multiplication of 256-bit in 1.2062ms with a maximum clock frequency of 192.5MHz, which provides 212.23kbps throughput and occupies 8.23k slices in Virtex-7 FPGA. Incorporating a pipeline in scalar multiplication improves the maximum clock frequency up to 15.12%, which reduces time consumption by 22.36%, which in turn increases the throughput by 22.36%. The proposed pipelined Vedic multiplier based ECC processor outperforms the existing designs in terms of area, operating frequency, areadelay product and throughput. Also, the security evaluation and analysis of the proposed ECC processor are performed, which ensures the safety of RKE systems. Hence, the implementation of the proposed method offers time-area-efficient and fast scalar multiplication with effective hardware utilization without any compromise in security level. Keywords: Urdhva Tiryagbhyam; Pipeline; Remote Keyless system Authentication; FPGA Programirljivo izvajanje časovno učinkovite kriptografije eliptičnih krivulj za avtentikacijo entitet Izvleček: Razvoj brezžičnih tehnologij, komunikacij in naprav je povzročil potrebo po učinkoviti varnosti z nizkimi strojnimi zahtevami in visoko hitrostjo. Med različnimi kriptografskimi algoritmi zagotavlja eliptična krivulja (ECC) privlačno rešitev za to. V tem članku je predstavljen postopek avtentikacije sistema brez ključa na daljavo (RKE) z uporabo ECC v FPGA (Field Programmable Gate Array). Zasnovani procesor ECC podpira 256-bitno množenje in seštevanje točk na Koblitzovi krivulji secp256k1. Skalarno množenje se izvaja s hitrejšim množiteljem Urdhva Tiryagbhyam (UT). Poleg tega je za pospešitev postopka množenja v procesorju vključena cevna povezava (pipelining). Predlagani procesor ECC izvede enotočkovno množenje 256-bitov v 1,2062 ms z največjo taktno frekvenco 192,5 MHz, kar zagotavlja prepustnost 212,23 kb/s in zasede 8,23k rezin v Virtex-7 FPGA. Vključitev cevovoda pri skalarnem množenju izboljša največjo taktno frekvenco do 15,12 %, kar zmanjša porabo časa za 22,36 %, to pa poveča prepustnost za 22,36 %. Predlagani procesor ECC, ki temelji na množitelju s cevovodi Vedic, je boljši od obstoječih modelov glede površine, delovne frekvence, produkta površine in zakasnitve ter prepustnosti. Izvedena sta tudi varnostna ocena in analiza predlaganega procesorja ECC, ki zagotavlja varnost sistemov RKE. Izvedba predlagane metode torej omogoča časovno učinkovito in hitro skalarno množenje z učinkovitim izkoristkom strojne opreme brez kompromisov na ravni varnosti. Ključne besede: Urdhva Tiryagbhyam; Cevovod; avtentikacija sistema brez ključa na daljavo; FPGA * Corresponding Author’s e-mail: kamarajvlsi@gmail.com How to cite: K. Arunachalam et al., “Programmable implementation of time-area-efficient Elliptic Curve Cryptography for entity authentication", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 52, No. 2(2022), pp. 89–103 89 K. Arunachalam et al.; Informacije Midem, Vol. 52, No. 2(2022), 89 – 103 1 Introduction the verification of the signed response of the user, then authentication would be granted. These kinds of authentication methods are widely popular in sensor networks. In such scenarios, strong encryption algorithms are required to avoid mischief [3]. This kind of entity authentication is to be initiated by the user that can be an equivalent word. This equivalent word checked by the verifier [4]. Nowadays, almost all cars are equipped with a smart keyless entry system. This is an electronic lock that controls admittance to a vehicle without utilizing a manual mechanical key. Such frameworks currently have a secret touch-enacted keypad, which is as yet accessible on certain Ford and Lincoln models. This method is termed as Remote Keyless System (RKS). A distant keyless framework can incorporate both a remote keyless entry (RKE), which opens the car door and a remote keyless ignition system (RKI), which turns the engine ON. Elliptic-curve cryptography [5] is a public key cryptography based on the algebraic structure of elliptic curves over finite fields. Elliptic curves are used in key agreement, digital signatures, pseudo-random generators and also in performing other tasks. In contrast to Rivest–Shamir–Adleman (RSA), the ECC approach is based on how elliptic curves are structured algebraically over finite fields. Therefore, ECC creates keys that are more mathematically difficult to crack [6]. Hence ECC is considered to be the next generation public key cryptography and it is more secure than RSA. ECC cryptography can provide strong security with a 164-bit key as other cryptosystems realize the same level of security with a 1024-bit key or more. With the advent of mobile devices being used for highly secured private transactions, low-overhead encryption schemes are becoming highly desirable in today’s applications. On account of the innovative keyless technology, programmers can utilize expert systems to fool the vehicle and to make them believe that the right fob is close by, permitting them access. Such attacks are listed as below [1], 1. Replay Attack: A replay attack (otherwise called playback attack) is a type of organized attack in which valid information transmission is perniciously or falsely rehashed or delayed [2]. 2. Rolljam Attack: The rolljam attack works by recording and blocking the radio signal from the key fob. Because the signal is blocked, the car doesn’t unlock and the owner will naturally try again. That creates a second signal that is also recorded and blocked, but this time the attacker replays the first code to unlock the door. 3. Brute Force Attack: Brute force attacks are simple and reliable. Attackers let a computer do the work – trying different combinations of usernames and passwords until they find one that works. The effectiveness of ECC can be improved by modifying its computations process. Vedic mathematics is a collection of procedures to solve complex mathematical functions effectively. It was invented by Sri Bharati Krishna Tirthaji from the Indian Veda scriptures. It consists of 16 sutras, among which Urdhva Tiryakbhayam, Nikhilam Sutram and Anurupye are the most widely used sutras for solving complex functions. The significant gain of the Vedic multipliers is that they have simple procedures for the resource consuming multiplications [7]. The multiplication operation can be extended to n-bits with some minor modifications. Some other attacks are radio jamming attack, scan attack and two-thief attack, which are also major attacks in Remote Keyless Entry (RKE) and Passive Remote Keyless Entry (PRKE) systems, which are shown in Figure 1. The factual meaning of the Urdhva Tiryagbhyam Sutra is “Vertically and Crosswise”. The vertical and crosswise manipulation is performed to generate the partial products; then they are summed for final product generation. 2×2 is the basic module of the Vedic multiplier. The n-bit multiplier could be derived by the repeated arrangement of 2×2 multipliers. This process makes the computation fast and the product is generated with a fewer number of steps [8]. Figure 1: Types of Attacks in Remote Key Fob [1] In order to overcome these attacks, a high level of security algorithms is needed for secure communication. The public key cryptography based authentication has no secret information to be shared between the entities. A user requesting to authenticate him has to use his private key to digitally sign a random number, which is issued by the verifying entity. This random number is a time-variant parameter and is unique to the authentication exchange. If the verifier completes 2 Literature survey Multiple attacks are strategized based on the technology used on the fob. A powerful attack will result in a definite loss to the user. There are many kinds of attacks 90 K. Arunachalam et al.; Informacije Midem, Vol. 52, No. 2(2022), 89 – 103 that are reported regarding the car locking mechanism. Wireless communication systems used for RKE seem to be more vulnerable to attack. Furthermore, the type of cryptographic algorithms deployed also limits the security in those systems [1]. wards authentication of smart remote vehicle control, which could provide security against 12 kinds of attacks. In the modern-day scenario, almost all automobiles are equipped with a remote keyless system. Hence the security of the communication system should be effective. Only a few studies focused on this issue. The presently available studies are lacking in, Effective Hardware implementation [14-17]. Proper key size against the attack [14-15]. A simple relay based passive keyless entry was constructed and tested for 10 cars from 8 different manufacturers at various physical distances. This methodology is an initiation towards the remote keyless car. These countermeasures carried against the attack itself act as a hindrance to the keyless operation [9]. In [10], a symmetric key based remote keyless secure transmission between car and fob was demonstrated, which provides secure communication against scan attack, playback attack and forward prediction attack. It requires less computation and consumes less energy with a message length of 80 bits. But, it requires frequent key updates by the user for better security. There is no safety without security in the progressively interconnected nature of a vehicle’s control modules. Also, according to Alan Grau [18], key fob fails due to Encryption keys generated from public data along with insufficient entropy for generating encryption keys, Discoverable encryption keys, and Deprecated key strength. It was suggested that deploying asymmetric encryption with proper key length on suitable hardware will improve the key fob encryption [18]. An effective scalar point multiplication for the elliptic curve is introduced. Then the critical path of the scalar point multiplication for the Lopez-Dahab curve is rearranged and reordered in such a way that parallel processing is enabled and the critical path operations are shifted to non-critical paths [6]. The point multiplication in ECC is a time consuming and slow process. Now, the ECC point multiplication is performed with Urdhva Tiryagbhyam Vedic multiplication [19]. The UT performs significantly better in terms of delay and logic levels compared to the conventional multiplier [20, 21]. Especially, the Vedic multiplier surpasses the performance of the Karatsuba multiplier in terms of area and delay; in addition to that, the UT has 90% less delay compared to the Booth multiplier. Even though the Booth multiplier is occupying less area, the delay for a single product generation is 287ms, which is 10 times higher than the Vedic multiplier [22] as shown in Table 1. Also, UT exhibits smaller path delay, logic delay, routing delay and dynamic power. The size of the UT may be 16-bit [19], 32-bit [23] and can be extended as desired. But, the hackers intercept the car’s remote key details while the owner is using them. Then, these intercepted details are utilized to unlock the car door without the knowledge of the owner. Recently, ‘Universal Remote’ [11], ‘EvanConnect’, ‘keyless repeater’ [12] and power amplifier are used to hack Honda, Toyota, Volvo, Volkswagen and Jaguar cars. These hackers capitalized on the communication design flaw present in the design of the protocol. Keeloq system from Microchip has been broken by the University of Bochum or NXP’s Hitag-2 system. At Fraunhofer AISEC the effectiveness of ECC in RKE applications was demonstrated. It was prototyped with the support of Field Programmable Gate Array (FPGA) [13]. A remote keyless system is widely used in automobile industries to lock or unlock the vehicle’s door. But the security of the remote keyless system is threat prone since the beginning. Initially, Advanced Encryption Standard (AES) based wireless protocol with fixed and variable key length system was introduced [14, 15]. Here, a maximum of 128-bit AES is used for encryption, which could provide effective security against three types of attacks [14]. But, they are implemented in an 8-bit ATMega128L microcontroller, which has a very low speed of operation. Thereafter, FPGA implementation of secured Controller Area Network (CAN) bus communication was developed with AES for internal vehicular communication [15]. Table 1: Performance of Vedic, Karatsuba and Booth multiplier [22] Parameter Vedic Karatsuba Booth No. of slice LUTs 51761 103246 1937 No. of IOBs 640 640 643 Time Delay (ns) 27.172 34.123 287.840 Area Delay Product 0.001406 0.003523 0.000558 An ECC protocol developed in Python can provide security against 9 different attacks, which is economical compared to its predecessors [16]. Thereafter [17], a software protocol was developed based on ECC to- Hence, a more secured and high performance remote keyless system can be developed using a hybrid of ECC incorporated with Vedic multiplier, which is to be implemented in FPGA. 91 K. Arunachalam et al.; Informacije Midem, Vol. 52, No. 2(2022), 89 – 103 Algorithm 1 VEDIC ALGORITHM INPUT: n- bit Multiplicand and Multiplier OUTPUT: 2n- bit product k ← 0 S(k): 2n- bit vector initialized to 0 for i = 0 to n-1 do for j = 0 to i do S(k) = S(k) + a(i) × b(i − j) end k = k + 1 end for i = n-1 to 1 do for j = n-1 to i do S(k) = S(k) + a(i) × b(n − (i − j)) end k = k + 1 end for i = 0 to (k − 1) do P = P + S(i) end 3 Mathematical background In this paper, the Koblitz curve is considered with secp256k1 for ECC as shown in Figure 2. This elliptic curve has the form of y² = x³ + ax + b, in which a = 0, b = 7, whose Prime Field (p) = 2256 – 232 – 977 and in the random case we have considered, Order (n) = FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFE FFFFFC2F Base Point (G) = 04 79BE667E F9DCBBAC 55A06295 CE870B07 029BFCDB 2DCE28D9 59F2815B 16F81798 483ADA77 26A3C465 5DA4FBFC 0E1108A8 FD17B448 A6855419 9C47D08F F Addition: Let P = (x1, y1) ∈ (K) and Q = (x2, y2) ∈ E(K), where P = ±Q. Then P + Q = (x3, y3), where, 𝑥3= (𝑦2−𝑦1/ 𝑥2−𝑥1)2−2𝑥1−𝑥2 and 𝑦3 = (𝑦2−𝑦1/𝑥2−𝑥1)2−(𝑥1−𝑥3)−𝑦1 Point Doubling: Let P = (x1, y1) ∈ E (K), where P = -P. Then 2P = (x3, y3), where: 𝑥3 = (3𝑥12+𝑎/2𝑦1)2−2𝑥1 and 𝑦3 = (3𝑥12+𝑎/2𝑦1)2−(𝑥1−𝑥2)−𝑦1 4 Main contribution According to Hankerson, Menezes, and Vanstone [24], the primary advantage of the Koblitz lies in the possibility of implementing ECC without point doublings when performing ECC Point Multiplication (ECPM). A time-area-efficient 256-bit ECC processor over prime field is implemented in FPGA. It is aimed to reduce the area and the delay for single point multiplication and increase the frequency and the throughput. In order to reach these objectives, the following major contributions are made in this paper, An efficient design for ECPM on a Koblitz curve secp256k1 for the 256-bit prime field is proposed. A faster Urdhva Tiryagbhyam multiplier is adopted for ECPM scalar multiplication, which reduces computation time. The computing frequency is further improved by incorporating the pipeline technique in the Vedic multiplier. Moreover, the area-delay product, throughput and efficiency of the proposed method shows improvement compared to the existing similar works in the literature. 5 Methodology This section presents the algorithms, hardware architectures for point addition, point multiplication, modular multiplication and pipelined Vedic multiplication for ECC based remote keyless system authentication. Figure 2: Diagram of Elliptic Curve The Urdhva Tiryagbhyam (UT) Vedic multiplication is as follows, 5.1 Remote keyless system authentication The ECC based remote keyless entity authentication system has various processes to be carried out between the key fob and the car. In the key fob, secret key generation, public key calculation and nonce decryption 92 K. Arunachalam et al.; Informacije Midem, Vol. 52, No. 2(2022), 89 – 103 Stage 2: Encrypted Nonce. processes are performed. In the car module, random nonce encryption and verification of decrypted nonce received from the key fob takes place. The overall diagram describing the process is given in Figure 3. In the Car The Car will transmit the encrypted nonce with the plain text through the Transceiver. In Key Fob The key fob receives the encrypted 256-bit randomly generated plain text nonce. Then the Key fob performs the decryption of the nonce using the 256-bit Private Key. Stage 3: Nonce Transmission. Figure 3: Block Diagram of Remote keyless system authentication Process In Key Fob After decryption, the key fob transmits the nonce to the Car. The above processes are accomplished in three stages as specified in Figure 4. They are described as follows, In the Car The Car compares the received nonce with the original nonce generated at STAGE 1. If they are matched, then the Car door will be unlocked, otherwise not. Stage 1: The authentication process starts when the car key fob is pressed. In Key Fob In the first stage, when the user wishes to unlock the car door, he initiates the key fob. Two 256-bit random numbers are generated in the key fob with the help of the Linear Feedback Shift Register (LFSR). Among those, one is the Public key and another is the Private Key. The Private Key is kept confidential by the key fob. The 256-bit Public key would be transmitted to the Car through the transceiver module. Both the Public and Private keys are known to key fob alone. 5.2 ECC The ECC core chooses a point on the ECC curve in Koblitz coordinates P(X, Y, Z) and finds the point Q(X, Y, Z)=k × P. The system controller releases necessary control signals to produce the desired output Q as shown in Figure 5. Private key: nA, where nA is a 256-bit Random number. Public key: PA=nA × G, where nA is the Private key generated by the user (Key fob) and G is the point on the Elliptic Curve. Encryption: Cm = {kG, M+K PA} (cipher text), where K is the random integer chosen at the beginning and M is the Mapped point on the Elliptic curve. Message=(M+(K × PA)) - (K × G × nA), Because PA=nA × G, M(plaintext) In the Car The Car receives the Public key and then, it generates a 256-bit random text (cipher text or plain text) using Linear Feedback Shift Register. Thereafter, plain text encryption takes place with the Public key. The sequence of plain text generation process is same for one complete process. Figure 5: Overall ECC Processor architecture Figure 4: Three stages of Communication between Key Fob and Car 93 K. Arunachalam et al.; Informacije Midem, Vol. 52, No. 2(2022), 89 – 103 Where M is the message point corresponding to the message. The Encryption operation generates a pair of points {C1, C2}. Point addition is a computation method used to add two different points over a finite field. Here, λ is the slope of the two points. Its computation is different for point addition and point doubling as shown in equations (1) and (2). Subtraction is performed employing two’s complement addition. λ= Y2 − Y1 (1) X 2 − X1 λ= 3x12 + a (2) 2Y1 Figure 6b: Architecture for Calculating Y3 Point doubling is performed using multiplication architecture with both inputs the same. Here also division is necessary to compute point doubling. The point addition has been performed with equation (3) and the hardware architecture is shown in Figure 6. The multiplications are performed with shift and add method with modulus operation. Figure 7: Architecture for Point Multiplication of the input point. Then a loop is needed to run this algorithm. So, the serial shift register is used during every iteration. The sequence of iterations should be from n-2 to 0. The integer value which needs to be multiplied with the point is loaded into the shift register. Once it gets loaded, shifting should start from (n-2)-th bit to the 0th bit. The shifted bit decides which operation will be performed and what content will be loaded into the registers. If it is 1, the first register is loaded with point addition result and the second register is loaded with point doubling result. If it is 0, then the second register loaded with point addition result and the first register is loaded with point doubling result. Once all bits get shifted out, the multiplication of the point with the integer is stored in the first register. Figure 6a: Architecture for Calculating X3 X 3 = λ 2 − X1 − X 2 Y3 = ( X 1 − X 3 ) λ − Y1 (3) Point Multiplication Point multiplication [6] is the operation that multiplies a point with an integer. Montgomery ladder technique is used to perform point addition and point doubling in parallel. In this algorithm, two registers are used to store the intermediate results. Initially, one register loaded with an input point and another loaded with doubling 94 K. Arunachalam et al.; Informacije Midem, Vol. 52, No. 2(2022), 89 – 103 Point Multiplication Algorithm: Q1 ←P; Q2 ←2P; for i from n−2 down to 0 do if ki =1 then Q1 ←Q1+Q2; // point addition Q2 ←2Q2; // point doubling else Q2 ←Q1+Q2; // point addition Q1 ←2Q1; // point doubling end if; end for; return Q1; Modular Multiplication Algorithm: Formula : C =(A·B) mod p ; C ←0; T ←B&‘1’; while T(n−1 downto 0) != 0 loop C ←2C; If Tn =1 then //nth bit of T C ←C +A; end if; C ←C mod p; T←T(n−1downto0)&‘0’; //left-shift operation end loop; return C; Figure 8: Architecture for Modular Multiplication The above algorithm is implemented as shown in Figure 8. In order to perform the multiplication of two integers, left shift and adder are used in this architecture. In this method, a multiplier loaded with the shift register and multiplicand is given to the adder circuit as shown in Figure 8. The shift-left register is used to perform a synthesizable loop operation for the left to right bitwise multiplication. The comparisons C ≥ p and C ≥ 2p are performed by checking the sign bits of the differences C−p and C −2p, respectively. At the end of every iteration, T is shifted to the left by one bit. After performing ‘n’ iterations, T(n−1 down to 0) is shifted to zero value and the content of the accumulator is stored in register ‘Reg C’, which is the final modular product of integers A and B. The module comprises two multiplexers, in which MUX1 is used to keep the content of the accumulator unchanged if Tn = 0; or add A to the accumulator if Tn = 1; and MUX2 is used for performing C mod p. At (n+1)th clock cycle, the result for multiplication of two inputs is available. To determine the end of the loop, a (n+1)-bit temporary variable T is used in which T (n down to 1) is precomputed as the multiplier B and the least significant bit (LSB) of T is pre-computed as 1. One extra bit is added at the LSB to cope with the completion of the leftshift operation in the case of b0 = 0. The multiplicand A is added to the accumulator in each iteration if the most significant bit (MSB) of T is 1. The content of the accumulator is then reduced to modulo p after every addition. In order to perform this modular operation, C is subtracted by the prime numbers p and 2p. As the content of the accumulator is always less than 3p, subtractions by p and 2p are enough to confine the content below the value of p. The subtractions C − p and C −2p are performed by adding the 2’s complement of the subtrahends p and 2p to the minuend C. 5.3 2*2 Vedic multiplier Considering two-bit numbers A (A1A0) and B (B1B0), the 2×2 Vedic multiplication is carried out as depicted in Figure 9. The logical expression of the final product is as shown in equation 4, P0 = A0 .B0 P1 = ( A1.B0 ) ⊕ ( A0 .B1 ) P2 = ( A0 . A1.B0 .B1 ) ⊕ ( A1.B1 ) P3 = A0 . A1.B0 B1 (4) This process consumes 4 AND gates and 2 EXOR gates. 95 K. Arunachalam et al.; Informacije Midem, Vol. 52, No. 2(2022), 89 – 103 (Pi - P7…P0) [25]. Here, the pipeline technique is introduced at 3 levels mentioned in Figure 10 (numbered 1, 2 and 3) by means of inserting registers. Similarly, higher order Vedic multipliers are constructed with the 2-bit VMi as the base module and RCA adders for summation of the partial products. The n-bit Vedic multiplier uses four n/2-bit multipliers, two n-bit RCA adders, one n/2bit adder, and one Half adder as shown in Figure 10. 6 Results and discussion 6.1 FPGA implementation and analysis This section presents the FPGA implementation for the proposed ECC processor architecture. The necessary parameters such as curve order, coefficients and base point coordinates are selected based on the NIST standard. Here, we have considered a 256-bit ECC processor. The ECC processor is designed using Verilog HDL and simulated using ModelSim. It was synthesized, placed and routed using Xilinx ISE 14.6. In the proposed methodology, the used FPGA platforms were Virtex- 6 (XC6VLX240T-1FF1156) and Virtex-7 (XC7VX485T-2FFG1761C) with the goal to achieve optimal speed and area. The implementation results of the proposed 256bit ECC module are summarized in Table 2. In which, the ECC is implemented with or without pipeline in Vedic multiplier. Figure 9: Graphical representation of 2*2 Vedic multiplication steps 4*4 Vedic multiplier The 4-bit Vedic multiplier comprises four 2-bit Vedic multipliers, three 4-bit full adders & one half adder gate. The two 4-bit inputs Ai (A3A2A1A0) and Bi (B3B2B1B0) are applied to the 2-bit Vedic multiplier, and then they are forwarded to the 4-bit adder. The output from the RCA adder consists of 4-bit sum output and a 1-bit carry value. The half adder is used to sum the carry at the first two phases of the ripple carry adder. The output of the 4-bit multiplier consists of an 8-bit product term The performance factors throughput and efficiency are calculated based on equation (5) [6, 22, 26, 27]. Cycle = Time for one ECPM × maximum frequency AT/Bit = Area-Delay product / Number of Bits Throughput = (maximum frequency × number of bits) / number of clock cycles Efficiency = Throughput / area (5) The Simulation results of point addition, point doubling, public key calculation, data encryption and decryption are shown in Figure 11 (a-e). In Figure 11a, the input points are (a,b) (c,d) and the resultant point addition is available in (x3, y3). It is produced in 945 clock cycles. Figure 11b shows the simulation result of point doubling, where (xp,yp) are input point and the result (x3, y3) is produced in 430 clock cycles. Figure 11c shows the simulation result of public key generation. The complete ECPM simulation is shown in Figure 11d, which is completed in 232.21k clock cycles. When the interim states are having less than 256-bits, then the ECPM gets completed in fewer cycles. The pipelined Vedic multiplier based ECC implemented on Virtex-7 occupies 8.23k slices, takes 32.2k clock cy- Figure 10: Generalized construction of n-bit Vedic Multiplier 96 K. Arunachalam et al.; Informacije Midem, Vol. 52, No. 2(2022), 89 – 103 Figure 11a: Simulation Result of Point Addition Figure 11b: Simulation Result of Point Doubling Figure 11c: Simulation Result of Public Key Calculation Figure 11d: Simulation Result of Encryption 97 K. Arunachalam et al.; Informacije Midem, Vol. 52, No. 2(2022), 89 – 103 Figure 11e: Simulation Result of Decryption cles for process completion, the maximum operating frequency is 192.5MHz, and the process takes 0.9365ms to complete. The Area-Delay product and throughput are 7.922 and 273.36kbps, respectively. The pipelined ECC has 32.31% efficiency. The pipelined Vedic ECC has 22.36% and 20.18% improvement in throughput and efficiency with respect to non-pipelined implementation. This is due to the increased frequency of operation (226.8MHz) of pipelined architecture. It leads to additional 2.72% overhead on the area; but the areadelay overhead is reduced by 20.19%. Table 2: Performance of Proposed Vedic multiplier based ECC Platform No Pipeline Pipeline No Pipeline Pipeline Percentage of improvement Virtex-7 Virtex-6 Virtex-7 Virtex-6 Number Number of Slices of bits (k) 8.23 8.46 8.82 256 9.12 2.72 3.29 Clock Maximum Area Time Throughput Cycles Frequency Delay AT/B Efficiency (ms) (kbps) (k) (MHz) Product 232.2 192.5 1.2062 9.927026 0.0387774 212.23 25.79 212.4 226.8 0.9365 7.92279 0.0309484 273.36 32.31 232.2 186.2 1.247 10.99854 0.042963 205.29 23.27 212.4 216.8 0.98 8.9376 0.0349125 261.3 28.65 8.53 15.12 22.36 20.19 20.19 22.36 20.18 8.53 14.11 21.41 18.74 18.74 21.44 18.78 Table 3: Performance comparison of Proposed ECC Ref Year woP wP Ours woP wP 26 2020 26 2020 28 2019 28 2019 29 2018 Platform Virtex-7 Virtex-6 Virtex-7 Virtex-6 Virtex-7 Virtex-6 Virtex-6 30 2018 Virtex-4 31 32 33 34 27 35 36 2017 Kintex-7 2017 Virtex-7 2017 Virtex-4 2017 Virtex-4 2016 Virtex-4 2016 Virtex-4 2016 Virtex-5 Number Clock Maximum Number Time Area Delay of Slices Cycles Frequency of bits (ms) Product (k) (k) (MHz) 8.23 232.2 192.5 1.2062 9.927026 8.46 212.4 226.8 0.9365 7.92279 256 8.82 232.2 186.2 1.247 10.99854 9.12 212.4 216.8 0.98 8.9376 256 6.5 198.7 104.39 1.9 12.35 256 6.6 198.7 93.23 2.13 14.05 256 8.9 262.7 177.7 1.48 13.17 256 9.2 262.7 161.1 1.63 15.00 256 65.6 153.2 327 0.47 30.83 9.4 + 256 610 20.44 29.84 280.5 14DSPs 256 11.3 397.3 121.5 3.27 63.95 256 24.2 215.9 72.9 2.96 71.63 193 12 459.9 36.5 12.6 151.2 256 20.6 191.6 49 3.91 80.55 256 13.2 200 40 5 66 192 35.7 207.1 70 2.96 105.67 256 8.7 361.6 160 2.26 19.66 woP – Without Pipeline; wP – with Pipeline; ϸ-calculated by author 98 AT/B Throughput Efficiency (kbps) 0.03878 0.03095 0.04296 0.03491 0.0482 0.0549 0.051 0.059 0.120 212.23 273.36 205.29 261.30 134.49 120.12 173.2 157.00 546.42 25.79 32.31 23.27 28.65 20.69 18.20 19.46 17.06 8.33 1.096 8.58 0.91 0.144 0.280 0.783 0.315 0.258 0.550 0.077 78.28 1816.20 20.32 65.47 51 86.53 113.27 6.92 3.57 1.69 3.18 3.88 2.42 13.02 K. Arunachalam et al.; Informacije Midem, Vol. 52, No. 2(2022), 89 – 103 Table 4: Security Evaluation criteria The same pipelined architecture has 261.30kbps throughput and 28.65 efficiency in Virtex 6. The pipeline structure has 21.44% and 18.78% improvement in throughput and efficiency with respect to nonpipelined implementation with 3.29% area overhead. Significantly, the maximum frequency of operation and time consumption are improved by 14.11% and 21.41% respectively. Short Form C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 The performance characteristics of ECC implementation in FPGA are shown in Table 3. Here, varieties of FPGA families such as Virtex-4, 5, 6, 7 and Kindtex-7 are used for implementation purposes. Most of the researchers designed for the 256-bit size ECC, except in [33, 35], where 192 and 193-bit are considered respectively. The significant performance factors considered for the analysis are Area, the number of clock cycles, maximum operating frequency, area-delay product, throughput and efficiency. Evaluation Criteria No password verifier-table Resist password guessing threat Defend replay attack Defend session key temporary information attack Accurate login and password change phase Defend user un-traceability attack Mutual authentication Facilitates user anonymity Defend insider attack Facilitates forward secrecy property Table 5: Security comparison among the authentication schemes Ref. Year From Table 3, it is observed that higher frequency of operation leads to a reduction in the required number of clock cycles, completion time and increases the throughput. The proposed pipelined Vedic multiplier has an optimized area, speed and throughput. The ECC based security systems are performing well against the attacks [37] such as algebraic attack, brute force attack and statistical attack [38, 39] and protects confidential data hiding in spatial images [40]. Ours 42 43 44 45 46 51 47 48 49 50 In [6], efficiency is calculated using throughput and area, which is represented in the equation (5). The same has been calculated and shown for comparison in Table 3. The efficiency of the proposed method is comparatively better with respect to all the previous works. Moreover, the pipelining of the multiplication process increases the efficiency by another 25%. The earlier FPGA studies using Virtex-I Pro, Virtex-E and Spartan 4 are omitted for comparison in Table 3 due to their nature of high power consumption and the limited number of Input/Outputs. 2022 2022 2020 2019 2019 2018 2018 2018 2018 2018 2017 C1 P P P P P P × P P P P C2 P P P P P P P P × P P C3 P P P P P P × P P P P Evaluation Criteria C4 C5 C6 C7 C8 P P P P P P × P P P P × × P P P × × P P P × P P P P × × P P P P P P P P × × P P P × × P P P × × P P P × × P P C9 C10 P P P P P P P P × × × P P P × P × P × × × × Table 6: Evaluation of computational cost Ref. Year Ours 42 43 44 45 46 51 47 48 49 50 6.2 Security Evaluation and Analysis The security evaluation criteria which are essential for the Remote Keyless Entry system are shown in Table 4. In order to illustrate the effectiveness of the proposed ECC scheme evaluation, a comparative assessment of 10 schemes for the RKE system has been done. By evaluating the 10 criteria of security attacks stated in [41, 42, 51] the performance of the proposed Vedic based ECC has been evaluated. The results are summarized in Table 5. 2022 2022 2020 2019 2019 2018 2018 2018 2018 2018 2017 Authentication User Car Sensor Tbe + 2TH TS + 2TH Tbe + 3TH Tse + 4TH + TS Tbe + 3TH Tse + TS + 4TH TPM + 3TH 2TPM + 4TH 5TH 5TH TC + 3TH 2TC + 6TH 5TH 11TH TPM + 2TH 2TPM + 4TH 6TH 5TH 8TH 6TH 5TH + TS 7TH + TS Time Period (Sec) User Car Sensor Total 0.0600 0.5733 0.6333 0.0605 0.583 0.6435 0.0605 0.583 0.6435 1.0518 2.0523 3.1041 0.0528 0.0528 0.1056 0.5738 1.0973 1.6711 0.0528 0.0558 0.1086 1.0513 2.0523 3.1036 0.0533 0.0528 0.1061 0.0543 0.0533 0.1076 3.0615 0.5758 3.6373 TH: time complexity of a hash function; TPM: the time complexity of ECC point multiplication operation; TS: time complexity of a symmetric key encryption/decryption operation; TME: time complexity of a modular exponentiation operation 99 K. Arunachalam et al.; Informacije Midem, Vol. 52, No. 2(2022), 89 – 103 In order to evaluate the execution time of the proposed protocol and relevant protocols, we have assumed that the hash function, modular exponentiation operation, a symmetric key encryption/decryption operation and point multiplication operation require 0.0005 seconds, 0.522 seconds, 0.0087 seconds and 0.0503 seconds [51], respectively. The computation cost for the RKE is estimated and compared with the existing literature in Table 6. It is observed that the proposed method is competent in computation cost with the previously published works. The proposed RKE has 1.58% improvement compared to the recently available method [42]. Hence, the proposed pipelined vedic ECC can be incorporated in RKE for effective secured communication of various applications such as smart cards [52], mobile devices [53] and wireless sensor networks [42]. 8 Conflicts of interest The authors declare that there are no conflicts of interest regarding the publication of this manuscript. 9 References 1. 2. 7 Conclusion 3. In this paper, a high-speed, area-efficient ECC processor is designed on the Koblitz curve secp256k1 for the Remote Keyless Authentication system. It supports 256-bit point addition and point multiplication over a prime field. A novel method of multiplication using Urdhva Tiryagbhyam is adopted for scalar multiplication. The speed of multiplication is improved by incorporating the pipeline technique. The proposed pipelined Vedic multiplier based ECC processor is implemented in the Xilinx Virtex-7 and Virtex-6 platforms for the 256-bit prime field. The implemented processor performs a single 256-bit multiplication in 1.2062ms with a maximum clock frequency of 192.5MHz, which provides 212.23kbps throughput and occupies 8.23k slices in Virtex-7 FPGA. Incorporating pipeline in scalar multiplication improves the maximum clock frequency up to 15.12%, and reduces time by 22.36%, which in turn increases the throughput by 22.36%. The pipeline has an additional area overhead of 2.72% and 3.29% in Virtex-7 and Virtex-6 respectively. Also, the computational cost of the proposed method is evaluated, which shows 1.58% improvement from the most recent literature. The pipelined Vedic multiplier based ECC processor outperforms the existing designs in terms of area, clock cycle count, operating frequency, time, area-delay product, throughput, efficiency and security. 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This is an open access article distributed under the Creative Commons Attribution (CC BY) License (https://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 04. 01. 2022 Accepted: 16. 05. 2022 103 104 Original scientific paper https://doi.org/10.33180/InfMIDEM2022.204 Journal of Microelectronics, Electronic Components and Materials Vol. 52, No. 2(2022), 105 – 115 Electronically Tunable Mixed Mode Universal Filter Employing Grounded Passive Components Ramesh Mishra1, Ganga Ram Mishra2, Shri Om Mishra1 , Mohammad Faseehuddin3 Department of Physics and Electronics, Dr. Rammanohar Lohia Avadh University Ayodhya U.P., India Department of Physics & Electronics, Dr. Rammanohar Lohia Avadh University, India 3 Department of Electronics and Telecommunication, Symbiosis Institute of Technology (SIT), Symbiosis International University (SIU), Lavale, Mulshi, Pune, Maharashtra, India 1 2 Abstract: A recently developed active element, namely Voltage Differencing Differential Voltage Current Conveyor (VD-DVCC), is employed in the design of electronically tunable mixed-mode universal filter. The filter provides low pass (LP), high pass (HP), band pass (BP), band reject (BR) and all pass (AP) responses in voltage-mode (VM), current-mode, trans-impedance-mode (TIM) and trans-admittance-mode (TAM). The filter employs two VD-DVCCs, three resistors and two capacitors. All the passive components employed are grounded. The attractive features of the filters include: (i) ability to operate in all four modes, (ii) use of grounded passive components, (iii) tunability of Q factor independent of pole frequency, (iv) high input impedance for VM and TIM mode, (v) high output impedance explicit current output for CM and TAM and (vi) no requirement for double/negative input signals (voltage/current) for response realization. The VD-DVCC is designed and validated in Cadence virtuoso using 0.18 µm PDK at supply voltage of ±1 V. The operation of filter is examined at 5.305 MHz frequency. The non-ideal gain and sensitivity analysis is also carried out to study the effect of process and components spread on the filter performance. The obtained results bear close resemblance with the theoretical findings. Keywords: communication, mixed-mode, current conveyor, filter, signal processing, VD-DVCC Elektronsko nastavljiv univerzalni filter mešanega načina z ozemljenimi pasivnimi komponentami Izvleček: Nedavno razviti aktivni element napetostni diferenčni napetostni tokovni transporter (VD-DVCC) je uporabljen pri zasnovi elektronsko nastavljivega univerzalnega filtra z mešanim načinom delovanja. Filter omogoča nizko prepustnost (LP), visoko prepustnost (HP), pasovno prepustnost (BP), pasovno zavrnitev (BR) in vse prepustne odzive (AP) v napetostnem (VM), tokovnem, trans-impedančnem (TIM) in trans-admitančnem (TAM) načinu. Filter uporablja dva VD-DVCC, tri upore in dva kondenzatorja. Vse uporabljene pasivne komponente so ozemljene. Privlačne lastnosti filtrov so: (i) možnost delovanja v vseh štirih načinih, (ii) uporaba ozemljenih pasivnih komponent, (iii) nastavljivost faktorja Q neodvisno od frekvence polov, (iv) visoka vhodna impedanca za način VM in TIM, (v) visoka izhodna impedanca z eksplicitnim izhodnim tokom za CM in TAM ter (vi) ni potrebe po dvojnih/negativnih vhodnih signalih (napetost/tok) za realizacijo odziva. VD-DVCC je zasnovan in preverjen v Cadence virtuoso z uporabo 0,18 µm PDK pri napajalni napetosti ±1 V. Delovanje filtra je preverjeno pri frekvenci 5,305 MHz. Izvedena je tudi analiza neidealnega ojačenja in občutljivosti, da bi preučili vpliv razpršenosti procesa in komponent na delovanje filtra. Dobljeni rezultati so zelo podobni teoretičnim ugotovitvam. Ključne besede: komunikacija, mešani način, tokovni transporter, filter, obdelava signalov, VD-DVCC * Corresponding Author’s e-mail: rameshmishra1985@gmail.com 1 Introduction range, wide bandwidth, simple structure, low power consumption and greater linearity [2-3]. Numerous filter structures employing CM-AEs can be found in the literature [1, 3]. Most of the proposed filters can work The current mode-active elements (CM-AEs) are extensively employed in designing universal frequency filters [1-4]. The CM-AEs exhibits enhanced dynamic How to cite: R. Mishra et al., “Electronically Tunable Mixed Mode Universal Filter Employing Grounded Passive Components", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 52, No. 2(2022), pp. 105–115 105 R. Mishra et al.; Informacije Midem, Vol. 52, No. 2(2022), 105 – 115 only in single mode of operation i.e. voltage-mode (VM), current-mode (CM), trans-admittance-mode (TAM), and trans-impedance-mode (TIM) [1-3,5]. In present day complex signal processing systems, the interaction between CM and VM circuits is required. This task can be performed by TAM and TIM filters that not only perform signal processing, but also provide interfacing between VM and CM systems [6-10]. The development of mixed-mode universal filters that can provide LP, HP, BP, BR and AP responses in CM, VM, TAM and TIM modes of operation are best suited for the task. sign of mixed-mode filter. The design requires two VDDVCCs, two capacitors, and three resistors. The striking features of the proposed filter are: (i) ability to work in all four modes of operation, (ii) provision for inbuilt tunability, (iii) the filters enjoy low active and passive sensitivities, and (iv) use of all grounded passive components. Beside these the filters enjoy all the properties mentioned in Table 1 except (vii). The design and simulation of the VD-DVCC is done in Cadence Virtuoso using 0.18µm PDK. The simulation results bear close resemblance with the theoretical findings. Numerous exemplary mixed-mode filter topologies have been developed [6-41] that employ CM-AEs. The mixed mode filters can be categorised into two groups (i) single input multi output (SIMO), (ii) multi input single output (MISO) structures. The filter structures [6-10, 12-13, 15-19, 22-24, 28, 31-33, 35, 37-39, 41] employ CM-AEs in excess of two. The designs in [6-7, 10,12,22,28-30, 36, 37, 39] employ more than five passive components. The filter structures in [6, 7, 10-12, 14, 20-22, 25, 27-30, 34, 36, 39, 48-52] does not employ all grounded passive components. The filters in [6-7, 9-13, 18, 19, 21, 24, 25, 27, 30, 32, 33, 36, 39] do not provide frequency control independent of quality factor. The filter topologies [6, 8, 9, 11, 13, 15, 16, 18, 21, 23, 25, 2628, 32, 34, 41, 50] do not provide all five filter responses in VM, CM, TAM, and TIM operation. The filter structures [6, 7, 10-12, 14, 16, 22, 25, 27-30, 34, 36, 37, 39, 41] lack inbuilt tunability. Some recent designs of the mixed mode filters proposed by the authors [48-52] suffer from one or more of the above discussed drawbacks. A detailed comparison of the state-of-the-art MISO filters with the proposed design is presented in Table 1, based on the following important measures of comparison: (i) number of CM-AEs employed, (ii) number of passive components needed, (iii) employment of all grounded passive components, (iv) no requirement for resistive matching except for obtaining a single response, (v) provision to control quality factor (Q) independent of the centre frequency, (vi) ability to provide all five filter responses in all four modes of operation, (vii) low output impedance for VM and TIM modes, (viii) availability of explicit current output in CM and TAM, (ix) no requirement for double/negative input signals (voltage/ current), (x) inbuilt tunability, and (xi) test frequency. 2 Voltage differencing differential voltage current conveyor (VD-DVCC) The VD-DVCC is a newly proposed [42] CM-AE that possess features of Differential Voltage Current Conveyor (DVCC) [41] and Operational Transconductance Amplifier (OTA). The voltage current relations of the VD-DVCC are given in Equations (1)-(4) and the block diagram is shown in Figure 1. IW = IWC + = − IWC − = g m (VP − VN ) (1) VX = VY 1 − VW (2) I X = I Z + = − I Z − (3) IY 1 = I w = 0 (4) It can be inferred from the literature review and table 1 that not all the proposed mixed mode filter structures work in all four modes of operation. It is also deduced from the literature survey that limited number of mixed-mode filters are available and to fill this technological void additional novel mixed-mode filter structures are needed. In this research, a recently developed CM-AE, the Voltage Differencing Differential Voltage Current Conveyor (VD-DVCC) is utilized in de- Figure 1: Block Diagram of VD-DVCC The CMOS implementation of VD-DVCC is presented in Figure 2. The transistors M19-M32 forms the OTA section. The output current of the OTA assuming all tran106 R. Mishra et al.; Informacije Midem, Vol. 52, No. 2(2022), 105 – 115 Figure 2: CMOS implementation of VD-DVCC sistors in saturation region and equal width and length for (M19-M20) will be IW = IWC = gm(VP – VN). The expression for gm is given in Equation 5. g m = µnCOX will accommodate the parasitic resistance present at X terminal. The important features of the filter include: (i) use of grounded passive components, (ii) employment of minimum number of passive components, (iii) no need for capacitive matching, (iv) no requirement for resistive matching except for AP response, (v) high input impedance in VM and TIM configuration, (vi) ability to provide all five filter responses in all four modes of operation, (vii) availability of explicit current output in CM and TAM, (viii) no requirement for double/negative input signals (voltage/current), and (xi) inbuilt tunability. The operation of the filter in all modes is explained below. W I B (5) L Where COX is the gate oxide capacitance, µn is the mobility of electrons in NMOS, gm denotes the transconductance of OTA set via bias current IB and W/L is the aspect ratio of the transistors. Extra copies of the OTA current can be utilized, if necessary, for the applications. The second stage comprising of transistors M1-M18 provides algebraic summation of input voltages and current transfer function. The voltage at the X terminal is the algebraic sum of voltages at W and Y1 terminals. The input current at the X terminal appears at the Z+ and Z- terminals, multiple copies of the current can be easily generated just by adding two extra transistors. The N, P, Y1 terminals are high impedance voltage input terminals. The W, WC+, WC-, Z + and Z - are high impedance current output terminals. The X terminal is low impedance current input terminal. Figure 3: Proposed Mixed-mode Filter 3 Proposed electronically tunable mixed-mode universal filter 3.1 Operation in VM and TAM mode: In this mode of operation, the inputs currents (I1 – I3) are set to zero. The filter is excited with input voltages (V1 – V3) as per the sequence given in Table 2. The Equations (10-11) give the filter response in VM and TAM modes of operation. The frequency and quality factor are given by Equations (12-13). It can be deduced from the Equations that the Q can be controlled independent of frequency. For all pass response a simple resistive matching of (R1 = R2) is required which is easy to achieve. The proposed filter as presented in Figure 3 requires two VD-DVCCs, two capacitors, and three resistors all grounded for the design. For VM and TAM mode of operation the filter has high input impedance. In addition, the CM and TAM responses are available from explicit high impedance terminals. Furthermore, in the design the capacitors are connected to high impedance terminals so they will absorb the parasitic associated with the terminals. Among the three resistors two are connected to the low resistance X terminal so they 107 R. Mishra et al.; Informacije Midem, Vol. 52, No. 2(2022), 105 – 115 s 2C C R R V − SC1 R2V3 + R2 g m 2V2 = 2 1 2 2 3 1 s C1C2 R1 R3 + g m1SC1 R3 R2 + R2 g m 2 Vout In Equation 15 the filter gain constants are H oLP = , g2 H oHP = g1 R2 , H oBP = 1 by adjusting these parameters the filter gain can be adjusted. (10) , In Equation 10 the filter gain constants are H oLP = 1 R H oHP = 2 , H oBP = g1 R2 by adjusting these parameters R1 the filter gain can be adjusted. As special case for notch pass or bad reject realization if R2 > R1 then high pass notch (HPN) is obtained and if R2 < R1 low pass notch (LPN) response is obtained. Table 3: Input current excitation sequence Response LP HP BR NP AP I out (TAM ) = g m1Vout I out (TAM )  s 2C C R R V − SC1 R2V3 + R2 g m 2V2  = g m1  2 1 2 2 3 1   s C1C2 R1 R3 + g m1SC1 R3 R2 + R2 g m 2  (11) 1 2π g m 2 R2 C1C2 R1 R3 (12) Q= 1 g m1 C2 g m 2 R1 C1 R2 R3 (13) LP HP BP BR AP V1 0 1 0 1 1 Matching Condition V3 0 0 1 1 1 No No No No R1 = R2, R3g1 = 1 3.2 Operation in CM and TIM mode: In this mode of operation all input voltages () are set to zero. The input currents () are applied according to Table 3. The transfer function for CM and TIM are given in Equations (14)-(15). The complete analysis of the circuit is given below. Matching Condition I3 1 0 0 1 1 No No No No g1R2 = 1, g1 = g2 The non-ideal analysis considering the effect of nonideal current, voltage, and transconductance transfer gains is carried out for MISO (VM, CM, TAM and TIM) configurations to see its effect on the transfer function, f0, and Q of the proposed filters. The modified expressions of filter transfer functions, f0‘, and Q‘ for the MISO configuration are presented in Equations (16)-(21).  s 2C C R R R I − SC1 R3 R2 I1 + R2 I 3  Vout (TIM ) =  2 1 2 1 3 2 2  (14)  s C1C2 R1 R3 + g m1SC1 R3 R2 + R2 g m 2  I out (CM ) = g m1Vout  s 2C C R R g R I − SC1 R3 g m1R2 I1 + g m1R2 I 3  I out (CM ) =  1 22 1 3 m1 2 2  s C1C2 R1 R3 + g m1SC1 R3 R2 + R2 g m 2   Inputs I2 0 1 0 1 1 The non-ideal model of the VD-DVCC is given in Figure 5. As can be deduced, various parasitic resistance and capacitance appear in parallel with the input and output nodes of the device. The low impedance X node has a parasitic resistance and inductance in series with it. Other non-ideal effects that influence the response of the VD-DVCC are the frequency dependent non-ideal current (), voltage (), and transconductance transfer (γ, γ‘) gains. These non-ideal gains result in a change in the current and voltage signals during transfer leading to undesired response. Taking in account the non-ideal gains the V-I characteristics of the VD-DVCC in (1) will be modified as follows: IW = 0, VX = β(V1 – VW), IZ+ = αpIX, IZ= αNIX, IW = IWC+ = γgm(Vp – VN), IWC- = -γ‘gm(Vp – VN) where βm = 1 – εvm, αPm = 1 - εiPm, αNm = 1 - εiNm, γm = 1 – εgmm, (***drugi m subsub***) and γ‘m = 1 – ε‘ gmm (***drugi m subsub***) for m = 1, 2, which refers to the number of VD-DVCCs. Here, εvm (|εvm| « 1) denote voltage tracking error, εiPm, εiNm (|εim|, |εiNm| « 1) denote current tracking errors, and εgmm, ε‘gmm (|εgmm|, |ε‘gmm| « 1) (***drugi m subsub***) denote transconductance errors of the VD-DVCC. Table 1: Excitation Sequence for VM and TAM Inputs V2 1 0 0 0 1 I1 0 0 1 0 1 4 Non-Ideal and Sensitivity Analysis fo = Response g1 (15) 108 R. Mishra et al.; Informacije Midem, Vol. 52, No. 2(2022), 105 – 115 Table 2: Comparative study of the state-of-the-art MISO Mixed mode filter designs with the proposed filter References [9]/2003 [7]/2004 [12]/2006 Mode of Operation MISO MISO MISO (i) 6-OTA 7-CCII 3-CCII (ii) 2C 2C+8R 3C+4R+ 2-switch [13]/2008 MISO 4-OTA 2C [19]/2010 MISO 5-OTA 2C [20]/2010 MISO 2-MOCCCII 2C+2R [27]/2010 MISO CFOA 2C+3R [24]/2013 MISO 4-MOCCCII 2C [25]/2013 MISO 1-FDCCII 2C+2R [26]/2013 MISO 2-VDTA 2C [29]/2016 MISO 1-FDCCII+1- 2C+6R DDCC [37]/2018 MISO 5-DVCC 2C+5R [40]/2018 MISO 4-CCII 2C+4R [38]/2019 MISO 5-OTA 2C [39]/2020 MISO 3-DDCCII 2C+4R [48]/2020 MISO/SIMO 2-EXCCTA 2C+4R [49]/2021 MISO 2-VD-DVCC 2C+3R [50]/2021 MISO 2-VDBA 2C+2R [51]/2021 MISO 3-VDBA 2C+R [52]/2022 MISO 1-VD-EXCCII 2C+2R This Works MISO 2-VD-DVCC 2C+3R (iii) (iv) (v) (vi) (vii) (viii) (ix) (x) (xi) Yes No No Yes Yes No No No No No Yes Yes No No No Yes Yes Yes Yes Yes Yes Yes No No - Yes Yes No No Yes No Yes No Yes Yes Yes No Yes Yes Yes Yes No No Yes Yes No No Yes Yes No Yes Yes No Yes No No Yes No No No No Yes No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No No Yes Yes No Yes Yes Yes No Yes No Yes No 2.25 MHz 1.59 MHz 1.27 MHz 12.7MHz 10 MHz 1 MHz 1.59 MHz Yes Yes Yes No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes No Yes Yes Yes No No No No No No Yes Yes No No Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes No Yes Yes Yes Yes Yes Yes 1MHz 31.8 MHz 3.390 MHz 3.978 MHz 7.622 MHz 5.305 MHz 1.52 MHz 16.631 MHz 8.08 MHz 5.305 MHz * Full nomenclature of the mentioned CM-AEs in Tables 1 and 2 in alphabetical order: CCCCTA: Current controlled current conveyor transconductance amplifier, CCII: Second-generation current conveyor, CFOA: Current feedback operational amplifier, DDCC: Differential difference current conveyor, DPCCII: Digitally programmable second-generation current conveyor, DVCC: Differential voltage current conveyor, EXCCTA: Extra X current conveyor differential input transconductance amplifier, FDCCII: Fully differential second-generation current conveyor, FTFN: Four terminal floating nullor, ICCII: Inverting second-generation current conveyor, MOCCCII: Multi output current controlled current conveyor, MOCCII: Multi output second-generation current conveyor, OTA: Operational transconductance amplifier, VDTA: Voltage differencing transconductance amplifier, VDBA: Voltage differencing buffered amplifier, VD-EXCC: Voltage differencing extra X current conveyor  s 2C1C2 R2 R3α P1β1V1 − SC1 R2α P 2 β 2α P1β1V3 + α P 2 β 2γ 2 g m 2 R2 g 2V2  ' Vout =  (VM − Mode)  s 2C1C2 R1 R3 + g m1SC1 R3 R2α P1β1γ 1 + α P 2 β 2γ 2α P1β1 R2 g m 2    s 2C1C2 R2 R3α P1β1V1 − SC1 R2α P 2 β 2α P1β1V3 + α P 2 β 2γ 2 g 2 R2 g m 2V2  = γ 1 g m1   s 2C1C2 R1 R3 + g m1SC1 R3 R2α P1β1γ 1 + α P 2 β 2γ 2α P1β1 R2 g m 2   (16) I ' out (TAM − Mode) I ' out (CM − Mode)  s 2C1C2 R1 R3 R2 I 2 − Sα P1β1C1 R3 R2 I1 + R2α P1β1α P 2 β 2 I 3  = γ 1 g m1  2   s C1C2 R1 R3 + g m1SC1 R3 R2α P1β1γ 1 + α P 2 β 2γ 2α P1β1 R2 g m 2  (18) ' out (TIM − Mode)  s 2C1C2 R1 R3 R2 I 2 − Sα P1β1C1 R3 R2 I1 + R2α P1β1α P 2 β 2 I 3  = 2   s C1C2 R1 R3 + g m1SC1 R3 R2α P1β1γ 1 + α P 2 β 2γ 2α P1β1 R2 g m 2  (19) V 109 (17) R. Mishra et al.; Informacije Midem, Vol. 52, No. 2(2022), 105 – 115 f 0' = Q′ = α P 2 β 2 Υ 2α P1β1 R2 g m 2 1 2π the VD-DVCC is given in Figure 5 it occupies an area of 50.2*21.50µm2. (20) C1C2 R3 R1 Table 4: Width and Length of the MOS transistors α P 2 β 2C2 Υ 2 g m 2 R1 1 α P1β1C1 R2 R3 Υ1 g m1 Transistors M1-M4 M5-M6 M7-M8, M13 M14-M15 M9-M10 M11-M12, M16 M17-M18 M19-M20 M21-M25, M29-M30 M26-M28, M31-M32 (21) Width (µm) 4.5 20 17.5 8.75 8.75 13.5 17.5 1.8 3 8 Length (µm) 0.36 0.36 0.36 0.36 0.36 0.36 0.36 0.36 0.72 0.36 Figure 5: The complete layout of the VD-DVCC The filter is designed for centre frequency of 5.305 MHz and quality factor of 1 by selecting passive component as R1 = R2 = R3 = 2kΩ C1 = C2 = 15pF and gm = 500 µS. The power dissipation of the filter is found to be 3.48 mW. All five filter responses in VM, CM, TAM and TIM modes are presented in Figures 6-13. Figure 4: Non-ideal model of VD-DVCC with parasitics The sensitivities of ω0‘ and Q‘ with respect to the nonideal gains and passive components are given below. ' ' ' ' ' ' ' ' ' ' ' ' ' 1 2 1 = ' 2 S gωmo2 = SαωPo2 = Sβω2o = SαωPo1 = Sβω1o = S Rω2o = Sγω2o = − SCω1o = − SCω2o = − S Rω3o = − S Rω1o = ' ' ' ' ' ' ' ' ' SαQP 2 = SβQ2 = − SCQ1 = SγQ2 = S gQm 2 = SCQ2 = − SαQP1 = − SβQ1 = S RQ1 = − S RQ3 = − S RQ2 − SγQ1 ′ = − S gQm′1 = 1, (22) (23) (24) The sensitivities are low and have absolute values not higher than unity. 5 Simulation and validation To verify the proposed mixed-mode filter it is designed and simulated in Cadence virtuoso design software. The newly proposed VD-DVCC is designed in 0.18 µm Silterra Malaysia technology at a supply voltage of ±1V. The width and length of the transistors used are given in Table 4. The bias current of the OTA is fixed at 47 µA resulting in transconductance of 500 µS. The layout of Figure 6: VM MISO configuration: Frequency responses of the LP, BP, HP, and BR filter To examine the signal processing capability of the proposed universal filter the transient analysis is carried out in VM mode for HP, LP, NP and BP responses. A VM 110 R. Mishra et al.; Informacije Midem, Vol. 52, No. 2(2022), 105 – 115 Figure 11: CM MISO configuration: Gain and phase responses of the AP filter Figure 7: VM MISO configuration: Gain and phase responses of the AP filter Figure 12: TIM MISO configuration: Frequency responses of the LP, BP, HP, and BR filter Figure 8: TAM MISO configuration: Frequency responses of the LP, BP, HP, and BR filter Figure 13: TIM MISO configuration: Gain and phase responses of the AP filter Figure 9: TAM MISO configuration: Gain and phase responses of the AP filter Figure 14: VM MISO configuration: Transient analysis results for BP, HP, LP filter configurations Figure 10: CM MISO configuration: Frequency responses of the LP, BP, HP, and BR filter In the presented filter the quality factor can be set independent of the pole frequency of the filter. The tunability of the quality factor is verified by analysing BP response in CM and TIM for different values of bias current IBIAS1 as shown in Figures 16-17. It can be deduced from figures that the quality factor of the filter can be tuned independent of the frequency. sinusoidal signal of 100 mV p-p and 5.305 MHz frequency is applied at the input and the output is analysed as presented in Figure 14. Similarly, a CM sinusoidal signal of 50 µA p-p and 5.305 MHz frequency is applied at the input and the BP output in CM and TIM is observed as shown in Figure 15. It can be inferred from figures that the filter works correctly. 111 R. Mishra et al.; Informacije Midem, Vol. 52, No. 2(2022), 105 – 115 Figure 15: CM/TIM MISO configuration: Transient analysis results for BP filter configuration Figure 19: VM MISO configuration: The Monte Carlo analysis results for BP configuration Figure 16: CM MISO configuration: Quality factor tuning for different values of OTA bias current Figure 20: TIM MISO configuration: The Monte Carlo analysis results for AP response Figure 17: TIM MISO configuration: Quality factor tuning for different values of OTA bias current in BP filter Figure 21: TIM MISO configuration: The Monte Carlo analysis results for AP configuration The total harmonic distortion (THD) of the filter for LP and BP responses is plotted for different input signal amplitudes for VM as shown in Figure 22. The THD plot for CM-BP is presented in Figure 23. The THD remains within acceptable limits (≤5%) for appreciable input range. To study the effect of process spread on the performance of the designed filter Mont Carlo analysis is carried out for 200 runs. The Mont Carlo analysis results for VM BP response are given in Figures 18 and 19. The results for TIM AP configuration are given Figures 20 and 21. Figure 22: Total harmonic distortion of VM-BP and VM-LP Figure 18: VM MISO configuration: The Monte Carlo analysis results for BP response 112 R. Mishra et al.; Informacije Midem, Vol. 52, No. 2(2022), 105 – 115 Figure 23: Total harmonic distortion of CM-BP Figure 25: Input and output referred noise for VM-LP filter configuration The pole frequency of the filter decreases due to rise in temperature Figure 24 because of the decrease in OTA transconductance. Two main contributing factors that influence the transconductance are the threshold voltage (Vt) and carrier mobility Vt. is approximated as a linear function of temperature [42,43] given by Equation 25. Where αVt denotes the threshold voltage temperature coefficient which varies from −1 mV/ oC to −4 mV/ o C and TO is the reference temperature (300 K). Vt (T ) = Vt (TO ) + αVt (T − TO ) To further highlight the merits of the designed filter its performance is compared with some exemplary mixed mode filters as presented in Table 6. It can be observed that filters [46-47] cannot work in all four modes. The filters [24, 47] requires negative/double inputs for response realization. The filters structures [24,38,45] requires excessive numbers of ABBs for the design. It can be inferred from the table that the proposed filter has performance comparable with the existing designs. The power dissipation of the proposed filter can be reduced by designing the VD-DVCC for low supply operation. (25) The dependence of carrier mobility on temperature is shown in [42-43]. αµ T µN (T ) = µN (TO )    TO  6 Conclusion (26) This paper presents a new VD-DVCC based electronically tunable mixed-mode filter structure. The filter employs two VD-DVCCs, three grounded resistors and two grounded capacitors. Presented MISO filter has inbuilt tunability and can realize all five filter responses in all four modes of operation (VM, CM, TAM, and TIM). The detailed theoretical analysis, non-ideal gain analysis, and parasitic study are given. The VD-DVCC is designed in Cadence Virtuoso software and extensive simulations are carried out to examine and validate the proposed filter in all four mode of operation. The proposed filter has all the advantages mentioned in (i)-(iv). The filter is designed for a frequency of 5.305 MHz with ±1V supply. The power dissipation of the filter stands at 3.48 mW. The Monte Carlo analysis shows that the frequency deviation is within acceptable limits. Furthermore, the THD is within 5% for considerable voltage/current input signal range. The simulation results are found to be consistent with the theoretical predictions. where, αµ is the mobility temperature exponent considered as a constant approximately equal to 1.5. The Equations (25) and (26), show that the threshold voltage (Vt) and mobility (µN) exhibit a negative temperature dependence. Figure 24: Variation of Filter Pole frequency with temperature The input and output noise of the filter for VM-LP configuration is shown in Figure 25. The input referred noise magnitude for the VM-LP is found to be below 0.2E-06 V / Hz1/2 till 10 MHz frequency. The maximum magnitude of output referred noise is 3.62E-08 V / Hz1/2. 7 Acknowledgement Part of this work was carried out at Institute of Microengineering and Nanoelectronics (IMEN), University Kebangsaan Malaysia (UKM). This work is 113 R. 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Applied Sciences. 2020,11(1):55. Copyright © 2022 by the Authors. This is an open access article distributed under the Creative Commons Attribution (CC BY) License (https://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 09. 04. 2022 Accepted: 22 .06. 2022 115 116 Original scientific paper https://doi.org/10.33180/InfMIDEM2022.205 Journal of Microelectronics, Electronic Components and Materials Vol. 52, No. 2(2022), 117 – 127 A Low Distortion Audio Amplifier Žiga Šmelcer, Aleksander Sešek University of Ljubljana, Faculty of Electrical Engineering, Laboratory of Microelectronics, Ljubljana, Slovenia Abstract: The paper presents a design and assembly of a high-quality audio amplifier. The design is simple, and it can achieve extremely low Total Harmonic Distortion (THD) less than −100 dB for a bookshelf speaker with output power levels up to 10 W. The solution for a high-quality output are transistor pairs used in the input stage along with a simple topology that does not need matched transistor pairs for a power stage. Such input and output stages were closely analyzed at different bias currents. It was found out that there is an optimal power stage bias current of 20 mA for lowest distortion. The THD of the proposed topology was simulated with the LTSpice simulator and measured with the audio spectrum analyzer U8903B from Keysight and by a simple solution using a handheld recorder and an integrated Digital to Analog Converter (DAC). The Keysight was able to measure −104.5 dB THDR, whereas simple solution did measure −92.8 dB. Keywords: audio amplifier; feedback loop; transistor pair; THD Avdio ojačevalnik z nizkim popačenjem Izvleček: Članek predstavlja načrtovanje in izvedbo visokokvalitetnega avdio ojačevalnika. Načrt je preprost in lahko doseže zelo nizka harmonska popačenja (THD), pod −100 dB za namizne zvočnike z močmi do 10 W. Rešitev za doseganje nizkih popačenj so tranzistorski pari skupaj s preprosto topologijo, ki v izhodni stopnji ne zahteva tranzistorjev z enakimi lastnostmi. Vhodna in izhodna stopnja sta bili analizirani pri različnih delovnih tokovih. Ugotovljeno je bilo, da obstaja optimalni delovni tok 20 mA za doseganje najmanjšega popačenja. THD predlagane topologije je bil analiziran v programu LTSpice in pomerjen z avdio spektralnim analizatorjem Keysight U8903B ter z uporabo ročnega diktafona in integriranega digitalno-analognega pretvornika. Z uporabo Keysight inštrumenta se je izmerilo −104.5 dB THDR, z enostavno rešitvijo pa −92.8 dB. Ključne besede: avdio ojačevalnik; povratna zanka; tranzistorski par; THD * Corresponding Author’s e-mail: ziga.smelcer@fe.uni-lj.si 1 Introduction nal power and the noise power. Because harmonic distortion is counted as a part of the noise in signal, it is included in SNR calculation. Audio amplifiers have three main parameters, that are important for listening experience. The first one is power. This parameter is important if the speakers will be used for music playback. In home speaker setup people would rarely need sound power in excess of 100 W, whereas in concert halls the power of amplifier systems needs to exceed 10 kW [1]. In the paper it was decided to optimize distortion parameter, as it has the biggest impact on the quality and timbre of the amplificated signal. A signal with lower THD offers more music details and higher quality reallife listening experience. The second parameter is Total Harmonic Distortion (THD). It presents main signal quality characteristics combined in one parameter. The main quality parameters are linearity, slew rate, overshoot and stability. At the beginning, research of audio amplifier market was done, which offers a lot of different audio systems. Many of them are implemented using standard Integrated Circuit (IC) amplifiers and are advertised to be superior without specifying any objective data with the following quotes: The Way The Artists Truly In- And third, the Signal to Noise Ratio (SNR). This is another quality parameter that compares the audio sig- How to cite: Ž. Šmelcer et al., “A Low Distortion Audio Amplifier", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 52, No. 2(2022), pp. 117–127 117 Ž. Šmelcer et al.; Informacije Midem, Vol. 52, No. 2(2022), 117 – 127 tended, Purer sound, Shut out the noise, Wide frequency response for ultra-clear harmonics, etc. [2]. On the other hand, there are many audiophile amplifiers that specify at least basic amplifier quality numbers (THD, Signal to Noise Ratio (SNR), Crosstalk…) but are significantly more expensive and sometimes they don’t offer better performance as cheaper integrated circuit solutions. by Linsley Hood in 1969 [13], was studied and analyzed. The design is presented in the next chapter, along with an operational amplifier LM2904 [14]. 2.1 Linsley hood simple amplifier (Class AB) Linsley Hood has published a very simple design with a good performance (THD less than −60 dB) in the magazine Wireless World [13]. Therefore, it is a great candidate for future analysis and to be used as building block for better and more complex architectures. A more thorough description of the simple output stage which uses 2 NPN transistors and was used in the proposed design is described in following chapter. A few commonly known audio amplifiers are compared in Table 1. The IC solutions have the worst performance, with the exception of LM3886 that is better than affordable medium class amplifiers from reputable companies Onkyo and Marantz. If a premium quality amplifier is chosen, such as Luxman or Classe Delta Mono, a price rises up to 10,000 € and more. In Linsley’s design, shown in Figure 1, a single PNP transistor (Q33) was used for an input stage and feedback from the output. An NPN transistor Q34 was used for the voltage amplification. The output stage was implemented with a double NPN stage (Q35 and Q36). As the output transistors are the same type (NPN), the matching that is necessary for a classical output stage with NPN and PNP is not needed, since the parameters are very similar between the same type of transistors. The development of the proposed high-quality amplifier was done under Master thesis [11], with budget accessible components. 2 Available circuit schematic performance analysis In the proposed design, bipolar transistors are used for multiple reasons. They are popular in discrete analog circuits, and they have faster and better phase margin because of lower input capacitance compared to MOS transistors. The low input biasing voltage of bipolar transistors increases the swing of output signal to use more supply voltage range and higher current gains call for less components in design. A crucial component for high quality amplifier design with discrete components is the precise transistor pair that is available in the standalone package and can be used for a precise differential input stage formation, assembly of current mirrors, logarithmic amplifiers, etc., which is suitable for the proposed solution. Different topologies from the simplest to the more complex ones were analyzed to find the most suitable solution. These topologies consist of classic amplifier Classes [12]: A, B and AB. Additionally, one of high-quality amplifiers, designed Amplifier was analyzed at signal voltage nodes (N1, N2, N3, N4, Vin, Vout) at different output stage bias currents Figure 1: Linsley Hood amplifier simulation design Table 1: Comparison of some audio amplifiers on the market Amplifier TI LM4950 (IC) [3] TI LM3886 (IC) [4] TI TLV320AIC3268 (IC) [5] Onkyo A9110 [6] Marantz PM6007 [7] Cambridge Audio Edge A [8] Luxman L-509x [9] Classe Delta Mono [10] THD at 1 kHz [dB] −55 (5 W, 8 Ω) –80 (30 W, 8 Ω) −40 (1 W, 8 Ω) −66 (55 W, 8 Ω) / −94 (100 W, 8 Ω) −83 (/, 8 Ω) −106 (78 W, 8 Ω) THD in FS [dB] −45 (5 W, 8 Ω) –70 (30 W, 8 Ω) / / −62 (/) −74 (100 W, 8 Ω) −64 (/, 8 Ω) −96 (78 W, 8 Ω) 118 PRICE [€] 2.50 7.66 9.49 249.00 640.00 5,999.00 9,900.00 11,999.00 PRICE [Source] mouser.com mouser.com mouser.com onkyo.com marantz.com md-sound.de soundtemple.eu afmerate.com Ž. Šmelcer et al.; Informacije Midem, Vol. 52, No. 2(2022), 117 – 127 (1 mA, 100 mA, 1.5 A) to see how they affect the performance. The bias is set by adjusting the resistor R40, which applies a bias current to the output transistor Q35. A 100 mA bias current was used for the Class AB output stage simulations which results are presented in Figure 2. In the circuit, there are 3 signals at nodes N1, Vout5 and N4 closely matching the input signal. They have offset defined by the transistor bias voltage which is approximately 0.7 V. The lowest voltage is at input of an amplifier (N1, base of transistor Q33) representing a non-inverting operational amplifier input. The output signal that drives speakers is marked with Vout5. This signal is also connected to an inverting input for a negative voltage feedback (emitter of transistor Q33). Another bias voltage higher is a signal driving base of the top output stage transistor (N4, Q36). The input transistor Q33 compensates the output signal (N2, collector Q33) to drive a voltage amplification transistor Q34, therefore signal N2 is not a perfect sine. The collector of Q34 (N4) then matches the sine and drives the upper output stage transistor Q36. The emitter of Q34 (N3) transfers the compensated signal to lower output stage transistor (Q35). The output signal matches input signal very closely with a distortion less than −60 dB, shown later in Table 3. Looking at the currents of the output stage transistors Q35 and Q36, shown on bottom traces in Figure 2, explains the situation behind the compensated voltage signal. The compensation is needed because transistor Q35 is not always conducting, whereas Q36 needs to conduct current at negative and positive sine wave. The difference in output currents of Q35 and Q36 represents the current that drives the output speakers (R42). The base connections of output transistors are driven in anti-phase. The lower transistor is driven by node N3 and upper transistor by node N4. It is important to note a time delay of voltage and current signals. If the delay becomes too big, the amplifier becomes unstable, therefore a proper phase compensation is needed. The main reason for delay is an influence of parasitic capacitances and inductances of PCB and components that shift voltage and current signals. The compensation is made with a capacitor and must be optimally chosen. If the compensation is weak, then feedback will respond too fast to the input signal change, and if the compensation is too strong, then feedback will not respond to the input signal fast enough. A bias current of 1 mA was used for Class B output stage as seen in Figure 3. It can be noticed that some signals (N2, N3, N4, Ib(Q34)) have sharp response at zero crossing resulting in output distortion, shown in detail in Figure 5. Figure 2: Voltage and current signals of a Class AB configuration (100 mA bias) The sharp response is the result of a small output stage bias (1 mA). The input transistor therefore needs to 119 Ž. Šmelcer et al.; Informacije Midem, Vol. 52, No. 2(2022), 117 – 127 quickly compensate it and it generates a very sharp output current that flows into base of Q34. An overshoot in regulation is inevitable and results in current spikes when output stage transistors Q35 and Q36 start to conduct. Also, voltage signals of N1, N4 and Vout nodes are not correlated through the whole sine wave. The negative sine half of N4 node is distorted because feedback loop tries to correct the error in the output signal. Figure 3: Voltage and current signals of a Class B configuration (1 mA bias) Figure 4: Voltage and current signals of a Class A configuration (1.5 A bias) 120 Ž. Šmelcer et al.; Informacije Midem, Vol. 52, No. 2(2022), 117 – 127 For the last simulation, a bias current of 1.5 A was used for a Class A output stage simulation, which results are shown in Figure 4. All signals are sinusoidal as transistors are always in the active region, therefore only a small correction is needed to compensate an exponential Ugate(Iemitter) transistor characteristic. The correction is done by negative feedback loop of the input transistor Q33. The output transistor currents graph shows why a Class A design is not appropriate as both transistors conduct 1.5 A in quiescence. When applying a signal that changes the load current from −500 mA to 500 mA, the current consumption of the output stage is in the from 500 mA to 3.0 A, showing the inefficiency of a Class A topology. put currents the input stage consists of transistors connected in a Darlington configuration. The second stage (Q10, Q11) has relatively high input impedance, not to distort the signal, and amplifies current from the input stage. For better output utilization, 2 transistors, NPN and PNP, are used in common collector configuration therefore cancelling out the 0.7 V bias voltage of this stage. The signal from the second stage is feed to the voltage amplification stage (Q12) with a 100 µA bias current. For the final stage, NPN and PNP transistors (Q6, Q13) are used. For higher current capability the upper output transistor (Q6) is additionally amplified, using transistor Q5 in Darlington configuration. A current protection is done with a shunt resistor (RSC), connected to a gate of transistor (Q7). A THD of different amplifier classes were also simulated and are presented in the following chapters. The main part of the LM2904 circuit used in the proposed design, is the input differential pair. Performed analysis and comparison of input stages of Linsley’s amplifier and LM2904 are presented in the next chapter. The Linsley’s input stage was analyzed in Linsley’s amplifier circuit and simplified LM2904 input stage without Darlington connection for additional amplification was analyzed in proposed design, show in Figure 7. Figure 5: Sharp response at zero crossing with a Class B (1 mA bias) 2.2 Industrial grade off-the-shelf operational amplifier LM2904 (Class AB) Figure 6: A simplified schematics of LM2904 operational amplifier The documentation of integrated circuits is an excellent source of quality and reliable circuit designs, although schematics of complete designs are omitted nowadays. One of reliable integrated solution with included simplified schematic is LM2904 operational amplifier [14]. The design is simple and robust with predictable stability. The schematics of LM2904 is presented in Figure 6. 2.3 The proposed design (Class AB) The base of the proposed design presents the LM2904 transistor differential pair input stage, together with a double NPN output stage from the Linsley Hood’s amplifier. Between input and output stages, additional components were used to shorten signal path, lower distortion and speed up the feedback path. The schematic of the proposed design is shown in Figure 7. The input stage consists of the differential input stage using PNP transistors (Q1, Q2, Q3, Q4) biased with current mirrors. For additional amplification and lower in- 121 Ž. Šmelcer et al.; Informacije Midem, Vol. 52, No. 2(2022), 117 – 127 Figure 7: Simulation schematics of proposed amplifier (single supply LEFT, dual supply RIGHT) To clarify the issue, Fast Fourier Transform (FFT) analysis was performed at different input stage bias currents. A signal of 1 kHz at 2.5 V amplitude was used for excitation. The bias current did not affect Linsley Hood’s amplifier input stage and the second harmonic caused approximate −70 dB distortion, whereas the proposed design with differential input stage, is affected by the input stage bias current – the higher it is, the lower is the distortion. In the proposed design, when the bias current is over 1 mA, the 2nd harmonic decreases, but the 3rd harmonic increases. At 2 mA bias current, the 3rd harmonic is at −94.5 dB and the second at −99.2 dB, showing that this is an optimal relation between supplied bias current and distortion. The bias current comparison results are shown in Table 2. 3 THD simulation of proposed design Simulations of THD were performed in LTSpice, which is a simple and powerful Spice based program with Graphical User Interface (GUI). All previously mentioned topologies were analyzed to get a good understanding of the circuit operation. The THD was measured by 1 kHz, 5 V sine wave excitation on input. The FFT analysis result of proposed design (topology 11 in Table 3) is shown in Figure 9. Figure 8: Single vs differential input stage: a) input current into base of single stage, b) current into emitter of single stage, c) current of differential stage, d) inverting differential input stage base current, e) non-inverting differential input stage base current A signal propagation comparison was made between Linsley Hood single transistor input stage (IS) and differential input stage in the proposed design. The amplifiers’ simulation schematics are shown in Figure 1 and Figure 7. The input stage currents (Figure 8) are consisting of DC bias and AC signal. Interestingly, the base input (Figure 8a) and emitter (Figure 8b) bias currents of single input stage were lower than the differential stage (Figure 8c, e) by 2.5 µA and 0.8 mA. Also, the phase shift of signals is smaller in single IS compared to the differential IS. Despite lower values, the THD was higher in a single input stage of Linsley Hood. Figure 9: FFT analysis results of proposed design 122 Ž. Šmelcer et al.; Informacije Midem, Vol. 52, No. 2(2022), 117 – 127 Table 2: 2nd harmonic comparison between Linsley Hood and the proposed amplifier input stage IS bias current [uA] Linsley Proposed 100 −67.5 (30) −75.7 (200) Fundamental to 2. harmonic ratio [dB] (IS bias resistor [kΩ]) 200 500 1000 2000 −70.2 (9) −70.8 (3) −71.0 (1.4) −70.7 (0.66) −81.8 (100) −89.4 (41) −95.0 (20) −99.2 (10) 5000 −70.2 (0.26) −102.2 (4) Table 3: Harmonic amplitudes at 5 Ω load and 5 V amplitude of in/out signal Topology 1 2 3 4 5 6 7 8 9 10 11 MOS follower 6k/10k BJT follower 2.8k BJT follower 2k BJT follower 430 BJT Class B BJT Class AB 5mA, 2k Linsley Hood AB Linsley Hood B Linsley Hood A Proposed with only + supply Proposed with ± supply 2. −43.1 −38.7 −56.0 −77.5 −43.4 −49.9 −66.1 −67.8 −69.4 −92.9 −94.1 Harmonic [dB] 3. 4. −48.5 −53.1 −40.6 −42.7 −61.2 −70.9 −70.6 −90.7 −24.0 −44.9 −65.0 −76.8 −79.5 −89.2 −63.7 −66.1 −72.4 −79.2 −94.3 −106.9 −94.2 −106.4 The higher harmonics from the FFT analysis plot were compared with the fundamental tone H1. In Table 3, results for individual harmonic distortion and bias currents are presented. Cells with the worst harmonics are shaded. The performance of Linsley Hood’s amplifier and proposed design is shown alongside with basic topologies consisting of single or dual transistors (topologies 1 − 6). The basic topologies are included to show a distortion which is caused by transistor’s nonlinear characteristic and an influence of feedback to linearization. 5. −57.6 −44.6 −76.1 −105.5 −29.2 −70.2 −93.8 −63.0 −94.1 −92.6 −92.7 Bias current of output stage [A] 2.0 2.0 2.3 10.0, 1 ΩLOAD 0.0 100 m 100 m 1m 2.0 100 m 100 m stay less time in a non-conducting region, therefore the signal is less distorted. By adding a small bias current through output transistors, the distortion can be lowered (topology 6). Class AB with 100 mA bias, has −49.9 dB distortion at 5 mA voltage amplification stage bias current. The THD also improves when simple feedback with one transistor is used which is utilized in the Linsley Hood design (topologies 7-9). The distortion from an ordinary AB stage is decreased by 16.2 dB to −66.1 dB. A distortion of Class B amplifier can also be decreased with feedback. A Linsley Hood amplifier in Class B therefore performs 39.0 dB better than a simple Class B amplifier (−24.0, −63.0 dB). With a simple voltage follower topology (topologies 1 - 4), the amplification quality is solely dependent of a single transistor characteristic. The main transfer characteristic is IOUT(UIN). The transistor models used are Infineon BSB012N03LX3 for MOSFET and Onsemi 2SC6144SG for BJT. At 2 A bias current, a BJT transistor had worse distortion as MOSFET by 4.4 dB (−43.1, −38.7 dB). By slight bias current raise to 2.3 A, the BJT distortion was greatly improved to −56.0 dB. In simulation, the bias was increased to unrealistic value 10 A, where a single BJT transistor has distortion −70.6 dB and it could compete with quality amplifiers. The proposed design achieved the lowest distortion around −92.6 dB, if supplied with a single (positive) or dual (positive and negative) supply voltages (topologies 10, 11). Using dual supply voltages is preferred to omit small signal and power coupling capacitors which realize middle voltage level. The usage of coupling capacitors is not desired because real capacitors have many parasitic elements, occupy space on a PCB and add additional phase delay which affects signal distortion. A Class B topology, without feedback (topology 5), has the worst distortion. The odd harmonics contribute most to the distortion, with third being the worst at −24.0 dB. It was found that the THD improves by increasing input signal levels. This is because transistors 123 Ž. Šmelcer et al.; Informacije Midem, Vol. 52, No. 2(2022), 117 – 127 4 Measurements The schematics and PCB of the circuit were drawn in Altium Designer. All appropriate power supplies, isolation, D/A converter and pre-amplification stage were also included on the PCB, as the proposed design (Figure 7 RIGHT) is used in a complete audio amplifier and marked as R AMPLIFIER and L AMPLIFIER in a block schematic of Figure 10. Figure 12: Star connection for ground signal nodes at load output connector of proposed amplifier Initially, power was supplied with a transformer from an AC grid and rectified on the circuit, but this resulted in a poor SINAD characteristic in the range of 65 dB. To improve this, a 12 V battery supply was used and the SINAD improved to 75 dB. Figure 10: Block schematics of complete circuit with including proposed amplifier The connection between pre-amplification stage and proposed amplifier was done differentially to limit the noise coupling from an environment. The output signal and ground reference signal from a block DIFF AMP were connected through a twisted pair cable to an input of the amplifier and ground. The connection is summarized in Figure 11. On a PCB circuit, a star connection for ground signals was used as close to the load ground connection as possible shown on Figure 12. Star connection lowers the noise coupling and ensures proper signal integrity. Figure 13: Keysight U8903B input-output characteristics In Figure 13, an input-output characteristic of an audio spectrum analyzer was measured to set a reference value. The instrument’s THDR is around −100 dB to −120 dB with 50 Hz line noise. Figure 11: Connection between pre-amplifier and proposed amplifier Figure 14: Influence of feedback capacitance The distortion of a proposed design was measured using an industry standard Audio Spectrum Analyzer U8903B from Keysight [15]. A measurement of THDR and SINAD (Signal to Noise and Distortion) were made at multiple frequencies and amplitudes. A power stage bias was also measured. The proposed amplifier was measured using two different compensations in the feedback – 100 pF and 1 nF. The same compensation was used on power stage transistors due to their high bandwidth. It was found that decreasing compensation greatly improves THDR at higher frequencies by 25 dB. In the region below 124 Ž. Šmelcer et al.; Informacije Midem, Vol. 52, No. 2(2022), 117 – 127 1 kHz, the THDR is even better than simulated where it surpasses −100 dB. The results of measurements are presented in Figure 14. Amplifier was also characterized with and without a load. Results are shown in Figure 16. The THDR difference is 5 dB. The reason is in higher currents needed for load driving; therefore a higher influence of transistor nonlinearities is present. A distortion comparison was made also with Linsley Hood’s design and quality integrated headphone amplifier TI TPA6120A2 and results are shown in Figure 15. The Linsley’s design did not perform as good as the proposed design, reaching THDR around −50 dB. At higher frequencies distortion worsens because of lowcost capacitors used for DC component decoupling. The integrated headphone amplifier also did not perform as good as the proposed design with THDR around −80 dB to −90 dB, except at higher frequencies where distortion improved under −100 dB. The circuit board and other used elements introduced a frequency pole nearby 10 kHz which resulted in a better THDR. Figure 16: Frequency response of proposed amplifier at different loads For measurement comparison, a simple and low-cost method for THDR measurement was used as shown in Figure 17. An integrated high quality DA converter PCM1794 with best case scenario −108 dB THDR was used as a signal generator. The DA needs a simple preamplifying stage that was made using TI operational amplifiers OPA1678 [16] with THDR of −120 dB. The THDR at 1 kHz was measured with a handheld voice recorder Tascam DR-22WL which uses a Cirrus Logic CS42L52 [17] codec with −88 dB THDR. A final THDR value was obtained from a recorded WAV file with FFT analysis performed within MATLAB program. In the measuring setup, the recorder has the worst distortion so a distortion of −88 dB was expected. Figure 15: Frequency characteristics at 2 VRMS input A bias current in the output stage has also impact on the THDR. A constant sine wave was used as the input and the bias current through output transistors was changed using potentiometer. In Table 4, results of distortion measurements are presented, where it can be found that the highest bias current does not necessarily mean the lowest THDR. Instead, when bias currents are in the range from 20 to 40 mA, a signal with lowest distortion −108.4 dB was measured. Despite the previous fact, total distortion of −92.8 dB was measured meaning some deviations from the circuit documentation exists. The control measurement was done with the Keysight equipment and a THDR of −104.5 dB was obtained. Results show that the simple method is not suitable for measuring the distortion of Biasing is influenced by the temperature of the transistors. The higher temperature will shift the IC(UBE) characteristic up, meaning that the same voltage bias will result in a higher current flow through a transistor. Temperature effect on bias was therefore canceled out by adjusting the bias to precise value before measuring the THD. Despite this, a difference of THD between measurements could be observed at the same bias current. This is due to a different temperature of output transistors between measurements. The current bias was adjusted in a sequence listed in Table 4 – from 4 mA to 320 mA to 5 mA. Consequently, the temperature of transistors before 320 mA measurement was lower than after the 320 mA measurement at the same current bias. Figure 17: A simple and low-cost method for measuring THDR 125 Ž. Šmelcer et al.; Informacije Midem, Vol. 52, No. 2(2022), 117 – 127 Table 4: Distortion at 440 Hz, 2 VRMS input signal Bias current with signal [mA] THD [dB] 4 10 20 40 80 160 320 160 80 40 20 10 5 -98.3 -102.0 -108.0 -107.3 -105.6 -103.7 -102.5 -103.8 -106.4 -107.7 -108.4 -105.0 -100.2 proposed amplifier, as a distortion of consumer recorders using off-the-shelf codecs are decades worse than tone frequency a high-fidelity audio equipment. The measurement results of this comparison are shown in Figure 18. 6 Acknowledgments Authors would like to thank a Slovenian distributor of instrumentational devices Amiteh for lending a Keysight U8903B audio spectrum analyzer and therefore enabling comparison between a real-world and simulation results. 7 Conflict of interest The authors confirm there are no conflicts of interests in connection to the work presented. 8 References Figure 18: Comparison of harmonics and 50 Hz distortion on proposed amplifier output 1. 5 Conclusions 2. The paper presents that a high-quality amplifier can be realized using simple schematics and affordable components. The proposed amplifier exceeded −100 dB THDR. Further feedback transfer function characterization would allow additional compensation optimization, which would result in distortion improvement. 3. 4. Although the analog amplifier distortion can be additionally improved, firstly the input signal must be improved to higher quality. A noise improvement would also be needed as the noise level is much higher (around 75 dB) than distortion. 5. 6. The problem is also how to obtain recorded music with −100 dB distortion. All the recording equipment must have low noise and distortion. The recordings must not be poorly compressed and must have lossless quality. Also, the room in which the music is played must have low noise floor to fully enjoy the quality. 7. 8. 9. All the above is hard to achieve, and yet the total noise and distortion using the proposed design is better than an average consumer amplifier and contributes to an excellent listening experience with a simple design. 10. 126 D. Mellor, “How much power do you need to fill a venue with sound?,” [Online]. Available: www. audiomasterclass.com/blog/how-much-powerdo-you-need-to-fill-a-venue-with-sound. Sony, “USB DAC Headphone Amplifier,” [Online]. Available: www.sony.com/ug/electronics/headphone-amplifiers/pha-1a. Texas Instruments, “LM4950 Boomer™ Audio Power Amplifier,” [Online]. Available: www.ti.com/ lit/ds/symlink/lm4950.pdf. Texas Instruments, “LM3886 Overture™ Audio Power Amplifier,” [Online]. Available: www.ti.com/ lit/ds/symlink/lm3886.pdf. Texas Instruments, “TLV320AIC3268 Low Power Stereo Audio Codec,” [Online]. Available: www. ti.com/lit/ds/symlink/tlv320aic3268.pdf. Onkyo, “A-9110 Integrated Stereo Amplifier DATASHEET,” [Online]. Available: eu.onkyo.com/enGLOBAL/brands/onkyo/a-9110/p/156271. Marantz, “PM6007 INTEGRATED AMPLIFIER WITH DIGITAL CONNECTIVITY,” [Online]. Available: www. marantz.com/en-gb/product/amplifiers/pm6007. Cambridge Audio, “Edge A Integrated Amplifier,” [Online]. Available: www.cambridgeaudio.com/ usa/en/products/hi-fi/edge/edge-a Luxman, “L-509X INTEGRATED AMPLIFIERS,” [Online]. Available: www.luxman.com/product/detail.php?id=26 Classe Audio, “Delta MONO Power Amplifier,” [Online]. Available: www.classeaudio.com/products/ delta-mono/. Ž. Šmelcer et al.; Informacije Midem, Vol. 52, No. 2(2022), 117 – 127 11. 12. 13. 14. 15. 16. 17. Ž. Šmelcer, “A low harmonic distortion audio amplifier development,” University of Ljubljana, Faculty of Electrical engineering, 24 June 2021. [Online]. Available: repozitorij.uni-lj.si/IzpisGradiva. php?id=127908. Wikipedia, “Power Amplifier Classes,” [Online]. Available: en.wikipedia.org/wiki/Power_amplifier_classes. J. L. L. Hood, “Simple Class A Amplifier,” Wireless World, 1969. STMicroelectronics, “Low-power dual operational amplifier LM2904,” [Online]. Available: www. st.com/resource/en/datasheet/lm2904.pdf. [Accessed 26 August 2021]. Keysight, “U8903B Performance Audio Analyzer,” [Online]. Available: www.keysight.com/en/pdxx202150-pn-U8903B/performance-audio-analyzer. [Accessed 28 August 2021]. Texas Instruments, “OPA167x Low-Distortion Audio Operational Amplifiers,” [Online]. Available: www.ti.com/lit/ds/symlink/opa1678.pdf. [Accessed 26 August 2021]. “Low Power Codec with Class D Speaker Driver,” Cirrus, [Online]. Available: www.cirrus.com/products/cs42l52/. Copyright © 2022 by the Authors. This is an open access article distributed under the Creative Commons Attribution (CC BY) License (https://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 10. 02. 2022 Accepted: 25. 06. 2022 127 128 Original scientific paper https://doi.org/10.33180/InfMIDEM2022.206 Journal of Microelectronics, Electronic Components and Materials Vol. 52, No. 2(2022), 129– 142 Analysis of effects of dangling-bond defects in doped a-Si:H layers in heterojunction silicon solar cells with different electron affinities of ITO contacts Jošt Balent, Franc Smole, Marko Topič, Janez Krč University of Ljubljana, Faculty of electrical engineering, Laboratory of Photovoltaics and Optoelectronics, Ljubljana, Slovenia Abstract: The effects of dangling-bond defects in doped hydrogenated amorphous-silicon layers (p-a-Si:H and n-a-Si:H) in heterojunction silicon (SHJ) solar cells are studied in relation to applied Indium-Tin-Oxide (ITO) contacts with different electron affinities. A state-of-the-art numerical model of the SHJ solar cell was employed, including ITO contacts as full, volumetric semiconductor layers, applying the trap-assisted, band-to-band and direct tunnelling mechanisms at heterointerfaces in the device. The levels of dangling bond defect concentrations were varied in both p-a-Si:H and n-a-Si:H layers and ITOs with two different electron affinities were considered at both sides of the device. We show that the effects of the defects on the short-circuit current density, open-circuit voltage, fill factor and conversion efficiency of the device become more pronounced if ITOs with non-optimal electron affinities are used. Possibility to reach higher doping levels of the doped a-Si:H layers would mitigate the effects of its dangling bond states, which becomes more important if ITO electron affinity is not optimized to the doped a-Si:H layers. We demonstrate that the reduced efficiency due to the increase in dangling-bond density originates from the decrease of the fill-factor and open-circuit voltage, whereas the short-circuit current density has a small effect on efficiency for the chosen variation span. The reduction of the fill-factor is further explained by a drop in maximum-power-point voltage, which is more pronounced if optimization of ITO electron affinity is not taken into account. Keywords: Silicon heterojunction solar cell; Opto-electrical simulation; Defect-states, Electron affinities Numerična analiza učinkov defektov bingljajočih vezi v dopiranih plasteh iz a-Si:H v heterospojnih silicijevih sončnih celicah s kontakti ITO z različnimi elektronskimi afinitetami Izvleček: Raziskali smo vpliv defektov bingljajočih vezi v dopiranih slojih hidrogeniziranega amorfnega silicija (p-a-Si:H in n-a-Si:H) v kombinaciji s kontakti iz indij-kositrovega oksida (ITO) pri heterospojnih silicijevih sončnih celicah (SHJ). Za raziskovanje notranjih in zunanjih lastnosti celice smo uporabili optoelektrične simulacije. Uporabljeni sodobni numerični model SHJ sončne celice je vseboval kontakte ITO, ki so bili modelirani kot dejanski polprevodniški sloji ter upošteval tuneliranje s pomočjo pasti, tuneliranje med energijskimi pasovi in tuneliranje znotraj energijskega pasu na heterospojih sončne celice. Spreminjali smo koncentracijo defektov bingljajočih vezi v p-a-Si:H in n-a-Si:H slojih pri dveh različnih elektronskih afinitetah kontaktov ITO na obeh straneh celice. Pokazali smo, da je vpliv defektov na izkoristek, polnilni faktor, napetost odprtih sponk in kratkostični tok bolj izražen, kadar elektronska afiniteta kontaktov ITO ni bila prilagojena dopiranim a-Si:H slojem. Ugotovili smo, da je zmanjšana učinkovitost zaradi povečanja gostote defektov bingljajočih vezi posledica zmanjšanja polnilnega faktorja in napetosti odprtih sponk, medtem ko kratkostični tok ni močno vplival na izkoristek znotraj izbranega območja variacije. Zmanjašanje polnilnega faktorja smo obrazložili preko upadanja napetosti pri maksimalni moči, ki se zmanjša še bolj občutno, kadar kontakti ITO niso optimizirani. Ključne besede: heterospojne silicijeve sončne celice; optoelektrične simulacije; defektna stanja, elektronske afinitete * Corresponding Author’s e-mail: jost.balent@fe.uni-lj.si How to cite: J. Balent et al., “Analysis of effects of dangling-bond defects in doped a-Si:H layers in heterojunction silicon solar cells with different electron affinities of ITO contacts", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 52, No. 2(2022), pp. 129–142 129 J. Balent et al.; Informacije Midem, Vol. 52, No. 2(2022), 129 – 142 (BBT) and direct tunnelling (DT) processes in simulations. We focus our analysis primarily on the maximumpower-point (MPP) operation of the solar cell, as this is the common operating condition of solar cells in a real scenario and is often not taken in consideration sufficiently in such modelling studies. Quantitative results of the presented analysis reveal the impact of defects, in particular dangling-bond states in doped a-Si:H layers (especially in the p-a-Si:H layer) when using ITO contacts with different electron affinities. It is necessary to study also the synergy between the defect states and the ITO electron affinity as they both have a big influence on the electronic state of the device (formation of the electric field needed for charge separation), which determines the efficiency of the cell. Additionally, the study aims to improve the physical understanding of the related effects. Simulation results are presented for the a-Si:H based selective contacts, however, the results can be usefully considered also in the design of the SHJ solar cells including novel materials for selective contacts. e.g. metal-oxides and fluorides [8], [22]–[27]. 1 Introduction The ever-growing demand for clean and affordable electrical energy opened up a substantial market for photovoltaics and other renewable energy technologies. In Photovoltaics the biggest market share (~95 %) belongs to the crystalline-silicon (c-Si) based solar-cell technology [1]. Of these, silicon heterojunction (SHJ) solar cells are gaining attraction with the potential to achieve high conversion efficiency, low temperature coefficients and competitive production costs. The current world-record efficiency of a c-Si-based terrestrial non-concentrating large area solar cell is 26.7 % [2] and is achieved by the heterojunction structure in combination with interdigitated back contacting [3]. The SHJ cells utilize the benefits of both, conventional (c-Si wafer-based) and thin-film (hydrogenated amorphous silicon - a-Si:H) technologies. A thorough understanding of the governing physical mechanisms in state-of-the-art structures of solar cells, such as SHJ, is crucial when designing cells at the limit of what is theoretically possible (~30 % for single junction devices) [4]. Numerical modelling and simulations are an indispensable part of the R&D cycle as they unveil, often immeasurable, internal quantities of the solar cell, which determine its external characteristics. The study presented in this paper is based on detailed opto-electrical modelling and simulations of SHJ solar cells. In particular, we analyse the effects of dangling bond defects in doped a-Si:H layers in relation to indium tin oxide (ITO) transparent conductive oxide (TCO) contacts with different electron affinities χ. Various numerical models emerged from the research of SHJ cells that vary in complexity and accuracy [5]–[14]. In this contribution we used the Sentaurus TCAD software suite [15] to numerically model and study the device’s internal and external performance related to the mentioned effects for applied ITO electrodes with optimized and non-optimal electron affinities. While our previous work [16] was focused on combined effects of defect states at i-a-Si:H/c-Si interfaces and in p-doped a-Si:H (p-a-Si:H) and n-doped (n-a-Si:H) thin layers considering one pre-selected electron affinity of ITO layers, in this work we extend the study to structures where ITO contacts have different electron affinities (optimized and non-optimal). Solar cells with ITO/doped a-Si:H selective contacts have already been studied numerically [11], [17]–[21] however, the authors either used a Schottky barrier as a Dirichlet boundary condition to model the ITO contacts or focused on other parameters of ITO and a-Si:H. Studies have not been performed in relation to specific defect types in a-Si:H doped layers in combination with different work functions or electron affinities of ITO contacts. In our research we use a fully volumetric semiconductor model of ITO, including the accompanying trap-assisted (TAT), band-to-band 2 Device structure and model In our analysis we considered the following SHJ solar cell structure (Fig. 1): ITO front cathode (70 nm), p-doped a-Si:H layer (p-a-Si:H, 10 nm), intrinsic a-Si:H passivation layer at p-side (i-a-Si:H, 5 nm), n-doped c-Si bulk absorber (n-c-Si, 150 μm) with interface regions at both i-a-Si:H/n-c-Si interfaces (2 nm), intrinsic a-Si:H passivation layer at n-side (i-a-Si:H, 5 nm), n-doped a- Figure 1: Structure of the simulated solar cell. Optical simulations were done on the entire device whereas electrical simulations used ideal ohmic boundary condition in lieu of the Aluminum layers. 130 J. Balent et al.; Informacije Midem, Vol. 52, No. 2(2022), 129 – 142 Si:H layer (n-a-Si:H, 10 nm), rear anode ITO (100 nm)/ Al contact layer (500 nm). The ITO/p-a-Si:H and ITO/na-Si:H layer stacks enable selective collection of generated holes and electrons at the cathode and anode, respectively. The input parameters of layers and interface regions are described later. gap narrowing and mobility dependence on dopant density was not included in the analysis, which shortened the simulation time with negligible effect on results as tested before for selected cases. The recombination of charge in the n-c-Si bulk was based on the parametrization first implemented by Richter et. al. [30], which includes both Auger and Radiative recombination mechanisms and accurately calculates their impact on minority carrier life-times in a broad range of dopant concentrations and injection levels. The Shockley-Read-Hall (SRH) recombination in the n-c-Si bulk was modelled via life-time of minority carriers (10 ms). In a-Si:H layers the defect states were represented by donor-like (don) and acceptor-like (acc) tail and dangling-bond (db) states. The amphoteric nature of dangling bonds was taken into account by two Gaussian functions, describing the so called +/0 and 0/- charged states [31]. The donor-like tail and the +/0 danglingbond states are positively charged when vacant and neutral when occupied by an electron. The acceptorlike tail and so-called 0/- dangling-bond states are neutral when vacant and negatively charged when occupied by an electron. The defect-density distribution of tail-states (Ntail) and dangling-bond states (Ndb) along the band-gap of the p-a-Si:H layer for the reference cell is presented in Fig. 2. The optical generation profile of the illuminated cell with standard AM1.5g spectrum was simulated with the SunShine simulator [28]. The coherent and incoherent nature of light was accounted for in the thick and thin layers, respectively, together with the light scattering and antireflection effects at the front and rear side of the device. Light enters into the device through the p-a-Si:H side (front) of the device in our basic case, however, selected simulation tests have been done also for the n-side illumination. In the simulated reference structure, the short-circuit current density (Jsc), calculated directly from optical generations in the nc-Si layer under AM1.5g solar spectrum, amounted to 39.06 mA/cm2. The Optical generation profile was kept unchanged during sweeps of the investigated electrical parameters (peak dangling bond defect density and doping of p-a-Si:H and n-a-Si:H layers, ITO electron affinity) to selectively indicate their effect on the solar cell performance. It should be noted that in this study we did not focus on the optical performance of the device. We chose the presented planar architecture instead of an interdigitated back-contact (IBC) solution to minimize external influences, such as lateral currents, normally present in IBC devices, to more clearly show the effects of defect density and ITO electron affinity on SHJ solar cell performance. Detailed optical simulations can be found elsewhere [10, 29]. Detailed electrical simulations of the device were performed with the Sentaurus TCAD software suite [15], also used and validated for simulation of SHJ solar cell structures in previous publications [9], [10]. The material interfaces were generally considered as geometrically flat in electrical simulations. The simulation domain in electrical simulations of the device was twodimensional, however, the problem at hand is one-dimensional. Therefore, the results of internal quantities were transformed in a one-dimensional function of the structure depth where applied. The temperature was kept at 300 K in all simulations. In the numerical description of the cell, the Drift-Diffusion model was employed to solve the Poisson equation coupled with the continuity equations for charge concentration inside the investigated solar cell structure. We used both Gummel and Newton solving schemes interchangeably to either ensure, or expedite the convergence of the simulations. The Fermi-Dirac statistics was used to accurately calculate free-charge density also in the regions of high effective dopant concentrations. Band- Figure 2: Representation of defect-state distribution in a-Si:H layers of the reference cell (selected case is shown for the p-a-Si:H layer, see corresponding values of the parameters for all a-Si:H based layers in Table I). The red dashed and full lines present the donor-like tail and +/0 dangling-bond states. The blue dashed and full lines correspond to acceptor-like tail and 0/- danglingbond states. However, all used defect-state parameters for the p-aSi:H, n-a-Si:H, i-a-Si:H layers, and the i-a-Si:H/n-c-Si interface regions in the starting, reference cell are available in Table I. Regarding the defect-state variation, in this study we focused only on the values of the Gauss131 J. Balent et al.; Informacije Midem, Vol. 52, No. 2(2022), 129 – 142 +/0 0/ian peak concentrations ( N db-peak , N db-peak ) and not the tail states, since it was indicated that they have a noticeable effect on device performance [16] including indium-tin-oxide (ITO). The defective n-c-Si surfaces (in simulations 2 nm regions) passivated by i-a-Si:H layers are described by dangling-bonds only, presented by two Gaussian peaks (see parameters in Table 1) and were also kept constant in this study. The ITO layers were modelled as semiconductor layers to fully encompass the band alignment with the a-Si:H layers, thus, taking into account the band-bending in both materials forming the heterojunction [17]. The electrical input parameters for ITO and all other layers are summarized in Table 2 in the Appendix. The dominant tunnelling transport depends on the shape of the barrier [11], [21]. The transport through the ITO/p-a-Si:H barrier was modelled accordingly by the trap-assisted and band-to-band tunnelling, whereas at the ITO/n-a-Si:H interface by the trap-assisted and direct tunnelling. We used only non-local tunnelling models (variation of band energies and electric field over depth fully considered, guaranteed zero current at equilibrium). The use of non-local models is necessary since simpler, local models tend to underestimate the tunnelling current at low electric fields [37]. Direct (intra-band) and band-to-band tunnelling are considered as a sum of elastic (momentum of the particle is constant along the tunnelling path) and in-elastic or phonon-assisted (momentum changes across the tunnelling path) mechanisms and are based on [38] and [39]. Trap-assisted tunnelling is modelled similarly as a sum of elastic [34] and in-elastic processes [35]. Regarding the transport mechanisms at heterointerfaces, the transport through the i-a-Si:H/n-c-Si (encircled 1a and 2a in Fig. 3) heterojunctions is mediated by the inclusion of the built-in thermionic emission model [32], where for particle fluxes across the interface, the condition of continuous quasi-Fermi level and carrier temperature is used [33]. The thermionic emission at these interfaces is also supported by the trap-assisted tunnelling in our modelling approach [34], [35], which is also applied to the ITO/a-Si:H heterointerfaces (encircled 1 and 2 in Fig. 3). In the reference cell the p-a-Si:H and n-a-Si:H layers doping densities were set to 2e19 cm-3 and 1.5e19 cm3, corresponding to activation energies of 300 meV and 200 meV, respectively. Their electron affinity was set to 3.9 eV and their mobility-gaps to 1.65 eV and 1.72 eV, respectively. All other material and tunnelling parameters used for the reference case are presented in Table 2 in the Appendix. Table 1: Defect-state parameters for a-Si:H layers and i-a-Si:H/n-c-Si interfaces Quantity Tail peak concentrations Symbol don acc N tailpeak / N tail-peak p-a-Si:H Tails 1e+21 / 1e+21 n-a-Si:H i-a-Si:H 1e+21 / 1e+21 1e+18 / 1e+18 (cm-3eV-1) [12] [12] [12] Tail slopes don acc σ tail / σ tail 120 / 70 60 / 40 120 / 70 [12] [12] [12] Tail capture cross-sections (charged/neutral) ch n Ctail / Ctail (cm2) 1e-16 / 1e-16 1e-16 / 1e-16 7e-15 / 7e-17 Dangling bonds peak Gaussian concentrations (meV) + /0 0/ − N dbpeak / N db-peak (cm-3eV-1) Dangling bonds std. deviations + /0 0/(meV) σ db / σ db Dangling bonds capture cross-sections (charged/neutral) Cdbch / Cdbn (cm2) Dangling bonds peak energies Edb+ /0 / Edb0/- (eV) [12] [12] [12] Dangling bonds 1.9e+19 / 1.9e+19 2e+19 / 2e+19 1e+16 / 1e+16 i-a-Si/n-c-Si / / / 2.5e+17 / 2.5+e17 [12] [12] [12] * 200 / 200 * 200 / 200 150 / 150 200 / 200 [12] [12] [12] [36] 5e-14 / 5e-15 5e-14 / 5e-15 [12] / [5] [12] [12] [36] 1.1 / 1.3 0.45 / 0.7 0.9 / 1.1 0.46 / 0.66 [12] [12] [12] [36] [36] 2e-14 / 2e-15 1e-18 / 1e-19 * N dbpeak values were changed from the reference in order to obtain realistic activation energies (300 meV and 200 meV) for the p-a-Si:H and n-a-Si:H layers, respectively. 132 J. Balent et al.; Informacije Midem, Vol. 52, No. 2(2022), 129 – 142 the electron affinity of ITO only on the p-side, while the dash-dot-dot lines present the variation on the n-side. Since similar conditions, with respect to the energetic barriers at the heterointerfaces occur also in the MPP condition, we did not show it in this graph for the sake of simplicity. At the p-side, the two barriers related to the heterojunctions hinder the flow of holes generated in the n-c-Si absorber towards the front ITO, whereas on the n-side they impede the flow of electrons toward the rear ITO contact. 3 Results and discussion The goal of this analysis is to quantify and understand the effects related to different levels of defect states, in particular the dangling-bond Gaussian peaks (Ndb-peak), in the p-a-Si:H and n-a-Si:H layers in a SHJ solar cell, for different affinities of ITO contacts as well as different doping levels of the a-Si:H layers. We start the analysis with the energy band-diagrams of selected structures in thermal equilibrium (Fig. 3). The green, blue and red colours present the vacuum level, conduction and valence bands respectively. The fermi level is presented by the black line. Full lines depict the reference cell (parameters from Tables 1 and 2). Electron affinity of ITO at both sides is marked (double-arrows) for the reference case. The electron affinities of ITOs in the reference cell at the p- and n-sides (χITO p-side = 5.30 eV and χITO n-side = 4.56 eV) of the device have been selected according to [40], presenting realistic values close to the optimum case with respect to the low work function mismatch (∆WF) between the ITOs and their adjacent doped a-Si:H layers (0.2 eV on both sides of the device) [19]. Please note that for our reference cell, to completely mitigate the mismatch of the work function just by manipulating the ITO electron affinity values, one would have to set them to 5.50 eV and 4.36 eV for the p-side and n-side, respectively. This could be achieved only for the ITO on the n-side of the device, since min. and max. values of electron affinities at the selected doping levels of ITO correspond to 4.2 eV and 5.3 eV [40]. However, besides ITO, there are also other TCO’s that could be applied, namely Aluminum doped Zync-Oxide (AZO) and Antimony doped Tin-Oxide (ATO), as they both have high optical transparency due to high band gaps (> 3.1 eV) and can be doped sufficiently to provide a low resistance contact [40]. Regarding the range of possible work functions, AZO work functions range from 3.1 eV to 4.5 eV and for ATO the range is from 3.8 eV to 5.2 eV [40]. Out of these three, ITO offers the highest possible work function of 5.3 eV and is best suited for the ITO/p-a-Si:H contact stack. Other TCOs exhibit lesser optical or electrical parameters in comparison. A review of TCO material characteristics and their application to various solar cells is available in [40] and [41], respectively. The alternative, non-optimal values for the electron affinities of ITOs was the same on both sides (χITO p-side = χITO n-side = 4.93 eV) and resulted in a work-function mismatch of 0.57 eV (same for both sides). This type of symmetric mismatch allowed us to make a fair comparison between the two sides. During the analysis, we changed the electron affinity of ITO from its reference value to the non-optimal case on one side only, while maintaining the reference level on the other side. The dashed lines in Fig. 3 present the energy bands of the case, in which we varied Figure 3: Band-diagrams in thermal equilibrium of the SHJ cell with different electron affinities of ITO layers (χITO) at front (p-side) and rear (n-side) of the device (see values in the legend). The reference cell with optimal electron affinities of ITOs is presented by full lines. Symbols EV, EF , EC and EVAC correspond to the conductionband edge, Fermi level, valence-band edge and the vacuum level, respectively. Circled numbers 1, and 2 mark the ITO/p-a-Si:H and ITO/n-a-Si:H interfaces, respectively. Circled numbers 1a and 2a present the i-aSi:H/n-c-Si heterojunctions on the p- and n-side of the device, respectively. In further analysis the Ndb-peak parameter of p-a-Si:H and n-a-Si:H layer was chosen for variation since it was pointed out in our previous study that it has detrimental effect on device performance. The variation was done separately for p-a-Si:H and n-a-Si:H layer. In the presented simulation results we varied Ndb-peak of both donor and acceptor states (0/- and +/0) simultaneously in a single layer. However, analysis showed that in the case of the p-a-Si:H layer the +/0 type of danglingbonds affects efficiency the most (see later discussion), whereas the n-a-Si:H layer is affected mostly by the 0/type. To illustrate and compare trends related to Ndb-peak variation, a series of device simulations were performed where the Ndb-peak peak value (height of Gaussian functions) was varied independently of other defect state parameters. Besides the selected reference level of Ndb133 J. Balent et al.; Informacije Midem, Vol. 52, No. 2(2022), 129 – 142 = 1.9e19 cm-3eV-1 and 2e19 cm-3eV-1 for the p-a-Si:H and n-a-Si:H, respectively, we also included an idealized case with zero Ndb-peak (but tail states still present in the material) and the cases with strongly enhanced Ndb-peak values up to and including 6e19 cm-3eV-1. Besides electron affinities of ITO, two doping levels of p-a-Si:H and n-a-Si:H layers were also included in simulations (reference values and hypothetically high doping values of NA = ND = 3e19 cm-3 for p- and n-layer respectively). Note that the chosen value for the high levels of doping density presents a purely hypothetical case that cannot be achieved with normal a-Si:H material as they would result in the corresponding activation energy values of ~0.2 eV and ~0.1 eV for the p-a-Si:H and n-a-Si:H layers, which is not achievable in praxis. This hypothetical case is used to indicate the effects related to materials where lower activation energies, and thus, higher effect of doping can be achieved, e.g. nano-crystalline silicon or other meta-materials such as metal oxides. With this hypothetical case we want to stress and quantify the importance of efficient doping of charge carrier selective layers in relation to different ITO contacts. peak (a) In Fig. 4a-b the black and red lines present cases with optimal (χITO = 5.30 eV and 4.56 eV for the p-a-Si:H and n-a-Si:H layers respectively) and non-optimal electron affinity values of ITO layers (χITO = 4.93 eV for both layers), respectively. The hypothetical case of high-doping values is presented with semi-transparent lines. The points on the graphs, presenting the reference case are also encircled. (b) The results presented in Fig 4a and 4b show that in general the increase of Ndb-peak starts to lower the efficiency of the device at all conditions, although the decreases start at different levels of defect states (Ndb-peak values). Focusing first on the p-a-Si:H side of the cell (Fig 4a), in the case with nominal doping level and reference electron affinity of ITO at the p-side (full black line) we can observe that efficiency starts to rapidly drop, when Ndbbecomes greater than ~2e19 cm-3eV-1. Higher level peak of doping in this case (dashed semi-transparent black line) shifts this decline of efficiency to Ndb-peak values of around 3.5e19 cm-3eV-1. In both cases, reducing the Ndbparameter below the reference value will yield an peak increase in efficiency of less than 1 % when compared to the reference Ndb-peak. In case of nominal doping we increase the reference efficiency from 24.28 % to ~25 % according to simulations. For higher doping this increase is even less significant. Focusing now on the second case, where the electron affinity of ITO at the p-side is not optimal and doping is nominal (full red line), we can observe that efficiency drops from the reference value of 24.28 % to 21.79 % even at the reference level of the Ndb-peak parameter (1.9e19 cm-3eV-1). Additionally, we can see an even faster decline in efficiency as Ndb-peak parameter surpasses the 2e19 cm-3eV-1 mark. Of note is the observation, that in this case, reducing the Ndb-peak significantly below its reference level (1.9e19 cm-3eV-1) Figure 4: a) Efficiency vs. Ndb-peak defect density variation in p-a-Si:H and b) in n-a-Si:H layer. Full lines represent nominal doping concentration of a-Si:H doped layers, whereas the dashed semi-transparent lines represent hypothetical high doping concentration (3e19 cm-3). Cells with optimized values of the adjacent ITO electron affinity are presented by black curves (5.30 eV for the p-side and 4.56 eV for the n-side). Red curves present the non-optimal values (4.93 eV for both pand n-side of the device). The case for the reference cell (Table 2, Appendix) is circled. It has to be noted that when the electron affinity of ITO is varied on one side of the device, the electron affinity of ITO at the other side is set to the reference (optimized) value. 134 J. Balent et al.; Informacije Midem, Vol. 52, No. 2(2022), 129 – 142 mitigates the negative effects of non-optimal electron affinity of ITO. Higher doping (dashed semi-transparent red line) has again a similar effect as before, as it delays the onset and slows down the decline in efficiency until Ndb-peak surpasses the 3.5e19 cm-3eV-1 mark. Reducing the defect density below 1.9e19 cm-3eV-1 does not significantly improve the efficiency also in this case. In general, the negative effects of increasing the defect density are amplified when ITO electron affinity is not optimized (high enough) for the p-a-Si:H layer. The effect can be mitigated by higher doping levels of the paSi:H. Additional simulations showed that variation of the ITO band-gap has a much lower effect on efficiency than the electron affinity at different Ndb-peak values (not shown here). one can observe in Fig. 3, that the conduction band of the ITO and the valence band of p-a-Si:H do not overlap at the heterojunction (encircled 1 in Fig. 3), which means that BBT is not very efficient, thus the transport of charges across the barrier on the p-side is heavily dependent on TAT. On the n-side, however, the transport across the barrier (encircled 2 in Fig. 3) relies on both TAT and Direct tunnelling, which makes the tunnelling on the n-side more efficient compared to the p-side [9], [11], [21] in this case. On a related note, optimal electron affinity of the ITO on the p-side also brings the mentioned energy bands closer together when compared to the non-optimal case (Fig 3.), which not only decreases the work function mismatch, but also improves BBT tunnelling efficiency. The effect is even more pronounced when hypothetically high doping is applied to the p-a-Si:H as activation energy decreases and makes the bands come closer together even more (not shown in Fig. 3). In contrast, on the n-side (encircled 2 in Fig. 3), the lower (optimal) value of the ITO electron affinity separates the conduction band of ITO from the valence band of n-a-Si:H even more, which does not affect the tunnelling noticeably, since BBT is not a factor on this side. However, it does lower the DT barrier height and improves the transport of electrons towards the anode. Similar to the p-side, this effect is even more pronounced when hypothetical levels of doping are applied. The general trends regarding sensitivity of efficiency to the Ndb-peak parameter are similar also for the n-a-Si:H layer. Although, it can be observed in the reference case of electron affinities of ITO at the n-side that the efficiency is much less sensitive to defects in the n-a-Si:H layer than that in the p-a-Si:H layer. Further simulation results (not shown in the graphs) revealed that this sensitivity trend remains almost the same when the device is illuminated from either the p- or n-side, and is also independent of the doping type of the c-Si wafer (n- or p-type). Further on, for simulations where non-optimal selection of electron affinities (in this case χITO = 4.93 eV) for the ITOs at both p- and n-side of the device (not included in Fig. 4) the sensitivity of the efficiency to variations of Ndb-peak in the p-a-Si:H and in the n-a-Si:H layer, surprisingly becomes comparable. It has to be noted that the differences between the reference (close to optimal) and the alternative values of the ITO electronaffinity for both sides are the same but differ in the sign: ∆χITO = 0.37 eV for the p-side and ∆χITO = -0.37 eV for the n-side. Additional simulations revealed that using an electron affinity value of 4.36 eV for the ITO at the n-side, which completely mitigates the work function mismatch, does not yield any increase in efficiency because the work function mismatch at the p-side already presents a bottle-neck even when an optimized value of electron affinity (5.3 eV) is used for ITO at the p-side. In order to see which tunnelling mechanism is dominant at the ITO/p-a-Si:H and ITO/n-a-Si:H heterointerfaces under various conditions (different electron affinities of ITO and various doping levels of the doped a-Si:H layers), we performed simulations where we applied only one tunnelling mechanism at the time at a specified ITO/a-Si:H heterointerface. The results showed, that TAT is the dominant tunnelling mechanism at the ITO/p-a-Si:H heterointerface for both optimal (5.3 eV) or non-optimal (4.93 eV) values of ITO electron affinity as well as for both realistic (2e19 cm-3) and hypothetical (3e19 cm-3) effective doping density levels of the p-a-Si:H layer. Simulations indicated that the contribution of BBT is negligible compared to TAT in this case. These observations are also in accordance to predictions published in [21]. At the ITO/n-a-Si:H side, however, according to simulation results either TAT or DT on their own can provide a sufficient transport path and yield almost identical efficiencies for both ITO electron affinity values, as well as for both realistic and hypothetically high effective doping levels of the n-aSi:H layers. A close comparison of the cases where non-optimal electron affinities were applied to ITOs on the p- and n-sides (red lines in Figs. 4a and 4b) and the Ndb-peak values were set to their reference values (1.9e19 cm-3eV-1 and 2e19 cm-3eV-1 for p-a-Si:H and n-a-Si:H respectively) revealed a significant difference between the efficiencies (21.79 % and 24.06 % for the p- and n-side respectively), despite the same work-function mismatch on both sides (∆WF=0.57 eV). This is due to a difference in the distribution of defect states in p-a-Si:H and n-aSi:H, with the distribution in p-a-Si:H affecting the cell more severely compared to n-a-Si:H [16]. Additionally, Note, that the change in electron affinity of ITO affects (i) band offsets between the ITO and a-Si:H as well as (ii) the work function mismatch between the materials, that influences the space-charge-region (SCR) prop135 J. Balent et al.; Informacije Midem, Vol. 52, No. 2(2022), 129 – 142 erties of the ITO/a-Si:H heterointerface, which will be discussed later. At the p-a-Si:H side, an increase in electron affinity of ITO also increases band offsets, resulting in higher barriers for electrons and holes (see Fig. 3), which could potentially reduce tunnelling efficiency. However, we observed an increase in efficiency when electron affinity was increased, which means that the possible negative effects of increased band offsets are far outweighed by the positive effects of decreasing the work function mismatch. At the n-side, the reduction of electron affinity results in smaller band offsets as well as a reduction in the work function mismatch and higher efficiency as well. The results indicate, that changes in band offsets due to variation in electron affinity of ITO in the presented range do not significantly affect tunnelling efficiency at the ITO/a-Si:H interface, but the same changes in electron affinity define the work function mismatch, and thus affect the SCR properties of the interface, as will be explained later. Note, that tunnelling must be applied at ITO/a-Si:H heterointerfaces for the cell to function properly, as explained in our previous publication [16]. We would like to state here, that tunnelling is already good enough in both cases of ITO electron affinity on both sides when defect density is not extremely high (Ndb-peak < 3e19 cm-3eV-1 as efficiency of the cell is above 20 % in those cases. Therefore, the main reasons for the observed efficiency trends when ITO electron affinity is varied and defect density is increased have to be related to other mechanisms. regardless of the chosen ITO electron affinity values. Let us now examine the effects of dangling-bonds in the p-a-Si:H layer on J(V) curves for some selected cells considering nominal doping levels (NA p-a-Si:H = 2e19 cm-3) in Fig. 5d. The grey line represents the reference cell (Tables 1, 2) with reference (optimal) electron affinity of ITOs and the reference Ndb-peak = 1.9e19 cm-3eV-1 in p-a-Si:H. The black curve corresponds to the cell with increased Ndb-peak = 2.5e19 cm-3eV-1, the remaining parameters are the same as for the reference cell (Tables 1 and 2). The red curve presents the case with a nonoptimal electron affinity of ITO (χITO p-a-Si:H = 4.93 eV) and increased Ndb-peak . The selected curves reflect the trends observed for the related parameters (JSC, VOC, FF) in the region of moderate increase in Ndb-peak. J(V) curves indicate that besides lower VOC, the FF decreased mostly due to the drop of the voltage at the maximum power point (VMPP) as indicated in the figure. The same general trend is observed for all cells, with different electron affinity of ITO layers, however the scale of change is different. The drop in VMPP is more pronounced when non-optimal electron affinity of ITO is used, and even more-so when defect states are increased. Of note is also the observation that applying non-optimal electron affinity of ITO alone decreases the FF in a similar manner as increasing only the defect states since VMPP drops in both cases. We found that the explanation for the decrease of VMPP and VOC can be related to the Poisson equation and how the total charge (free holes and electrons, ionized dopants and trapped charge) determines the final voltage of the cell when electron affinity of ITO and dangling-bond defect states are varied. In our previous publication [16] we explained in great detail how the voltage drops due to increased defect density and related charge re-distribution as the electric field that is needed for charge separation becomes weaker. We also explained that work-function mismatch dictates the amount of ionized ITO charge that needs to be screened in the adjacent a-Si:H layer in order to obtain a sufficient electric field in the c-Si bulk that is needed for charge separation and good MPP voltages [16]. When ITO with a non-optimal electron affinity is applied, as was the case here, the work function mismatch is increased. Then, higher dangling-bond defect density reduces the charge-screening capability of the p-a-Si:H which leads to an even lower electric field and the observed trends of low VMPP and VOC. To further examine and explain the efficiency trends presented in Fig. 4a, we show in Fig. 5a-c also simulation results of the fill-factor (FF), short-circuit-current density (JSC) and open-circuit voltage (VOC) of the cell as a function of the Ndb-peak parameter in the p-a-Si:H layer. From now on, we will focus on the p-side of the device, recognizing that the defects in the p-a-Si:H layer have a stronger impact on the performance of the device under the given circumstances. Similar to the previous figures, the black and red curves in Fig. 5a-c show cases with optimal χITO (5.30 eV on the p-side and 4.56 eV on the n-side), and non-optimal χITO values (4.93 eV on both sides). The solid and dashed lines correspond to the nominal (2e19 cm-3) and hypothetically high (3e19 cm-3) doping levels, respectively. The simulation point corresponding to the reference cell (Table 2, Appendix) is circled. Detailed comparison between the graphs in Fig. 5 reveals that FF and VOC are more sensitive to Ndb-peak, followed by JSC. For the highly doped p-a-Si:H layer one can observe almost no decrease in JSC even for extremely high Ndb-peak values, which has to be considered as a hypothetical (idealised) case. These observations also corroborate the statement that tunnelling is sufficient Changes in electron affinity of ITO directly affect the ITO work function. When the work function of ITO is smaller than that of p-a-Si:H (the difference is referred to as work function mismatch), electrons (mediated by tunnelling) flow from ITO toward p-a-Si:H and a positively charged part of the space-charge-region (SCR) is 136 J. Balent et al.; Informacije Midem, Vol. 52, No. 2(2022), 129 – 142 (a) (b) (c) (d) Figure 5: a) FF, b) VOC, c) JSC vs. Ndb-peak defect-density variation in the p-a-Si:H layer. Full lines correspond to nominal doping density of p-a-Si:H layer (2e19 cm-3), whereas dashed lines represent the device with high doping density NA p-a-Si:H = 3e19 cm-3). Devices with reference (optimal) values of the ITO electron affinities are presented by black curves (χITO = 5.3 eV for the p-side and 4.56 eV for the ITO at the n-side). Red curves correspond to cases where ITOs are not optimal (χITO = 4.93 eV for both p- and n-side of the device). The legend in a) applies also to b) and c). d) J(V) curve for the reference cell (grey) and selected cases with high Ndb-peak (2.5e19 cm-3eV-1) and ITO electron affinity at the p-side set to 5.30 eV (black) and 4.93 eV (red). All presented cases were simulated at nominal doping level of the p-a-Si:H layer (2e19 cm3). formed on the ITO side of the ITO/p-a-Si:H heterojunction (due to ionized donor atoms), whereas the negatively charged part of the SCR forms in the p-a-Si:H due to ionized acceptor dopants and neutralized +/0 states (that are now occupied by electrons that came from ITO and no longer contribute to the positive charge). The resulting electric field is oriented in the opposite direction than the electric field at the i-a-Si:H/n-c-Si heterojunction. As the work function mismatch is increased, the SCR is broadened even deeper into the p-a-Si:H region. The broadening of this SCR is actually depleting the p-a-Si:H layer, which can result in a weaker electric field (needed for charge separation) in the n-c-Si absorber when the SCR is not well contained in the p-a-Si:H. The mentioned changes affect the redistribution of charges throughout the device, which also determines the external voltage. In order to mitigate the negative effect of the work function mismatch, that lowers the voltage (VMPP and VOC) and FF, at the ITO/p-a-Si:H (n-a-Si:H) heterointerface, the negative (positive) charge in the p-a-Si:H (n-aSi:H) layer must be able to screen the opposite charge in the SCR of ITO. The screening capability of a-Si:H de137 J. Balent et al.; Informacije Midem, Vol. 52, No. 2(2022), 129 – 142 pends on effective doping concentration, defect density and layer thickness. Thicker layers with high doping concentrations and low defect density are capable of screening more ITO charge. The increase in danglingbond defect density mitigates the positive effect of doping and reduces the screening capability of the layer. In addition, as we discussed in our previous publication [16], an increase in peak dangling-bond defect density (Ndb-peak) in the p-a-Si:H layer reduced both VOC and FF, whereas JSC changed only slightly. The drop in FF was explained by lowering of the VMPP, whereas JMPP was observed to be almost unaffected, since at MPP conditions, total recombination was still far smaller compared to optically generated current. We concluded, that an increase in Ndb, peak reduces efficiency especially J ⋅ V ⋅ FF J MPP ⋅ VMPP due to lower VMPP ( Eff = SC OC ). = Pin Pin 26.5 %, which is also in accordance to the simulations presented in other publications that were simulating and optimizing IBC SHJ solar cells [9]. Therefore, the difference between the efficiencies of IBC and planar architectures can be mostly attributed to better JSC of IBC devices. In addition, the VOC and FF values of our reference cell simulations are very similar to the ones reported for the record cell and comparable to the ones presented in [9]. 4 Conclusion We applied opto-electrical modelling of a SHJ solar cell to study ITO/doped a-Si:H selective contacts in terms of ITO electron affinity and dangling-bond Gaussian peaks (amphoteric defects) of the doped a-Si:H layers. In the simulation structure, the ITO layer at the p- and n-side of the device was considered as a full semiconductor layer. DT, BBT and TAT tunnelling mechanisms were included in simulations at ITO/doped a-Si:H selective contacts. We demonstrated that optimizing the electron affinity of the ITO layers is critical when the doped a-Si:H layers are insufficiently doped or have high concentrations of dangling-bond defect states. We showed that optimization of electron affinity of ITO is especially important at the p-side of the device due to a less favourable trap distribution and poorer tunnelling efficiency compared to the n-side. We showed that the ITO at the p-a-Si:H layer should have electron affinity as high as possible (~5.3 eV) in order to minimize the work function mismatch (which was only 0.2 eV in this case), as higher values of the work function mismatch can deplete the p-a-Si:H layer to the point, where it is unable to sufficiently screen the positive charge in the space-charge-region of ITO, resulting in a diminished electric field in the n-c-Si absorber, and consequently poor charge separation capability of the cell, leading to a reduction in FF and VOC. Conversely, the ITO at the n-a-Si:H layer should have electron affinity as low as 4.56 eV (work function mismatch is 0.2 eV in this case). Lower values of electron affinity enabling lower work function mismatch on the n-side did not further improve efficiency, due to the already present work function mismatch at the p-side (0.2 eV in the optimal case). Low values of VOC also confirmed poor charge-separation capability of the cell, when electron affinity of ITO results in a higher work function mismatch between the ITOs and doped a-Si:H layers. We demonstrated that the work function mismatch between ITO and doped a-Si:H layers makes the solar cell efficiency more sensitive to increased dangling-bond defect states in the doped a-Si:H layers as higher dangling-bond defect density reduces the layers’ ability to screen the charge in the SCR of ITO as it negates the positive effect of doping. We also observed that when To explain the drop in VMPP we followed the Poisson’s equation, which relates charge distribution to the voltage between the terminals. A thorough analysis of total charge and all of its components (free charge, trapped charge in defect states and ionized dopant atoms) revealed that the increase in Ndb-peak in p-a-Si:H resulted in a reduction of positive charge in the SCR of ITO and a reduction of negative charge in the SCR of p-a-Si:H. The reduction of negative charge in p-a-Si:H was shown to be an increase in positive charge in the p-a-Si:H layer due to unoccupied +/0 dangling-bond states, that are positioned at energies where they are unlikely to be occupied by an electron and remained positively charged. We used the Poisson’s equation and showed, that this virtual shift of positive charge from ITO into the p-a-Si:H layer due to an increase in Ndb-peak resulted in the observed reduction in VMPP. We also showed, that 0/- states remained neutral and did not significantly affect the total charge in p-a-Si:H. All of the above is true also for all the cases presented in this work (both doping levels and dangling-bond defect densities). Before moving on to conclusions, we would like to provide a brief commentary regarding the reference efficiency of our simulated device (24.28 %), where both ITO layers have optimal electron affinity values (5.3 eV and 4.56 eV for the p- and n-side, respectively). It has been reported that SHJ cells have the potential to reach efficiencies as high as ~27 % [9]. However, this can be achieved by employing additional layers, such as p-type SiCx or SiOx and using the IBC architecture. Without these additional layers, the record cell, made by Kaneka, reached efficiency of 26.7 % [42], thanks to the IBC design, that allows for high JSC = 42.65 mA/cm2. In comparison, our reference cell, that uses optimized ITO layers, achieves JSC = 39.02 mA/cm2. Should we calculate the efficiency of our reference cell, by using the JSC of the record cell, we would get efficiency around 138 J. Balent et al.; Informacije Midem, Vol. 52, No. 2(2022), 129 – 142 ITO electron affinity at the p-a-Si:H (n-a-Si:H) layer is lower than 5.3 eV (higher than 4.56 eV) and doping is nominal (2e19 cm-3 and 1.5e19 cm-3 for p-a-Si:H and na-Si:H, respectively), only the FF (and not VOC or JSC) can be improved by lowering the dangling-bond defect density below the reference level (1e19 cm-3eV-1). In contrast, JSC was affected only at extremely high levels of defect densities even when electron affinity of ITO at the p-a-Si:H (n-a-Si:H) was lower (higher) than 5.3 eV (4.56 eV). We also concluded that tunnelling efficiency at the ITO/a-Si:H interface is not significantly affected by the changes in the band offsets, caused by variation in electron affinity of ITO, whereas the changes in the work function mismatch, as the SCR properties of the heterointerface were changed, affected the cell significantly. An increase in electron affinity of ITO at the p-a-Si:H layer results in increased conduction and valence band offsets, but the reduction in work function mismatch outweighs the negative impact of increased barrier heights and an increase in efficiency was observed, whereas a reduction in electron affinity of ITO at the n-a-Si:H layer results in even lower band offsets as well as a reduction in work function mismatch. It was also shown that TAT is the dominant transport mechanism at the ITO/p-a-Si:H heterojunction for all presented cases. At the ITO/n-a-Si:H interface, both DT and TAT provide an efficient transport path and yield very similar results when either of the two is applied as the only tunnelling mechanism at that interface. Results presented in this paper give indications for acceptable defect levels in doped amorphous-silicon layers in relation to optimality of ITO electron affinity for the ITO/a-Si:H selective contacts and can serve as a roadmap when designing selective contacts with alternative materials for SHJ cells. 5 Appendix Table 2: Input parameters for the reference case Quantity Relative Dielectric Constant er n-c-Si 11.9 [43] p-a-Si:H 11.9 [43] n-a-Si:H 11.9 [43] i-a-Si:H 11.9 [43] i-a-Si:H/n-c-Si 11.9 [43] Electron Affinity χ (eV) 4.05 [12] 3.9 [12] 3.9 [12] 3.9 [12] 4.05 [12] Band-gap (Mobility-gap) Effective Doping Conc. Egap (eV) ND / NA (cm-3) Density of States NC / NV (cm-3) 1.12 [36] 2e+15 / 0 [12] 2.8e+19 / 3.1e+19 [43] SRH life-times Mobilities Tunnelling mass (DT, TAT and BBT) Trap volume (TAT) Huang-Rhys con. (TAT) Phonon Energy (TAT) Coupling factor (DIRECT, BBT) Symbol τe / τh 1 / 10 [36] (ms) µe / µ h (cm2/Vs) 1342 / 452 [43] m* / Vtrap (μm-3) / Hrhys / Eph (meV) / ge/gh / 1.65 1.72 1.70 [12] [12] [12] 0 / 2e+19 1.5e+19 / 0 2.2e+15 / 0 [12] [12] * [12] 2e+20 2e+20 2e+20 / / / 2e+20 2e+20 2e+20 [43] [43] [43] 1.12 [36] 2e+15 / 0 [12] 2.8e+19 / 3.1e+19 [43] / / / 1/10 [36] 10 / 1 [12] 0.1 [9] 1e-11 [8] 2 [8] 37.78 [8] 1/1 [9] 10 / 1 [12] 0.1 [9] 1e-11 [8] 2 [8] 37.78 [8] 1/1 [9] 10 / 1 [12] 0.1 [9] 1e-11 [8] 2 [8] 37.78 [8] 1/1 [9] 1342 / 452 [43] 0.1 [9] 1e-11 [8] 2 [8] 37.78 [8] 1/1 [9] ITO 8.9 [44] 5.3 / 4.56 (p-side/n-side) [40] 3.7 [9] 1e+20 / 0 [9] 4.12e+18 / 1.17e+19 [44], [45] / 50 / 30 [9] 0.1 [9] / / / 1/1 [9] * Effective doping concentration was changed from the reference to obtain realistic activation energy for the n-a-Si:H layer (200 meV) 139 J. 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Arrived: 11. 03. 2022 Accepted: 08. 07. 2022 142 Call for papers Journal of Microelectronics, Electronic Components and Materials Vol. 52, No. 2(2022), 143 – 143 MIDEM 2022 57th INTERNATIONAL CONFERENCE ON MICROELECTRONICS, DEVICES AND MATERIALS WITH THE WORKSHOP ON ENERGY HARVESTING: MATERIALS AND APPLICATIONS September 14th – September 16th, 2022 Hotel City, Maribor, Slovenia Announcement and Call for Papers Chairs: Prof. Dr. Tadej Rojac Assist. Prof. Dr. Mojca Otoničar IMPORTANT DATES Abstract submission deadline: May 1, 2022 Acceptance notification: June 15, 2022 Full paper submission deadline: July 31, 2022 Invited and accepted papers will be published in the Conference Proceedings. Detailed and updated information about the MIDEM Conferences, as well as for paper preparation can be found on http://www.midem-drustvo.si// GENERAL INFORMATION The 57th International Conference on Microelectronics, Devices and Materials with the Workshop on Energy harvesting: materials and applications continues a successful tradition of the annual international conferences organised by the MIDEM Society, the Society for Microelectronics, Electronic Components and Materials. The conference will be held in Hotel City, Maribor, Slovenia from SEPTEMBER 14th – 16th, 2022. Topics of interest include but are not limited to: • Energy harvesting: modelling, materials, devices, • Novel monolithic and hybrid circuit processing techniques, • New device and circuit design, • Process and device modelling, • Semiconductor physics, • Sensors and actuators, • Electromechanical devices, microsystems and nanosystems, • Nanoelectronics, • Optoelectronics, • Photovoltaic devices, • Electronic materials science and technology, • New electronic materials and applications, • Materials characterization techniques, • Reliability and failure analysis, • Education in microelectronics, devices and materials. ORGANIZER: MIDEM Society - Society for Microelectronics, Electronic Components and Materials, Slovenia CO-ORGANIZER: Republic of Slovenia, Ministry of Economic Development and Technology European Union, European Regional Development fund CONFERENCE SPONSORS: UL FE, UL FS, IJS, IMAPS, Slovenia Chapter; IEEE, Slovenia Section 143 Boards of MIDEM Society | Organi društva MIDEM MIDEM Executive Board | Izvršilni odbor MIDEM President of the MIDEM Society | Predsednik društva MIDEM Prof. Dr. Barbara Malič, Jožef Stefan Institute, Ljubljana, Slovenia Vice-presidents | Podpredsednika Prof. Dr. Janez Krč, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Dr. Iztok Šorli, Mikroiks d.o.o., Ljubljana, Slovenia Secretary | Tajnik Olga Zakrajšek, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia MIDEM Executive Board Members | Člani izvršilnega odbora MIDEM Prof. Dr. Slavko Bernik, Jožef Stefan Institute, Slovenia Assoc. Prof. Dr. Miha Čekada, Jožef Stefan Institute, Ljubljana, Slovenia Prof. DDr. Denis Đonlagić, UM, Faculty of Electrical Engineering and Computer Science, Maribor, Slovenia Prof. Dr. Leszek J. Golonka, Technical University, Wroclaw, Poljska Prof. Dr. Vera Gradišnik, Tehnički fakultet Sveučilišta u Rijeci, Rijeka, Croatia Mag. Leopold Knez, Iskra TELA, d.d., Ljubljana, Slovenia Mag. Mitja Koprivšek, ETI Elektroelementi, Izlake, Slovenia Asst. Prof. Dr. Gregor Primc, Jožef Stefan Institute, Ljubljana, Slovenia Prof. Dr. Janez Trontelj, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Asst. Prof. Dr. Hana Uršič Nemevšek, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Danilo Vrtačnik, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Supervisory Board | Nadzorni odbor Prof. Dr. Franc Smole, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Prof. Dr. Drago Strle, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Igor Pompe, retired Court of honour | Častno razsodišče Darko Belavič, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Miloš Komac, retired Dr. Hana Uršič Nemevšek, Jožef Stefan Institute, Ljubljana, Slovenia Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials ISSN 0352-9045 Publisher / Založnik: MIDEM Society / Društvo MIDEM Society for Microelectronics, Electronic Components and Materials, Ljubljana, Slovenia Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale, Ljubljana, Slovenija www.midem-drustvo.si