Fakulteta za elektrotehniko, Univerza v Ljubljani, Ljubljana Keywords: integrated Hall sensors, integrated Hall elements, sensor arrays, sensor array electronics, microelectronics bias circuits electrical spinning, electronic circuits, circuit optimization, autocalibration, CMOS processes, SP, signal processing, signal to noL atb S sensors, circuit design, temperature coefficients, voltage coefficients, signal amplifiers ' "magnetic Abstract: The paper describes the approaches for various integrated smart magnetic sensors design in CMOS processes It presents both sensor biasing electronics and sensor signal processing to obtain the best performance. Magnetic sensor systems are optSd in'the folfoS areas • The use of multiple sensors - sensor array. This helps to minimize random phenomena like the offset voltage and the noise and allows to compensate for phenomena dependent on sensor orientation and position (piezzo effect) or allows to sense spatial magnetic fie^d dTstr bution - Hall sensor biasing - to minimize temperature coefficient and voltage coefficient. magneiic rieia aistnbution, • Two-phase Hall sensor spinning - to minimize the offset voltage. " Hall sensor signal amplification for signal to noise optimization. Design examples for each of the listed topic are discussed. ro iraTe efe^n ' cenzorska, elektronika polj senzorskih, mikroelektronika, vezja napajalna ^lnnlfLt i ; ^ ®l®ktronska optimiranje vezij, avtokalibracija, CMOS procesi, SP procesiranje signalov, signal-šum razmerirsenzohl magnetni inteligentni, snovanje vezij, koeticienti temperaturni, koeficienti napetostni, ojačevalniki signalov razmerje, senzorji TiZn obravnava metodologijo za načrtovanje raznih integriranih "pametnih" magnetnih senzorjev v procesih CMOS Predstavi rsfsJeSxir^Te^ ^ sr: Uporaba vec senzorjev - senzorska polja. To pomaga minimizirati naključne pojave kot so napetost ničenja in šuma in pomaga reševati orobleme ki so povezani z orientacijo senzorja ,n njegovo pozicijo (piezzo effect) ali pa omogoča zaznavo krajevn J porazdelitve rgnetneS pdja • Napajanje Hallovega senzorja za minimizacijo temperaturnega in napetostnega koeficienta • Dvofazno električno rotiranje Hallovega senzorja za minimizacijo napetosti ničenja • Ojačevalniki za ojačenje senzorskega signala glede na optimizacijo razmerja signal/šum. Podani so zgledi načrtovanja za navedena področja. 1. Integrated Hali sensor opens a way to reduce cost in various applications such as: ® contactless current measurement ® contactless multiturn switch ® power and energy measurements • position and angle measurements CMOS process offers effective solutions to compensate or eliminate various problems associated with non-ideal sensors. It turns out that integrated Hall element offers the best possibility for magnetic sensor systems. The main advantages of Hall elements are: possibility to spin the element and therefore to minimize the offset voltage; large linear range of operation; predictable temperature coefficient of the sensitivity, a possibility to design element with minimal dimensions offered by the process. The main disadvantage of the Hall element is its relatively low sensitivity, so it requires high gain and low noise preamplifiers. 2. HALL ARRAY APPROACH The idea to use more than one Hall element was selected mostly to minimize the random phenomena which are offset voltage and Hall element noise. The offset voltage and the noise are improved by factor Vn where N is the number of sensors. This implies that it is helpful to use the highest number of sensors possible, so it is not unusual to use several tens of sensors if the design calls for the best possible offset voltage or signal to noise ratio is required. Fig.1 shows a typical Hall element in 0.8 jum CMOS process. Small dimensions of the element (23 ^m x 23 ^m) present no obstacle to multiply it; the array consisting one hundred elements would occupy less than 0.1 mm^ of silicon area. The benefit of this approach is not only the noise and the offset minimization by square root of number of sensors, it allows the designer to orientate each element for 90 degrees compared to the nearby sensors. This further reduces the offset voltage introduced by piezzo effect and the offset caused by low gradient of Hall plate material properties. Furthermore a string of sensors can detect spatial gradient of the applied magnetic field and so help to detect position of the ASIC relative to the magnetic field. Finally this approach allows the designer to build on the chip the reference magnetic field, which can be used either for testing, autocalibration or even for long term ratiometric measurement of the magnetic field. Such arrangement is very useful when the magnetic sensor system has to fulfill a strict requirements like the requirements for Watt-hour metering. Fig. 2 shows the integrated coil which generates magnetic field of 100 fjJ per 1mA coil current. The coil efficiency increases with decreasing overall dimensions; this is additional reason to use minimal Hall element dimensions. Ü i H lil i lili! i Pili Bil m i P^B pflfiii m iSi w ____________ Fig. 1: Layout of minimal Hall element in 0.8 fjm CMOS technology. Overall dimensons are 23 jjm x 23 fum. 3. HALL ELEMENT BIASING The purpose of Hall element bias electronics is to provide bias current which compensates the temperature effect of the Hall element sensitivity and compensates the effect of the sensitivity change due to substrate to Hall element potential. The schematic shown in fig.3 solves both problems. The Hall bias current is linearly proportional to the reference voltage Vref with required temperature coefficient and inversely proportional to the resistor RE. For the total temperature coefficient also temperature coefficient of resistor RE, usually poly-silicon resistor, should be observed. The substrate potential can be kept constant by the use amplifier 2 and resistor divider R1, R2 which sets the selected percentage of Hall element bias voltage to the required substrate bias voltage. VrcRicrnp) lli(teinp)=------ Vsub Rc((ciiip) Fig. 3: Bias circuit for Haii eiement ■ I ' m a Fig. 2: Integrated coil using one turn of metal 2 Ro L O- Ö R D U Ü Fig. 4: Equivalent circuit of Hall element offset voltage (first order approximation) v(w_24,w_2S 1 m. 500 IL O _ -500 u. -1 m. TIME — 400 300 200 u. 100 u. -2.7105. -100 IL -200 u_ -300 iL -400 iL s u 10 u IS u F/g. 5: Upper trace: simulation results for 1 mV of Hall element offset voltage Lower trace: Two phase spinning results for offset voltage cancellation Maximal contribution to offset voltage is poor clock feed through cancellation fl Vdh f4 iiiv44a n Q invi!v3a f|2i, invja m n inP O vb O loui Output current "O out Fig. 8: Differential amplifier - Hall element voltage to current converter ./f.imp.,IC o * inoise(mag_ 35 a 30 tL 25 a. 20 a. 15 a. 10 a 5 a HERTZ 1 k S k 10 k 50 k 100 k Fig. 9: Simulation results for Hall element voltage to current converter input noise density 500 k lu 50u«0i. 20u«0u 20iir20o H5 HP 20U/20U 2ChißOu 3H lOnßOu HE HE lOOuöOü lOp 80!! In H5 501; 300 4.5u OUI ,>2 in2 inl 'bo DM31 JCflfe lu 20« lo -o Fig. 10: Close loop amplifier to generate bias current for Hall element voltage to current converter -H ^ CP i V25 Fig. 11: Hall signal current summation and differentia! to single ended conversion schematic 4. HALL SENSOR SPINNING It is well known that electrical rotation for 90 degrees reduces the first order effect of Hall element asymmetry caused by various reasons. The model of such asymmetry is shown in fig. 4, where Ro represents the asymmetry. This model was used in SPICE simulatorto prove its efficiency. Fig. 5 shows the results of SPICE simulation, proving that the offset cancellation by two-phase spinning is completely efficient. Fig. 6 shows the actual spinning circuit. The selection of spinning frequency helps to minimize the 1/f amplifier noise and determines the frequency response of the systems according to sampling theorem. Very important feature of spinning is non-overlapping spinning clock for input signals as shown in fig. 7. 5. HALL SIGNAL AMPLIFIERS signal The following features are important for Hall amplifiers; - Differential voltage to current conversion to facilitate Hall array signal summation. ® Low noise. Ideally the amplifier noise should be less than Hall element noise. This is achievable only in the high frequencies where 1/f noise becomes insignificant. ® Small size. This allows the use of many Hall elements in the array. ® Controlled gain. Fig.8 shows the schematic diagram of the Hall signal amplifier. The simple voltage to current converter is achieved by the use of amplifier MOS transistor operating in saturation region. This schematic gives the best possible noise behavior. As shown in fig.9 the noise can drop below in the spinning clock frequency region between 300kHz and 1MHz. This noise level is just below the Hall element noise. The control of gain is achieved by amplifier bias current which is derived from a closed loop amplifier to assure the supply voltage variation, temperature independence and, process parameter variations. The amplifier bias schematic is shown in fig.10. In fig.11 current summation and current to voltage conversion is shown. The spinning clock is at the same time used to eliminate the amplifier stage offset voltage. Several projects were successfully designed using the described approach. The typical figures achieved are: Noise density: <50 nT/VHz Offset voltage: < lOO^^T Temperature coefficient of sensitivity: < 100 ppm/°C Temperature range: -40°C - -t-150°C These results are better than reported in papers using either single Hall element or other types of integrated magnetic sensors. This proves that the described design approach is very promising. REFERENCES /1/ J. Trontelj, A. Pevec, J. Trontelj ml., "Contactless Current Measurement with Integrated Hall Elements", Proceedings of the 33rd Int. Conference on Microelectronics, Devices and Materials, MIDEM'97, Gozd Martuljek, 165-170, 1997 /2/ J. Trontelj, L. Trontelj, "ASIC for Precise Position Measurement with Integrated Magnetic Microsensor Array", Proceedings of the European Design & Test Conference EDTC 1997, Pariz, 83-86, 1997. /3/ A. Haberii, M. Schneider, P. Maicovati, R. Castagnetti, F. Maloberti, and H. Baltes, "2D Magnetic Microsensor with On-Chip Signal Processing for Contactless Angle Measurement", 1996 IEEE Int. Solid-State Circuits Conf. (ISSCC), pp 332-333 /4/ Hall Signal Bias Generator. Patentna številka 9505314.6 z dne 16.3.1995. /J.Trontelj/ /5/ Hali Sensor Interconnection Circuit. Patentna številka 9505317.9 z dne 16.3.1995. /J.Trontelj/ /6/ AC Hall Current to Frequency Converter. Patentna številka 9505313.8 2 dne 16.3.1995. /J.Trontelj/ /7/ Integrirano vezje magnetnega senzorja. Patentna številka 9300622. /J. Trontelj, R. Opara, A. Pleteršek/ /8/ Integrirano vezje, obsegajoče magnetne senzorje, za določanje faze krajevno periodičnega magnetnega polja. Patentna številka 97 O 0148, 1997. /J. Trontelj/ /9/ Integrirano vezje, obsegajoče magnetne senzorje, za določanje faze in smeri spreminjanja faze krajevno periodičnega magnetnega polja. Patentna številka 9500275,1997. /Trontelj Janez/ prof.dr. Janez Trontelj Fakulteta za elektrotehniko Tržaška 25, 1000 Ljubljana, Slovenija E-mail: janez@kalvarija.fe. uni-lj. si Prispelo (Arrived): 14.7.1998 Sprejeto (Accepted): 28.7.1998