ISSN 0352-9045 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 4(2025), December 2025 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 55, številka 4(2025), December 2025 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 4-2025 Journal of Microelectronics, Electronic Components and Materials VOLUME 55, NO. 4(196), LJUBLJANA, DECEMBER 2025 | LETNIK 55, NO. 4(196), LJUBLJANA, DECEMBER 2025 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2025. All rights reserved. | Revija izhaja trimesečno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale – Društvo MIDEM. Copyright © 2025. Vse pravice pridržane. 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Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madić Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana Journal of Microelectronics, Electronic Components and Materials vol. 55, No. 4(2025) Content | Vsebina Original scientific papers Izvirni znanstveni članki J. V. S. Thirunavukkarasu, P. Kuppusamy: 201 J. V. S. Thirunavukkarasu, P. Kuppusamy: Design and analysis of Low power Rapid Charge Oblikovanje in analiza dinamičnega komparatorja z Holding Dynamic Latched Comparator zapahom z nizko porabo energije in hitrim polnjenjem S. Deivasigamani, R. Dhandapani: 219 S. Deivasigamani, R. Dhandapani: Smart Prediction and Trust-based Transmission Pametno napovedovanje in prenos na podlagi in Delay-Targeted Networks for zaupanja v omrežjih z zamikom za letalsko Aviation Communication komunikacijo A. Kos, E. Keš, M. Hribernik, S. Tomažič, A. Umek: 229 A. Kos, E. Keš, M. Hribernik, S. Tomažič, A. Umek: A Wireless Optical Gate and IMU System Brezžični sistem za ocenjevanje agilnosti na osnovi for Agility Assessment: Architecture, optičnih vrat in kinematičnih senzorjev: Synchronization and Validation arhitektura, sinhronizacija in validacija N. Natarajan, P. Kuppusamy: 239 N. Natarajan, P. Kuppusamy: Memristor based Majority Logic Adders for Error Memristorski logični večinski seštevalniki za aplikacije Resilient Image Processing Applications za obdelavo slik, odporne proti napakam M. Jiang, L. Zeng, L. Gan, B. Jia, X. Wang, Z. Zhu: 255 M. Jiang, L. Zeng, L. Gan, B. Jia, X. Wang, Z. Zhu: Enhanced Neutron-Gamma Discrimination Izboljšana razločevanje med nevtroni in gama žarki Using Deep Neural Networks for z uporabo globokih nevronskih mrež za natančno Precision Nuclear Medicine nuklearno medicine Front page: Naslovnica: Dr. Marko Jošt, Zois Certificate of Recognition dr. Marko Jošt, prejemnik Zoisovega priznanja 199 200 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.401 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 4(2025), 201 – 217 Design and analysis of Low power Rapid Charge Holding Dynamic Latched Comparator Jaspar Vinitha Sundari Thirunavukkarasu1, Paramasivam Kuppusamy2 1Department of Electronics and Communication Engineering, Kumaraguru College of Technology, Coimbatore, Tamil Nadu, India 2Department of Electrical and Electronics Engineering, Kumaraguru College of Technology, Coimbatore, Tamil Nadu, India Abstract: The need for portable devices with high precision has raised the demand for optimization of power and delay in various dynamic comparator topologies. In this paper, an efficient architecture that does timely yet rapid comparison with reduced power dissipation and optimal energy per comparison is proposed. Introducing an extra tail transistor in preamplifier of comparator, assists in holding the high gain, thereby reducing delay as well as power. The latch is meanwhile ready with a minimum threshold value at its output nodes with the help of a pass transistor in between latch output nodes. The conventional, hybrid, and proposed architecture, namely Low power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC) are simulated and verified for power, delay, and energy efficiency in Cadence Virtuoso Spectre. The proposed technique shows a significant improvement in delay and power consumption when compared to conventional comparators. Monte Carlo simulation shows that the proposed technique is robust to the process mismatch, sustaining optimal power, delay and energy efficiency. Keywords: Average Power consumption, Latch regeneration delay, Hybrid Dynamic Latched Comparator, Rapid Charge holding Latched comparator Oblikovanje in analiza dinamičnega komparatorja z zapahom z nizko porabo energije in hitrim polnjenjem Izvleček: Potreba po prenosnih napravah z visoko natančnostjo je povečala povpraševanje po optimizaciji moči in zamika v različnih dinamičnih topologijah komparatorjev. V članku je predlagana učinkovita arhitektura, ki omogoča pravočasno in hkrati hitro primerjavo z zmanjšano porabo energije. Dodajanje dodatnega repnega tranzistorja v predojačevalnik komparatorja pomaga ohraniti visoko ojačenje, s čimer se zmanjša zakasnitev in poraba energije. Zapah je medtem pripravljen z minimalno mejno vrednostjo na izhodnih vozliščih. Konvencionalna, hibridna in predlagana arhitektura, imenovana Low power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC), je simulirana in preverjena glede moči, zakasnitve in energetske učinkovitosti v Cadence Virtuoso Spectre. Predlagana tehnika kaže znatno izboljšanje zakasnitve in porabe moči v primerjavi s konvencionalnimi komparatorji. Simulacija Monte Carlo kaže, da je predlagana tehnika odporna na neskladje procesov, pri čemer ohranja optimalno moč, zakasnitev in energetsko učinkovitost. Ključne besede: Povprečna poraba energije, zakasnitev regeneracije zapaha, hibridni dinamični komparator z zapahom, hitro polnjenje * Corresponding Author’s e-mail: jasparvinithasundari.t.ece@kct.ac.in, paramasivam.k.ece@kct.ac.in How to cite: J. V. S. Thirunavukkarasu et al., “Design and analysis of Low power Rapid Charge Holding Dynamic Latched Comparator", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 4(2025), pp. 201–217 201 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 1 Introduction TFETs, Nanosheet transistors, and Nanowires assist in fast switching and low power consumption. Miniaturization and portability in electronic products are highly demanded in an environment of rapid tech- nological growth. The efficiency of any electronic sys- 2 Related works tem is reflected in the individual performance of every subsystem within the product. The efficacy of a com- Ata Khorami [1] has proposed a low offset low power parator is reflected in the efficacy of the whole system comparator that extends full swing output of the first and any device that employs it as a subcomponent. stage for effective comparison. Their proposed pream- The need for high speed, low power and low offset has plifier consumes less power in addition to fast decision increased due to the demand for highly precise and making for lower common mode voltages. Also, When fast Analog to Digital Conversion units, Operational VCM values are higher, latch activation becomes com- Transconductance Amplifiers, voltage references, feed- plex and influences the delay even though latching back amplifier setups and many other consumer elec- process is made easy. Latch topologies that rely on pos- tronic products. Comparators can be broadly classified itive feedback, especially sense amplifier type-based into static and dynamic topologies. In general, Static latches are usually dependent on common mode volt- comparators which offers high power consumption ages despite offering low offset voltages [2]. Savani and slow switching during latch regeneration phase [3] embedded a pass transistor between the output are of less priority. In contrast Dynamic comparators nodes of latch to sustain the NMOS transistors of the are widely preferred since they offer better switching cross connected inverters receive its threshold voltage. speed and low power consumption through positive Hence the time lapse for the outputs of the preampli- feedback. Dynamic comparators are further catego- fier to discharge is decreased. The time taken for latch rized into single tail and double tail comparators. Sin- initiation is also reduced, resulting in a delay of 51 ps gle tail dynamic comparators offer optimized delays, and power consumption of 33 µW. Uneven charging of notable offset voltage, and high dynamic power con- preamplifier output nodes results in static power con- sumption. Due to single tail current path, the kickback sumption, which is avoided in their proposed work by noise is high. Most preferred parent topology of single the inclusion of pass transistor in between the output tail comparator, namely strong-arm latch is highly in- nodes. fluenced by the range of VCM values. An advanced ver- sion and alternative to this is the double tail dynamic One of the vital reasons for kickback noise is the capaci- latched comparator. The double tail dynamic compara- tive coupling between the output nodes of the first tors incorporate two tail transistors, weakening the stage and the input transistors of the second stage. coupling between the preamplifier output and the out- This can be eliminated when the output nodes of pre- puts of the latch. Double tail comparators offer signifi- amplifier are cross coupled to pull up pair, which also cant reduction in kickback noise due to two separate reduces power dissipation at the time of evaluation current paths which further optimize power and de- phase. A significant delay reduction is achieved by cas- lay in its conventional as well as various architectures. cading the input transistors and latch of second stage. Topological changes for power and delay optimization [4] require a preamplifier that not only amplifies the input voltages with enough gain but also that consumes low To address the kick back noise reduction, yet another power by remaining dormant during evaluation phase. modified latch [5] with a wider path resulting in both Every topological change must ensure that the neces- output nodes in same state is recorded. This architec- sary output swing will be fed to latch at an appropri- ture cuts off the direct coupling between the outputs ate time lapse for comparison. Also, the topological of first stage and the inputs of second stage thus result- changes in latch always aim at a timely comparison of ing in reduced kickback noise with negligible counter the preamplifier outputs with optimized power intake effect on delay. Meanwhile, this topology increases the and less voltage headroom. Most of the comparator to- intermediate output nodal resistance thereby signifi- pologies fail to either provide a full swing output at an cantly reducing the power consumption. instant when comparison occurs or consumes power during evaluation phase. Many architectures show a significant reduction in per- formance parameters especially power and delay, by The trade-off between power and offset, delay and modifying conventional preamplifier topologies [6] [7] kickback noise need to be counterbalanced with ar- [8], latch topologies [9], adding intermediate stages to chitectural innovations. Beyond a superseded phase minimize noise [10] and few architectures that neglect of unending circuit topologies, in alteration to exist- either of the stages and introducing compensatory ing CMOS technology, emerging devices like FinFETs, combined architectures [11] 202 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 Introducing transistors (with specific bias) parallel to Latched Comparator (LRCHDLC) and its parent archi- latch inputs makes the first stage consume power for tecture, Hybrid Dynamic Latched Comparator HDLC. only a short period of entire evaluation phase [12]. Section 5 describes the analysis of performance met- These architectures are designed for applications rics with its sub sections describing the detailed analy- where low power is prioritized over speed. Topological sis of delay, power and energy efficiency. Subsection improvisations have always demonstrated a trade-off 5.1.1 & 5.1.2 includes mathematical analysis of delay of amongst the performance metrics, mostly between the conventional comparator and proposed compara- power and delay. Using heuristic algorithms, it is vali- tor respectively. The analysis of performance metrics dated in [9] that power and CMOS scaling have trade- with VCM and VDIFF is presented in section 5.1.3. Section 6 off with delay and offset, respectively. describes the comparison of the performance metrics of the proposed architecture with existing literature, Numerous architectures have been proposed to avoid process corner, influence of transistor sizing ratio, Mon- static power consumption in either reset or compari- te Carlo analysis for various performance parameters, son phase. Whenever extra transistors are introduced summary of results and key advantages. With progres- to improve comparison speed or minimize power con- sive simulation results, it can be observed that there is sumption, reduced power generates counter-effects simultaneous improvement in delay and power with leading to significant rise in delay and vice versa. No- minimal trade off. Section 7 concludes the paper. table single stage architecture [14] links the latch through preamplifier currents rather than voltage. It is driven by a clock and a delayed version of the same clock that improves latching speed. Introducing cur- 3 Conventional double tail dynamic rents to the latch nodes reduces both power and the latched comparator number of transistors significantly. Delayed clock and specific time sequence can also be achieved by intro- Figure 1 shows the topology of conventional dynamic ducing control gates [15]. latched comparator [7], and its transient response can be seen in Figure 2. The comparator works on recharg- Most of the recorded literature proves to improve one ing its intermediate and output nodes during the reset of the performance metrics compromising the other. phase and performs the comparison during evalua- The tradeoff between power and delay is seen in most tion phase. No direct coupling of intermediate output of the comparators where topological changes are nodes to the input terminals in conventional topology made in either preamplifier or latch. For applications makes it more resistant to kickback noise and, this ar- that demand less operating voltage, regenerative type chitecture lowers offset voltage. Preamplifier and latch comparators with doubled transistor latch with two circuits have lesser and larger tail currents respectively, fully NMOS / PMOS based preamplifiers are used. This thereby accomplishing lower offset voltage and high avoids completely charging and discharging of the speed. output nodes of preamplifier reflecting a significant reduction in power concurrently increasing the speed During the precharging phase where the clock is high of latch [19]. and the clock bar is low, M5 remains off thereby ensur- ing no static power consumption. In the case of the An effective topology is required to overcome these latch circuitry, the pull-down transistors M10 and M13 fed drawbacks without significant increase in area and by clock turn on, forming a path for the output nodes counter effects like kickback noise. In this paper, a to- with temporarily available charges to drain to ground. pology that helps reduce delay and power consump- The pull up network M1 and M2 of the first stage fed by tion during nodal charging and discharging of pre- clock bar, turns on and charges the nodes Fn and Fp to amplifier as well as latch is proposed. The modified VDD. At the end of precharging phase, the preamplifier preamplifier and latch in tandem help in avoiding output nodes Fn and Fp are at VDD and the latch output complete charging and discharging of all the output nodes outn and outp are at ground. nodes during every clock transition. The proposed comparator has made a noteworthy effort to diminish During the decision-making phase, the clock is low, power consumption by holding the minimum required and the clock bar is high. Also, with inputs fed, the tail charge at latch output nodes that negotiates charging transistor of the preamplifier turns on creating a path and discharging time. Section 3 describes the working for the output nodes Fn / Fp to discharge. of the basic conventional double tail comparator and its transient response. Section 4 describes the work- Depending upon the ratio of input values, the output ing and circuit implementation of the proposed archi- nodes discharge with different proportions. For exam- tecture, Low power Rapid Charge Holding Dynamic ple, when Vinp>Vinn, Fp discharges faster than Fn. Once 203 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 results in one of the output nodes of the latch pulled high and the other pulled down to zero. 4 The proposed comparator The proposed comparator shown in Figure 3 is the Hy- brid Dynamic Latched Comparator (HDLC) combining the principles of shared charge reset [2] and charge sharing techniques [3]. Figure 5 shows the proposed ar- chitecture Low-power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC) which is an architec- tural improvisation from a hybrid dynamic latched comparator architecture (HDLC). The transient re- Figure 1: Conventional architecture the charge at the output nodes of the preamplifier reaches the threshold of pull up transistors of latch cir- cuit, latching is initiated. Meanwhile, in the latch circuit, the pull-down transistors M10 and M13 fed by clock turn off and both the pull-down transistor of cross connect- ed inverter is activated resulting in latching. Latching Figure 2: Transient Response of Conventional architec- ture Figure 3: Schematic diagram of HDLC 204 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 sponse of the hybrid architecture HDLC and proposed at the latch inputs pulling both the latch outputs to LRCHDLC are shown in Figures 4 and 6 respectively. a strong 1 and strong 0 at precise times even though NAND type latches are prone to metastable conditions. HDLC aims at effective optimization of power and de- lay with minimal tradeoff for wider range of VCM and The sustained gain from preamplifier is available exactly VDIFF. The countereffect recorded in [3] was a high delay at the time instant when comparison happens which is during high range of VCM values. Similarly, the counter achieved with the help of extra tail transistors with para- effect that is witnessed in [2] was high power consump- sitic capacitances CP1 and CP2 at the drain of M5 and M6. tion despite achieving a shorter time lapse for latching. The correct outputs are transferred to the latch within The hybrid architecture is carefully designed with an an appropriate time frame with less power consumption appropriate choice of transistor sizing and capacitance because of the extra tail transistors in preamplifier. values. The transient response of this HDLC architec- The reset phase occurs in similar fashion in both HDLC ture implemented in 90 nm CMOS technology shows and LRCHDLC architectures. During the reset phase, a slight logic degradation in the output voltages. Also, when power and delay were analyzed for wider VCM and VDIFF values, the corresponding architecture offers power as well as delay without much countereffects. This concurrent optimization of power and delay using charge shared preamplifier and shared charge latch is taken as the base for the improvised architecture, LRCHDLC. In LRCHDLC, the concurrent optimization of power and delay is retained with no logical degrada- tion, by shifting of a modified NAND based latch. The charging / discharging path is simplified and chan- nelized smoothly in the proposed architecture, LRCH- DLC. The topological changes in HDLC have paved the way for further power and delay reduction, whereas switch- ing to NAND based modified latch in LRCHDLC helps in overcoming logical degradation. In both LRCHDLC shown in Figure 5 and its parent architecture HDLC shown in Figure 3, a pass transistor presets both the output nodes, outp and outn ,to a minimum thresh- old voltage (as shown in transient waveform, around 0.5 to 0.6 V for second evaluation phase after charge shared between the nodes through pass transistor) to overcome the time lapse of the nodes to charge and discharge, making the comparison faster. The fore- mentioned factor assures almost similar voltage levels Figure 4: Transient response of HDLC simulated at 45 nm technology with VDD- 1V, Fclk – 1 GHz, VCM- 0.7 V and VDIFF – 20 mV Figure 5: Schematic diagram of LRCHDLC 205 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 the clock is high, and the clock bar is low. During this phase the output nodes of preamplifier charges to VDD and only M6 is active with no parasitic capacitances be- ing charged. These high outputs of preamplifiers are connected to input pull down transistors M9 and M10 of the latch which turns them on. The pass transistor is on through a low clock bar, which distributes the available charges at the output nodes of the latch equally. During the evaluation phase, the inputs Vinp and Vinn are given, the clock goes low, and the clock bar goes high. Assuming Vinp is greater than Vinn. Thus, the transistors M1 and M2 go off, unable to sustain the output nodes high, further. The available charge at the output nodes of preamplifier follows the path to discharge via M3/M5 and M4/M5 charging both CP1 and CP2. Since Vinp is larger, Figure 6: Transient response of LRCHDLC simulated at the node Fn discharges faster than Fp, making the in- 45 nm technology with VDD- 1V, Fclk – 1 GHz, VCM- 0.7 V put NMOS transistor of latch circuit, say M9 go off faster and VDIFF – 20 mV than the other one M12. The differential voltage deteriorates before serious In the case of hybrid architecture (HDLC), the tail tran- latching starts. Most of the conventional topologies sistor M13 of latch is on since the clock bar is high, thus showcases more power consumption as well as dis- draining the charge of both outn and outp to ground sipation with notable delay because of this phenom- through M10 and M11. enon. There are few options to overcome this technical challenge to obtain a significant performance. Similarly, in the case of LRCHDLC, the tail transistor i) Deactivate the preamplifier when the differential M13 is on. Since Vinp > Vinn, the node Fp discharges faster output voltage is high enough for effective latch- than Fn. The sooner Fp discharges, the sooner it switch- ing process. es M10 off. It is significant that the pass transistor is off ii) Preactivated latch when the preamplifier offers since the clock bar is high. Hence the already available maximum differential gain. shared charge at outn and outp is around 0.6 V. At this threshold, M11 and M12 are still in active region. In the Moving the preamplifier into idle state when the out- short time of Fp falling below the threshold voltage re- put differential voltage is high, thereby sustaining the quired by M10, there is discharge of outn through M maximum differential voltage until the latch turns on 9/ M11/M13. Whereas the outp still at 0.5 is raised to V is the first option. The second option creates the same DD with regeneration of cross connected inverters. power during latch activation and the time required for latch initiation remains the same. Also, the differential This effectively reduces power dissipation and shortens voltage will eventually go down during the latch initia- the discharge time. Once M9/M10 goes off, the latching tion period. Prior activation of latch as well as freezing begins. The cross connected inverters pull up the node the preamplifier to hold its maximum output differ- outn to VDD and pull down the node outp to zero both ential voltage requires separate clocking and control in HDLC and LRCHDLC. Also, the availability of output techniques [20] which will introduce additional power nodes linked to ground directly in hybrid architecture, and delay. makes it dissipate only minimal charge. Hence con- stant high output is not attained at the end of compari- Beyond these options, without complex gating tech- son, which can be observed as a slight decrease from 1 niques or clocking techniques, introducing parasitic V in the transient response of HDLC in Figure 4. This is capacitance is preferred. Using an extra tail transistor overcome in LRCHDLC, which prevents the leakage at with parasitic capacitances holds the maximum out- the end of comparison, offering a strong 1 as shown in put differential voltage of preamplifier with alternative Figure 6. activation of tail transistors. Proper sizing of both the tail transistors and input transistors with channelized In conventional dynamic comparators, when there is a charging of parasitic capacitances guarantee holding transition from reset to evaluation phase, the moment of maximum difference gain at the preamplifier out- the clock changes, the differential discharging of pre- puts. Meanwhile latch activation is also fastened by amplifier outputs is rapid, and the effective differential prior charging of output nodal voltages of latch so that voltage is channelized into the latch for comparison. the time taken for latch initiation is neglected. In the 206 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 conventional comparator, during the evaluation phase voltage and the drain current of M11 or M12 as depicted the output nodes of preamplifier start discharging in Eq. (1) and once it goes less than threshold required for input transistors of second stage, the latch gets activated. In t C the proposed comparator, when the clock moves into 1  LVthn (1) I a transition for evaluation phase, the preamplifier is M11/M12 ready with maximum differential voltage and latching where Vthn is the threshold voltage of NMOS transistor starts without taking time for initiation thereby signifi- of cross connected inverter to be on. IM11/M12 can also be cantly reducing power consumption and delay. approximated as half of the tail current of T3. Hence IM11/ M12 can be written as shown in Eq. (2) The proposed comparator has made significant efforts to reduce power by sustaining the latch output nodal t 2 CLV 1  thn voltages at a minimum voltage which reduces the (2) time lapse of complete discharging down to zero and Itail3 charging from initial value. In preamplifier, larger input The second component tlatching is the time taken for re- transistors are employed to increase the transconduct- generation to begin which involves the latching pro- ance which in turn deteriorates the offset voltage [4]. cess and is given in Eq. (3) as follows Amongst many topologies that render fast latching process, introducing pass transistor guarantees equal charging at both output nodes in due course reducing t CL ln VDDlatching  g (3 power consumption. m,eff 2V ) o Where ΔVo is the initial output voltage difference, gmeff is the effective transconductance of the latch stage, es- 5 Analysis of performance metrics pecially covering transistors that couple the preampli- fier and latch stage. CL is the output load capacitance. Three performance metrics, namely delay, power and The initial output voltage difference can be derived energy efficiency are analyzed for the proposed archi- through Eq. (4), Eq. (5), Eq. (6) and Eq. (7). tecture to prove its suitability for high end applications. Section 5 discusses all the three-performance metrics Vo  IORO (4) in detail in the subsections with necessary graphs and mathematical analysis. Section 5.1 discusses the anal- The initial output voltage difference can be written as ysis of delay with sub sections discussing the mathe- the product of effective resistance Ro and current differ- matical analysis of delay and influence of input voltage ence Io. Io can be expanded as the product of transcon- over delay. Section 5.2 and 5.3 discusses the analysis ductance gm0 and input voltage Vio of the correspond- of average power consumption and energy efficiency, ing stage. Also, effective resistance Ro can be written respectively. as the ratio of output nodal voltage difference ∆VFn/Fp in the preamplifier stage and the tail current of second 5.1 Delay stage. To compare the factors that influence the delay in con- V V Fn/Fp O  gmoVio (5) ventional as well as proposed architectures, detailed Itail3 derivation of both the architectures is presented in this section. The input voltage Vio is the threshold requirement of pull-down transistors of preamplifier and hence re- 5.1.1 Delay of Conventional Comparator placed as follows in equation (7). The delay associated with conventional double tail dy- namic latched comparator architecture comprises two V V  2V  Fn/Fp factors, namely t1 and tlatching. t1 is the time taken by the o thn gmo1,2 (6) I output capacitance to discharge until anyone of the tail3 NMOS transistors of the cross connected inverters is on The preamplifier output nodal difference can be de- as shown in Eq. (0). rived as shown in eq. (7) and eq. (8). The resistance is written with time constant equivalent and hence writ- t1  R1CL (0) ten as the time lapse for discharging CL. The effective resistance R1 during the discharging of CL (7) at output nodes can be replaced as ratio of threshold 207 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 To find ΔVo for the proposed comparator, it is signifi- (8) cant to note that the preamplifier, which is equipped with two tail transistors generating only the minimum required tail current for amplification. This necessary Substituting eq. (2) in the above eq. (8), the final equa- tail current helps in sustaining the maximum gain with tion of ∆VFn/Fp is given as, low power consumption. Figure 7 illustrates the tail currents of transistor M5 in both the conventional and proposed comparators. The gain can also be increased (9) further and sustained further with a compromise on power consumption. The differential output voltage for the proposed comparator is shown in eq. (17). The final value of ∆Vo after substituting the preamplifier output nodal difference as V V  2 V V  g Fn/Fp 4V  o DD tp mo1,2 (17) I  thn Vthn  gmo1,2Vdiff gV m1,2 CL tail3 o 2 (10) CL, preamp Itail3 The sizing of the tail transistors is chosen in such a way that the preamplifier will offer maximum gain (optimal The total latching delay can be further obtained as tail current which will in turn not increase the power) equation (15) by substituting in (4). during the initiation of the latch. This helps with effec- tive and fast decisions during the latching phase. The threshold offered by the PMOS pass transistor takes the t CL latc ing  lnV 1 h D (11) g D place of the threshold of NMOS transistor of cross con- m,eff 2VO nected latch as shown below in eq. (18). Substituting ΔVfn/fp, the ΔVo can be expanded as eq. (19). Which can be rewritten as follows as shown in eq. (14) C 2 (18) L V ln DDCL, preampItail3   (14) g 2 m,eff 8 Vthn gmo1,2Vdiff gm1,2CL The total delay for a conventional comparator is de- (19) rived by adding t1 and tlatching given in eq. (15) In proposed comparator, the parameter ∆V o is not only T 2 CLV thn improved since the capacitance CP1 + CP2 is lesser when total ,Conventional   I compared to the output capacitance C tail3 L, preamp in case of (15) conventional comparator. The tlatching can now be up- C V C I 2 dated as eq. (19)  L DD L, preamp tail3 gm ,eff 8V 2 thn  gmo1,2Vdiff gm1,2CL C  2 L ln VDD (CP1 CP2 )Itail3 g (19) m,eff 2VDD V tp VDD  2Vtp  gmo1,2Vdiff gm1,2CL 5.1.2 Delay of Low power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC) For the proposed comparator LRCHDLC, the first com- The total delay for the proposed comparator LRCHDLC ponent of delay t is shown in eq. (20) 1 can be derived as shown in eq. (16). In proposed comparator, the necessary threshold is of- fered by the charge equally shared between the output nodes by the PMOS pass transistor which is represent- ed as V (20) DD- 2Vtp. C ( 2 1  L VDD  V t tp ) (16) Itail3 Both the discharging of preamplifier output nodes and charging of latch output nodes (to threshold required The second component of total delay, tlatching as shown for latching) is not required in the proposed architecture. in eq. (3) can be approximated for the proposed com- Hence the component t parator as shown below. 1 as well as tlatching is reduced. The 208 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 transient response of the proposed comparator in Fig- tional comparator, LRCHDLC (90 nm) and LRCHDLC (45 ure 6 depicts the improvement in ΔVo through change nm) as shown in Table 1.The conventional comparator in ΔVFn/Fp. records delays ranging from 138 ps to 592 ps for vari- ous VCM and VDIFF values, whereas the proposed com- parator shows less and consistent delay values, within lower range varying from 26.79 ps to 25.73 ps in case of LRCHDLC using 90 nm technology and from 19.79 ps to 29.09 ps in case of LRCHDLC using 45 nm technology. This implies that in case of proposed comparator, only minimal standard time lapses are taken for charging and discharging at the output nodes of the proposed comparator. Wide varying VCM and VDIFF does not influ- ence the range of delays in the proposed comparator due to minimum t1 and tlatching. Figure 8 and 9 shows the transient response of LRCHDLC and conventional architecture at 45 nm for various sets of VCM ranging from 0.5 V to 0.9 V. Figure 10 shows the variations in Figure 7: Tail currents of the preamplifier in conven- the output nodal voltages, outn and outp in the tran- tional as well as proposed comparator sient response for various VDIFF ranging from 20 mV to 100 mV with a step size of 20 mV for VCM – 0.7 V. Dur- With respect to the proposed comparator, the influ- ing second evaluation phase, Figure 8 shows that outp ence of the component t1 on the total delay is reduced rises first for VCM – 0.5 V first and then it can be observed qualitatively. The reason is that the proposed architec- that it is followed by VCM – 0.6 V upto 0.9 V. Similarly, in ture utilizes the internal parasitic capacitances. The Figure 9, outn rises first for VCM – 0.9 V and then goes load capacitances are replaced by parasitic capacitanc- down to VCM- 0.5 V. In case of conventional comparator, es (CP1 + CP2) predominantly to take up the charge from Delay is inversely proportional to VCM and VDIFF. Whereas, Fn/Fp nodes, rather than CL. The outcome of t1 which is in the case of proposed comparators, the delay is di- latch initiation, is already achieved through pass tran- rectly proportional to VCM and inversely proportional sistor precharging the outn/outp to 0.5 V during reset to VDIFF. The mathematical equations for total delay of phase itself. Also, the preamplifier with two tail transis- conventional and proposed comparators are derived tors transfers the maximum gain earlier to the latch. in the previous section as seen in Equations (15) and Added advantage is that the preamplifier is not actively (20) respectively. The initial output voltage difference consuming any power for amplification after the maxi- ΔVo , which is directly proportional to ΔVfn/fp is observed mum gain is transferred. The need for NMOS threshold to be proportional to the differential voltage, ΔVdiff as is now replaced as the threshold of PMOS Pass transis- shown in Equations (5), (6) and (8). From Equation (3), tors since they pull up outn/outp to 0.5 V or VDD/2. There Tlatching is inversely proportional to ΔVo proving the in- is a major reduction in tlatching as the outn and outp are direct proportionality between VDIFF and delay. The re- already charged up to 0.5 V during the reset phase, way duction of delay with increase in VDIFF can be explained before the latching is initiated. with respect to two factors. The first factor is that when the VDIFF becomes larger, the gain naturally increases, 5.1.3 Variation of delay with VCM and VDIFF A meticulous study of the variation in delay with vari- ous factors such as VCM, VDIFF and supply voltage is also presented in this section. A fast-decision-making pro- cess is one of the key requirements of high-speed ADC, that can be assured by analyzing the variation of de- lay with VCM and VDIFF. To determine the robustness and efficiency of the proposed architecture, rigorous and multiple simulations are carried out for a wide range of VCM and VDIFF. The proposed architecture offers con- sistent range of delay and power even when VCM and VDIFF drops down proving its high sensitivity in decision making during evaluation phase. Simulations were car- ried out for observing delay at various VCM values (0.5 V to 0.9 V with a step size of 0.1 V) and VDIFF values (10 Figure 8: Transient response of LRCHDLC (45 nm) with mV to 100 mV with a step size of 10 mV) on conven- VDIFF = 20 mV for various VCM values from 0.5 V to 0.9 V 209 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 Table 1: Analysis of delay for various VCM and VDIFF for conventional (90 nm) and LRCHDLC (90 nm & 45 nm) Conventional Comparator LRCHDLC (90 nm) LRCHDLC (45 nm) VDIFF (mV) VCM (V) VCM (V) VCM (V) 0.9 0.8 0.7 0.6 0.5 0.9 0.8 0.7 0.6 0.5 0.9 0.8 0.7 0.6 0.5 10 179 206 261 404 592 26.79 26.41 26.1 25.92 25.86 19.79 19.51 19.31 19.2 19.13 20 166 190 240 369 584 26.57 26.26 26 25.86 25.83 19.72 19.46 19.28 19.18 19.12 30 158 182 228 346 578 26.37 26.11 25.91 25.81 25.81 19.64 19.41 19.25 19.17 19.12 40 153 175 219 329 572 26.2 25.98 25.84 25.76 25.79 19.57 19.37 19.23 19.15 19.11 50 150 171 212 314 567 26.06 25.85 25.76 25.72 25.78 19.51 19.32 19.2 19.14 19.11 60 147 167 206 301 560 25.91 25.75 25.69 25.68 25.76 19.45 19.29 19.18 19.13 19.1 70 144 163 200 290 554 25.78 25.66 25.63 25.65 25.75 19.39 19.25 19.17 19.12 19.1 80 142 160 195 280 545 25.66 25.58 25.58 25.63 25.74 19.34 19.22 19.15 19.11 19.1 90 140 157 191 270 535 25.55 25.51 25.53 25.61 25.74 19.28 19.19 19.13 19.11 19.09 100 138 154 186 262 521 25.46 25.44 25.48 25.59 25.73 19.25 19.16 19.12 19.1 19.09 and the topology also supports by transferring maxi- mum gain to the readily precharged latch. Secondly, the charging and discharging time during evaluation phase is well sustained by precharging of output nodes during reset phase itself, which significantly reduces the latching delay, tLatching. In all conventional dynamic comparator topologies, a lower VCM makes it difficult for the input transistors of preamplifier to switch to linear state for amplification. Also, insufficient gain further slows down the decision- making process. However, the proposed architecture precharges the output nodes outn and outp during reset phase, making it easier to proceed to latching Figure 10: Transient response of LRCHDLC (45 nm) with phase more easily on time. In LRCHDLC, during the sec- V ond evaluation phase after charge sharing, the latching CM – 0.7 V for various VDIFF values from 20 mV to 100 mV. time increases with a rise in VCM as seen in Figure 8 served seen in Table 1 where there is a direct proportion- ality between VCM and delay values. It can be observed Whereas in conventional architecture, Figure 9 shows from Figure 8 and 9 shows that the decision-making time that the latching time decreases with rise in VCM but is larger in the case of conventional architecture, when results in a larger delay due to the absence of a charge compared to the proposed architecture, LRCHDLC. sharing mechanism. Quantitatively, this can also be ob- Figure 9: Transient response of Conventional compar- Figure 11: Variation of delay with VDD for VCM - 0.7 V and ator (45 nm) with VDIFF = 20 mV for various VCM values VDIFF – 20 mV, Fclk – 1GHz (LRCHDLC – 45 nm) from 0.5 V to 0.9 V 210 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 Table 2: Analysis of power consumption for various VCM and VDIFF for conventional (90 nm) and LRCHDLC (90 nm & 45 nm) V Conventional Comparator (90 nm) LRCHDLC (90 nm) LRCHDLC (45 nm) DIFF V (mV) CM (V) VCM (V) VCM (V) 0.9 0.8 0.7 0.6 0.5 0.9 0.8 0.7 0.6 0.5 0.9 0.8 0.7 0.6 0.5 10 5.01 4.96 4.91 4.87 4.76 2.62 2.54 2.47 2.4 2.31 1.49 1.32 1.11 0.88 0.69 20 4.94 4.9 4.85 4.81 4.71 2.61 2.53 2.46 2.39 2.3 1.49 1.32 1.1 0.88 0.68 30 4.9 4.86 4.81 4.76 4.67 2.59 2.51 2.44 2.38 2.3 1.5 1.32 1.09 0.87 0.68 40 4.88 4.83 478 4.72 4.64 2.58 2.5 2.44 2.37 2.3 1.5 1.31 1.09 0.86 0.67 50 4.86 4.81 4.75 4.69 4.61 2.57 2.49 2.43 2.37 2.29 1.5 1.31 1.08 0.85 0.67 60 4.84 4.79 4.73 4.66 4.58 2.55 2.48 2.42 2.36 2.29 1.49 1.3 1.07 0.85 0.66 70 4.82 4.77 4.71 4.64 4.56 2.54 2.47 2.41 2.35 2.29 1.49 1.29 1.07 0.84 0.66 80 4.8 4.75 4.69 4.62 4.54 2.54 2.47 2.4 2.34 2.28 1.49 1.29 1.06 0.84 0.65 90 4.79 4.74 4.68 4.6 4.53 2.53 2.46 2.4 2.34 2.28 1.48 1.28 1.05 0.83 0.65 100 4.78 4.72 4.66 4.59 4.51 2.52 2.45 2.39 2.33 2.27 1.48 1.28 1.05 0.83 0.65 The delay of the proposed architecture, LRCHDLC (45 rect proportionality with VCM. The significant change in nm) is analyzed for various supply voltages ranging from the case of the proposed comparator is that the over- 0.7 V to 1 V as shown in Figure 11. As the supply voltage all range has dropped to a greater extent, maintaining increases, the charge quantity to be held by the nodes the same direct proportionality with VCM and indirect also increases. As per the latching mechanism in the pro- proportionality with VDIFF. Power consumption at each posed circuit, tlatching increases as the minimum charge to instant is measured for two cycles of complete com- be held at the output nodes also increases. The regen- parison process for both conventional and LRCHDLC eration time required for decision making also propor- simulated at 45 nm technology, as shown in Figure 12. tionally increases. It can be noted from Figure 11 that the proposed architecture offers stable delay irrespective of In the case of LRCHDLC, the modified preamplifier with VDIFF values for VDD values from 1 V to 0.8 V, reassuring the two tail transistors limits power dissipation by turning robustness of the proposed architecture. off the preamplifier once maximum gain is transferred. Figures 13 and 14 show power consumption at every 5.2 Average power consumption instant of the proposed architecture for various sets of VDIFF and VCM respectively, to observe their influence on Analogous to delay, power consumption is also ana- the performance. Power consumption during the sec- lyzed for the conventional dynamic comparator, LRCH- ond evaluation phase shows a significant drop when DLC (90 nm), and LRCHDLC (45 nm) with respect to var- compared to the evaluation phase before successful iations in VCM and VDIFF, as shown in Table 2. With respect charge sharing, ensuring minimal power consumption. to average power consumption, conventional architec- Also, the time lapse of active state of preamplifier is less ture reflects a direct proportionality with V in the case of proposed comparator, thereby offering a DIFF and indi- Figure 12: Power consumption of Conventional and Figure 13: Power consumption of LRCHDLC (45 nm) at proposed comparator, LRCHDLC with VDIFF – 20 mV, VCM every instant for various VDIFF values – 0.7 V, VDD – 1V at 45 nm technology 211 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 regularized power consumption for all wide variations 5.3 Energy efficiency in VCM and VDIFF. Energy efficiency is a metric that indicates the ability of the comparator to complete a full cycle of reset phase and comparison phase, with minimal power consump- tion while maintaining maximum accuracy and perfor- mance. By integrating the power formulae over a pe- riod of two full cycles, energy efficiency is calculated. In the case of proposed comparator, the range of energy efficiency has drastically decreased when compared to the conventional architecture as seen in Table 7. This can be aligned with the drastic reduction in over- all power consumption. This is mainly because com- plete charging and discharging of output nodes is not required in the proposed architecture, which reduces power and energy efficiency. Because of this charge Figure 14: Power consumption of LRCHDLC (45 nm) at held at the output nodes of the latch by the pass tran- very instant for various VCM values sistor, significant amount of power dissipated during charging and discharging of latch output nodes at Figures 13 and 14 clearly align with Table 2, proving every cycle (reset & evaluation) is reduced and hence the direct proportionality with VCM and indirect propor- there is a reduction in energy spent per comparison. tionality with VDIFF. Peak power consumption points are The energy spent for effective comparison is observed highlighted for various VCM and VDIFF values. The peak varying the supply voltages for proposed architecture, power is consumed exactly at the onset of the second LRCHDLC with VCM – 0.7 V varying the value of VDIFF from reset phase where charge sharing is set to occur. It is 10 to 100 mV, as shown in Figure 16. highly significant to note that the power consumed during the second evaluation phase is lower than the previous evaluation phase, irrespective of changes in VCM and VDIFF. Figure 16: Variation of energy efficiency with VDD for VCM - 0.7 V and VDIFF – 20 mV, Fclk – 1GHz The overall range of energy efficiency decreases with a Figure 15: Variation of power consumption with VDD for reduction in VDD, but the individual response shows di- VCM -0.7 V and VDIFF – 20 mV, Fclk – 1GHz rect proportionality with VDIFF, whereas delay and pow- er show stable responses with VDIFF. This is one of the Like delay, average power consumption is analyzed reasons that as the technology of the proposed com- for proposed architecture for various supply voltages parator goes from 90 nm to 45nm, energy efficiency ranging from 0.7 V to 1 V as shown in Figure 15. The increases as seen in Table 7. power consumption of any analog circuit is directly proportional to VDD until there is no major variation in current proportionality due to change in device phys- ics. Both delay and power are highly stable irrespective of VDIFF for VDD values ranging from 1 V to 0.8 V. 212 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 6 Results and discussion 6.2 Influence of transistor sizing ratio on performance 6.1 Monte Carlo analysis The sizing ratio of the transistors is chosen after wide variation of widths of all transistors to optimize delay and power without causing any logic degradation, Monte Carlo simulations were performed for all the thereby ensuring accurate transient response for every performance parameters which in case of hybrid archi- comparison. For the proposed architecture LRCHDLC tecture, gives a delay of 56 ps, power consumption of simulated at 45 nm technology, the variation of per- 8.6µW, and energy efficiency of 98 aJ/comparison. For formance parameters like delay, energy efficiency and the final proposed architecture, LRCHDLC simulated in power with respect to transistor sizing are depicted in 90 nm, Monte Carlo simulation offered better perfor- Figures 17, 18 and 19 respectively. mance parameters such as a delay of 15.32 ps, power consumption of 2.42 µW, and energy efficiency of 37.15 aJ/comparison. When Monte Carlo simulations per- formed for LRCHDLC at 45 nm CMOS technology, the architecture offered Power consumption of 890.62 nW, an energy efficiency of 1.1 fJ/comparison and delay of 18.67 ps. The mean and standard deviation of the per- formance metrics say power consumption, delay and energy efficiency for the proposed comparator (both 90 nm and 45 nm technology) are listed in Table 3. Monte Carlo simulations are carried out to analyze the robustness of the proposed architecture for every mis- match and fabrication errors. Mathematically, it can be proven that the histogram follows a gaussian distribu- tion since 99% of the samples in histogram lie between Figure 17: Variation of delay with respect to width of +3 σ and -3 σ. the transistors in LRCHDLC (45 nm) Table 3: Mean and standard deviation of performance metrics using Monte Carlo Simulation Monte Carlo simulation (N=1000) Mean Standard deviation LRCHDLC at 90 nm technology Power consumption 2.42 µW 195.37 nW Delay 15.32 ps 2.48 ps Energy efficiency 37.15 aJ 16.09 aJ LRCHDLC at 45 nm technology Power consumption 890.62 nW 23.81 nW Delay 18.67 ps 1.32 ps Figure 18: Variation of Energy Efficiency with respect Energy efficiency 1.11 fJ 53.17 aJ to width of the transistors in LRCHDLC (45 nm) Table 4: Sizing of the transistors used in the proposed Also, more than 90% of the samples lie between +2σ architecture, LRCHDLC (45 nm) and -2σ and 70% of samples in the histogram fall be- tween +1σ and -1σ. The lower standard deviation val- Transistors Width (m) ues in the case of the proposed comparators ensure consistency and reliability of the design. Most of the M1 3µ values fall within +1σ and -1σ in the normal distribu- M2 1 µ tion, proving the robustness of the design. Also, the M3, M4 120n histogram matches the Gaussian curve with slight M5 3.1 µ skewness. M6 1 µ M7 – M12 120n M13 300n M14 120n 213 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 used in preamplifier and latch, and the common mode voltage. The transistor sizing impacts the delay by en- hancing the effective transconductance of preamplifier and latch input transistors. Inferred from mathemati- cal analysis of delay, the differential voltage ∆V0 is in- creased in the proposed architecture. 6.3 Summary and discussion For proper comparison, the conventional and proposed comparator LRCHDLC are designed in 90 nm as well as 45 nm technology with a clock frequency of 1 GHz for optimized transistor sizing ratios using Cadence Virtu- Figure 19: Variation of Power consumption with re- oso Spectre Simulator. Also, process corner variations spect to width of the transistors in LRCHDLC (45 nm) are analyzed for power, delay, and energy efficiency in case of conventional, hybrid and proposed architec- The sizing of the transistors influences the transcon- tures shown in Table 7. The simulation results in Table ductance thereby causing a major change in power 7 are carried out using Cadence Virtuoso Spectre using consumption and delay of the circuit. From Figure 17, 90 nm and 45 nm CMOS technology, for VDD =1 V, FCLK=1 it is observed that there is a drastic increase in delay GHz, VCM = 0.7 V and VDIFF = 20 mV. when the transistor width increases in the case of pass transistor M14 and Pull up transistors M7 and M8, rang- Table 5 shows the comparison of the performance met- ing up to 160 ps. This influence tends to decrease in the rics of the proposed architecture with existing architec- case of the pull-down input transistors of the latch M9 tures from literature. When compared to the existing and M10. The rest of the transistors show stable yet mi- works in the literature review, the proposed architec- nor variations in the range of 20 ps to 40 ps. ture demonstrates a significant reduction in power consumption, energy efficiency and delay without any The graph in Figure 18 shows the variation of energy compromise between each other. Compared to the ex- efficiency with respect to transistor width. The pull up isting works as seen in Table 5, it is significantly evident transistors of the preamplifier M1 and M2 shows a de- that the Power delay product is optimized with optimi- cline in energy efficiency per comparison, whereas the zation in both power and delay rather than increased pass transistor M14 as well as pull up transistors of the power with lowered delay or vice versa. The proposed latch M7 and M8 shows a significant increase in energy comparator shows significant improvement in delay efficiency per comparison. The rest of the transistors and power when compared to conventional architec- show very minor variation in the range of atto joules ture, [1], [4], [8], [17], and [21]. Rather than achieving rather than femto joules from which it can be inferred drastic improvement in one of the performance pa- that the overall range of energy efficiency is narrow and rameters, compromising the other performance met- robust to sizing changes. The graphical plot depicted rics, concurrent improvement in power and delay is in Figure 19 shows the variation of power with respect achieved in the proposed architectures. The trade-off to the width of the transistors. The pass transistor M14 as observed between power and delay in the proposed well as pull up transistors of the latch M7 and M8 offers comparator is low when compared to the existing to- a notable increase in power consumption up to 4 µW. pologies of the literature. Table 6 shows the progres- The intensity of variation is reduced yet minimal rise in sive reduction of power and delay right from con- power until 2.5 µW is seen when the width of transis- ventional architecture to the proposed architecture. tors M11, M12, M5, and M13 is increased. The modified preamplifier with an extra tail transistor and latch with pass transistor to hold charge shows a The input pull-down transistors of the preamplifier as drastic improvement in power consumption, reduced well as latch say M3, M4, M9, and M10 offer almost con- three times when compared to conventional compara- stant power consumption in the range of 0.9 nW to 1 tor architectures. The drastic reduction in power and µW. On the contrary, the transistors M5, M1 and M2 offer delay simultaneously is solely due to the architectural a decline in power when their widths are increased. The change in latch and the tail transistors in preamplifier transistor sizing used in LRCHDLC (45 nm) is shown in that helps in parallel sustaining of charge in output Table 4. It is inferred from simulations and mathemati- nodes and holding maximum gain in preamplification cal study that the delay and power solely depend not respectively. only on transistor sizing but also on the supply volt- age, the input differential voltage, load capacitances 214 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 Table 5: Comparison of the proposed work with existing literary works Ref [1] [8] [4] [21] [17] [2] Conventional HDLC LRCHDLC LRCHDLC Technology (nm) 65 90 180 180 90 90 90 90 90 45 Operating frequency 5 1 1.5 0.5 0.5 1 1 1 1 1 (GHz) VDD (V) 1 1 1.8 1.8 1 1 1 1 1 1 Offset voltage(mV) 8 2.44 2.60 2.19 1 - - - - Power (µW) 73 - - 347 140.76 32.62 4.8 6.53 2.46 1 Delay (ps) - 20.95 196.9 - 91.19 - 276 47 26 19 Energy efficiency(fJ) 0.253 8.18 40.45 - - 32.6 12.61 0.48 0.33 0.969 No of transistors 14 18 19 15 15 14 13 14 14 14 PDP (fJ) - - - - 12.8 - 0.41 0.30 0.063 0.019 Table 6: Comparison of delay and power of literature and proposed work for VCM = 0.7 V and VDIFF = 20 mV Technology Architecture Delay(ps) Power(µW) 90 nm Conventional DTDLC 276 4.83 65 nm Charge sharing DTDLC [1] - 73 90 nm Shared charge reset DTDLC [2] 51 32.62 90 nm Hybrid DTDLC 47 6.53 90 nm Low power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC) 26 2.46 45 nm Low power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC) 19 1 Table 7: Comparison of conventional and proposed architecture with improvisation for VCM =0.7 V VDIFF = 20 mV Fclk = 1 GHz for various process corner variations Conventional architecture Hybrid Architecture Proposed architecture Proposed architecture (90 nm) HDLC (90 nm) LRCHDLC (90 nm) LRCHDLC (45 nm) Average Delay Energy ef- Average Delay Energy ef- Average Delay Energy ef- Average Delay Energy ef- power (ps) ficiency power (ps) ficiency power (ps) ficiency power (ps) ficiency (µW) (fJ) ( µW ) (fJ) (µW ) (fJ) ( µW ) (fJ) FF 5.02 130 13.21 8.68 41 0.834 2.65 19 0.581 1.32 14 0.563 SS 4.63 645 11.91 4.99 58 0.250 2.28 36 0.170 0.675 28 1.5 SF 4.60 590 11.91 5.10 43 0.285 2.35 38 0.185 0.888 24 1.2 FS 4.89 192 12.81 8.03 56 0.743 2.55 18 0.536 1.15 14 0.655 TT 4.83 276 12.61 6.53 47 0.480 2.46 26 0.332 1 19 0.969 The layout of the proposed architecture using 45 nm Peak differential voltage is sustained by ensuring maxi- CMOS technology is shown in Figure 20. The proposed mum voltage swing with the help of the additional tail architecture LRCHDLC using 45 nm CMOS technology transistor (through nodal parasitic capacitances) in the holds an area of 23.66 µm2. (4.855 µm * 4.875 µm). preamplifier circuit. This helps with accurate decision making and improves the sensitivity of the comparator. 6.4 Key advantages of the proposed architecture The proposed architecture achieves concurrent optimi- zation of power and delays using a simplified control The power consumption of the proposed topology, phenomena with an additional transistor in both pre- LRCHDLC, is reduced by restricting the active duration amplifier and latch, say M6 and M14 respectively. of the preamplifier and prior precharging of the output nodes of the latch. The proposed architecture is suitable for Flash ADC The process of latching starts without waiting for the which requires high speed and low power consump- latch output nodes for charging up to minimum thresh- tion, with minimum complexity in clocking and control old as its already completed in reset phase, thereby re- schemes. ducing the overall time for completing decision mak- ing phase. 215 J. V. S. Thirunavukkarasu et al.; Informacije Midem, Vol. 55, No. 4(2025), 201 – 217 2. H. S. Bindra, C. E. Lokin, D. Schinkel, A. Annema and B. Nauta, “A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise,” in IEEE Journal of Solid-State Circuits, vol. 53, no. 7, pp. 1902-1912, July 2018, https://doi.org/10.1109/JSSC.2018.2820147. 3. Vijay Savani, N.M. Devashrayee,”Design and analysis of low-power high-speed shared charge reset tech- nique based dynamic latch comparator”, Microelec- tronics Journal, Volume 74, Pages 116-126, 2018, https://doi.org/10.1016/j.mejo.2018.01.020. 4. Dubey, A. K., & Nagaria, R. K, “Design and Analy- sis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect” J. Circuits Syst. Comput. 28, 1950157:1-1950157:18, 2019, https://doi.org/10.1142/S0218126619501573. 5. B. Goll and H. Zimmermann, “A Comparator with Figure 20: Layout of the proposed architecture, LRCH- Reduced Delay Time in 65-nm CMOS for Supply DLC Voltages Down to 0.65 V,” IEEE Transactions on Cir- cuits and Systems II: Express Briefs, vol. 56, no. 11, pp. 810-814, Nov. 2009, 7 Conclusion https://doi.org/10.1109/TCSII.2009.2030357. 6. Varshney, V., & Nagaria, R. K, “Design and analysis of ultra high-speed low-power double tail dy- This paper demonstrates that the proposed latch stage namic comparator using charge sharing scheme” is more effective in achieving optimized power and de- Aeu-international Journal of Electronics and lay without any counter mechanisms rising one anoth- Communications 116, 153068, 2020, er parameter. Monte Carlo analysis considering corner https://doi.org/10.1016/j.aeue.2020.153068. and mismatch concludes that the proposed compara- 7. S. Chevella, D. O’Hare and I. O’Connell, “A Low- tor LRCHDLC simulated at 45 nm CMOS technology of- Power 1-V Supply Dynamic Comparator,” in  IEEE fers a delay of 18.67 ps, power consumption of 0.890 Solid-State Circuits Letters, vol. 3, pp. 154-157, µW, and an energy efficiency of 1.1fJ/conversion. A 2020, thorough simulation study validates the effectiveness https://doi.org/10.1109/LSSC.2020.3009437 of managing the counter effects that arise when there 8. Avaneesh K. Dubey, R.K. Nagaria,” Optimization is a rise in power with a delay reduction. When the pro- for offset and kickback-noise in novel CMOS dou- posed LRCHDLC (90 nm) is compared to conventional ble-tail dynamic comparator: A low-power, high- architecture, the delay is reduced by 91%, energy effi- speed design approach using bulk-driven load”, ciency is reduced by 92%, and the average power con- Volume 78, pages 1-10, 2018, sumption is reduced by 49%. https://doi.org/10.1016/j.mejo.2018.05.006. 9. Yaqubi, E., Zahiri, S.H. Optimum design of a dou- ble-tail latch comparator on power, speed, offset 8 Conflict of Interest and size. Analog Integr Circ Sig Process 90, 309– 319 (2017), The authors declare no conflict of interest. https://doi.org/10.1007/s10470-016-0903-1. 10. Mehrdad Amirkhan Dehkordi, Massoud Dousti, Seyed Mehdi Mirsanei, Soorena Zohoori, “ A dy- 9 References namic power-efficient 4 GS/s CMOS compara- tor“, Aeu-international Journal of Electronics and Communications, Volume 170, 154812, 1. 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Hadi Pahlavanzadeh, Mohammad Azim Karami, “A Doubled Transistor Latch Common-Mode In- sensitive Rail-to-Rail Regenerative Comparator for Low Supply Voltage Applications Aeu-inter- national Journal of Electronics and Communica- tions, Volume 169, 154744,2023, https://doi.org/10.1016/j.aeue.2023.154744. 217 218 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.402 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 4(2025), 219 – 228 Smart Prediction and Trust-based Transmission in Delay-Targeted Networks for Aviation Communication Shanmugavel Deivasigamani1, Rajinigirinath Dhandapani2 1Department of Artificial Intelligence and Data Science, JEPPIAAR Institute of Technology, Chennai, Tamilnadu, India. 2Department of Computer Science and Engineering, Sri Muthukumaran Institute of Technology, Chennai, India Abstract: Delay Targeted Networking (DTN) facilitates communication in environments with sporadic connectivity and long delays, such as space missions and isolated locations. The rise of 5G technology has increased the demand for in-flight services, challenging aviation communication to provide reliable data through satellite systems and traditional macro-cellular networks. However, airborne communication’s dynamic nature poses significant challenges, including irregular connections and variable delays. To tackle these challenges, a novel Smart Prediction and trAnsmission mechanism for delay taRgeted networK (SPARK) technique has been proposed to enhance the efficiency and reliability of DTNs in aviation communication. The proposed SPARK method includes a comprehensive node trust evaluation system, utilizing direct and indirect trust metrics to ensure network reliability. After evaluating node trustworthiness, the proposed method restricts heavy load traffic based on trustworthiness. The Prediction and Transmission Module incorporates the Cooperative Watchdog System (CWS) to dynamically update each node’s reputation score. Nodes are classified into cooperative, partially cooperative, neutral, mislead, and selfish nodes. Experimental results demonstrate the effectiveness of the suggested SPARK framework utilizing evaluation parameters including delivery rate, delay, overhead, hop count, throughput, complexity, and resource utilization. The delay rate of the proposed SPARK method is 18.67%, 19.87%, and 14.45% is lower than the existing OPRNET, IDRL, and CCMA, techniques respectively. The distribution of the proposed SPARK framework attains a forwarding rate of 11% for selfish, and 9.2% for misleading based on their packet forwarding behavior. Keywords: Delay Targeted Network; transmission; routing; prediction; communication Pametno napovedovanje in prenos na podlagi zaupanja v omrežjih z zamikom za letalsko komunikacijo Izvleček: Omrežje z zamikom (DTN) olajšuje komunikacijo v okoljih z naključno povezljivostjo in dolgimi zamiki, kot so vesoljske misije in izolirane lokacije. Razvoj tehnologije 5G je povečal povpraševanje po storitvah med letom, kar predstavlja izziv za letalsko komunikacijo, da zagotovi zanesljive podatke prek satelitskih sistemov in tradicionalnih makrocelularnih omrežij. Vendar pa dinamična narava letalske komunikacije predstavlja pomembne izzive, vključno z nepravilnimi povezavami in spremenljivimi zamiki. Za reševanje teh izzivov je bila predlagana nova tehnika Smart Prediction and trAnsmission mechanism for delay taRgeted networK (SPARK), ki izboljšuje učinkovitost in zanesljivost DTN v letalski komunikaciji. Predlagana metoda SPARK vključuje celovit sistem ocenjevanja zaupanja vozlišč, ki uporablja neposredne in posredne metrike zaupanja za zagotavljanje zanesljivosti omrežja. Po oceni zanesljivosti vozlišč predlagana metoda omeji promet z veliko obremenitvijo na podlagi zanesljivosti. Modul za napovedovanje in prenos vključuje sistem Cooperative Watchdog System (CWS) za dinamično posodabljanje ocene ugleda vsakega vozlišča. Vozlišča so razvrščena v sodelujoča, delno sodelujoča, nevtralna, zavajajoča in sebična vozlišča. Rezultati poskusov dokazujejo učinkovitost predlaganega okvira SPARK, ki uporablja parametre ocenjevanja, vključno s hitrostjo dostave, zamudo, režijskimi stroški, številom skokov, prepustnostjo, kompleksnostjo in izkoriščenostjo virov. Stopnja zamude predlagane metode SPARK je 18,67%, 19,87% in 14,45% nižja od obstoječih tehnik OPRNET, IDRL in CCMA. Porazdelitev predlaganega okvira SPARK doseže stopnjo posredovanja 11% za sebične in 9,2% za zavajajoče vozlišča na podlagi njihovega vedenja pri posredovanju paketov. Ključne besede: Mreža z zamikom; prenos; usmerjanje; napovedovanje; komunikacija * Corresponding Author’s e-mail: shankan2005@gmail.com How to cite: D. Shanmugavel et al., “Smart Prediction and Trust-based Transmission in Delay-Targeted Networks for Aviation Communication", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 4(2025), pp. 219–228 219 D. Shanmugavel et al.; Informacije Midem, Vol. 55, No. 4(2025), 219 – 228 1 Introduction The rest of the work are ordered in the following man- ner. Section II provides the literature evaluation, while Delay Targeted Networking (DTN) is a networking Section III describes the proposed methodology. Sec- protocol that is intended to function well across very tion IV examines the experiment results. Section V con- long distances and in conditions that conventional tains the paper’s conclusion. networking may find challenging [1,2]. In the realm of aviation communication, the advent of 5G technology has raised passenger expectations for in-flight services 2 Literature review [3-5]. Presently, data services for both passenger and airline operations are facilitated through macro-cellu- In recent years, numerous models have been intro- lar networks, inflight satellite systems, or air-to-ground duced to improve the efficiency of DTNs. This section (A2G) links [6-8]. However, the considerable financial discusses some of the most prominent models and expense and propagation delays associated with satel- their respective benefits and limitations. lite communication, notably the Ad hoc Network uti- lizing Air-to-Air (A2A) radio broadcasts [9-11]. This ap- In 2021, Parameswari et al., [24] introduced OPRNET, proach offers power and transmission rate advantages an Opportunistic Routing Protocol that utilizes global over traditional methods, which is especially crucial location data for routing verdicts. OPRNET aims to en- for air traffic management and offshore coverage en- hance network capacity, while also increasing distribu- hancement [12-15]. tion opportunities and reducing latency and overhead. In 2021, Chourasia et al., [25] created a routing tech- Despite its potential benefits, the dynamic nature of nique that gives packet scheduling priority over copy airborne communication poses significant challenges, distribution counts in the network. The results indicate including irregular connections, inadequate links, and that the suggested method performs better than the variable delays during data transfer [16-19]. Moreover, current VDTN routing techniques. existing research often overlooks the intermittent na- ture of connections, limiting the exploration of flexible In 2023, Gupta and Khaitan [26] introduced a queueing transmission methods and impeding the development network model to depict message dissemination in hy- of efficient DTNs [20-23]. To address these challenges, brid VANET architecture. The paper offers an analysis of this paper focuses on assessing the interactions among hybrid VANET with two conventional VANET architec- key network properties within a DTN framework, con- tures. In 2023, Yu et al., [27] presented a MANET routing sidering its fast-changing topology and occasional technique for high-speed applications. The outcomes connectivity. By enabling opportunistic transmissions demonstrate that the suggested algorithm reducing and employing realistic transatlantic data traces, aim to communication delays by 75% and increasing data ar- quantify the efficacy of DTNs, with a particular empha- rival rates by 15%. sis on data flow, transmission delays, and system over- head. In this paper, a novel SPARK method has been In 2023, Han et al., [28] presented a hybrid routing proposed to enhance the efficiency and reliability of technique with dynamic addressing that integrates DTNs in aviation communication. The major contribu- the concepts of static setup. Then, an analysis and tions of the proposed method are as follows: comparison are conducted on the performance met- - Nodes within the DTN are evaluated for trust us- rics of each algorithm. In 2023, Upadhyay et al., [29] ing both direct and indirect trust metrics. presented a routing method for enhanced deep rein- - After trust evaluation, heavy load traffic is re- forcement learning (IDRL) that minimizes augmented stricted based on node trustworthiness. The pre- control overhead. The suggested IDRL routing strategy diction and Transmission Module incorporates performs better than the innovative in terms of data the CWS which dynamically updates each node’s dependability, PDR, and latency. reputation score based on several factors and cat- egorizing nodes into five types: cooperative, par- In 2024, Nakayima et al., [30] offered a cutting-edge tially cooperative, neutral, mislead, and selfish. method for improving VANET performance using a - After classification, cooperative, partially cooper- centralized-controller multi-agent (CCMA) algorithm ative, and neutral nodes proceed to data forward- that combines Reinforcement Learning (RL) with SDN ing. and DTN principles. Evaluations show that the sug- - This process involves efficiently routing data gested approach performs better in a variety of VANET packets through the network to ensure reliable circumstances. Table 1 describes the comparison of ex- delivery to the destination node. isting techniques. 220 D. Shanmugavel et al.; Informacije Midem, Vol. 55, No. 4(2025), 219 – 228 Table 1: Comparison of existing techniques 3 Smart prediction and transmission Tech- Aim Strengths Weak- mechanism for delay-targeted network niques nesses OPRNET To enhance Reducing Increased In this section, a novel SPARK technique has been sug- [24] network latency and energy gested to enhance the efficiency and reliability of DTNs capacity, overhead consump- in aviation communication. including tion energy con- sumption, optimiza- tion latency, and storage Routing VDTNs that Improved High buff- technique limits the delivery per- er usage, [25] number formance, increased of copies reduced processing distributed network con- overhead. to enhance gestion, and efficiency. enhanced packet prior- itization. Queueing Analyze Improving Increased network end-to-end network per- compu- model delay and formance tational [26] backlog in complexity a hybrid Figure 1: Proposed SPARK Methodology VANET MANET To enhance Reducing High com- Direct and indirect trust metrics are used to assess routing routing de- communica- putational nodes in the DTN for trustworthiness. While indirect technique cisions and tion delay and complexity trust considers the opinions of nearby nodes to en- [27] network increasing hance overall network stability, direct trust assesses stability data arrival rates node behavior based on direct interactions. Following the trust assessment, heavy load traffic is limited ac- A hybrid To reduce Lower rout- Increased routing network ing discovery processing cording to the trustworthiness of the node. The CWS, technique overhead delay, and load, and which dynamically adjusts each node’s reputation [28] and increase improved reli- potential score depending on several variables, is incorporated network ability. routing into the Prediction and Transmission Module. Five longevity inefficien- node categories such as cooperative (class 0), partially cies. cooperative (class 1), neutral (class 2), misleading (class IDRL [29] To reduce Reduced Increased 3), and selfish (class 4) are created from the CWS scores control latency, im- resource assigned to nodes. Cooperative, moderately coopera- overhead proved PDR, consump- and trans- enhanced tion. tive, and neutral nodes move on to data forwarding mission data reliabil- after classification. Data packets are effectively routed delay. ity. through the network during this step to guarantee de- CCMA [30] Enhance Reduced High com- pendable delivery to the destination node. The overall VANET per- latency, and putational workflow of the suggested SPARK model is given in Fig- formance better buffer complexity ure 1. management, Node trust evaluation However, several significant studies have been under- taken on efficiency issues in DTNs. Despite notable ad- Nodes’ trustworthiness is evaluated through a combi- vancements, existing approaches exhibit limitations nation of direct and indirect trust. Direct trust is based such as scalability challenges, high overhead, complex- on the actual interactions between nodes, while indi- ity, delay, etc. To overcome these challenges, a novel rect trust considers past behaviors and the level of con- SPARK technique has been suggested in this paper, fidence in those assessments. Ultimately, weighted val- which is covered in the following section 3 and the ues of both are used to compute the overall trust value. subsections. 221 D. Shanmugavel et al.; Informacije Midem, Vol. 55, No. 4(2025), 219 – 228 3.1 Direct trust (DT) Dxy V1BTDxy V2 DSDxy V3 NADxy (4) DT is the immediate impression of the assessed node The weight coefficients are the parameters V by the evaluation node. For the direct trust computa- 1, V2 and V3. Depending on the network environment, the weights tion, the three elements listed as trust factors, where x may have varying values allocated to them. stands for trust in the assessed node and y for the node that has to be assessed. 3.2 Indirect trust 3.1.1 Direct trust bayesian trust degree (BTD) A Node x should reflect the “view” of neighboring BTD model uses the trust degree as an arbitrary vari- nodes on y, just like in social life, to evaluate node y able with a possibility circulation to predict future node more completely. Let x and y be two nodes that have behavior (posterior) based on past node interactions neighbors in common. The trust threshold is deter- (prior). The parameter b indicates the number of un- mined by averaging the trust values found in the node successful interactions. Equation (1) gives the Bayes- x’s trust table, which is given in equation (5). ian trust degree, which used to visually represent the node’s packet forwarding success rate and trend. m H H  i1,ix xi (5) threshold  BTD a os 1 m 1 xy   2 (1) a  b os  ou  Where Hxi is the node x’s direct trust value to its com- mon neighbor nodes, where m is the number of com- Where os is the record of effective y connections and ou mon nodes at present. Afterward solving equation (5), denotes the record of failed y interactions. m co-neighboring nodes remain. The departure of the number of contacts between node y and nearby nodes 3.1.2 Data similarity degree (DSD) from the number of connections between node x and The degree of comparison among 2 nodes transmitting node y, which is determined as in equation (6). data is indicated by data similarity; and incorporating resemblance into the trust value control might help mitigate malicious assaults to some extent. The calcu- n  IN  r 1 r y IN  x 2 , ,y lation is done using equation (2).   (6) n DSD MsgSame xy  c Listx  List  y / 2 (2) D D I   i1 x,i  i ,y (7 xy ) c Where MsgSame indicates how many comparable The above equation (7) provides the ultimate indirect packets there are between nodes x and y and (Listx + trust computation algorithm. Where ρ defines the cal- Listy)/2 indicates how many packets on average are culated metric, n represents the total number of ele- stored in each node’s cache. ments, INr,y is the number of interactions that a neigh- bor node r has had. At node r, the “view” will be deemed 3.1.3 Node activity degree (NAD) invalid if INr,y < INx,y-- ρ, c indicates the remaining shared The quantity of nodes encountered in a given amount neighbor nodes. of time determines a node’s activity level inside the network. To prevent malicious assaults, node activity 3.3 Limit heavy load traffic is zeroed at the beginning of each unit time. This is its calculating in equation (3). Limiting heavy load traffic after Node Trust Evaluation involves a crucial assessment process aimed at enhanc- NAD t Internum  t  1  ing network reliability and security. This ensures that xy   NAD No     xyOld (3)    only nodes deemed trustworthy are allowed to handle Where t is the time in units, Internum is a representation heavy loads, thereby reducing the risk of network con- of the number of nodes encountered in the network. gestion, and potential breaches. Once heavy load traf- The entire number of nodes in the present network is fic is limited, it enters the prediction and transmission denoted as No and NADxyOld is the activity of the node at phase where nodes are categorized for efficient data the most recent reset. As a result, equation (4) can be transmission. used to define the DT value (D). 222 D. Shanmugavel et al.; Informacije Midem, Vol. 55, No. 4(2025), 219 – 228 3.4 Prediction and transmission n . RSI   I  . RS CW (12) n Nn Wn After reducing heavy traffic load, optimized input is fed where ∞ into the prediction and transmission phase for efficient n represents the degree to which the CWS re- lies on nodes’ self-reported observations and ranges data transfer. The core of the Prediction and Transmis- from [0,1]. The classification module updates its classi- sion module is the CWS, which aims to ensure network fication table after receiving the decision module’s up- access while identifying non-compliant nodes. The dated nodes’ reputation scores. Using this score finally node’s reputation score (RSI), its neighbors’ reputa- the nodes are classified into 5 types they are class 0, tion score (RSN), a value of cooperation offered by the class 1, class 2, class 3, and class 4. Subsequently, the watchdog (CVW), and Delay. The node’s associated co- classified output is transferred to the data forwarding operative value (CVW). Eq. (8) determines a cooperative phase. value for node n. 3.5 Data forwarding CVw   . n (8) n After node prediction, if classified as class 0, class 1, or Where γ represents the punctuation that the classifica- class 2, nodes proceed to data forwarding. Immediate tion module assigns to node n is the node performance neighbors of the downstream node assist in this pro- coefficient represented by β. Eq. (9) is used by the clas- cess. The next upstream sender is noted in the failed sification module to generate this value, where RBi is the node’s Pending Credit Table. Once the forwarder tim- number of bundles that have been relayed from node er expires, a neighboring node broadcasts the data i, DBi is the number of packages that have already been packet to lower-layer nodes using the credit table. delivered from node i and DpBi is the number of bundles When the designated lower-layer node retransmits the that have already been dumped from node i. Eq. (10) is packet, nearby nodes with the same data in their credit used to determine the value. table delete their cache and stop their timers. This pro- cess reduces transmission delays, prevents redundant N R D transmissions, and enhances the interest satisfaction i x   iI Bi B ratio. The process of data packet forwarding and rout- N (9)  R DP ing is shown in Figure 2. iI Bi Bi  x min x    max   min   (10) x  x The neighbor assessment module establishes the RSN of each node. The module for neighbor evaluation polls N neighbors (Ng) for feedback on the participating nodes at each contact opportunity. These neighbors provide the corresponding RSN value in response to the evalu- ation module request from the neighbor. Each time a neighbor creates a direct communication channel with a node (n), the node’s RSN value is modified is given in equation (11). Figure 2: Data forwarding and routing mechanism N RS RS n  iI Ri (11) N N The reputation score that the node itself (RSI), the neighbor’s evaluation module (RSN), and the categori- zation module (CVW) have seen are all taken into con- sideration by the decision module when updating a network node’s reputation score () following a contract opportunity. An updated node reputation scores (∞n) which is the sum of the three ratings and is determined as follows in equation (12). 223 D. Shanmugavel et al.; Informacije Midem, Vol. 55, No. 4(2025), 219 – 228 Algorithm: Proposed SPARK model data forwarding in Table 2: Parameter setup DTN network Input Data: DTN network topology, Node interaction Parameter Value data, Trust evaluation parameters Region 5000m*5000m Output: Data forwarding to the destination Data size 500 KB Step-1: Initialize the DTN network and establish com- Interval 40s munication links. TTL 4 hours Step-2: Perform node trust evaluation Time 10 hours Transmission range 10 m Step-2.1: Determine direct trust based on the past node interactions (prior) using equation (1) Transmission speed 250 KB/s Step-2.2: Determine indirect trust from neigh- attain a forwarding rate of 13.8% are neutral, and mis- boring nodes using equation (5). leading nodes are forward less than 9.2% of packets. Step-3: Limiting heavy load traffic to enhance net- Finally, selfish nodes that function correctly in 11% of work reliability and security interactions within the DTN. Step-4: Perform prediction and transmission to iden- tify optimal paths. Step-4.1: Compute the node’s reputation score based on forwarding behavior Step-4.2: Analyze neighbor’s reputation score to assess cooperation level Step-4.3: Evaluate the value of cooperation to identify malicious nodes Step-4.4: Measure delay to detect misbehavior Step-5: Classify the network nodes using cooperative watchdog system (CWS) Step-6: Forward data based on trust scores and coop- erative behavior Step-7: Deliver data to the destination efficiently and Figure 3: Classification distribution of the proposed securely. SPARK framework 4.1 Comparative analysis 4 Results and discussion The suggested SPARK model’s simulation findings are examined and a discussion of efficacy is done in terms of numerous evaluation parameters within this section. The effectiveness of the proposed SPARK method is tested using the ONE (opportunistic network environ- ment) simulator. The efficacy of the suggested SPARK approach is examined using four metrics: hop count, overhead, delivery ratio, delivery delay throughput, complexity, and resource utilization. All of the signifi- cant factors that were utilized in the simulation are enumerated in Table 2. Figure 4: Comparison in terms of delivery rate Figure 3 presents the distribution of the proposed Figure 4 illustrates a comparison of delivery rates be- SPARK model categories based on their packet for- tween existing methods and the proposed SPARK warding behavior. This provides how node behaviors method. Our proposed work effectively minimizes the are evaluated and categorized within the DTN. A co- packet drops by utilizing an optimized routing mech- operative node is defined as one that forwards packets anism, which selects the most reliable route dynami- in 39.4% of interactions, while a partially cooperative cally. This demonstrate that the greater performance of node forwards packets in 26.6% of the time. Nodes that 224 D. Shanmugavel et al.; Informacije Midem, Vol. 55, No. 4(2025), 219 – 228 the proposed SPARK method in ensuring higher deliv- ery rates under the given conditions. Figure 7: Comparison in terms of Hop Count Figure 8 illustrates a comparison of throughput among Figure 5: Comparison in terms of delay the proposed SPARK method and the existing meth- ods. The proposed SPARK method maintains a relative- Figure 5 presents a comparative analysis of delay times ly stable and high throughput. Overall, the proposed with existing techniques and a proposed method. By SPARK method shows superior presentation in terms of implementing the efficient path selection, our pro- maintaining consistent and high throughput related to posed SPARK method reduces the time required for the other protocols. packet transmission. The delay rate of the proposed SPARK method is 18.67%, 19.87%, and 14.45% is lower than the existing OPRNET, IDRL, and CCMA techniques respectively. Figure 6 illustrates a comparative analysis of overhead. For reducing the network control traffic, the suggest- ed work employs a routing mechanism through opti- mized control message transmission. It shows that the suggested model’s effectives significant efficiency in reducing overhead, highlighting its potential advan- tages over the other methods. Figure 8: Comparison in terms of Throughput Figure 6: Comparison in terms of overhead Figure 7 presents a comparison of hop counts. The pro- posed method constantly attains advanced hop counts associated with the other protocols, particularly notice- able at larger network sizes. OPNET consistently results Figure 9: Comparison in terms of Complexity in the lowest hop counts across all network sizes, dem- onstrating a more efficient routing performance in Figure 9 illustrates the comparation of complexity terms of hop count. between the suggested SPARK approach and current methods. The proposed method shows the lowest complexity, while IDRL is the most complex. This shows 225 D. Shanmugavel et al.; Informacije Midem, Vol. 55, No. 4(2025), 219 – 228 the proposed SPARK method’s maintaining lower com- 6 Acknowledgments plexity compared to the others. The author would like to express his heartfelt gratitude to the supervisor for his guidance and unwavering sup- port during this research for his guidance and support. 7 Conflict of interest No financial or interpersonal conflicts have been re- ported by the authors that would have affected the study’s finding 8 References 1. S. Ullah and A. Qayyum, “Socially-aware adaptive Figure 10: Comparison of Resource utilization delay tolerant network (dtn) routing protocol”, PloS one, vol. 17, no. 1, pp. 0262565, 2022. Figure 10 shows the comparation of resource utiliza- http://dx.doi.org/10.1371/journal.pone.0262565 tion between the proposed SPARK method and exist- 2. G. Koukis, K. Safouri and V. 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Technol., 2024. http://dx.doi.org/10.1038/s41598-023-48956-y Copyright © 2025 by the Authors. This is an open access article dis- tributed under the Creative Com- mons Attribution (CC BY) License (https://creativecom- mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 05. 10. 2024 Accepted: 01. 10. 2025 228 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.403 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 4(2025), 229 – 238 A Wireless Optical Gate and IMU System for Agility Assessment: Architecture, Synchronization and Validation Anton Kos, Erik Keš, Matevž Hribernik, Sašo Tomažič, Anton Umek Faculty of Electrical Engineering, University of Ljubljana, Ljubljana, Slovenia Abstract: Accurate, field-ready timing and motion capture are essential for assessing agility beyond the limits of manual stopwatches. We present a modular measurement system that fuses infrared (IR) optical gates for robust event detection with a trunk-worn inertial measurement unit (IMU) for kinematic profiling. Each sensing node is built on an Adafruit Feather M0 Wi-Fi microcontroller and communicates via UDP to a laptop server. Time alignment is accomplished without internet connectivity: the server establishes a relative epoch and executes a triple-handshake broadcast protocol, while timestamps are generated at the edge to avoid latency bias from transport or processing. Module- and device-level characterization shows that IR-receiver processing combined with interrupt service routine latency yields a per-event timestamp error of 0.54 ms ± 0.14 ms (latency ± uncertainty), and local clocks remain stable over the durations relevant to agility trials. In wireless operation, accepted synchronization attempts form tight response clusters in favorable RF conditions, whereas congested environments may require retries; for section times across different gates we therefore report a conservative inter-node uncertainty. End-to-end validation across laboratory, entry-hall, and gym venues using the Agility T-test confirms that total test time measured on the same start/finish gate remains below 1 ms error over 10–20 s trials. Synchronized IMU waveforms add explanatory value beyond total and split times by revealing braking, change-of-direction, and re-acceleration phases. The system provides a deployable workflow with substantially improved precision over manual timing. Future work will target more robust synchronization and expanded analytics, including automated phase detection, asymmetry indices, and optional integration with indoor positioning. Keywords: infrared gates; IMU; embedded systems; wearable sensor device; wireless synchronization; agility testing Brezžični sistem za ocenjevanje agilnosti na osnovi optičnih vrat in kinematičnih senzorjev: arhitektura, sinhronizacija in validacija Izvleček: Natančno merjenje časa in zajem gibanja na terenu sta ključna za ocenjevanje agilnosti onkraj omejitev ročnih štoparic. Predstavljamo nizkocenovni, modularni merilni sistem, ki združuje infrardeča (IR) optična vrata za robustno zaznavanje dogodkov in na trupu nameščeni inercialni merilni senzor (IMU) za kinematično profiliranje. Vsako merilno vozlišče temelji na mikrokrmilniku Adafruit Feather M0 Wi-Fi in z uporabo UDP komunicira s strežnikom na prenosniku. Časovno uskladitev izvedemo brez internetne povezave: strežnik vzpostavi relativno epoho in izvede oddajni protokol s trojnim rokovanjem, medtem ko se časovni žigi tvorijo na robu sistema (na napravi), da se izognemo pristranskosti zaradi zakasnitev prenosa ali obdelave. Karakterizacija na ravni modulov in naprav pokaže, da kombinacija obdelave v IR sprejemniku in zakasnitve prekinitvene rutine prinese napako časovnega žiga na dogodek 0.54 ms ± 0.14 ms (zakasnitev ± negotovost), lokalne ure pa ostanejo stabilne v časovnih intervalih, pomembnih za preizkuse agilnosti. Pri brezžičnem delovanju sprejeti poskusi sinhronizacije v ugodnih RF-razmerah tvorijo tesne skupke odzivov, medtem ko v zasičenih okoljih lahko zahtevajo ponovitve; zato pri časih odsekov med različnimi vrati navajamo večjo negotovost. Celovita validacija v laboratoriju, avli in telovadnici z uporabo T-testa agilnosti potrjuje, da ima skupni čas testa, izmerjen na istih začetnih/končnih vratih, napako manjšo od 1 ms pri poskusih, dolgih 10–20 s. Sinhronizirani IMU signali dodajo pojasnjevalno vrednost onkraj skupnih in delnih časov, saj razkrivajo faze zaviranja, menjave smeri in ponovne pospešitve. Sistem omogoča enostavno uvedljiv potek dela z bistveno izboljšano natančnostjo v primerjavi z ročnim merjenjem. V prihodnje načrtujemo še zanesljivejšo sinhronizacijo in razširjeno analitiko, vključno s samodejnim zaznavanjem faz, indeksi asimetrije ter po potrebi integracijo s pozicioniranjem v zaprtih prostorih. Ključne besede: infrardeča vrata; IMU; vgrajeni sistemi; nosljiva senzorska naprava; brezžična sinhronizacija; testiranje agilnosti * Corresponding Author’s e-mail: anton.kos@fe.uni-lj.si, anton.umek@fe.uni-lj.si How to cite: A. Kos et al., “A Wireless Optical Gate and IMU System for Agility Assessment: Architecture, Synchronization and Validation", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 4(2025), pp. 229–238 229 A. Kos et al.; Informacije Midem, Vol. 55, No. 4(2025), 229 – 238 1 Introduction Motivated by the lack of systems that provide synchro- nized timing gate events and IMU signals in real-world Time–motion tests, especially change-of-direction settings without Internet access, and aiming for a low- (COD) tasks, remain a staple of field-based perfor- cost, hardware-independent solution, we present a mance assessment because they are simple to admin- wireless synchronized sensor system that integrates (i) ister and show good reliability and construct validity IR gates for robust, low-latency location-bound event across sporting populations [1]. One example of COD timing, (ii) body-worn IMUs for rich kinematic profiling, task is T-test studied in this work. However, manual and (iii) a synchronization layer to ensure sub-frame timing introduces human start and stop reaction la- timestamp coherence across nodes. Building on our tency and split-time variability when compared with prior engineering work that demonstrated millisec- electronic solutions [2]. Infrared (IR) timing gates and ond-level timing accuracy at the device level [14], we photoelectric cells help reduce operator delay, but target sports-relevant tasks (e.g., agility tests) where their accuracy can still be affected by several factors. both total time and movement quality matter. Athlete posture (e.g., knee or arm swing), beam geom- etry, and starting procedures can interfere with trigger- Our contributions are: (1) a low-cost, modular, field- ing, and performance also differs between single- and deployable architecture that unifies IR-gate events and dual-beam configurations. Recent systematic evidence IMU streams under a common clock, (2) a synchroniza- further shows that commercial systems can produce tion strategy compatible with commodity Wi-Fi while significant offsets and are not universally comparable, remaining energy-aware, and (3) an analysis pipeline particularly during the first 5–10 m of acceleration of that provides both standard split times and additional the linear speed test [3]. kinematic micro-metrics of execution. In parallel, inertial measurement units (IMUs) have become a practical way to capture kinematics in envi- 2 Background & related work ronmentally valid settings. A 2021 scoping review con- cluded that IMUs can quantify COD performance, but Timing technologies. Manual timing is convenient highlighted heterogeneity of metrics and the need for but systematically biased relative to electronic systems rigorous validation in sport-specific tasks [4]. Newer [2]. Photoelectric timing gates reduce operator error, studies have started to fill this gap: single-sensor weara- but the height of the beam and the number of beams, bles can segment COD and derive interpretable perfor- the starting protocol and the morphology of the object mance markers in the field [5]; multi-IMU systems can affect the triggers and thus the measured times. A re- capture lower-limb kinematics with high sagittal-plane cent systematic review found that double-beam gates agreement to optoelectronic references, albeit with reduce false triggers more effectively than single-beam greater error in frontal and transverse planes [6], [7]; and systems. It also reported that different systems are not foot-mounted IMUs show promising validity for velocity always interchangeable, particularly in the early accel- tracking in team sports [8]. There is also growing interest eration phase. This emphasizes the need to specify de- in combining IMUs with phone-based markerless meth- vice models and setups in studies [3]. Recent validation ods to balance practicality and accuracy [9]. studies characterize the differences between systems (e.g. Chronojump vs. Witty) and propose fitting equa- A persistent systems-engineering challenge is pre- tions for comparability [3]. cise time alignment across distributed, wireless nodes so that timing-gate events and IMU signals are fused Wearable sensing for agility tests. IMUs are widely without drift. Energy-efficient clock discipline for Wi-Fi/ used to capture movement quality alongside total time. IoT devices has been proposed (e.g., ecoSync) to trade The scoping review by Alanen et al. summarizes relia- synchronization accuracy for battery life in multi-sen- bility/validity evidence and calls for standardized met- sor settings [10]. Precision Time Protocol (PTP) over Wi- rics in COD analysis [4]. Subsequent work shows that a Fi can reach microsecond-level accuracy with careful single trunk-worn GNSS-IMU can decompose standard tuning/hardware support, but performance depends agility tests into interpretable phases [5], while labora- on network interface capabilities and timestamping tory-grade comparisons indicate high waveform agree- paths [11], while Network Time Protocol (NTPv4) re- ment in the sagittal plane and task-/plane-dependent mains a robust baseline for general deployments [13]. limitations elsewhere [6], [7]. Foot-mounted IMUs have When spatial context is needed (e.g., split timing plus been shown to provide valid measurements of velocity trajectories), Ultra-Wideband (UWB) real-time locating in team sports [8]. Early studies also suggest they can systems are an established option for indoor position- work well alongside modern phone-based markerless ing with high update rates and robustness to multipath systems [9]. [12]. 230 A. Kos et al.; Informacije Midem, Vol. 55, No. 4(2025), 229 – 238 Clock synchronization and spatial context. Multi- 3.2 Hardware sensor fusion in the field depends on stable sub-mil- lisecond alignment. Energy-aware Wi-Fi synchroniza- Microcontroller & radio. Each mobile node (IR tim- tion (ecoSync) reduces overhead for battery-powered ing gates and wearable IMU devices) uses an Adafruit nodes [10]; PTP over Wi-Fi can reach ≈1 µs accuracy Feather M0 Wi-Fi microcontroller board (SAMD21 + with careful engineering, though commodity hardware ATWINC1500) [15]–[17]. The AP used in development support is uneven [11], while NTPv4 remains a practi- was a TP-Link Archer C7 (802.11b/g/n); the server is cal, standards-based baseline [13]. For positioning, wired to the AP for stability and reduced radio use. UWB RTLS offers accurate, robust indoor tracking and is widely reviewed for real-time deployments [12]. Compared with timing-only protocols that report to- Opcal tal or coarse split times and remain sensitive to beam gate Processing device (PC) WiFi Access point setup and inter-system offsets [1]–[3], our approach fuses robust IR-gate events with IMU signals under a common clock. This yields not only how much time IMU was spent, but where and why within each section; IR gates also curb the segmentation uncertainty that af- Opcal fects IMU-only pipelines [4]–[9]. We further quantify gate the full error budget, per-device measurement error, Opcal local clock drift, and inter-node synchronization, so gate uncertainties propagate to both total and section-level metrics. In our system, we implement lightweight Wi-Fi syn- chro-nization positioned between NTP (practically ms- Opcal gate level, but dependent on the network connection) and hardware-assisted PTP (µs-level, but less commodity- friendly) [10], [11], [13], along with edge timestamping, compact UDP transport, and a stable time base. In prac- Figure 1: System architecture with a processing device tice, this provides sub-ms device coherence and explic- (server), multiple IR optical gates, wearable IMU, Wi-Fi itly characterized uncertainty between nodes in con- Access point. Configuration showing a T-test case. gested RF environments. This results in a field-suitable workflow for agility testing with comparable times and IR timing gates. Gates consist of a 940 nm IR emit- explanatory IMU waveforms [3], [5]–[9]. Thus, our solu- ter and modulated receiver (IS471F), see Figure 2. The tion is comparable to NTP, but network independent, IS471F’s data sheet specifies a 400–670 µs internal and although less accurate than PTP, it is independent processing delay, i.e., an absolute uncertainty of up to of specific network interface functionalities. ±135 µs around a ~535 µs mean [18]. Indicator red LED IR LED 3 Materials and methods Connecon cable 3.1 System architecture Heat shrink tube The system shown in Figure 1 comprises (1) distributed measurement nodes of two different types: IR timing gates and a wearable IMU unit, (2) a laptop server con- nected to (3) a Wi-Fi access point (AP). Nodes transmit ASCII-encoded UDP packets to the server; UDP was IS471F chosen to minimize head-of-line blocking and reduce latency from acknowledgments. As the system oper- Figure 2: IR timing gates. ates without connection to the internet, synchroniza- tion does not use NTP; instead, devices align to a rela- Wearable IMU. We used LSM6DS33 (accelerometer & tive time established by the server at a synchronization gyroscope, set to ±16 g and ±2000 dps, 100 Hz) and instant. Devices are uniquely identified and assigned BNO055 (orientation/acc/gyro/mag, 100 Hz) mounted roles (gate index, wearable) by the server before a trial. 231 A. Kos et al.; Informacije Midem, Vol. 55, No. 4(2025), 229 – 238 at users’ lower back, near the center of mass of the derives from timestamps produced by a single gate. body. Logged channels, depending on a sensor, include For inter-device outcomes, e.g., partial (split) times be- fused orientation, linear acceleration (gravity-compen- tween successive gates, component (c) is critical, since sated), raw accelerometer/gyroscope, magnetometer, the result combines timestamps from different, imper- and battery voltage [21], [22]. fectly synchronized nodes. 3.3 Firmware and communication Notably, processing and communication latencies do not bias timestamp accuracy. As illustrated in Fig- Node operation. Gate crossings trigger interrupts that ure 4, delays in the system stem from sensor device, immediately store the local timestamp and raise a flag; microcontroller processing, communication, and the packet assembly and transmission occur in the main processing device. Only the first contributes to time- loop to keep interrupt service routines (ISRs) minimal. measurement error; the others affect overall system IMU sampling follows a fixed-interval loop (read LSM performance and are therefore not analyzed further in → read BNO → check send window → send). Both this paper. flows are implemented as lightweight state machines. Sensor Microcontroller Communicaon Processing Server application. The LabVIEW program manages device (1) synchronization exchanges, (2) receive loops for Event UDP, (3) role assignment and configuration, and (4) log- ging and live visualization. The code modules and GUI Figure 4: Delay sources in the system. tabs for sync/config and packet reception are docu- mented with block diagrams and front-panel screen- 3.5 Device synchronization shots [14]. During system development, two synchronization methods were implemented: (a) wired and (b) wireless. In the wired approach, all devices (optical gates or wearable sensors) are physically connected to a syn- chronization apparatus that provides a common trig- ger signal simultaneously, as shown schematically in Figure 5. This method is suitable when the test setup allows straightforward handling of optical gates and wearable sensors. Device 1 Device 2 Figure 3: Appearance of the LabVIEW application graphical interface when performing a T-test. 3.4 Time measurement accuracy Device N Synchronizaon apparatus During operation, the system’s primary function is time measurement; either for event stamping or sensor sampling. Owing to imperfections, timing errors arise Figure 5: Wired synchronization scenario in which an at both intra- and inter-device levels. We decompose apparatus drives the sync signal for gates/sensors. the total timing error into: (a) electronics, (b) local clock drift, and (c) inter-node synchronization. In the wireless approach, the processing device broad- casts a Wi-Fi synchronization packet to all mobile For intra-device outcomes, only (a) and (b) are relevant. nodes. This method is particularly advantageous when A typical case is the total test time when the athlete regular synchronization is needed but physical manip- starts and finishes at the same gate (as in our T-test); ulation of the gates and/or wearable devices is imprac- synchronization error is irrelevant because the result tical, or when time constraints limit access to athletes, 232 : : : : A. Kos et al.; Informacije Midem, Vol. 55, No. 4(2025), 229 – 238 as is often the case with elite teams. To address these maximum number of unsuccessful synchronization at- scenarios, we developed and implemented a triple- tempts is reached, synchronization ends and the user is handshake synchronization protocol: notified. Some internal operations, such as setting the - The server is configured with the number of mi- local time or advancing counters, are not shown in the crocontrollers in the system (N). diagram. - Before each measurement, all microcontrollers wait for a synchronization packet. Figure 7 illustrates the synchronization process of an - The server initiates synchronization by broadcast- example system with four devices, showing one failed ing a packet containing the current synchroniza- and one successful synchronization attempt. The initial tion attempt index (0–9). synchronization request, TREQ-0, at time tr0 receives - Upon reception, each microcontroller records its only three responses, TRESP-0, at the server, resulting current local time from system startup. in a failed attempt. After the protocol timeout, the next - Each microcontroller responds to the server with attempt, TREQ-1 at time tr1 succeeds, as all four respons- a packet that includes the synchronization at- es TRESP-1 are received. The successful synchronization tempt index. is communicated to the devices with the confirmation - Once the server has received responses from all message TSUCC. N nodes, it broadcasts a confirmation packet to conclude synchronization. N≠4 N=4 OK Broadcast Unicast Broadcast Unicast Broadcast - Each microcontroller then stores the most recent TREQ-0 TRESP-0 TREQ-1 TRESP-1 TSUCC t recorded timestamp as t₀, which is used as the ref- N=4 erence time for subsequent measurements. Dev 1 ݱ ݱ ݱ Dev 2 ݶ ݱ ݱ The messages used in this protocol are defined as: - TREQ-N: server synchronization request with at- Dev 3 ݱ ݱ ݱ tempt index N, Dev 4 ݱ ݱ ݱ - TRESP-N: microcontroller response to synchroni- t Timeout zation attempt N, r0 tr1 - TSUCC: server broadcast confirming successful Figure 7: Triple-handshake synchronization protocol. synchronization to all nodes. Protocol diagrams for the server and device sides are shown in Figure 6. The server controls communica- 4 Results tion by sending TREQ and TSUCC messages based on the number of successfully received responses from The focus in this section is on time measurement and the devices (TRESP) and any possible timeouts. If the synchronization inaccuracies and not on the actual athletes’ results of the performed agility tests. 4.1 Agility T-test Agility T-test trials were conducted in three environ- ments: the laboratory (device functionality testing), the faculty entry hall (initial system validation), and the gymnasium (real-world conditions). The configuration of optical gates for the left-side execution is shown in Figure 8. In this mode, the athlete turns left after the first passage through gate 2. Both IMUs were config- ured as described previously (LSM6DS33 at 100 Hz; BNO055 at 100 Hz). Field measurements outcomes are reported as split times and basic kinematic signals [14]. Detailed sport-science interpretation is planned in col- laboration with domain experts. 4.2 Device-level timing measurements As noted in Section 3.2, the IS471F introduces an inter- Figure 6: Server and device side protocol diagrams. nal processing delay of 400–670 µs (mean ≈ 535 µs), 233 A. Kos et al.; Informacije Midem, Vol. 55, No. 4(2025), 229 – 238 garded as reliable. If the measurement clock exhibits excessive error, deviations may accumulate over longer intervals and exceed acceptable limits. To address this, we evaluated the clock accuracy of the microcontrollers used in our measurement system, which depends on quartz crystal tolerances. As shown in Figure 10, four microcontrollers were test- ed. Following thermal stabilization, the devices were synchronized, and a series of measurement episodes was performed to monitor differences in recorded times relative to the initial synchronization. After ap- proximately 400 s of operation, individual devices ex- hibited drift of up to ±2.5 ms, corresponding to about 6.25 μs/s. At this rate, a single microcontroller would ac- cumulate a timing error of 1 ms in roughly 160 s, what is more than suitable for standard agility tests that gen- erally do not last more than 20 s. Figure 8: Setup of measurement gates for the T-test: green circles indicate the sequential numbering of gates for the left-side execution. yielding an absolute uncertainty of ± 135 µs as speci- fied in the data sheet [18]. Digital toggling contributes < 100 ns and is therefore negligible [14]. Oscilloscope measurements show a constant ISR entry latency of ≈ 1.6 µs from input edge of the IR optical gate signal to the first MCU output transition (Figure 9). Together, the per-event timestamp at a gate is 536.6 ± 135 µs (mean Figure 10: Deviation of microcontroller clocks within a latency ± uncertainty). 400 seconds interval relative to the average event time. 4.4 Synchronization error Because the system is not connected to the internet, devices are not disciplined to absolute time. The server sends a synchronization request; devices record local times on receipt and reply, after which the server as- signs a relative epoch and estimates offsets and rates per device. In wired scenarios, synchronization errors are in the range of microseconds and are therefore negligible. In Figure 9: Oscilloscope screenshot of interrupt service wireless scenarios, the errors can become much larger. routine latency measurement. The yellow trace shows By conducting measurements of the delay of the triple the signal at the digital input, while the green trace handshake protocol in different environments, we ob- represents the signal at the digital output of the micro- tained these results. In favorable RF conditions (gym), controller. the inter-device spread during sync was ≈45–55 µs. Un- der congested RF (faculty hall), sync quality degraded to several milliseconds and many retries were needed. 4.3 Microcontroller clock drift Conservatively, we report an upper-bound system-lev- el synchronization term of 15 ms ± 10 ms for inter-node When assessing timing performance, a fundamental section times. Unfavorable results can be improved via question is whether the obtained results can be re- a dedicated radio channel [14]. 234 A. Kos et al.; Informacije Midem, Vol. 55, No. 4(2025), 229 – 238 4.5 End-to-end and section timing accuracy study: laboratory shakedown, entry-hall pilot, gym de- ployment (real-world conditions). Each trial began with Combining electronics delay, ISR latency, local drift and node discovery and sync, followed by execution of the favorable synchronization, we can see that: (a) the error left-side Agility T-test layout (Figure 8). Quality control for total T-test time, which is of duration between 10 included: (i) internal consistency checks (sum of sec- and 20 seconds, remains well below 1 ms, and (b) for tion times vs. total time from the start/finish gate), (ii) section times spanning different gates we propagate visual alignment of IMU bursts with gate crossings on the drift and sync terms alongside device-level error the server UI, (iii) trial-level flags for atypical packets or when reporting uncertainty. In favorable RF conditions missed replies, and (iv) manual time measurement with the clock drift and synchronization error add less than a stopwatch. Because timestamps are generated at the 100 µs, while in unfavorable conditions the additional edge (ISR), measured network and processing latencies error can be up to 25 ms (conservatively). affect throughput and visualization but not timing ac- curacy. The laboratory shakedown and entry-hall pilot 4.6 System validation validation were conducted by the authors, while the gym validation was performed with the help of 13 ca- We validated the system in stages: module, device, net- dets from the Slovenian men’s cadet volleyball team, work, and end-to-end. We used procedures designed each completing two trials. We emphasize again that to mirror real use and to isolate each source of uncer- the measurements were intended solely for validating tainty reported in Sections 4.2–4.5. the system under real-world conditions, not for assess- ing the athletes’ abilities. Module level. To characterize sensing and stamping, we drove controlled interruptions of the IR beam and Together, these procedures verify that per-event observed the signal path with an oscilloscope: IR re- stamping and intra-device timing behave as expected ceiver output → MCU interrupt pin → ISR entry marker on the bench, that local clocks remain stable over the (test firmware toggles a GPIO on ISR entry). This bench durations of interest, that the wireless sync protocol setup verified that timestamps are produced at the provides an explicit and enforceable quality thresh- interrupt edge, that ISR handling is constant across old, and that the full system yields coherent total and repeats, and that transport/processing downstream section times with aligned kinematic signals in realis- (UDP, server logging) does not bias event times. The tic field conditions. Quantitative outcomes referenced resulting timing budget is summarized in Section 4.2 above are reported in Sections 4.2–4.5. and in Figure 9. Device level. To evaluate clock stability independently 5 Discussion of networking, four microcontrollers were wired in par- allel to a common trigger that emulates an optical-gate The results confirm that a low-cost, modular system event. After thermal stabilization and an initial sync, we combining infrared gates with a body-worn IMU can issued repeated triggers at variable intervals and com- achieve timing accuracy sufficient for field-based agil- pared each node’s recorded time to the run’s reference ity assessment. Device-level uncertainty is dominated trace. This procedure reveals relative drift and informs by the IR receiver’s processing delay and ISR latency, the practical re-synchronization policy used in trials yielding a per-event timestamp error of 0.54 ms ± 0.14 (Figure 10). ms (latency ± uncertainty). This translates into a total- time error below 1 ms for trials lasting 10–20 s, which is System level. Wireless synchronization was exercised well within the requirements of standard agility proto- with the triple-handshake procedure (Figure 7). Before cols and clearly superior to manual stopwatch timing. each trial, the server broadcast a sync request; nodes It also satisfies sports measurement precision require- stamped local receipt time and replied; the server ac- ments, which are typically set at 0.01 s [2]. cepted the attempt only if responses formed a tight cluster (indicating near-simultaneous delivery). Oth- Integrating gate events with IMU signals extends be- erwise, the attempt was retried. This acceptance–retry yond conventional timing by enabling interpretation policy was tested in two RF environments (quiet gym, of how performance is achieved. Binding IMU streams congested hall) and motivates the conservative inter- to IR events reduces segmentation ambiguity and sup- node term we propagate for section times (see Section ports extraction of kinematic markers such as braking 4.4). and re-acceleration, complementing total and split times. This approach is consistent with recent studies End-to-end (T-test workflow). Finally, we validated the that highlight the utility of IMUs for COD tasks, particu- complete workflow across the three venues used in this 235 A. Kos et al.; Informacije Midem, Vol. 55, No. 4(2025), 229 – 238 larly in the sagittal plane [4]–[9]. Sagittal-plane COD is 6 Conclusions a core component of real-world agility, so agility tests that meaningfully stress sagittal braking and re-accel- We presented a wireless, modular measurement sys- eration provide more valid, sport-relevant assessments tem that fuses infrared timing gates with a body-worn of an athlete’s ability to change speed and direction un- IMU for precise, field-ready agility assessment. Device- der realistic conditions. level total-time errors are below 1 ms over 10–20 s tri- als, meeting practical requirements for sports testing The main limitation arises from inter-node synchroni- while preserving a simple, deployable workflow. zation in wireless conditions. In favorable RF environ- ments, synchronization spreads remained below 55 By combining gate events with IMU signals, the sys- µs, but congestion increased jitter and required retries, tem provides explanatory value beyond total or split leading us to conservatively report 15 ms ± 10 ms for times: aligned kinematic waveforms capture braking, section times across gates. It should be noted, that our change-of-direction, and re-acceleration phases, sup- system is specifically designed for sports halls, where porting technique-aware feedback. For section times the T-test is typically conducted and where RF condi- across gates, uncertainty is dominated by inter-node tions are favorable. This positions our approach be- synchronization; this term is explicitly quantified to en- tween NTP-level accuracy and hardware-assisted PTP, sure transparent interpretation. while remaining deployable with of-the-shelf Wi-Fi hardware [10], [11], [13]. Future work will focus on (i) replacing or augmenting the AP-based synchronization with a dedicated radio For practical deployment, several recommendations channel or hybrid time-sync method to reduce inter- emerge: stable access point hardware with a wired node error, (ii) expanding analytics toward automatic server connection, consistent beam height and align- phase classification and asymmetry indices using syn- ment, reliable and consistent body placement of the chronized IMU signals, and (iii) optional integration IMU, and reliance on a watch-crystal time base to with indoor positioning technologies such as UWB for bound drift. These practices improve robustness across spatial trajectory analysis. venues and align with known sources of variability in photocell and IMU-based systems [3]–[7], [21], [22]. Limitations include the reliance on commodity Wi-Fi 7 Acknowledgments without hardware timestamping, which constrains synchronization in noisy environments, and the plane- This work was supported in part by the Slovenian Re- specific accuracy of IMU kinematics reported in the lit- search and Innovation Agency within the research erature [6], [7], and [9]. program ICT4QoL-Information and Communications Technologies for Quality of Life (research core funding Beyond controlled laboratory validation, the present- no. P2-0246). ed system can be directly applied in sports science and coaching environments for performance assess- ment, return-to-play testing, and individualized train- 8 Conflict of interest ing monitoring. The modular, wireless design makes it suitable for team sports agility drills, rehabilitation pro- The authors declare no conflict of interest. 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Online: https://cdn- shop.adafruit.com/datasheets/BST_BNO055_ DS000_12.pdf Copyright © 2025 by the Authors. This is an open access article dis- tributed under the Creative Com- mons Attribution (CC BY) License (https://creativecom- mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 03. 10. 2025 Accepted: 20. 11. 2025 238 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.404 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 4(2025), 239 – 254 Memristor based Majority Logic Adders for Error Resilient Image Processing Applications Nithya Natarajan, Paramasivam Kuppusamy Department of Electrical and Electronics Engineering, Kumaraguru College of Technology, Coimbatore, Tamil Nadu, India. Abstract: Approximate Computing (AC) enables energy-efficient and high-performance computation for error-resilient applications such as data analytics, image processing, and multimedia. With the growing demand for low-power, high-density storage in Artificial Intelligence and Machine learning applications, researchers are exploring emerging technologies like FinFETs, memristors, Carbon Nano Tube FET(CNTFET), and Quantum-dot Cellular Automata (QCA) to mitigate the constraints of CMOS scaling. This paper proposes an efficient majority logic design using hybrid memristor-CMOS technology for low-power arithmetic applications. A power-efficient 1-bit adder, comprising three majority gates and one inverter, is designed and compared with existing memristor-based adders. Three Approximate Adder designs such as MAA1, MAA2, and MAA3 are implemented in 8-bit fully approximate ripple carry structure and 8-bit error-tolerant ripple carry structure, integrating four approximate and four accurate adders. Circuit performance, including power and delay, is analyzed using Cadence Virtuoso, where MAA1 achieves the lowest Power-Delay Product (PDP) in both structures. Image quality metrics, assessed using MATLAB with 8-bit pixel depth images, indicate that MAA3 attains the highest Peak Signal-to-Noise Ratio (PSNR) in the fully approximate structure. Error analysis using Verilog coding shows that the proposed MAA2 design achieves a 24.12% error rate reduction in the error-tolerant structure compared to its fully approximate counterpart, demonstrating its efficiency in balancing accuracy and power consumption. Keywords: memristor, majority logic, approximate computing, image processing, HRTEM image Memristorski logični večinski seštevalniki za aplikacije za obdelavo slik, odporne proti napakam Izvleček: Približno računanje (AC) omogoča energetsko učinkovito in visoko zmogljivo računanje za aplikacije, odporne na napake, kot so analiza podatkov, obdelava slik in multimedija. Zaradi naraščajočega povpraševanja po nizkoenergijskem shranjevanju z visoko gostoto v aplikacijah umetne inteligence in strojnega učenja raziskovalci raziskujejo nastajajoče tehnologije, kot so FinFET, memristorji, FET z ogljikovimi nano cevkami (CNTFET) in kvantno-točkovni celični avtomati (QCA), da bi zmanjšali omejitve CMOS-skaliranja. Članek predlaga učinkovit večinski logični dizajn z uporabo hibridne memristor-CMOS tehnologije za nizkoenergijske aritmetične aplikacije. Oblikovan je energijsko učinkovit 1-biten seštevalnik s tremi vrati in inverterjem. Tri zasnove seštevalnikov, kot so MAA1, MAA2 in MAA3, so implementirane v 8-bitno strukturo polne propagacije prenosa in propagacije prenosa tolerantne na napako. Delovanje vezja, vključno z močjo in zakasnitvijo, je analizirano z uporabo Cadence Virtuoso, kjer MAA1 doseže najnižji produkt moči in zakasnitve (PDP) v obeh strukturah. Merila kakovosti slike, ocenjena z uporabo MATLAB-a s slikami z 8-bitno globino pikslov, kažejo, da MAA3 doseže najvišje razmerje med signalom in šumom (PSNR) v polni približni strukturi. Analiza napak z uporabo kodiranja Verilog kaže, da predlagana zasnova MAA2 doseže 24,12-odstotno zmanjšanje stopnje napak v strukturi, tolerantni do napak, v primerjavi s polno približno strukturo, kar dokazuje njeno učinkovitost pri uravnoteženju natančnosti in porabe energije. Ključne besede: memristor, večinska logika, približno računanje, obdelava slik, HRTEM slika * Corresponding Author’s e-mail: nithyaame@gmail.com , nithya.19phd@kct.ac.in 1 Introduction processing, has amplified the demand for high-density The rapid evolution of Artificial Intelligence and Ma- storage solutions, driven further by the extensive in- chine Learning applications, particularly in big data tegration of the Internet of Things (IoT). Efficient han- How to cite: N. Natarajan et al., “Memristor based Majority Logic Adders for Error Resilient Image Processing Applications", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 4(2025), pp. 239–254 239 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 dling of these data-intensive tasks necessitates storage signs, while Hybrid NMOS-Memristor logic replaces technologies characterized by low power consump- PMOS transistors for efficient NOR logic [10]. In [11], a tion, high density, and fast operation speeds. AC has comprehensive survey on Memristive Threshold Logic gained recognition as an efficient technique to reduce (MTL)-based circuits is presented, which forms the power and area requirements in arithmetic circuits, foundation for our proposed work. making it well-suited for error-resilient tasks such as data analytics, image and video processing, multime- This research investigates the implementation of ma- dia, and signal processing in communication systems. jority logic using an experimentally demonstrated Unlike conventional computing paradigms that prior- memristor. Initially, an Al2O3/HfO2-based memristor itize absolute accuracy, AC architectures emphasize device was fabricated, and its structural and electri- performance and efficiency by allowing controlled im- cal properties were thoroughly characterized. High- precision in computations [1]. Resolution Transmission Electron Microscopy (HRTEM) analysis confirmed the correct formation of the device As conventional CMOS technology approaches its scal- structure. The electrical characteristics, measured using ing limits, challenges such as leakage current, power a DC probe station, were subsequently modelled math- dissipation, and reduced switching speed hinder fur- ematically through Verilog-A coding for integration ther miniaturization and performance improvements. into circuit simulations within the Cadence Virtuoso To address these limitations, alternative nanoelectron- environment [12]. A comprehensive description of the ic devices such as FinFETs, Ferroelectric FETs (FeFETs), process flow and device modelling is provided in Sec- memristors, CNTFETs, and QCA are being explored for tion 3. Further, this paper is structured as follows: Sec- advanced logic applications [2]. Among these, memris- tion 2 surveys the preliminary works related to memris- tors, first theorized by L. Chua in 1971 and experimen- tor based adders, along with previously implemented tally proven by HP Labs in 2008, have shown promise in approximate adders using both CMOS and emerging enabling high-density, energy-efficient computing [3]. technologies. Section 3 presents the experimental de- The HP researchers fabricated nanoscale TiO₂ junction tails of the proposed memristor. Section 4 details the devices with platinum electrodes, demonstrating fast implementation of memristor-based majority logic. bipolar non-volatile switching. Memristors are made Section 5 explores the design of a 1-bit adder using the from organic or inorganic materials, with inorganic op- majority logic and provides a comparative analysis with tions such as TiO₂, Ta₂O₅, HfO₂, and ZnO offering high existing memristor-based adders. Section 6 introduces electrical performance, stability, energy efficiency, and and implements majority logic-based approximate ad- CMOS compatibility. In contrast, organic materials, der designs in 8-bit complete approximate and error- including polymers, graphene oxide derivatives, and tolerant adder structure. Finally, Section 7 discusses the biomaterials, exhibit lower performance and reproduc- results and performance analysis. ibility [4]. Device modeling is essential for developing semicon- ductor devices, providing accurate insights, optimal 2 Prior studies designs, and specification compliance [5]. Various models with window functions for memristors have The comprehensive review of memristor-based 1-bit been developed, each optimized for specific applica- adders are detailed as follows: tions, balancing accuracy, complexity, and computa- tional efficiency. Among this, SPICE and Verilog-based A 4T-1M-based XOR gate and a non-volatile full adder models like linear ion drift and VTEAM are widely used using an Ag/AIST/Ta memristor were modelled with a for their simplicity in circuit-level implementation [6]. threshold memristor model in 0.35μm CMOS technol- Memristive logic designs, advancing VLSI and CMOS ogy. This hybrid memristor-CMOS XOR gate achieves scaling, use memristors for logic gates with resistance significant area and power reductions, offering a com- states representing logic ‘0’ and ‘1.’ IMPLY [7] and MAGIC pact, energy-efficient solution. However, issues such as [8] are key memristive logics, with IMPLY facing high signal degradation in cascading stages and the neces- latency and MAGIC suffering with gate connections. sity of CMOS inverters for level restoration remain bot- Memristor-based design faces challenges like signal tlenecks [13]. The memristor-based MeMOS approach degradation, fanout, and sneak-path currents, which streamlines integration with existing CMOS processes hinder performance and scalability. Integrating mem- and provides a flexible platform for computational ristors with CMOS improves logic density and mitigates architectures [14]. A Silver-Chalcogenide-based Mem- degradation, particularly in AND, OR, NOR, and NAND ristor-CMOS design was introduced for primitive logic gate implementations. Memristor Ratioed Logic (MRL) blocks and extended to specialized logic structures [9] integrates with CMOS inverters for low-power de- [15]. In this approach, the memristor is set to its ON state while the NMOS transistor remains open, and a 240 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 pull-up nanowire resistor controls the charging rate of logic functions within a single structure. The hybrid full the load capacitor to maintain proper voltage levels at adder by combining MRL based AND and OR gates with the node. NMOS-memristor based inverter is proposed in [27]. Memristor Ratioed Logic (MRL) has been widely em- The preliminary studies related to approximate adders ployed for designing universal logic gates, including are as follows: AND, OR, and XOR functions [16]. However, these de- signs often lack detailed power and delay analysis. A Approximate computing (AC) is applied at various lev- combinational circuit using TiO₂ memristors replaced els, but its most critical use is in circuit design, particu- PMOS transistors with memristors to reduce leakage larly for arithmetic circuits. This approach intention- current and improve speed and energy efficiency, par- ally introduces errors to optimize parameters such as ticularly in 180nm CMOS technology. An MRL-based power, delay, energy, and area. AC aims to balance per- full adder, consisting of XOR, AND, and OR gates along formance trade-offs, where reducing transistor count with two inverters, was simulated in 180nm CMOS lowers power consumption but increases error rates. technology using SPICE, demonstrating potential for Thus, transistor count and error rate remain crucial con- reduced area and power consumption [17]. Similarly, a siderations in circuit design. The Approximate Mirror full adder using silver chalcogenide memristors incor- Adder (AMA) designs are implemented by modifying porated multifunctional XOR and AND gates, achieving conventional mirror adder for low complexity digital a delay improvement compared to conventional CMOS applications [28]. The CMOS based energy efficient and designs [18]. Additionally, it combines traditional MRL variation aware Approximate Full Adder (AFA) designs logic with a 1-memristor 1-NMOS (1M1N) design to ad- are introduced for imprecision tolerant image process- dress output signal amplification issues. ing applications [29]. The Approximate Adder (AA) de- signs aim to integrate adders and multipliers at the fun- A transistor-free memristor-based full adder employ- damental level of Digital Signal Processor design [30]. ing XOR and OR gates in MRL logic, using 14 memris- Area and power efficient reversible full adders were tors and two inverters [19], yielding a simplified design implemented using GDI logic in [31]. similar to prior MRL based implementations reported in [16]. Further advancements in memristor-based log- Beyond CMOS-based designs, emerging technologies ic include the 1T2M design, which exploits the non-vol- such as FinFET, CNTFET, QCA, memristors and spin- atile nature of memristors for XOR/XNOR operations, tronic devices based approximate adders have been reducing power consumption and circuit complexity explored. Gate Diffusion Input (GDI) logic implement- while integrating one-bit full adder and comparator ed using 11nm FinFET technology based approximate functionalities [20]. Additionally, a Y₂O₃-based mem- adders known as FFA face challenges related to output ristor model was designed to enhance signal integrity voltage level degradation [32]. CNTFET-based approxi- and prevent output degradation, though it requires ini- mate adders such as GMFA design suffer from non-full tialization of memristance value for proper operation swing operation, leading to voltage level degrada- [21]. A calibrated HfO₂ memristor model was assessed tion [33]. QCA-based majority logic adders have been for variability and timing analysis in a full adder circuit designed [34] and labelled as PAA, but their practical [22], while yttrium oxide memristors were employed adoption is hindered by fabrication complexity, tem- for low-power logic circuit designs where, the memris- perature sensitivity, defect tolerance, scalability issues, tor functions as a programmable resistor controlled by clocking overhead, and high-power dissipation. Spin- an NMOS transistor for enhanced logic performance tronic full adders using Magnetic Tunnelling Junctions [23]. (MTJs) exhibit high power consumption and delay, though reconfigurable magnetic full adders have been A Hybrid Memristor-CMOS (HMC) logic-based adder de- explored to mitigate some of these drawbacks [35, sign, combining transmission gates, MRL-based AND/ 36]. Additionally, approximate adders and subtractors OR gates, and 1T-1M inverters, demonstrated efficiency using memristor-based architectures have been ex- through its simple structure and implementation in 32- plored, further highlighting the advantages of memris- bit ripple carry adders [24].A TaOₓ memristor, modelled tors in logic circuit implementations [37]. with a compact Verilog-A model, demonstrated correct functionality in a 1-bit full adder. Minor glitches from Among emerging technologies, memristors have delay mismatches between MRL and CMOS compo- gained significant prominence due to their high com- nents had minimal impact on performance at 1 MHz patibility with CMOS transistors, enabling the develop- frequency [25]. In [26], a full adder implementation us- ment of compact and energy-efficient logic circuits. ing a universal logic circuit improve integration density and reduce power consumption by enabling multiple 241 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 3 Experimental section implemented using Verilog-A in Cadence virtuoso environment. The comparison of experimental I-V The fabrication process for the Pt/Al₂O₃/HfO₂/Ti/TiN na- characteristics and modelled I-V characteristics with a noscale device, outlining the specific materials, depo- compliance current of 100 µA are illustrated in Figure 3. sition techniques, and process parameters used to The memristor device is implemented in Cadence Vir- achieve its precise dimensions and well-defined struc- tuoso, and its compatibility with CMOS technology is ture is illustrated in Figure 1. The device was annealed validated through the design and simulation of a mem- at 400 °C, and the incorporation of a Ti capping layer ristor–NMOS-based inverter [38]. In this configuration, enables forming-free switching behavior with reduced the proposed memristor functions as a resistive pull-up set and reset voltages. The annealing process, com- element, replacing the PMOS transistor. This design bined with the forming-free nature of the device, con- maintains acceptable noise margins in the CMOS cir- tributes to improved uniformity and reduced variabil- cuit, as the memristor provides an optimal resistance ity. A detailed analysis of its electrical characteristics is that results in minimal voltage drop at the output. provided in our previous work [38]. HRTEM analysis was employed to examine the morphological and struc- tural properties of the device, confirming the uniform- ity, interface quality, and thickness consistency of the deposited layers. Additionally, Energy Dispersive Spec- troscopy (EDS) mapping, shown in Figure 2. provides a detailed representation of the elemental distribution within the fabricated device. The observed elemental distribution closely matches the expected outcomes based on the fabrication process flow, confirming the consistency and accuracy of the device fabrication. Figure 3: Comparison of Experimental and modelled I-V Characteristics Table 1. Mathematical Model Parameters Parameters Pt/Al2O3/HfO2/Ti/TiN Figure 1: Fabrication process flow of proposed device Memristor device Roff (off-Resistance) 36729 Ron (on-Resistance) 6600 Von(on voltage) -0.93 Voff (off Voltage) 0.66 Koff (Fitting parameter) 8e-5 Kon(Fitting parameter) -8e-5 Alphaoff (Fitting parameter) 2.25 Alpha on (Fitting parameter) 3.2 These experimental findings provide valuable insights Figure 2: The nanostructure and interfacial morpholo- into the device’s behaviour, serving as a foundation for gies of the proposed Al2O3/HfO2bi-layer RRAM device performance optimization and further studies. were investigated using HRTEM. 3.1 Experimental and modelled IV characteristics 4 Memristor majority logic (M-ML) The electrical performance of the fabricated device was rigorously characterized using a DC probe station, Majority logic is a crucial component in the approxi- enabling precise measurement of key electrical param- mate computing paradigm, and is widely adopted eters such as resistance states and switching voltages. across various emerging technologies, including QCA, The mathematical modelling is done using the model ferroelectric devices, spintronic devices, and CNTFETs. [12]. The Table 1. describes the modelling parameters In these technologies, majority logic is typically im- 242 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 plemented using capacitive or resistive elements, en- of the inputs is 1, thus the output is 1. Functionally, the hancing area and power efficiency. Majority logic is circuit behaves as an AND gate when the Control input commonly utilized in the design of adders and can be is set to 0, and as an OR gate when the Control input is extended to approximate compressors with minimal set to 1 as given in Table 2. error distance. These compressors are integral compo- nents in multipliers and digital filters, which are used to Table2: Truth table for majority logic develop area-efficient image processing architectures with a reduced number of transistors. This reduction in Inputs Working Outputs transistor count leads to lower overall power consump- condition of tion and enables high-speed computing, where minor transistors compromises in accuracy have negligible impact on Control B A P1 N1 Minority Majority image quality. However, implementing majority logic Logic Logic in CMOS technology is often area-inefficient due to the 0 0 0 ON OFF 1 0 requirement of a greater number of transistors. 0 0 1 ON OFF 1 0 0 1 0 ON OFF 1 0 The M-ML logic circuit is implemented by combining 0 1 1 OFF ON 0 1 memristors and CMOS inverters as shown in Figure 4. 1 0 0 ON OFF 1 0 In this design, two inputs A and B, along with a control input, are fed into a CMOS-based inverter Via memris- 1 0 1 OFF ON 0 1 tors. When the control input is set to either 0 or 1, the 1 1 0 OFF ON 0 1 input voltages at A and B determine the resistances of 1 1 1 OFF ON 0 1 M1 and M2 memristors respectively. To configure the circuit as a NAND gate, the control input is set to ‘0’ or below the threshold voltage; in this case, the output is 5 M-ML based 1-bit adder (M-MLA) logic ‘1’ for all input combinations except when A =B =1, where both memristors conduct and the output be- comes logic ‘0’. Conversely, to operate the circuit as a NOR gate, the control input is set to 1, resulting in an output of logic ‘0’ for all combinations except when A =B =0, where the output is logic ‘1’. Figure 5: 1-bit Majority Logic based full adder The proposed M-MLA circuit shown in Figure 5. is de- signed using majority logic. The carry circuit is con- structed with transistors P1-P2, N1-N2 and M1, M2, M3 Figure 4: Majority and Minority logic circuit with de- . When Cin=0, the output is A AND B; when Cin=1, the vice structure output is A OR B. The sum circuit is realized using tran- sistors P3 –P6 and N3 – N6 . At node X, the circuit gener- Additionally, the circuit can be configured to operate ates the output A OR B when Cin=0 and A AND B when as minority logic, where the least frequent input value Cin=1. The final sum output is derived by using Cin as determines the output. For instance, if A=0, B=1, and a control input, with X and Cout′ as inputs. The Table 3 the control input is 1, the output is logic ‘0’. Similarly, illustrates the functionality of the majority logic in gen- the output is ‘1’ for all ‘0’ inputs and ‘0’ for all ‘1’ inputs. erating the sum and carry output. When an inverter consisting of transistors P2 and N2 is integrated into the proposed circuit, the resulting configuration implements majority logic, producing the output corresponding to the majority value of the inputs. For instance, when A=B=Control=0, the output is 0. Conversely, when A=B= Control = 1, the majority 243 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 Table 3: Truth table for output of 1-bit M-MLA free operation. A comparison of various mathemati- cal models, as discussed in Section 1, indicates that Inputs Intermediate Sum output Carry threshold-based approaches such as TEAM and VTEAM Inputs Output are preferred for their simplicity and ability to capture Cin’ B A Cin Cout’ X Maj Maj asymmetric switching behavior, resulting in minimal (Cin,Cout’,X) (A,B,Cin) deviation between experimental and simulated char- 1 0 0 0 1 0 0 0 acteristics. 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 The adders presented in [23] employ 1NMOS-1Mem- 1 1 1 0 0 1 0 1 ristor-based inverters, where the gate terminal of the transistor in the off state consistently experiences a 0 0 0 1 1 0 1 0 high output, contingent on the high off-resistance val- 0 0 1 1 0 0 0 1 ue. MRL logic is utilized exclusively for AND and OR gate 0 1 0 1 0 0 0 1 implementations and necessitates CMOS-based invert- 0 1 1 1 0 1 1 1 ers for other logic circuit implementation [14,17,25]. By modifying MRL logic through the inclusion of a mem- The M-MLA is simulated in Cadence Virtuoso and com- ristor with a control input, a stacked NAND/NOR output pared with other memristor-based adders implement- is achieved. Additionally, integrating an extra inverter ed in 180 nm technology, using the process parameters facilitates majority logic implementation. Majority specified in [23]. The experimental section 3 provides logic exhibits higher power consumption compared to detailed information on the memristor’s design param- MINI logic [39], but MINI logic is affected by output volt- eters, structural configuration, and electrical character- age level degradation. Conversely, post-CMOS majority istics for implementing the proposed majority logic in logic offers high output driving capability and does not memristor-based architectures. require additional buffers or resistors to restore output levels, as indicated in [26]. The proposed post-CMOS Table 4 provides a comparative analysis of traditional majority logic-based memristor adders offer the po- memristor based adders with proposed majority logic tential for extending the design towards more complex adder. The logic circuits reported in [14, 17, 26] employ logic circuit implementations, enhancing their applica- titanium dioxide (TiO₂)-based memristors, which ex- bility in advanced computing architectures. hibit set and reset voltages exceeding 1 V and require an electroforming voltage above 2 V. The design pre- sented in [23] utilizes an yttrium oxide (Y₂O₃)-based memristor with relatively high switching voltages of > 6 M-ML based approximate adder 4V. Although operated at a 1 V input level, this imple- (MMA) designs mentation achieves a power consumption of about 38 µW and a delay of approximately 200 ps. The work in The approximate adders are increasingly being utilized [25] employs a tantalum oxide (TaOₓ)-based memristor for high-density image processing applications, where with a set voltage of 0.7 V, but it still requires an elec- performance is prioritized over perfect accuracy. Three troforming step. In contrast, the proposed memristor distinct types of approximate adders are proposed and demonstrates a low set voltage of 0.66 V and forming- numbered based on the number of inverters required Table 4. Performance Evaluation of Proposed vs. Existing Memristor based Adders in 180nm Technology Adder Types Model Used Device count Power Delay References MeMOS logic TEAM 16T+18M 17.87uW 212.3ps [14] MRL Logic Non-Linear dopant drift 24T+18M 53.08uW 62.4ps [17] Hybrid Memristor-NMOS only logic Analytical 23T+14M 38uW 200ps [23] Transmission gate logic with 1T1M VTEAM 12T+6M 8.2uW 112.7ps [24] inverters and MRL based AND/OR logic CMOS logic with MRL logic Compact 16T+10M 0.615mW 1.78ns [25] MRL logic with 1T-1R inverter and Non-Linear 14T+12M+2R 121.78uW 62.55ps [26] CMOS inverter M-ML Logic VTEAM 14T+9M 4.752uW 218ps Proposed Logic *R-Resistors; M-Memristors; T-Transistors 244 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 such as MAA1, MAA2, MAA3 respectively shown in Fig- units of image processing systems. However, due to the ure 6(a-c). Table 5 compares the proposed approximate nature of the majority logic, the MAA2 may experience adders with accurate full adders and calculates the er- a slight degradation in sum accuracy, which is compen- ror distance (ED) by obtaining the absolute difference sated by its error-free carry output. between exact and approximate output. The MAA1 incorporates two errors in both the sum and (a) carry outputs. It uses one inverter and three memris- tors, resulting in a smaller area footprint compared to other adder designs. This reduction in area translates directly to lower power consumption and improved speed efficiency, making the MAA1 a suitable can- didate for high-performance, power-efficient image processing applications. This efficiency comes at the cost of increased image quality degradation compared to the MAA2, as the additional errors in both sum and (b) carry outputs contribute to more significant distortion in the processed image. The MAA3 is designed using 3 memristors and 3 invert- ers. It introduces two errors at the sum and carry out- put for same combinations of inputs. 6.1 Comparison of 1-bit approximate adders (c) Tables 6 and 7 present the outputs of approximate ad- ders along with the corresponding error distance (ED) for conventional CMOS logic and emerging logic tech- nologies, respectively. The ED is calculated using eq. (1). The error rate (ER) quantifies the percentage of ED occurrences relative to the total possible input combinations as shown in Figure 6: Proposed approximate adder designs (a) eq. (2). The normalized mean error distance (NMED) is MAA1 (b) MAA2 (c) MAA3 computed for each approximate output by dividing the ED by the total number of inputs as shown in eq. (3). The MAA2 is designed to introduce two errors in the sum output while maintaining an error-free carry out- The error metrics for approximate adders are evaluated put. The carry output, being error-free, is propagated using the parameters formulated as follows: to the next stage, effectively reducing the overall error rate in the adder. This feature makes the MAA2 particu- EDi  ExactOutput  ApproximateOutput (1) larly suitable for applications where minimizing carry i i propagation errors is essential, such as in arithmetic Table 5: Truth table of Proposed Majority logic based Approximate adders Inputs FA MAA1 MAA2 MAA3 a b Cin Carry Sum ED Carry Sum ED Carry Sum ED Carry Sum ED 0 0 0 0 0 0 0ü 1û 1 0ü 1û 1 0ü 0ü 0 0 0 1 0 1 0 0ü 1ü 0 0ü 1ü 0 0ü 1ü 0 0 1 0 0 1 0 0ü 1ü 0 0ü 1ü 0 0ü 1ü 0 0 1 1 1 0 0 0û 0ü 2 1ü 0ü 0 0û 1û 1 1 0 0 0 1 0 1û 1ü 2 0ü 1ü 0 1û 0û 1 1 0 1 1 0 0 1ü 0ü 0 1ü 0ü 0 1ü 0ü 0 1 1 0 1 0 0 1ü 0ü 0 1ü 0ü 0 1ü 0ü 0 1 1 1 1 1 0 1ü 0û 1 1ü 0û 1 1ü 1ü 0 245 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 plementing them within 8-bit Ripple Carry Adder (RCA) ER Number of Erroneos Outputs  100 (2) structures. Two types of memristor-based approxi- n mate adder architectures have been designed: the 8-bit Memristor-based Complete Approximate Adder 1 n Exact  Approximate (MCAA), which utilizes approximate adders for all eight NMED   Outputi Outputi (3) bits, as illustrated in Figure 7 (a), and the 8-bit Memris- n i1 ExactOutputmax tor-based Error-Tolerant Adder (META), which employs a hybrid approach. In the META design, the least sig- Table 8 outlines the logic equations for 1-bit existing nificant 4 bits (LSBs) are implemented using approxi- approximate adders, detailing the number of errors, mate adders, while the most significant 4 bits (MSBs) Device Count (DC), ER and NMED. The memristor-based utilize exact adders based on majority logic for PAA’s approximate adder (MFA) exhibits a high error rate of and MAA’s and CMOS based conventional full adder for 62.5%, with five errors exceeding the 50% threshold. other approximate adders, as shown in Figure 7 (b). Adders with an error rate of ≤ 50% have been selected for the implementation of 8-bit approximate adder ar- 7.1 Circuit metrics of 8-bit approximate adders chitectures. Furthermore, the PAA1 and PAA2 adders, originally designed in QCA technology, have been re- The 1-bit adder structure were simulated at a frequen- simulated utilizing the proposed memristor-based ma- cy of 100 MHz, with power and delay metrics extracted jority logic to ensure a fair comparative analysis. for comparative analysis. The performance of the 1-bit adders were evaluated in the context of 8-bit META and 8-bit MCAA architectures. The FFA and GMFA, imple- 7 Performance analysis of 8-bit mented using Gate Diffusion Input (GDI) logic, exhibit non-full-swing voltage output characteristics. Instead approximate adders of achieving the expected 1V VDD output level, an out- put voltage of 0.702V was obtained, with some instanc- This section investigates the effects of seventeen ap- es producing VDD/2. While this voltage level remains proximate full adders, as described in Table 8, by im- above the noise margin, the output driving capability Table 6: CMOS Logic based Approximate adders Inputs FA AMA1 AMA2 AMA3 AMA4 AFA1 AFA2 AFA3 AA2 AA4 a b Cin CS CS (ED) CS (ED) CS (ED) CS (ED) CS (ED) CS (ED) CS (ED) CS (ED) CS (ED) 0 0 0 00 00 01(1) 01(1) 00 01(1) 00 00 00 00 0 0 1 01 01 01 01 01 01 00(1) 00(1) 01 01 0 1 0 01 10(1) 01 10(1) 00(1) 01 01 01 01 01 0 1 1 10 10 10 10 01(1) 01(1) 11(1) 01(1) 10 01(1) 1 0 0 01 00(1) 01 01 10(1) 01 01 01 10(1) 10(1) 1 0 1 10 10 10 10 10 10 11(1) 11(1) 10 10 1 1 0 10 10 10 10 10 10 11(1) 11(1) 10 10 1 1 1 11 11 10(1) 10(1) 11 10(1) 11 11 10(1) 11 Table 7: GDI Logic and emerging logic based Approximate adders Inputs FFA2 FFA3 GMFA MFA PAA1 PAA2 A b Cin CS (ED) CS (ED) CS (ED) CS (ED) CS (ED) CS (ED) 0 0 0 00 00 01(1) 00 00 01(1) 0 0 1 01 01 00(1) 11(2) 01 00(1) 0 1 0 01 01 00(1) 00(1) 00(1) 01 0 1 1 01(1) 00(2) 10 11(1) 11(1) 10 1 0 0 00(1) 00(1) 01 00(1) 00(1) 01 1 0 1 11(1) 11(1) 10 00(2) 11(1) 10 1 1 0 10 10 10 10 10 11(1) 1 1 1 11 11 10(1) 11 11 10(1) *ED-Error Distance, C-carry output, S-Sum output 246 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 (a) for ripple-based structures is significantly reduced. The comparative analysis of DC, power consumption, and delay is presented in Figure 8(a-c). The MAA1 adder is designed with a minimal DC, uti- lizing only three memristors and two transistors. In contrast, the AMA1 and AA2 adders incur significant area overhead due to their reliance on 20 transistors. The AFA1 and GMFA architectures exhibit area effi- ciency comparable to MAA-based designs within the 8-bit MCAA configuration. However, in error-tolerant 8-bit META architectures, the DC increases. Notably, (b) the MAA1 requires only 5 DC, achieving a reduction of 41.67% and 75% compared to AMA1 and AA2 in 8-bit META and MCAA structures, respectively. Moreover, conventional adders such as AMA and AA, as well as most AFA designs except AFA1, implemented using standard CMOS logic, require a significantly higher DC compared to emerging logic-based approximate ad- ders, resulting in increased area and power consump- tion. Power analysis reveal that MAA1 exhibit better power Figure 7: Block diagram of 8-Bit Memristor based (a) efficiency compared to all evaluated cases. Within the Complete Approximate Adder (MCAA) (b) Error Toler- 8-bit MCAA configuration, GMFA consume less power ant adder (META) than MAA3 and AFA1 due to its non-full-swing output Table 8: Error Metric Analysis of Approximate adders Approximate Sum Equation Carry Equation Number DC ER NMED adder of Errors (%) AMA1 [28] A . B .Cin  ABCin B  A.Cin 2 20 25 0.083 AMA2 [28] Cin.A  B   (A.B ) A.B  B.Cin  A.Cin 2 16 25 0.083 AMA3 [28] B  A.Cin B  A.Cin 3 13 37.5 0.125 AMA4 [28] Cin.A  B A 3 15 37.5 0.125 AFA1 [29] A.B Cin A.B Cin 3 8 37.5 0.125 AFA2 [29] A B Cin.A B  A.B 4 18 50 0.167 AFA3 [29] A B A.B Cin 4 14 50 0.167 AA2 [30] BCin  B.Cin  A A B.Cin 2 20 25 0.083 AA4 [30] Cin.A B  B A B A 2 14 25 0.083 FFA2 [32] A.B Cin A.B  B.Cin 3 10 37.5 0.125 FFA3 [32] A.BCin A.B  B.Cin 3 12 37.5 0.125 GMFA [33] B Cin A.B.Cin  A.B Cin 4 8 50 0.167 MFA [37] A.B.Cin  A.B. Cin A.B.Cin  A.B.Cin A.B.Cin  A.B.Cin AA..BB.C. iin  A.B.Cin 5 10M+6T 62.5 0.208 PAA1 [34] Cin Maj A,B,Cin 4 3M+4T 50 0.167 PAA2 [34] Cin Maj A,B,Cin 4 3M+6T 50 0.167 MAA1 Min A,B,Cin A 4 3M+2T 50 0.167 MAA2 Min A,B,Cin Maj A,B,Cin 2 3M+4T 25 0.083 MAA3 Maj A,B,Cin A 2 3M+6T 25 0.083 247 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 characteristics. The delay analysis is calculated for the a power consumption of 5.771 µW and a delay of 0.289 longest propagation path, where the sum output ex- ns. Additionally, the power and delay characteristics of hibits the highest delay in most approximate adders. the Majority Full Adder (MFA) are presented in Table 4. However, in architectures such as PAA, FFA, and AFA, The Power-Delay-Area-Product (PDAP) analysis is done the carry output experienced the highest delay. Among by calculating the evaluated circuits, AMA1 and AA2 demonstrate the highest worst-case delay. Additionally, GDI logic-based PDAP = PDP ×DC approximate adders exhibit increased delay compared to MAA-based designs. and graphically represented in Figure 9(b). The PDP analysis, as depicted in Figure 10, is presented in de- The PDP analysis for the 1-bit adder, as illustrated in creasing order for the 8-bit MCAA and 8-bit META Figure 9(a), includes a Conventional Full Adder (CFA) structures, evaluated using all approximate adders. The implemented using CMOS transistors. The CFA exhibits MAA1 show an improvement of 23.40% and 33.85% compared to MAA2 and MAA3 respectively in 8-bit (a) META architecture. Similarly, MAA1 shows 71.37% and 79.99% improvement in PDP compared to MAA2 and MAA3 designs in 8-bit MCAA architecture. These find- ings provide insights into the trade-offs between area, power, and delay in various approximate adder de- signs, highlighting the advantages and limitations of different implementation approaches for low-power and energy-efficient arithmetic circuits. (a) (b) (b) (c) Figure 9: Comparison of 1-bit accurate and approxi- mate adders (a) PDP analysis (b) PDAP analysis Figure 8: Comparative analysis of 1-Bit AA, 8-Bit MCAA, 8-Bit META structures in terms of (a) Device Count (b) Figure 10: PDP analysis of approximate adders in 8-Bit Power (c) Delay META and MCAA structure 248 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 7.2 Error metrics of 8-bit approximate adders PDAP. The analysis of PDP versus NMED highlights the trade-off between accuracy and circuit performance in The accuracy of the proposed majority-based adders is majority-logic-based adders compared to other adder evaluated using key error metrics, including the NMED, designs. The majority-logic-based adders demonstrate ER, and Mean Absolute Error (MAE). These adders are efficiency, as their PDP values predominantly fall within compared with previously reported approximate ad- the left half of the vertical axis in both 8-Bit MCAA and ders by implementing in 8-bit architectures and testing 8-bit META structure as shown in Figure 11 (a) and (b) them against all possible input combinations using a respectively. Verilog-based testbench. Table 9 presents the average PDAP values alongside the error metrics. The analysis Additionally, MAA2 and MAA3 exhibit lower error rates, indicates that for the 8-bit META adders, MAA2 and positioning them in the first half of the horizontal axis, AMA2 exhibit the lowest error rates with minimal error along with GMFA and PAA2 in 8-Bit META structure as distances. However, in terms of PDAP, MAA2 demon- shown in Figure 11(b). However, GMFA produces a non- strates superior efficiency, achieving an 80.54% reduc- full-swing output, reinforcing the advantage of majori- tion in PDAP compared to AMA2. Additionally, MAA1 in ty-logic-based adders in achieving an optimal balance META and MCAA architectures also report lower PDAP of performance, accuracy, and efficiency. values at the cost of reduced accuracy. 7.3 Image quality metrics of 8-bit approximate adders Furthermore, the error rates of PAA’s and FFA2 designs are significantly higher than those of other adders. Three distinct sets of 512 X 512 sized input images Notably, MAA2 exhibits the lowest MAE value, con- with 8-bit pixel depth were selected from an image da- tributing to a reduction in NMED. In the case of the tabase [40] and processed using accurate adders. For 8-bit MCAA adder, AMA1 achieves a lower error rate comparison, the same images were processed using all than MAA-based designs, albeit with an increase in proposed approximate adders implemented in MCAA and META based 8-bit ripple carry structures. The ad- ders were implemented using Verilog and integrated (a) into MATLAB via the importhdl command for image quality analysis. Image quality metrics, including PSNR and Structural Similarity Index (SSIM), are evaluated. (b) Figure 12: Comparative analysis of image quality met- rics in 8-bit META and MCAA The graphical representation of PSNR and SSIM analy- sis for 8-bit META and 8-bit MCAA adders is shown in Figure 12. The majority-logic-based adders demon- strate superior performance, achieving higher PSNR and SSIM values, particularly in the META structure. Among them, MAA3 exhibits the highest PSNR and SSIM values; however, it requires an additional inverter compared to MAA2. Figure 11: PDP vs NMED analysis for (a) 8-Bit MCAA (b) 8-Bit META structure 249 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 Table 9. Comparison of error metrics with average PDAP for 8-bit approximate adders Approximate adder 8-BIT MCAA 8-BIT META Average PDAP NMED MAE ER Average PDAP NMED MAE ER AMA1 9057.888 0.2099 255 86.05 16535.5 0.02138 255 73.63 AMA2 6687.171 0.2342 255 89.98 14616.84 0.014101 15 68.27 AMA3 3774.135 0.3198 255 97.44 10484.57 0.02892 255 86.57 AMA4 4033.536 0.2827 255 97.57 10629.5 0.031062 255 86.72 AFA1 1270.368 0.3201 255 96.12 7085.261 0.02499 254 78.42 AFA2 7722.922 0.3321 255 89.81 15217.72 0.01890 15 68.22 AFA3 3474.979 0.3321 255 89.81 9011.402 0.0220 255 68.22 AA2 8816.896 0.2733 254 89.97 16311.86 0.0240 252 68.17 AA4 2447.98 0.2189 254 90.08 6803.731 0.0258 255 68.26 FFA2 993.3784 0.2988 255 96.05 6809.858 0.0255 253 78.37 FFA3 2067.71 0.2728 254 95.09 8310.144 0.0293 252 78.37 GMFA 679.814 0.3734 255 99.60 5535.605 0.0219 15 93.78 PAA1 308.0386 0.4475 255 99.58 2843.808 0.02751 15 93.76 PAA2 625.312 0.3335 255 99.60 3623.731 0.02078 15 93.74 MAA1 62.9982 0.3013 255 97.86 2032.934 0.0430 254 88.68 MAA2 308.0386 0.2342 255 89.98 2843.808 0.01410 15 68.27 MAA3 566.676 0.2189 254 90.08 3512.448 0.0258 255 68.26 7.4 Figure of merit computing by ensuring an optimal balance between power consumption and accuracy. Meanwhile, MAA2 The circuit performance analysis and Error metrics can and MAA3 are well-suited for fully approximate archi- be jointly analysed using Figure of Merit (FOM) calcula- tectures, excelling in applications that tolerate higher tions in approximate computing [36]. The FoM is calcu- error rates in exchange for reduced power consump- lated using the formula: tion and delay. (a) FoM Normalized PDAP  1 Average NMED It must be noted that the circuit performs better for lower FoM. The FoM values for the 8-bit META and 8-bit MCAA adders are presented in decreasing order, highlighting the optimal performance of the proposed (b) majority-logic-based designs compared to existing ad- ders. Among these, MAA1 achieves the lowest FOM due to its minimal power-delay product (PDP); how- ever, its output image quality is inferior to that of MAA2 and MAA3. For fully approximate adders, MAA2 and MAA3 provide a better trade-off between accuracy and efficiency. Conversely, in error-tolerant applications, where only the least significant bits (LSBs) utilize ap- proximate adders, MAA1 emerges as the most efficient Figure 13: FoM analysis for 8-bit adders using (a) MCAA choice due to its low FOM. (b) META The post-CMOS majority-logic-based approach dem- Compared to conventional CMOS-based designs such onstrates greater efficiency compared to traditional as AMA, AFA, and AA adders, the FOM of emerging log- CMOS logic, making it a promising alternative for arith- ic-based designs is significantly lower, reflecting their metic circuit design. Each of the proposed approximate superior performance. Notably, the PAA2 and MAA3 adders is tailored to specific application requirements, designs, as well as the PAA1 and MAA2 designs, have with MAA1 proving highly efficient for error-tolerant an equal device count. However, the proposed MAA2 250 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 and MAA3 architectures achieve a lower FOM, resulting structures, where power efficiency and computational in improved performance over PAA1 and PAA2, primar- accuracy need to be balanced. ily due to their lower error rates and reduced normal- ized mean error distance (NMED). Additionally, GDI Conversely, MAA2 and MAA3, incorporating two and logic, an optimized variant of conventional CMOS logic, three inverters respectively, offer an optimal solution demonstrates a relatively small FOM difference when for fully approximate adder architectures, enabling en- compared to the proposed majority-based designs in hanced performance in applications that can accom- the MCAA architecture, while a more significant differ- modate higher levels of approximation while benefit- ence is observed in the META architecture as shown in ing from reduced power consumption and latency. The Figure 13 (a) and (b) respectively. analysis of both META and MCAA architectures posi- tions MAA2 as an intermediate solution, balancing the The proposed 8-bit approximate adder can be scaled to trade-offs between MAA1 and MAA3. higher bit-width versions using a modular design, with LSBs approximated and MSBs kept accurate to limit Comparative evaluation with conventional CMOS and worst-case error. In 16-bit implementations, MCAA ar- Gate Diffusion Input (GDI)-based approximate adders chitecture shows higher error rates compared to the demonstrates that majority-logic-based designs offer META architecture. Simulations of 16-bit META archi- significant advantages in device count optimization, tecture with 50% approximation is validated by writ- leading to reduced circuit complexity and improved ef- ing Verilog testbench and results show error rates of ficiency. Extensive simulations assess key performance 90% for MAA2 and MAA3, still lower than other designs parameters, including power consumption, propaga- reaching up to 99%, indicating better error efficiency. tion delay, error metrics, and image quality metrics. These evaluations contribute to the estimation of the Accuracy can be enhanced by reducing the approxima- Figure of Merit (FoM), where majority-logic-based ad- tion ratio or employing dynamic approximation tech- ders consistently outperform conventional logic-based niques based on input sensitivity. However, decreasing approximate adders. By considering various design pa- the extent of approximation introduces area overhead rameters, trade-offs, and application-specific require- due to the increased transistor count in the accurate ments, the most suitable adder architecture can be se- portion of conventional designs. For instance, at a 25% lected for integration into complex logic circuits. approximation level, the accurate adder section using conventional design requires 60 additional transistors The results highlight the potential of emerging mem- compared to a majority logic-based implementation ristor-based majority logic for designing high-perfor- in error tolerant architecture. Notably, majority logic mance, energy-efficient adder architectures. Applica- in the META architecture proves efficient across all tions such as neural network accelerators, digital signal metrics, offering improved PDAP and linear scalability, processing (DSP), and encryption circuits can leverage making it ideal for larger arithmetic units. Overall, these the power and area benefits of approximate comput- adders provide a balanced trade-off among power, de- ing. Neural networks and DSP algorithms are inher- lay, and accuracy, making them effective for energy- ently error-tolerant, while non-critical components efficient, high-performance computing. in encryption circuits can be approximated without compromising security. As memristor technology con- tinues to advance, majority-logic-based designs could 8 Conclusion play a pivotal role in the development of next-gener- ation computing systems. Broadening the application This work presents the design and analysis of a ma- scope to these domains further underscores the prac- jority-logic-based 1-bit adder using experimentally tical relevance and impact of the proposed design for assessed and modelled memristor technology. The next-generation energy-efficient computing systems. proposed design is evaluated against various existing memristor-based adders to assess its performance and efficiency. Additionally, three 1-bit approximate ad- 9 Acknowledgments ders are developed using majority logic by integrating memristors with CMOS inverters, offering a balance This research was partially supported by Institutional between performance, power consumption, and cir- SEED grant from Kumaraguru College of Technology, cuit complexity. Among the designed approximate Coimbatore-641049. adders, MAA1 achieves the lowest Power-Delay-Area Product (PDAP) and Power-Delay Product (PDP), mak- ing it the most suitable choice for error-tolerant adder 251 N. Natarajan et al.; Informacije Midem, Vol. 55, No. 4(2025), 239 – 254 10 Conflict of interest 9. K.A. Ali, M. Rizk, A. Baghdadi, J.P. Diguet and J. Jomaah, “Hybrid Memristor–CMOS Implemen- The authors declare that they have no conflict of inter- tation of Combinational Logic Based on X-MRL,” est. Electronics, vol.10, no.9, 2021, https://doi.org/10.3390/electronics10091018. 10. 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This is an open access article dis- tributed under the Creative Com- mons Attribution (CC BY) License (https://creativecom- mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 11. 04. 2025 Accepted: 09. 08. 2025 254 Original scientific paper https://doi.org/10.33180/InfMIDEM2025.405 Journal of Microelectronics, Electronic Components and Materials Vol. 55, No. 4(2025), 255 – 262 Enhanced Neutron-Gamma Discrimination Using Deep Neural Networks for Precision Nuclear Medicine Min Jiang1,2,3, Longwei Zeng4, Lingli Gan4, Bin Jia4, Xiuwan Wang5, Zhiyuan Zhu3 1South Zhejiang Institute of Radiation Medicine and Nuclear Technology, Wenzhou Key Laboratory of Precision General Practice and Health Management, Wenzhou, China 2Zhejiang Provincial Key Laboratory of Watershed Sciences and Health, Wenzhou Medical University, Wenzhou, China 3College of Electronic and Information Engineering, Southwest University, Chongqing, China 4Center for Neurology, The Thirteenth People’s Hospital of Chongqing, Railway New Village, Huangjueping Jiulongpo District, Chongqing, China 5State Key Laboratory of Reproductive Medicine and Offspring Health, Nanjing Medical University, Nanjing, China Abstract: Scintillator detectors, widely used in nuclear medicine and industrial applications such as radiation monitoring and material analysis, are sensitive to both neutrons and gamma rays (n/γ). A key challenge in neutron detection is minimizing gamma- ray interference to ensure accurate measurements. Neutron-gamma discrimination is difficult because the two particle types often produce overlapping signals in scintillator detectors, with similar pulse amplitudes but subtle differences in shape and timing. Traditional methods struggle to distinguish these subtle features, leading to misclassification and reduced detection accuracy.To address this, we propose a deep neural network (DNN)-based approach combined with pulse shape discrimination (PSD) techniques to achieve high-precision particle discrimination in mixed n/γ fields. Leveraging DNN‘s ability to learn complex patterns, our method effectively classifies neutron and gamma-ray pulses. The trained DNN model was evaluated against traditional discrimination algorithms, including the charge comparison method, rise-time analysis, frequency-domain gradient analysis, and K-means clustering. Quantitative results demonstrate a discrimination accuracy of 99%, significantly outperforming conventional techniques. Furthermore, the proposed DNN method not only enhances discrimination reliability in mixed radiation fields but also reduces processing time compared to existing methods, making it suitable for real-time applications in medical imaging and industrial neutron detection. Keywords: neutrons and gamma rays, deep neural network, pulse shape discrimination Izboljšana razločevanje med nevtroni in gama žarki z uporabo globokih nevronskih mrež za natančno nuklearno medicine Izvleček: Scinilatorji, ki se pogosto uporabljajo v nuklearni medicini in industrijskih aplikacijah, kot so nadzor sevanja in analiza materialov, so občutljivi tako na nevtrone kot na gama žarke (n/γ). Ključni izziv pri zaznavanju nevtronov je zmanjšanje motenj gama žarkov, da se zagotovijo natančne meritve. Razlikovanje med nevtroni in gama žarki je težko, ker ti dve vrsti delcev v scinilatorjih pogosto proizvajajo prekrivajoče se signale s podobnimi amplitudami impulzov, vendar z neznatnimi razlikami v obliki in časovnem poteku. Tradicionalne metode težko razlikujejo te subtilne značilnosti, kar vodi do napačne klasifikacije in zmanjšane natančnosti detekcije. Da bi to rešili, predlagamo pristop, ki temelji na globoki nevronski mreži (DNN) v kombinaciji s tehnikami razlikovanja oblike impulza (PSD), da bi dosegli visoko natančno razlikovanje delcev v mešanih n/γ poljih. Naša metoda izkorišča sposobnost DNN za učenje kompleksnih vzorcev in učinkovito razvršča nevtronske in gama impulze. Usposobljeni model DNN je bil ocenjen v primerjavi s tradicionalnimi algoritmi razlikovanja, vključno z metodo primerjave naboja, analizo časa vzpona, analizo gradienta v frekvenčnem prostoru in združevanjem K-povprečij. Kvantitativni rezultati kažejo 99-odstotno natančnost razlikovanja, kar znatno presega How to cite: M. Jiang et al., “Enhanced Neutron-Gamma Discrimination Using Deep Neural Networks for Precision Nuclear Medicine ", Inf. Midem-J. Microelectron. Electron. Compon. Mater., Vol. 55, No. 4(2025), pp. 255–262 255 M. Jiang et al.; Informacije Midem, Vol. 55, No. 4(2025), 255 – 262 zmogljivosti konvencionalnih tehnik. Poleg tega predlagana metoda DNN ne le izboljša zanesljivost razlikovanja v mešanih sevalnih poljih, ampak tudi skrajša čas obdelave v primerjavi z obstoječimi metodami, zaradi česar je primerna za uporabo v realnem času v medicinskih slikah in industrijskem zaznavanju nevtronov. Ključne besede: neutroni in gama žarki, globoka nevronska mreža, razlikovanje oblike impulza * Corresponding Author’s e-mail: xiuwan.wang@my.cityu.edu.hk; zyuanzhu@swu.edu.cn 1 Introduction from the time domain or frequency domain, relying on a particular signal feature to identify and classify the Neutron detection technology plays a crucial role in discriminated information, which requires a long calcu- various applications within nuclear medicine, includ- lation time for the n/γ discrimination results. ing material analysis for medical isotopes [1], ensuring safety in radiopharmaceutical handling [2-3], moni- Artificial intelligence (AI) techniques have developed toring environmental radioactivity that could impact rapidly in recent years, and there has been a growing healthcare facilities [4], and supporting advanced di- trend to use deep learning (DL) methods to analyse agnostic imaging in aerospace medicine [5]. Addition- data. Deep learning generally refers to neural networks ally, it is vital for the nuclear industry to ensure safe consisting of interconnected artificial neurons, which and effective medical radioisotope production [6-11]. combine low-level features to create abstract high- However, the challenge arises from the omnipresence level attributes. It can be used to identify distributed of γ-rays in the vicinity of neutron sources. Scintillator features in data, which plays a key role in modeling detectors, which are widely relied upon for neutron de- artificial intelligence. The advent of this technology tection, are also sensitive to γ-rays [12]. This sensitivity offers a new perspective and an innovative approach can compromise the accuracy of neutron detection, to the rapid prediction of complex tasks. DL is not only underscoring the need to enhance detector perfor- applicable to computer science fields such as natural mance through the development of effective discrimi- language processing [19] and computer vision [20] nation techniques. but also be applied to interdisciplinary studies such as the mechanical design of materials [21], biosensors In 1958, Owen [13] first discovered the property of dif- [22], marine research [23], redox flow batteries [24], ferent decay times of blinking light produced by n/γ and nanogenerator performance prediction [25]. The interacting with scintillator materials, then proposed combination of AI algorithms and PSD techniques has a pulse shape discrimination (PSD) technique and suc- evolved significantly, transitioning from early feature- cessfully discriminated n/γ mixed signals using the augmented approaches to hybrid systems that merge PSD technique based on analogue circuits. As a result, PSD features with neural networks, and finally to mod- a large number of researchers have combined digital ern end-to-end deep learning models capable of raw techniques with earlier discrimination methods that pulse classification without manual feature extraction. required the construction of analogue circuits, while The combination of AI algorithms and PSD techniques other digital-based n/γ discrimination algorithms has also achieved good results in the field of n/γ sig- have also been proposed. For example, Jastaniah et al. nal discrimination. In 1998, the first application of AI [14] implemented a rise time algorithm in 2004 based algorithms to n/γ signal discrimination was proposed on digital techniques. In 2007, Flaska [15] achieved a by Cao [26] et al., who used the time-of-flight method charge comparison algorithm and Liu [16] et al. pro- to identify particle species and verify the feasibility of posed a time-domain pulse gradient algorithm [17], the algorithm. Esposito [27] and Ronchi [28] used AI which can reduce the effect of time-domain noise on algorithms to solve the signal stacking problem well the discrimination results of n/γ pulse signals. In 2018, during 2004-2009, respectively. And then, Liu [29] and Huang [18] applied the K-means clustering algorithm Zhou [30] further developed neural network algo- to discriminate n/γ mixed pulse signals to reduce the rithms in the field of n/γ pulse signal discrimination. influence of human factors in the processing. Howev- Despite these advances, earlier AI methods still faced er, these methods face inherent limitations, rise-time challenges such as limited accuracy and high computa- analysis struggles with pulse pileup and electronic tional costs, necessitating further innovation in model noise, charge comparison fails when n/γ pulses exhibit architecture and training efficiency. similar charge distributions, and K-means clustering requires pre-labeled data and performs poorly with This paper uses deep neural network (DNN) algorithms overlapping pulse features. Moreover, the above dis- to address the problems of n/γ signal discrimination. crimination methods can only extract signal features DNNs were specifically chosen for this task due to their 256 M. Jiang et al.; Informacije Midem, Vol. 55, No. 4(2025), 255 – 262 exceptional capability in handling complex pattern photomultiplier tube, high voltage supply unit, and recognition problems, which can discover subtle, non- electronics. The structure of the scintillator neutron de- linear relationships in the temporal and spectral char- tector is shown in Fig. 1. acteristics of n/γ signals that are often imperceptible to conventional analysis techniques. The test samples are 2.1 Data processing compared with the charge comparison algorithm, rise time algorithm, frequency domain gradient analysis We have considered the experiments in reference [34] algorithm, and K-means clustering algorithm, and the with a neutron source of 252Cf and a detector module us- DNN discrimination method can successfully discrimi- ing the plastic scintillator EJ-299-33. The power supply nate n/γ mixed pulse signals. The results show that the unit provides the operating voltage for the photomul- proposed DNN discrimination method not only pro- tiplier, which amplifies the scintillation light produced vides effective discrimination of the mixed radiation by the scintillator under the irradiation of the neutron fields but also improves the discrimination time com- source 252Cf and transforms it into a pulse signal. The pared with other discrimination methods. This dual ad- amplified signal is then transferred to a 12-bit 65 MS/ vantage of high accuracy and computational efficiency PS digital converter, where the ADC converts the ampli- makes the DNN approach particularly suitable for real- fied analog signal into a digital signal. The digital signal time applications in nuclear medicine and industrial is transmitted via an optical bridge to a computer for radiation monitoring, where both precision and speed subsequent processing and analysis. are critical requirements. 2 Materials and methods 2.1 Scintillator detector principle Figure 2: The workflow of the DNN modeling process. Neutrons cannot directly cause ionization or excita- tion of matter, so they cannot be detected directly [31]. As shown in Fig. 2, the DNN model with input, hidden, However, scintillator detectors are sensitive not only to and output layers are proposed to implement neutron neutrons but also to γ-rays, which can be helpful for the and γ-rays discrimination. The layers of the model are detection of n/γ mixed pulse signals [32]. When neu- connected in a fully connected manner, with any neu- trons or γ-rays are irradiated in the scintillator detec- ron in layer i necessarily connected to any neuron in tor, the atoms in the astragalus crystal can be ionized layer i+1 [35]. Each local model is composed of a linear and excited. Weak scintillation photons are generated relationship and an activation function. The input x is when the atoms jump from the excited state back to the used to provide the initial information (including PSD ground state. The photomultiplier tube converts these corresponding to neutrons and gamma rays), which is weak scintillations into photoelectrons after the photo- then propagated to the hidden units in each layer to electrons enter the photomultiplier tube through the produce the output categories y. The data information electro-optical input system. The photoelectrons are flows forward through the network to achieve forward multiplied and all electrons are collected by the anode propagation until a scalar cost function Cost is generat- of the photomultiplier tube to form a pulse signal digi- ed, and the back propagation is achieved when the in- tal (PSD) and then enter the signal processing circuit formation of the cost function flows backward through [33]. The commonly used scintillator neutron detector the network to calculate the gradient. All data samples consists of four parts, including scintillator material, are used for training and evaluation of the model, and the cross-entropy loss error J(θ) is used to evaluate the accuracy of the model with the formula. Cost  min J ( ) (1) N J ( ) 1   N y log yˆ  (1 y ) log(1 yˆ ) (2) n n n n1 n Where θ is the optimal parameters, N is the number of samples, yn is the DNN model output value, and yˆ n Figure 1: Working principal diagram of scintillator de- is the test value. tector. 257 M. Jiang et al.; Informacije Midem, Vol. 55, No. 4(2025), 255 – 262 The cost function can be decomposed into the sum of 3.2 Comparative analysis of results the cost functions of each sample, and a small batch of samples is drawn uniformly from the training set using the stochastic gradient descent algorithm (SGD). When the training set size M grows and m remains constant, the estimate of the gradient g can be expressed as: 1 m g   ( ) ( ) Cost(x i , y i , ) (3) M i1    g (4) where x(i) is the i-th sample, y(i) is the true label of the i-th sample, and α is the learning rate. Figure 3: The discrimination results of DNN on the The SGD enables the training of deep network models training set. Blue means neutrons and red means gam- on large-scale data. For a fixed-size model, the compu- ma rays. tation of each step of stochastic gradient descent up- date does not depend on the size of the training set, thus effectively reducing the computational cost of the model with good fitting performance. The relevant pa- rameter settings are as follows, the corresponding net- work outputs of neutron and γ-ray events are 1 and 0, the epochs are 3000, the batch size is 256, the optimizer is SGD, the learning rate is 0.000001, the momentum is 0.9, and the early stop is 200. The model environment is a Windows 10 system, 2.3 GHz Intel Core (TM) i7–11800 H GPU, 16.0 GB memory, 3050Ti graphics card, utilizing Python 3.8, Pytorch 1.9.0 + cuda 11.1. 3 Results Figure 4: The discrimination results of DNN on the test set. Blue means neutron and red means gamma rays. 3.1 Discrimination results based on DNN The discrimination results using the charge compari- In this research, the data of neutron pulse signal and son algorithm (Fig. 5a), the rise time algorithm (Fig. 5b), γ-rays pulse signal from 252Cf scintillation detectors the frequency domain gradient analysis algorithm (Fig. are extracted using Python tools, and the sampled 5c), and the K-means clustering algorithm (Fig. 5d) are 7291 pulse signals are used to construct the data set, shown in Fig. 5, respectively. The five discrimination which is divided into an 80% training set and a 20% methods are used to discriminate the same 5000 sets test set. The deep neural network algorithm model of n/γ mixed pulse signals and the results showed that is constructed to achieve the classification process of they are all successful in discriminating the n/γ mixed neutron and γ-rays particle identification, as shown in pulse signals, as shown in Table 1. In terms of discrimi- Fig. 3 and Fig. 4. The training samples of 5832 pulse sig- nation accuracy, the discrimination accuracy rate (DAR) nals are fed into the DNN model, and the discrimina- is improved compared to other discrimination algo- tion results of the training set are shown in Fig. 3. The rithms, the DNN achieves the highest accuracy (DAR_N: neutron and gamma samples in the training set are 99.60%, DAR_G: 99.93%), outperforming charge com- well discriminated out. Fig. 4 shows the discrimination parison (99.20%, 99.86%) due to its ability to automati- results of 1459 test samples of n/γ mixed pulse signals cally learn subtle pulse-shape features. Rise-time analy- into the trained DNN network. Since the pulse signals sis shows significantly lower neutron accuracy (89.75%, in both the training and test sets are well discriminated 98.19%) because of overlapping rise times in mixed ra- out, the DNN model can separate the mixed n/γ well. diation fields, while K-means clustering performs worst (75.77%, 95.72%) as its unsupervised approach strug- gles with overlapping pulse distributions. In terms of speed, the DNN is fastest (1.6s), being twice as quick 258 M. Jiang et al.; Informacije Midem, Vol. 55, No. 4(2025), 255 – 262 as traditional methods (3-4s) and four times faster than K-means (6.4s), thanks to GPU processing. Tradi- N N DAR Pre_G Mea_G _G  (1 )100% (6) tional methods like charge comparison and frequency- NMea_G domain gradient analysis are slower due to per-pulse mathematical operations, while K-means suffers from Where NPre_N represents the number of correctly dis- iterative distance calculations. The DNN clearly pro- criminated neutron pulse signals, NMea_N represents the vides the best balance, offering superior accuracy with number of neutron pulse signals tested, NPre_G repre- significantly reduced processing time, making it ideal sents the number of correctly discriminated gamma for real-time applications. Charge comparison remains pulse signals, and NMea_G represents the number of a viable alternative where marginal accuracy loss is ac- gamma pulse signals tested. ceptable or DNN deployment is constrained, whereas K-means should only be considered when labeled In implementing the five discrimination algorithms, training data is unavailable. The results demonstrate it is found that each discrimination method has its that while all methods can discriminate n/γ pulses, the advantages. The charge comparison algorithm is the DNN delivers optimal performance where both preci- simplest in principle, therefore, the easiest of all the sion and speed are critical. discrimination methods to implement. Although the largest difference between the neutron and γ-ray pulse N -N signals is only in the falling edge of the pulse, the ris- DAR Pre_N Mea_N _N =(1- )100% (5) ing time algorithm maximizes the difference between NMea_N the two particle-induced signals by taking into ac- Figure 5: Four discrimination algorithms. (a) Charge comparison integration time scale diagram and charge com- parison algorithm discrimination results. (b) Signal of time integration and rise time algorithm discrimination results. (c) The spectrum graph of the n/γ signal and the discrimination result of the frequency domain gradient analysis algorithm. (d) Two cluster centers are determined by K-means and the after-time integration result of the K-means clustering algorithm. Table 1: Comparison of the results of five n/γ discrimination methods Method Neutron Gamma DAR_N DAR_G Time Charge Comparison 757 4243 99.20% 99.86% 3.4s Rise time 828 4172 89.75% 98.19% 3.5s Frequency Gradient Analysis 742 4258 98.80% 99.79% 3.9s K-means Clustering 933 4067 75.77% 95.72% 6.4s DNN 748 4252 99.60% 99.93% 1.6s 259 M. Jiang et al.; Informacije Midem, Vol. 55, No. 4(2025), 255 – 262 count the rising and falling edges of the entire pulse 6 Conflict of interest statement signal in extracting the eigenvalues. The frequency domain gradient analysis algorithm is more resistant The authors declare that there are no conflict of inter- to interference by extracting features in the frequency ests. domain, so it is not sensitive to changes in the shape of the pulse caused by noise. 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Wakeford, “Pulse shape discrimination algo- rithms, figures of merit, and gamma-rejection for liquid and solid scintillators,” IEEE Transactions 262 Boards of MIDEM Society | Organi društva MIDEM MIDEM Executive Board | Izvršilni odbor MIDEM President of the MIDEM Society | Predsednik društva MIDEM Prof. Dr. Barbara Malič, Jožef Stefan Institute, Ljubljana, Slovenia Honorary president: Prof. Dr. Marko Topič, UL, Faculty of Electrical Engineering, Slovenia Vice-presidents | Podpredsednika Prof. Dr. Janez Krč, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Dr. Iztok Šorli, Mikroiks d.o.o., Ljubljana, Slovenia Secretary | Tajnik Olga Zakrajšek, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia MIDEM Executive Board Members | Člani izvršilnega odbora MIDEM Prof. Dr. Slavko Bernik, Jožef Stefan Institute, Slovenia Assoc. Prof. Dr. Miha Čekada, Jožef Stefan Institute, Ljubljana, Slovenia Prof. DDr. Denis Đonlagić, UM, Faculty of Electrical Engineering and Computer Science, Maribor, Slovenia Prof. Dr. Vera Gradišnik, Tehnički fakultet Sveučilišta u Rijeci, Rijeka, Croatia Mag. Leopold Knez, Iskra TELA, d.d., Ljubljana, Slovenia Mag. Mitja Koprivšek, ETI Elektroelementi, Izlake, Slovenia Asst. Prof. Dr. Gregor Primc, Jožef Stefan Institute, Ljubljana, Slovenia Prof. Dr. Janez Trontelj, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Asst. Prof. Dr. Hana Uršič Nemevšek, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Danilo Vrtačnik, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Supervisory Board | Nadzorni odbor Dr. Drago Resnik, retired, Slovenia Prof. Dr. Franc Smole, retired, Slovenia Prof. Dr. Drago Strle, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Court of honour | Častno razsodišče Darko Belavič, retired, Slovenia Prof. Dr. Danjela Kuščer Hrovatin, Jožef Stefan Institute, Ljubljana Dr. Hana Uršič Nemevšek, Jožef Stefan Institute, Ljubljana, Slovenia Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials ISSN 0352-9045 Publisher / Založnik: MIDEM Society / Društvo MIDEM Society for Microelectronics, Electronic Components and Materials, Ljubljana, Slovenia Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale, Ljubljana, Slovenija www.midem-drustvo.si