issn o: Informal Journal ofMicroelec Electronic Components and M Vol. 48, No. 4(2018), Decembi Revija za mikroelek elektronske sestavne dele in m letnik 48, številka 4(2018), Decembi :tronics; Material s sr2018 troniko, ateriale sr2018 i« «Utrni, ZOISOVO PRIZNANJI 2(7 Pometnh. UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 4-2018 Journalof Microelectronics, Electronic Components and Materials VOLUME 48, NO. 4(168), LJUBLJANA, DECEMBER 2018 | LETNIK 48, NO. 4(168), LJUBLJANA, DECEMBER 2018 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2018. All rights reserved. | Revija izhaja trimesečno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale - Društvo MIDEM. Copyright © 2018. Vse pravice pridržane. Editor in Chief | Glavni in odgovorni urednik Marko Topič, University of Ljubljana (UL), Faculty of Electrical Engineering, Slovenia Editor of Electronic Edition | Urednik elektronske izdaje Kristijan Brecl, UL, Faculty of Electrical Engineering, Slovenia Associate Editors | Odgovorni področni uredniki Vanja Ambrožič, UL, Faculty of Electrical Engineering, Slovenia Arpad Burmen, UL, Faculty of Electrical Engineering, Slovenia Danjela Kuščer Hrovatin, Jožef Stefan Institute, Slovenia Matija Pirc, UL, Faculty of Electrical Engineering, Slovenia Matjaž Vidmar, UL, Faculty of Electrical Engineering, Slovenia Editorial Board | Uredniški odbor Mohamed Akil, ESIEE PARIS, France Giuseppe Buja, University of Padova, Italy Gian-Franco Dalla Betta, University of Trento, Italy Martyn Fice, University College London, United Kingdom Ciprian Iliescu, Institute of Bioengineering and Nanotechnology, A*STAR, Singapore Marc Lethiecq, University of Tours, France Teresa Orlowska-Kowalska, Wroclaw University of Technology, Poland Luca Palmieri, University of Padova, Italy Goran Stojanovic, University of Novi Sad, Serbia International Advisory Board | Časopisni svet Janez Trontelj, UL, Faculty of Electrical Engineering, Slovenia - Chairman Cor Claeys, IMEC, Leuven, Belgium Denis Donlagic, University of Maribor, Faculty of Elec. Eng. and Computer Science, Slovenia Zvonko Fazarinc, CIS, Stanford University, Stanford, USA Leszek J. Golonka, Technical University Wroclaw, Wroclaw, Poland Jean-Marie Haussonne, EIC-LUSAC, Octeville, France Barbara Malič, Jožef Stefan Institute, Slovenia Miran Mozetič, Jožef Stefan Institute, Slovenia Stane Pejovnik, UL, Faculty of Chemistry and Chemical Technology, Slovenia Giorgio Pignatel, University of Perugia, Italy Giovanni Soncini, University of Trento, Trento, Italy Iztok Šorli, MIKROIKS d.o.o., Ljubljana, Slovenia Hong Wang, Xi'an Jiaotong University, China Headquarters | Naslov uredništva Uredništvo Informacije MIDEM MIDEM pri MIKROIKS Stegne 11, 1521 Ljubljana, Slovenia T. +386 (0)1 513 37 68 F. + 386 (0)1 513 37 71 E. info@midem-drustvo.si www.midem-drustvo.si Annual subscription rate is 160 EUR, separate issue is 40 EUR. MIDEM members and Society sponsors receive current issues for free. Scientific Council for Technical Sciences of Slovenian Research Agency has recognized Informacije MIDEM as scientific Journal for microelectronics, electronic components and materials. Publishing of the Journal is cofi-nanced by Slovenian Research Agency and by Society sponsors. Scientific and professional papers published in the journal are indexed and abstracted in COBISS and INSPEC databases. The Journal is indexed by ISI® for Sci Search®, Research Alert® and Material Science Citation Index™. | Letna naročnina je 160 EUR, cena posamezne številke pa 40 EUR. Člani in sponzorji MIDEM prejemajo posamezne številke brezplačno. Znanstveni svet za tehnične vede je podal pozitivno mnenje o reviji kot znanstveno-strokovni reviji za mikroelektroniko, elektronske sestavne dele in materiale. Izdajo revije sofinancirajo ARRS in sponzorji društva. Znanstveno-strokovne prispevke objavljene v Informacijah MIDEM zajemamo v podatkovne baze COBISS in INSPEC. Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madic Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana Informacije IMIDEM Journal of Microelectronics, Electronic Components and Materials vol. 48, No. 4(2018) Content | Vsebina Original scientific papers Izvirni znanstveni članki Pousia S., Manjith R.: Proficient Static RAM design using Sleepy Keeper Leakage Control Transistor & PT-Decoder for handheld application 197 Pousia S., Manjith R.: Načrtovanje učinkovitega statičenega RAMa z uporabo tranzistorja za kontrolo uhajalne moči z ohranjanjem stanja in PT dekoderja za ročne aplikacije D. D. N. Ponkumar, P. Jagatheeswari, T. S. A. Samuel: Implementation of VIP for Bus Interface Logic of 32-bit Processor Using System Verilog 205 D. D. N. Ponkumar, P. Jagatheeswari, T. S. A. Samuel: Uporaba VIP za vmesnik logičnega vodila 32-bitnega procesorja s uporabo System Verilog Z. Zhu, K. Xia, Z. Xu, H. Zhang, H. Lou: Temporary Bonding Using Paper Inserted PPC Layer 213 Z. Zhu, K. Xia, Z. Xu, H. Zhang, H. Lou: Začasno bondiranje z uporabo s papirjem vnesene PPC plasti M. Mojibi, M. Radmehr: Reliability Evaluation of Buck Converter Based on Thermal Analysis 217 M. Mojibi, M. Radmehr: Ocena zanesljivosti buck pretvornika na osnovi termične analize V. Furlan, S. Glinsek, T. Pecnik, M. Vidmar, B. Kmet, B. Malic: Elliptically Polarized Frequency Agile Antenna on Ferroelectric Substrate 229 V. Furlan, S. Glinšek, T. Pečnik, M. Vidmar, B. Kmet, B. Malič: Eliptično polarizirana in frekvenčno nastavljiva antena na feroelektrični podlagi N. Lokar, V. Kononenko, D. Drobne, D. Vrtacnik: Electrochemical Acetylcholinesterase Biosensor for Detection of Cholinesterase Inhibitors: Study with Eserine 235 N. Lokar, V. Kononenko, D. Drobne, D. Vrtačnik: Elektrokemijski acetilholinesterazni biosenzor za detekcijo holinesteraznih inhibitorjev: raziskava z eserinom M. Kikelj, B. Lipovsek, F. Smole: Orthodox Theory Monte-Carlo Simulation of Single-Electron Logic Circuits 241 M. Kikelj, B. Lipovšek, F. Smole: Monte-Carlo simulacija enoelektronskih logičnih vezij na podlagi Ortodoksne teorije M. Gradisek, D. Strle: Digitally Adjustable Differential Gain Stage 249 M. Gradišek, D. Strle: Digitalno nastavljiva diferencialna ojačevalna stopnja S. Pevec, B. Lenardic, D. Donlagic Multiparameter Miniature Fiber-optic Sensor: Design and Signal Interrogation 255 S. Pevec, B. Lenardič, D. Donlagic: Večparametrični miniaturni optični vlakenski senzorji: načrtovanje in signalno razločevanje Slovene Science Awards 2018 263 Najvišja priznanja v slovenski znanosti v letu 2018 Front page: Dr. Tadej Rojac, Zois Certificate of Recognition (Photo: M. Topic) Naslovnica: doc. dr. Tadej Rojac, prejemnik Zoisovega priznanja (Foto: M. Topič) 193 Editorial | Uvodnik Dear reader, Year 2018 almost ran out and this editorial brings up some statistics about manuscripts submitted. In 2018 we have received more than 180 manuscripts, out of which only 23 have been accepted for publication and more than 140 manuscript were rejected. The number of manuscripts that are out of our journal's scope has been drastically reduced. In 2018 we published 26 original scientific papers. The success rate remains below 15% in 2018 and reflects determination for quality that will path long-term quality growth. Citation metrics (JCR IF-2017=0.476, SNIP-2017=0.265 and CiteScore-2017=0,61) is one of the performance indicators. I sincerely thank all reviewers and Editorial Board Members for their valuable contribution to the journal quality growth. In light of quality growth, we introduce a digital object identifier (DOI) to all papers in this issue for the first time. We sincerely hope that DOI will help us in wider dissemination and path to the open access publishing, which is planned already for the next volume, starting with the first issue of the volume 49. December is time for recognition and celebration, not only in Slovenian science arena but also elsewhere. We are happy to congratulate Dr. Tadej ROJAC to be honoured with the "Zoisovo priznanje" - the Zois Certificate of Recognition as the second highest Award of the Republic of Slovenia for Scientific and Research Achievements - that he received for important achievements in research of the synthesis and characterization of high-temperature piezoelectric ceramics based on bismuth ferrite. Let the festive days bring joy and peace in each home, office or research laboratory. It is the time to look ahead and make plans for the coming year. This brings me to editorial wishes for 2018. As a part of your success we look forward to receiving your future manuscript(s) on our submission page (http://ojs.midem-drustvo.si/). Merry Christmas and a Happy, Healthy and Prosperous New Year! Prof. Marko Topic Editor-in-Chief P.S. We look forward to receiving your next manuscript(s) in our on-line submission platform: http://ojs.midem-drustvo.si/index.php/InfMIDEM 194 Original scientific paper https://doi.org/10.33180/InfMIDEM2018.401 Informacije Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 4(2018), 197 - 203 Proficient Static RAM design using Sleepy Keeper Leakage Control Transistor & PT-Decoder for Pousia. S.1, Manjith. R.2 1PG scholar, Dr. Sivanthi Aditanar College of Engineering, Tiruchendur, Tamil Nadu, India 2Associate Professor, Dr.Sivanthi Aditanar College of Engineering, Tiruchendur, Tamil Nadu, India Abstract: Due to their large storage capacity and small access time static random access memory (SRAM) has become a vital part in numerous VLSI chips. Low power adequate memory configuration is a standout among the most challenging issues in SRAM design. As the technology node scaling down, leakage power utilization has turned into a noteworthy issue. In this paper a novel power gating technique, namely sleepy keeper leakage control transistor technique (SK-LCT) is proposed for a handheld gadget application. The SRAM architecture has two primary components, specifically SRAM cell and sense amplifier. The proposed SK-LCT technique is applied in both SRAM cell and sense amplifier for a new low power high speed SRAM architecture design. The outline of SRAM architecture utilizing pass transistor decoder (PT-Decoder) gives better outcomes in term of power. Simulation is done using Tanner EDA tool in 180nm technology and the results demonstrate a noteworthy change in leakage power utilization and speed. Keywords: SRAM; SK-LCT Technique; sense amplifier; Tanner EDA; Leakage Power Načrtovanje učinkovitega statičenega RAMa z uporabo tranzistorja za kontrolo uhajalne moči Izvleček: Zaradi visoke pomnilne kapacitete in kratkih dostopnih časov so statični pomnilniki z naključnim dostopom (SRAM) postali bistveni del VLSI čipov. Nizka moč zadostne konfiguracije pomnilnika je ena od najzahtevnejših problemov v zasnovi SRAM. V članku je predstavljena nova tehnika uporabe tranzistorja za nadzor uhajanja moči z ohranjanjem stanja (SK-LCT) za uporabo v ročnih aplikacijah. Arhitektura SRAM ima dve primarni komponenti, SRAM calico in tipalni ojačevalnik. Predlagana tehnika SK-LCT se uporablja tako v celici SRAM kakor v tipalnem ojačevalniku za novo zasnovano arhitekturo SRAM z nizko močjo. Okvir arhitekture SRAM, ki uporablja prehodni tranzistorski dekoder (PT-dekoder), ki daje boljše rezultate v smislu moči. Simulacija se izvaja z orodjem Tanner EDA v tehnologiji 180 nm, rezultati pa kažejo na opazno spremembo v kontroli uhajanja in hitrosti. Ključne besede: SRAM; SK-LCT tehnika; tipalni ojačevalnik; Tanner EDA; uhajalna moč * Corresponding Author's e-mail: manjith@drsacoe.com Very Large Scale Integration (VLSI) is the way towards than the current advancement [2]. At the same time, incorporating a million of transistors inside a single mi- increment of power dissipation has ended up the macrochip. Quick advancement in the VLSI design process jor impediment against the further advancement of VLSI brings about the expansion of densities of the integrat- circuits. In a computing framework, power utilization ed circuit [1]. With the progression of innovation that because of the memory gets to frequently constitute a are occurring in the universe, the demand for large stor- prevailing part of the aggregate power utilization [3]. 195 © MIDEM Society Pousia. S.et al; Informacije Midem, Vol. 48, No. 4(2018), 197 - 203 Static Random Access Memory (SRAM) is a critical part in the vast majority of the VLSI chips; it regularly expends a prevailing part of power in each chip. By decreasing the power of SRAM, the overall power of chips can be diminished. Because of the quadratic connection amongst power and supply voltage of transistors [4]; one of the most compelling strategies to diminish the power utilization is by lessening the supply voltage. The strong demand of SRAM memory in handheld gadgets, system on-chip (SoC) & high performance VLSI circuits, the reduction of power utilization is imperative. Owing to high bit-line swing requirement, the leakage power utilization of memory circuit is high. Sleep technique, stack technique, sleepy stack technique, sleepy keeper technique, lector technique, foot switch technique & double switch technique are probably the most regularly utilized power gating for leakage power reduction. To overcome the drawback of the above existing method, a novel strategy is recommended. In computerized frameworks, instructions are conveyed by means of binary levels. The decoder is broadly utilized in memory framework to change over n-bit twofold input code into m yield lines. The address input code from the central processor is utilized to trigger the memory storage location assigned by address code [5]. Low power consumption is essentially crucial parameter, so pass transistor based decoders have been used due to the low leakage and dynamic switching currents. Among the overall power consumption of memory circuit, static power dissipation plays an predominant role. (2) A novel power gating technique, namely SK-LCT technique (Sleepy keeper Leakage Control Transistor Technique) is proposed in order to reduce the static power dissipation. SK-LCT technique is the combination of sleepy keeper and LECTOR technique which is employed in the design of SRAM cell and sense amplifier. The SRAM architecture using a SK-LCT method and pass transistor decoder (PT-decoder) has several advantages over the ordinary SRAM's design with high speed and low power consumption. (1) 2 Literature survey During standby mode, a large portion of the power is squandered in SRAM design; since leakage power maneuvers an overwhelming part in SRAM power utilization. SRAM cell, sense amplifier & decoder are the indispensable portion of memory design. Improper design of these elements contributes to influence the robustness of the memory device. Both memory access time and memory power dissipation are emphatically affected by a sense amplifier circuitry. The power gating technique such as sleep technique, stack technique, sleepy stack technique, sleepy keeper technique & lector technique are utilized to shrink the static power of the SRAM cell. In order to diminish leakage power & delay of sense amplifier; latch-type sense amplifier is designed using a foot switch technique & double switch Technique. In sleep technique, "PMOS-S" sleep transistor is embedded between VDD & pull up network and "NMOS-S BAR" sleep transistor is embedded between the pull down network & ground. The wake up time of the sleep method has a considerable impact on the competence of the circuit [6]. Stack technique is state maintenance technique with the detriment of increased delay and area [7]. The divided transistor of sleepy stack technique increases the delay drastically & also limits the convenience of this technique [8]. In Sleepy Keeper Technique parallel connected PMOS and NMOS transistor is embedded between pull up network & VDD and pull down network & ground. Lector technique has two leakage control transistors (LCT1 &LCT2) which are inserted between the pull up & pull down network. It has a very low leakage power which results in a delay penalty [9]. The data retention issue occurs in the circuit, which can be minimized by placing sleep transistor [10]. The footer switch voltage latch sense amplifier (FS-VLSA) senses the voltage difference between the bit line voltage & bit line bar voltage and amplifies it to rail yield voltages. The footer switch current latch sense amplifier (FS-CLSA) senses the current difference produced by AVBL and amplifies it. By introducing an extra head switch (i.e. Double Switch PMOS Access & Double Switch NMOS Access) the invalid current paths in FS-VLSA can be expelled which introducing a complementary sense enable signal. Double switch transmission access-voltage latch sense amplifier (DSTA-VLSA) is used to remove the sensing dead zone of the memory [11]. Based on the specific combination of input levels, the decoder is initiated. The most commonly utilized decoders in the design of SRAM architecture are AND decoder, NOR decoder, pseudo NMOS decoder. The speed of the AND decoder is more proficient than other decoders with the disadvantage of high power consumption. The design of decoder using NOR gate prompts low power consumption with increased time lag. In pseudo-NMOS decoder static power dissipation dominates the circuit. There is an indigence of a novel power gating technique & the decoder circuitry to overcome the disadvantages of the above issue in SRAM architecture. By 196 Pousia. S.et al; Informacije Midem, Vol. 48, No. 4(2018), 197 - 203 appropriate outline of SRAM cell, sense amplifier & decoder; the general execution of memory design can be advanced. 3 SK-LCT technique & PT decoder SRAM architecture comprises of SRAM cell, sense amplifier, préchargé circuit, row/ column decoder and write driver circuit. A novel sleepy keeper leakage control transistor technique (SK-LCT Technique) is proposed in order to design SRAM cell and sense amplifier circuitry. The decoder using pass transistor gives better outcomes in terms of static power. The SRAM architecture for handheld gadget application is designed using the SK-LCT method and pass transistor decoder (PT-decoder) has a few favorable circumstances over the conventional SRAM's outline with high speed and low power consumption. 3.1 Sleepy Keeper Leakage Control Transistor Technique (SK-LCT Technique) To overcome the problem in SRAM architecture, a novel SK-LCT Technique is applied. The delay & power of the SRAM architecture can be further scaled down and the data retention can be preserved using this novel technique. (3) Figurel: SK-LCT Technique Fig.1 illustrates the sleepy keeper leakage control transistor technique (SK-LCT Technique). Here, leakage control transistor (PMOS-LCT & NMOS-LCT) is placed in between pull up & pull down network. Both PMOS and NMOS are tied up parallel to preserve the stable retention in standby mode. The PMOS-LCT gate is associated with the drain of pull down network and NMOS -LCT gate is associated with the drain of pull up network. Hither, the sleep PMOS (S) transistor is put beneath VDD and sleep NMOS (S BAR) transistor is set over the ground. In sleep mode, parallel connected NMOS is the only terminal between pull up network & VDD and parallel connected PMOS is the only terminal between pull down network & ground. Sleep transistors cutoffs the power rails when the circuit is not in use while the state of circuit is saved by keeper transistors. This leads to the reduction of static power dissipation of memory circuit. The SRAM cell and sense amplifier are the two main fundamental components of SRAM Architecture; by outlining SRAM cell and sense amplifier using sleepy keeper-leakage control transistor (SK-LCT) technique low power high speed memory architecture can be obtained. 3.2 Pass Transistor Decoder (PT-Decoder) Pass transistor decoder frequently requires less power consumption, runs faster and utilizes fewer transistors than a similar function implemented in complementary CMOS logic. The leakage power dissipation of PT-decoder is completely arrested. Fig. 2 demonstrates the pass transistor decoder. Figure 2: PT-Decoder In memory design, the decoder is used to translate the given address and enable the particular row & column of the memory cluster. Row and column pass decoder is utilized to enable word line and write enable of a SRAM array. Based on the address line, specific memory cell is chosen and the data is read and written in the memory array. 4 Proficient static ram architecture The low power and high speed SRAM architecture is outlined using sleepy keeper leakage control transistor (SK-LCT Technique) & pass transistor decoder. Fig. 3 illustrates the block diagram of SRAM architecture using the SK-LCT Technique & PT decoder. Initially, precharge 197 Pousia. S.et al; Informacije Midem, Vol. 48, No. 4(2018), 197 - 203 both the bit lines (BL & BLB) by using a precharge circuit. The storage location inside the memory devices are selected by the pass transistor decoder. By enabling the word line (WL) of the SRAM cell using PT-decoder, the data either '0' or '1' is stored. If data '1' is written in SRAM cell, BLB automatically discharges to '0' & BL remains high and vice-versa. Sense amplifier boosts the data in SRAM cell and acts as a read part circuitry. No change in the memory cell takes place during hold operation. Figure 3: SRAM Architecture Table 1 demonstrates the read and write operation of SRAM architecture. When word line (WL) and write enable circuitry (WE) is enabled, previous data is modified and new data is written in the memory. When either word Line (WL) or write enable circuitry (WE) is disabled, the previous data is hold in the memory. No change in the memory takes place during hold operation. Table 1: Read and Write operation of SRAM WRITE OPERATION READ OPERATION WRITE '1' Q=0, Q-bar=1 Word Line=1 Bit bar=0 Bit =1 READ '1' Precharge both the bit lines Word line=1 Bit bar=0 (discharges to 0) Bit=1 WRITE '0' Q=1, Q-bar=0 Word Line=1 Bit bar=1 Bit =0 READ '0' Precharge both the bit lines Word line=1 Bit bar=1 Bit =0 (discharges to 0) 4.1 Design of SRAM cell using the SK-LCT Technique SRAM cell is designed using the SK-LCT Technique to reduce the leakage power dissipation of memory. Fig. 4 illustrates SRAM cell the using the SK-LCT Technique. When word line (WL) is asserted high, access transistors are turned 'ON' for write operation. This connects the cell to two complementary bit lines columns (BL &BLB) and the data either '1' or '0' is written in the memory cell. When WL=0, SRAM cell is being inaccessible from both bit lines; keeping it in standby mode. This keeps prior stored value in the cell unchanged.(5) Figure 4: SRAM cell using SK-LCT Technique 4.2 Design of Sense Amplifier using the SK-LCT Technique The power and delay of the voltage latch sense amplifier (VLSA) is reduced using SK-LCT Technique. Here, the additional transmission gate is inserted along with bit lines. During read mode, the PMOS sleep transistor(S) is activated to high and the NMOS sleep transistor(S-BAR) is activated to low; thus turning on the transmission gate and switching off the PMOS transistor whereas in standby mode the transmission gate is turned off and PMOS transistor turns on. Fig.5 illustrates voltage latch type sense amplifier using SK-LCT Technique.(6) Figure 5: Sense Amplifier using SK-LCT Technique 198 Pousia. S.et al; Informacije Midem, Vol. 48, No. 4(2018), 197 - 203 4.3 Design of SRAM architecture using the SK-LCT Technique & PT-decoder Fig:6 illustrates 4 bit SRAM architecture using the SK-LCT Technique and PT-decoder for handheld gadget application. Each column has a single precharge circuit in the memory array to precharge both bit lines (BL & BLB) to VDD during read and write operation. The address line of the memory is activated using row/column PT-decoder. SRAM cell using the SK-LCT Technique diminishes the leakage power dissipation of memory. When the word line (WL) is high, NMOS access transistors are turned 'ON' for write operation. This interfaces the cell to two complementary bit lines and the data either '1' or '0' is written in the memory cell. When WL=0, SRAM cell is inaccessible from both bit lines (BL & BLB). The write enable (WE) signal is turned on; when the write operation is intended. Otherwise, the WE signal isolates the bit lines from write drivers. The voltage difference between both the bit lines (BL&BLB) of voltage latch sense amplifier (VLSA) is sensed and amplifies the small voltage signal in the bit lines to conspicuous logic levels. Figure 6: 16 bit SRAM architecture using SK-LCT Technique & PT-decoder 5 Results & discussion The low power, high speed SRAM architecture is outlined using sleepy keeper leakage control transistor (SK-LCT Technique) & PT-decoder. The entire work is conveyed using Tanner EDA 180nm technology. The simulation result indicates the examination of various parameters like power consumption, leakage power and delay. 5.1 SRAM cell using the SK-LCT Technique SRAM cell is designed using the SK-LCT technique to diminish the leakage power and improve the speed of the memory. If WL=1 and bit lines BL=1 (remains high, i.e. '1') & BLB=0 (remains low, i.e. '0'), data '1' is written in the SRAM cell. If WL=1 & bit lines BLB=1(remains high, i.e. '1') & BL=0 (remains low, i.e. '0'), data '0' is written in the SRAM cell. Fig.7 illustrates the simulation waveform of SRAM cell using the SK-LCT Technique Figure 7: Simulation waveform for SRAM cell using SK-LCT Technique Table 2 demonstrates the correlation of SRAM cell with power gating technique and without power gating technique. By utilizing the existing technique the static power and delay of the SRAM cell can be upgraded. A new power gating technique, namely SK-LCT Technique is proposed which saves 57.53% of static power (7) and 44.70% of delay compared to SRAM cell without power gating. Table 2: Performance comparison of the SRAM cell SRAM CELL POWER DELAY WITHOUT POWER GATING 106.7 nW 1.0934ns WITH POWER GATING Sleep Technique 45.83 nW 0.7924ns Stack Technique 95.86nW 0.9556ns Sleepy stack Technique 68.58nW 1.0019ns Sleepy keeper Technique 89.18nW 1.0575ns LECTOR Technique 57.04nW 0.7069ns SK-LCT Technique 45.33nW 0.6041ns 5.2 Sense amplifier using the SK-LCT Technique The voltage difference between both the bit lines (i.e. BL & BLB complement to each other) of the voltage latch sense amplifier (VLSA) is sensed and amplifies the small voltage signal in the bit lines to conspicuous logic levels. The data in memory cluster are greatly diminished & unstable, which can be boosted by using the amplifier circuitry. The simulation waveform for voltage latch sense amplifier using the SK-LCT Technique is illustrated in Fig.8 199 Pousia. S.et al; Informacije Midem, Vol. 48, No. 4(2018), 197 - 203 iirm^jm- Figure 8: Simulation waveform for sense amplifier using the SK-LCT Technique The Table 3 demonstrates the correlation of sense amplifier with power gating technique and without power gating technique. By using the existing technique the power and delay of the sense amplifier can be reduced. A novel technique, namely SK-LCT Technique is proposed which saves 93.65% of static power (7) and 95.26% of delay contrasted to a differential sense amplifier. Table 3: Performance comparison of the Sense amplifier SENSE AMPLIFIER POWER DELAY WITHOUT POWER GATING Differential Sense Amplifier 0.9034|W 4.2953ns WITH POWER GATING Footer Switch-VLSA 0.1556|W 0.25325ns Footer Switch-CLSA 0.8592|W 0.25328ns DSPA -VLSA 0.1708|W 0.25325ns DSNA -VLSA 0.6003|W 0.25325ns DSTA -VLSA 0.1401|W 0.23605ns SK-LCT Technique(VLSA) 0.0573|W 0.20328ns 5.3 PT-decoder Based on the address line, particular memory cell is chosen and the data is read and written in the memory cluster. In memory design, the decoder is used to decode the given address and enable the particular row or column of the memory array. Row and column decoder is used to enable word line (WL) and write enable (WE). The speed of the PT-decoder is more proficient than other decoders with the advantage of low power consumption. The simulation waveform of pass transistor decoder is illustrated in Fig. 9. Figure 9: Simulation waveform for PT-decoder Table 4 demonstrates the comparison of 2:4 decoder. The PT-decoder is more efficient both in power consumption & speed compared to other decoder. Table 4: Performance comparison of Decoder DECODER (2:4) POWER DELAY AND Decoder 0.95229 mW 8.5113ps NOR Decoder 0.23732 mW 29.990ns Pseudo NMOS Decoder 11.1572 mW 25.206ps Pass Transistor Decoder (PT-decoder) 8.33171 nW 1.9717ns 5.4 SRAM architecture using SK-LCT technique & PT-decoder Figure 10: Simulation waveform for SRAM architecture 4 bit, 16 bit & 64 bit SRAM architectures are designed using the proposed SK-LCT technique & PT-decoder provides considerable reduction in leakage power and delay. Fig.10 illustrates the simulation waveform of SRAM architecture using write and read mode. By enabling the PT-decoder, data is written in any one of the memory cell (SRAM cell) and remaining SRAM cell is in hold mode (shut down mode). (4) The data is read by sense amplifier circuitry. 200 Pousia. S.et al; Informacije Midem, Vol. 48, No. 4(2018), 197 - 203 Table S: Performance comparison of SRAM architecture SRAM architecture Without SK-LCT Technique & PT-Decoder With SK-LCT Technique & PT-Decoder POWER DELAY POWER DELAY 4bit 37.422|W 25.458ns 9.7465|W 11.794ns 16 bit 53.526|W 46.736ns 13.615|W 22.571ns 64 bit 94.63|W 92.219ns 29.607|W 47.383ns Table 5 demonstrates the performance comparison of 4 bit, 16 bit & 64 bit SRAM architecture using sleepy keeper leakage control transistor & PT decoder. The power & delay of memory architecture are limited using this novel technique. About, 68.71% of static power (7) & 44.83% of delay is reduced, which is more attractive than conventional SRAM architecture design. 6 Conclusion SRAM cell design using the novel SK-LCT technique saves 57.53% of power and 44.70% of delay. Similarly, the sense amplifier design using the novel SK-LCT technique saves 93.65% of power and 95.26% of delay compared to conventional method. SRAM architecture using PT-Decoder is effective compared to other decoders. 4 bit, 8 bit & 64 bit memory architecture save 68.71% of power & 44.83% of delay and are intended for low power application such as handheld gadget. Therefore, from the simulation results it is observed that low power, high speed SRAM architecture for low power application is obtained using SK-LCT technique & PT-decoder. 7 References 1. Andrea Calimera, Alberto Macii, Enrico Macii & Massimo Poncino (2012), "Design Techniques and Architectures for Low-Leakage SRAMs" IEEE Transactions on Circuits and Systems, Vol. 59, No. 9, Sep 2012, pp.1992-2007 2. Yeap G. K. et al (1998), "Practical Low Power Digital VLSI Design, Kluwer Academic Publishers', Norwell, MA, ISBN: 0792380096, pp-233. 3. F. Catthoor, S. Wuytack, E. DeGreef (1998), "Custom Memory Management Methodology Exploration of Memory Organization for Embedded Multimedia System Design", Kluer Acadamic Publishers, Boston. 4. J. M. Rabaey, A. P. Chandrakasan (2003), "Digital Integrated Circuits: A Design Perspective", Upper Saddle River, NJ, USA: Prentice-Hall. 5. A. Anand Kumar, "Fundamentals of Digital Circuits" Second Edition, Prentice Hall of India, pp. 337-340, 2006. 6. Hina Malviya and Sudha Nayar (2013), "A new Approach for Leakage Power Reduction Techniques in Deep Submicron Technologies in CMOS circuit for VLSI Application'; IEEE Int. Solid State Circuits Conf. (ISSCC) Dig. Tech, Vol.3 Mar 2013, pp. 11-16. 7. Anu Tonk and Shilpa Goyal (2015), "A Literature Review on Leakage and Power Reduction Techniques in CMOS VLSI Design", International Journal of Advanced Research in Computer and Communication Engineering, Vol.3, Issue.2, pp.554-558. 8. J. Park (2014), "Sleepy Stack: a New Approach to Low Power VLSI and Memory", Ph.D. Dissertation, School of Electrical and Computer Engineering, Georgia Institute of Technology, May 2014. 9. Narender Hanchate (2011), "LECTOR: A Technique for Leakage Reduction in CMOS Circuits", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.12, No. 2, Feb 2011, pp.198205 10. M. Geetha Priya, Dr. K. Baskaran and D. Krishnaveni (2012), "Leakage Power Reduction Technique in Deep Submicron Technologies for VLSI Applications", Elsevier-Sciverse Science Direct, Procedia Engineering, Vol. 30, Dec 2012, pp.1163-1170 11. Taehui Na, Seung-Han Woo, Jisu Kimg, Hanwool Jeon, and Seong-Ook Jung(2013), "Comparative Study of Various Latch-Type Sense Amplifiers", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 6, Sep 2013, pp.1-5 Arrived: 25. 04. 2018 Accepted: 11. 09. 2018 201 202 Original scientific paper https://doi.org/10.33180/InfMIDEM2018.402 Informacije IMIDEM Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 4(2018), 205 - 211 Implementation of VIP for bus interface logic of 32-bit processor using System Verilog D. David Neels Ponkumar1, P. Jagatheeswari1, T.S.Arun Samuel2 1,2Dept. of Electronics and Communication Engineering, Dr. Sivanthi Aditanar Engineering, Tiruchendur, Tamil Nadu, India. 2Dept. of Electronics and Communication Engineering, National Engineering College, India Abstract: A verification environment to verify an ARM-based SoC is proposed in this work. This work introduces the design of a Verification Intellectual Property (VIP) of Advanced Microcontroller Bus Architecture (AMBA). AMBA protocols are today the best standards for 32-bit processor because they are well documented and can be used without royalties. The VIP provides Coverage Driven Verification (CDV) which significantly reduces the design verification time. The code coverage verification of the AHB bus master, Icache controller, Dcache controller and APB peripherals such as APB bridge, timer, UART, and ACE is done in this work. The test cases done for the APB peripherals are ACE with the mil_std_protocol, Timers for generation of interrupt and watchdog reset, UART for transmitting and receive messages, and interrupt registers for Reading and Write. The functional verification of AMBA is carried out using the Mentor Graphics Questasim tool with the system Verilog language. Keywords: Verification Intellectual Property; AMBA; Coverage Driven Verification; timer; ACE; UART; system Verilog College of Kovilpatti, Uporaba VIP za vmesnik logičnega vodila 32-bitnega procesorja s uporabo System Verilog Izvleček: V članku je predlagano okolje preverjanja SoC na osnovi ARMa. Struktura uvaja verifikacijo intelektualne lastnine (VIP) na napredni arhitekturi vodila mikrokontrolerja (AMBA). AMB protokoli so danes najbolj standardni protokoli na 32- bitni procesorjih, saj so dobro dokumentirani in brez avtorskih zaščit. VIP uporablja CVD, ki močno zmanjša čas verifikacije. V tem delu je predstavljena verifikacija AHB master vodila, Icache in Dcache kontrolerjev ter APB perifernih enot, kot so časovnik, UART in ACE. Testni primeri za APB periferne enote so ACE z mil_std_protocol, časovniki za generacijo prekinjanj in resetiranja kontrolne enote (watchdog), UART za pošiljanje in sprejemanje sporočil in prekinitveni registri za zapis in branje. Funkcionalno preverjanje je izvedeno s pomočjo orodja Mentor Graphics Questasim v jeziku Verilog. Ključne besede: verifikacija intelektualne lastnine; AMBA; verifikacija; časovnik; ACE; UART; Verilog * Corresponding Author's e-mail: david26571@gmail.com 1 Introduction With the continued progression of chip geometries to ever smaller sizes, designers are finding themselves with a wealth of available gates in which to create their latest designs [1-4]. With design from scratch entirely out of the question, designers now build these systems with off-the-shelf IP blocks that are pre-designed and verified, helping them meet their goals of differentiation, cost control and time to market.VIP blocks are well-tested simulation models of industry-standard buses and protocols that generate and respond to stimulus and check protocol rule adherence. VIP reduces system verification time and improves quality. VIP design of AMBA AXI bus is done in the previous works [5-9][11], But the VIP for Dcache controller, Icache controller and APB peripherals such as APB bridge, timer, UART, and ACE is done for the first time. The implemented VIP finds application in the realization of onboard computers for navigation, guidance, 203 © MIDEM Society D. D. N. Ponkumar.et al; Informacije Midem, Vol. 48, No. 4(2018), 205 - 211 and control processing in-flight applications as well as for general purpose processing applications. The verification environment is managed with Questa Sim Simulator ver.10.0, test bench and SVA in System Verilog HDL and DUT in VHDL. Separate assertion files in system Verilog are bound with the corresponding test benches to validate design specifications. 2 Proposed system design 2.1 AMBA Bus The Advanced Microcontroller Bus Architecture specification defines an on-chip communications standard regarding bus protocols for communication between various system devices and peripherals. AMBA is a registered trademark of ARM Limited and is an open standard, on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip (SoC) [2]. This work provides Coverage Driven Verification (CDV) for the implementation of Verification Intellectual Property (VIP) for the AMBA bus. In this paper, the verification of the APB peripherals such as APB Bridge, timer, UART, and ACE is done. 2.2 AMBA Architecture An AMBA based microcontroller typically consists of a high-performance system backbone bus (AMBA AHB or AMBA ASB), able to sustain the external memory bandwidth, on which the CPU, on-chip memory, and other Direct Memory Access (DMA) devices reside. A typical AMBA Architecture is shown in figure 1[2]. Figure 1: AMBA Architecture 2.3 AHB Master AHB_master generates chip select signals, the external memory address for instruction and data memory. The FSM of AHB_master is shown in figure 2. The FSM works on clk_x2_pos. Wait states are added for external instruction and data memory access. They are selected from the Memory Configuration Register depending on the memory bank accessed. Instr_state: It is selected when instruction access is requested by fetch stage of the pipeline when instruction cache is disabled. Chip select signals and address for external memory access are generated. The instruction read from external memory is sent to the fetch stage of the pipeline. FSM waits in the instr_state till the specified wait states are over and transitions back to idle state. Figure 2: FSM of AHB_master Data_state: It is selected when data memory access is requested by the memory stage of the pipeline when data cache is disabled. Chip select signals for load/store and address for external memory access are generated. For load, the data read from external memory is sent to the memory stage of the pipeline. For the store, the data from the memory stage of the pipeline is sent to the external memory. FSM waits in the data_state till the specified wait states are over and transitions back to idle state. ICache_state: This state is selected if Icache is enabled and a cache miss occurs. FSM2 handling miss in icache_controller.vhd is active here. The chip select signals are generated when fsm2 in icache_controller. vhd is in wait_for_mfc (wait_for_mfc_icache = 1) state. FSM transitions to idle when icache access is complete (icache_access_complete=1, from icache_controller. vhd) DCache_state: This state is selected if Dcache is enabled and a cache miss occurs. FSM2 handling miss in dcache_controller.vhd is active here. The chip select signals are generated when fsm2 in dcache_controller. vhd is in wait_for_mfc (wait_for_mfc_dcache = 1) state. FSM transitions to idle when dcache access is complete (dcache_access_complete=1, from dcache_controller. vhd). APB_sel: If a memory mapped peripheral is selected apb_sel state is encountered. FSM transitions to idle when hready_apb = '1' from apb_bridge.vhd, the external memory address for instruction access, is generat- 204 D. D. N. Ponkumar.et al; Informacije Midem, Vol. 48, No. 4(2018), 205 - 211 ed in instr_state or icache_state. The external memory address for data access is generated in data_state or dcache_state. 2.4 Icache controller The instruction cache controller is used to cache copies of frequently accessed instructions, thus eliminating the program memory access bottleneck. The cache controller receives instruction read request an address from the Fetch stage. Depending on hit/miss the cache controller supplies instruction from the on-chip cache or reads from external program memory via AHB and provides instruction to the pipeline. Till external memory access is complete, the pipeline is stalled. - 32KB size.Can store 8K instructions - Two way set associative - Uses Least Recently Used (LRU) algorithm for block replacement - Block size: 4 words LRU Replacement Algorithm The LRU (Least Recently Used) algorithm is implemented for the two-way associative cache conFigure uration. This algorithm selects a block for replacement based on its usage, thus benefiting from the temporal locality principle. A single bit is added as part of the tag entry in the tag ram. Whenever a tag match is found in a block, the LRU bit of that block is cleared and the LRU bit of the second block in the set is made T.When a block is to be evicted, the tag entry in the set which has its LRU bit set to 1 is selected. 2.5 Dcache controller The data cache controller caches frequently used data items. The data cache implements copy back with write allocate on a write miss. The dirty blocks are written back to external memory only when they need to be evicted. - Size = 32KB - Cache line size = 4words - Uses an LRU replacement algorithm - Copy back policy - Write allocate on a write miss - Two way set associative Hardware Organization: Data cache is identical to the instruction cache, except that each tag ram location has an additional bit called the dirty bit, which indicates whether the cache block had been modified during its cache residency. Thus each tag ram array has 23 bits * 1024 locations. Address Decoding: This is identical to two-way associative instruction cache implementation. The 10-bit ad- dress is used to index the tag ram arrays. The two-word locator bits are appended to the 10-bit set address to address the cache ram arrays. Copy Back Architecture: When there is a store request from the memory stage of the pipeline, the corresponding cache array entry is updated in the cache if it already exists in the cache. If it is a cache miss, the block which includes the address requested by the store operation is brought into the cache from the external memory (write allocate on a write miss) and the required location is updated. This policy is especially beneficial when frequent writes to a memory location (store instruction) occur since there is no need to access external memory once the word is in the cache. This policy uses the memory bandwidth more efficiently compared to the write through policy wherein each store location writes to the external memory. Data Cache Parity Error detection of cache tags and data is implemented using two parity bits per tag and 4-byte data sub-block. The tag parity is generated from the tag value, LRU, dirty and the valid bits. The data parity is derived from the sub-block data. The parity bits are written simultaneously with the associated tag or sub-block and checked on each access. The two parity bits corresponding to the parity of odd and even data (tag) bits. 2.6 APR Bridge APB bridge acts as the master for the APB slaves - four ACE, two UART, interrupt registers and four timers. The APB bridge converts the AHB signals from the bus master to corresponding signals in APB. Memory configuration register specifies the no. of wait states for different memory banks and internal RAM. Select signal for selecting a memory mapped register is generated by decoding the address (haddr). Hwrite=1 indicates a register write operation. Hwrite=0 indicates a register read operation. The ACE, UART, timer, interrupt, and processor configuration registers are read or written in a single clock cycle, and hready_apb is asserted. For ace access hready_apb is asserted when already signal is asserted. The Processor Configuration Register is shown in table 1. Table.1: Processor Configuration Register Bit Description 31:13 Unused 12 Interrupt Enable 11 Watchdog enable 10 SECDED enable for Internal RAM 205 D. D. N. Ponkumar.et al; Informacije Midem, Vol. 48, No. 4(2018), 205 - 211 9 SECDED enable for external memory bank 6 8 SECDED enable for external memory bank 5 7 SECDED enable for external memory bank 4 6 SECDED enable for external memory bank 3 5 SECDED enable for external memory bank 2 4 SECDED enable for external memory bank 1 3 SECDED enable for external memory bank 0 2 SECDED enable for Internal Registers 1 Instruction Cache Enable 0 Data Cache Enable 2.6 AMBA Advanced Peripheral Bus The APB Bridge is the only bus master on the AMBA APB. Also, the APB Bridge is also a slave on the higherlevel system bus (for example AHB). The bridge unit converts system bus transfers into APB transfers and performs the following functions: - Latches the address and holds it valid throughout the transfer. - Decodes the address and generates a peripheral select, PSELx. Only one select signal can be active during a transfer. - Drives the data onto the APB for a write transfer. 2.7 Code Coverage Analysis Code coverage is a verification technology is used to recognize what code has been executed (figure 3). It has to be checked only after the simulation part. If the design may look like a good design, but the problem is that it can contain unknown bugs. It is hardly possible to know the verification is functionally correct, with cent percent certainty and all of the test benches simulate successfully. The main objective of the code coverage is to find out which code has to forget to exercise in the design. Figure 3: Verification plan Statement coverage: It is also known as Block coverage, where the block is series of statements. If a single statement is executed, all of the statements in the block will be executed. By the verification suite, it measures how much of the total line of code was executed. Figure 4 shows the analysis window for the statement coverage verification. It will be generated after the simulation part. The tick (V) mark indicates that statement code which includes in the DUT are functionally correct. If shows (x) mark, indicate that design is functionally incorrect. It will quickly identify, and we can browse which statements that were not executed. I & H P s vc % H ■ by instance -LUUU lA-yiLl I." l^'JJLmjl— ✓ X E 1367 kkc<-1 : ■;//rs23J_ritl<=l,&l: 1306 I023S :; 1S69 nen_l:>:rr ;<- bl: 1890 datancm_addresj(Jl:OJ<-Ji 'hEOOODOSO; 3torc_data_Bi«ii | J1 ::]<... —1 1395 begin KpoKOge eu> 1396 uartl_cocireg_Hr( J r J :."*:■.■:■ I ; 1699 uartl_dtareg_wr (I t{latj :kI ://|(60*tlck] 1900 -1 : -1 asms wr 1 11 : » ; * t Lcïl J 190L uaïc:_îtrïg_rd(ï: * : '-le.:).' 1903 uartl_di.areg_wrl (J; t i *:■.:; m I ; 1904 DCD_l(Md_reC)CBl1 fc 1 ;sjem_atoc«_req<"l ' 10 ; ♦ ( : *tick); 1905 uart:_Mïrtg_vjil Hi 1.906 uut 1 ■ : r-g Ed {) ; 1906 uartl_dtareg_HTl() 11 *::■!; 1910 uartl_dtartg_wr2(I !t(10*tict): 1912 uartl_coa»g_tfr£(] : // itn 1914 uarLl_dtareg_Hr3;t\ ■:''."¿.'..ft''' s £ ¡Kg 1916 11 ; i : I ; // ... bpa Figure 4: Statement coverage The term "test bench" specifies the stimulus used to initiate a predestined input sequence for the design and to examine its response. The test bench describes the stimulus for the DUT along with its responsibility for the outputs. Here, the test bench is written in SystemVer-ilog with a preset input sequence, and they may be included with external data files. The main task of the test bench is that to verify what input patterns to provide to the design and what is the anticipated throughput of a properly working design. If the test bench was not exactly executed, it should be returned in the design. So, code coverage technology is used for the 100% certainty. It can be classified into four categories. They are Statement coverage, Path coverage (Branch and Toggle coverage), Expression coverage, FSM coverage. FSM: It is usually, coded using a choice in a case statement, the unvisited state identified with uncovered statements. During the verification time, it clearly or correctly identifies the state transitions. Figure 5 shows the bubble diagram for FSM. It indicates that state transitions of decoder sections. Branch and Toggle coverage: A signal is considered to have fully toggled when it has experienced at least one rising edge and at least one falling edge during the simulation. It has been found from the simulated results that the coverage windows, which indicate all the branch and toggles present in the design of AMBA was functionally, correct. 206 D. D. N. Ponkumar.et al; Informacije Midem, Vol. 48, No. 4(2018), 205 - 211 3 Results and discussion Figure 5: FSM coverage Transition Coverage: Transition coverage measures the presence or occurrence of sequences of values. Transition coverage can involve more than two consecutive values of the same coverage point. However, the number of possible bins grows factorially with the number of transition states. Mechanically, transition coverage is identical to coverage points. Specific values are sampled at specific locations at specific points in time with specific bins. Table 2 and 3 show the Assertions for the Timer module and the UART module. Table.2: Assertions for the Timer Module The functional verification of AMBA is carried out using the Mentor Graphics Questasim tool in the code coverage mode with the SystemVerilog language. The Sys-temVerilog simulation is performed to verify the AMBA design by using the VIP. Functional integrity of DUT is checked by using Assertions and cover groups along with necessary test inputs. Figure 6 shows the instance coverage analysis of the AMBA peripherals. The instance analysis is done a state of the peripherals during each instance. It provides the coverage of the individual modules in the AMBA peripherals. This window analyzes coverage statistics for each instance in a flat and non-hierarchical view. The window contains the same code coverage statistics columns as in the Files and Structure windows. Figure 6: Instance coverage Assertion Description Timer_hreset_prdata prdata_timer=32'h00000000 when hreset is asserted Timer_hreset_intr Intr_timer1, Intr_timer2, Intr_timer3, Intr_timer4=0 when hreset is asserted Timer1 underflow When prdata_timer<=32'h00000000 and haddr <= 32'hE0000048 then intr_timer1=0 Timer2 underflow When prdata_timer<=32'h00000000 and haddr <= 32'hE0000054 then intr_timer2=0 Timer3 underflow When prdata_timer<=32'h00000000 and haddr <= 32'hE0000060 then intr_timer3=0 Timer4 underflow When prdata_timer<=32'h00000000 and haddr <= 32'hE000006c then intr_timer4=0 Timer1_disable When prdata_timer<=32'h00000000 and haddr <= 32'hE0000040 then intr_timer1=1 Timer2_disable When prdata_timer<=32'h00000000 and haddr <= 32'hE000004c then intr_timer2=1 Timer3_disable When prdata_timer<=32'h00000000 and haddr <= 32'hE0000058 then intr_timer3=1 Timer4_disable When prdata_timer<=32'h00000000 and haddr <= 32'hE0000064 then intr_timer4=1 Table.3: Assertions for the UART Module Assertion Description Uart1_transmit enable When hreset is asserted and haddr==32'hE0000020 && hwdata==24'h0000A5 then rs232_tx1==1'b1 Uart1_recieve enable When hreset is asserted and haddr==32'hE0000024 && rs232 rx1==1'b1 then hrdata apb==32'h000000A5 Uart2_transmit enable When hreset is asserted and haddr==32'hE0000080 && hwdata==24'h0000A5 then rs232_tx2==1'b1 Uart2_recieve enable When hreset is asserted and haddr==32'hE0000084 && then rs232 rx2==1'b1 then hrdata_apb==32'h000000A5 207 D. D. N. Ponkumar.et al; Informacije Midem, Vol. 48, No. 4(2018), 205 - 211 Figure 7 shows the coverage aggregation analysis of the AMBA peripherals. The coverage aggregation analysis shows, the state of the toggle graph, state graph, and the transition graph during the coverage analysis. Figure 7: Coverage aggregation The Assertion Coverage of the AMBA peripherals is also analyzed using a simulation tool. Assertion/properties provide a clear indication to the VIP module. The assertions can be set as true or false throughout the VIP module. It has been found from the simulated results that, the total of 17 assertions are used for the analysis and each of them has been satisfied throughout the analysis. Hence, the assertion coverage of the proposed VIP module is 100 %. Figure 8 and 9 shows the coverage analysis report of the AMBA peripherals. The coverage analysis depicts the coverage obtained by the proposed VIP module for each of the AMBA peripherals. For the coverage analysis, the VIP considered seven aspects for each module, and they are the statement, Branches, FEC condition trees, FEC expression trees, States, transition, and tog- File Edit Foimat Vpew Help :overa9? ftepoi-T- sumnary Data by file File: 3£up_vd/32_sepl4/bljs Interface/vhdl/ahb_pnaster■vhd Enabled coverage Active MltS Misses % covered stmts 284 284 0 100.0 Branches 209 205 4 96.1 Fee condition Terms O 0 O 100.0 fec Expression Terms 0 0 0 lOO.O States 6 6 0 100.0 Transitions 16 16 0 100,0 Toggle Bins 1464 1464 0 lOO.O î: 32uP_v4/32_sepl4/eus interface/vhdl/apb_br idge. vhd Enabled coverage Active Hits Hisses % covered Stmts 177 177 O 100.0 Branches 189 184 5 97. 3 fec condition Terms 0 0 O lOO.O FEC Expression Terms O 0 O 100.0 States 0 0 0 100.0 Transitions 0 0 0 100,0 Toggle Bins 2752 2330 422 84.6 ï i 32UP_V4/32_sepl4/BliS interface/vhdl/cacbes_ahb_top.vhd Enabled Coverage Active Hits Hisses * Covered Stmts 61 61 O 1QO.O Branches 43 25 O lOO.O FEC Condition Terms O 0 O 100.0 FEC Expression Terms 0 0 0 100.0 states 0 0 0 100r0 Transiti ons 0 0 0 100.0 Toggle Bins 2372 less 484 79.5 ï: 32UP_V4/32_sepl4/BuS Interface/vhdl/decoder_uart, vhd Enabled Coverage Act1ve Hits Misses % Covered stmts 34 34 O 100.0 Branches 7 7 O 100.0 FEC Condition Terms O 0 0 100.0 fec Expression Terms 0 0 0 lOO.O States 0 0 0 100.0 Transltlons 0 0 0 100.0 Toggle Bins 12 12 0 lOO.O 32ltP_V4/32_sepl4/eus interface/vhdl/uart. vhd Enabled Coverage acc1ve HltS Hisses % Covered Stmts 229 217 12 94.7 Branches 221 204 17 92. 3 fec condition Terms 0 0 0 lOO.O FEC Expression Terms 0 0 O 100.0 states 3 3 0 100.0 Transitions 7 7 O lOO.O gle bin. In total, proposed VIP has achieved coverage value of 91.4%, for each AMBA peripherals. Besides, the total 17 assertions provided for the analysis has never failed throughout the process, !: 32UP_v4/32_sepl4/eus ïnterf ace/vhdl/uarc. _apb_iface. vhd Enabled coverage Active Hits Misses % Covered Stmts S S 0 100,0 Branches 6 6 0 100.0 fec condition Terms 0 0 0 100' 0 FEC Expression Terms 0 0 0 100.0 States 0 0 0 100. 0 Transitions 0 0 0 100.0 Toggle Bins 232 166 66 71. 5 !: ace_top,vhd Enabled coverage Active Hits Hisses % Covered stmt s 15S9 1380 179 88. 5 Branches 1237 1073 164 86- 7 FEC Condition Terms 0 0 0 100.0 fec Expression Terms 0 0 0 100. 0 states 5 5 0 100.0 Transitions 14 13 1 92. S Toggle Bins 6269 44 39 1780 71- 6 !: dcache.vhd Enabled coverage Active HitS Misses % covered stmts 347 306 41 88.1 Branches 276 225 51 81, 5 fec Condition Terms 0 0 0 100. 0 fec Expression Terms 0 0 0 100.0 States 9 s 1 SS.S Transitions 20 14 6 70.0 Toggle Bins 2990 2098 892 70.2 î: icache, vhd Enabled coverage Active Hits Misses % Covered Stmts 186 176 10 94.6 Branches 150 135 IS 90. 0 fec condition Terms 0 0 0 100.0 FEC Expression Terms 0 0 0 100.0 States S S 0 100. 0 Transitions 17 14 3 82. :: Toggle S1ns 2348 1818 530 77.4 le: tfmer_new.vhd Enabled coverage Active Hits Misses % coveredi stmts 125 117 8 93.6 Branches 201 193 8 96,0 FEC Condition Terms 0 0 0 100.0 FEC Expression Terms 0 0 0 100,0 states 0 0 0 100.0 Transitions 0 0 0 100.0 Toggle Bins 492 444 48 90.2 NEVE Ft FAILEO: lOO.Ofc ASSERTIONS: 17 Figure 9: Coverage report (Continued) 4 Conclusion Figure 8:Coverage report In this work, verification environment for Caches AHB_ Top, AHB Master, Instruction cache, Data cache the free running counters/timers of APB, ACE Controller, UART and APB Bridge is done. The verification scenario includes Read and Write transfer phases of the APB which are verified with the values of the count and reset. The test cases done for the APB peripherals are ACE with the mil_std_protocol, Timers for generation of interrupt and watchdog reset, UART for transmitting and receive messages, and interrupt registers for Reading and Write. From the simulation results, the state of operation of the AMBA is obtained. The overall coverage obtained for the AMBA peripherals is 91.4%, and the Assertion Coverage is 100%. This work can be extended by creating the verification environment for AMBA with the UVM library. Questasim collects all coverage data, code coverage, assertions, formal, and functional 208 D. D. N. Ponkumar.et al; Informacije Midem, Vol. 48, No. 4(2018), 205 - 211 coverage into a single highly efficient Unified Coverage Database (UCDB) and makes them available in realtime within the test bench. 5 Reference 1. "AMBA AHB"- specification by ARM limited. 2. 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Arrived: 25. 04. 2018 Accepted: 03. 10. 2018 209 210 Original scientific paper Informacije (midem Journal of M https://doi.org/10.33180/InfMIDEM2018.403 Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 4(2018), 213 - 216 Temporary Bonding Using Paper Inserted PPC Layer Zhiyuan Zhu1, Kequan Xia1, Zhiwei Xu1, Hongze Zhang3, Haijun Lou2 1Ocean College, Zhejiang University, Zhejiang, China 2Institute of Advanced Technology, Zhejiang University, Zhejiang, China 3Nanjing Electronic Devices Institute, Nanjing, China Abstract: Temporary bonding using paper inserted polypropylene carbonate (PPC) layer is demonstrated. The inserted paper layer can absorb photo acid generator (PAG)-induced acid and protect the substrate. Large improvements of bonding strength are achieved using paper inserted PPC layer. Especially, the bonding strength is much higher than that of PPC/PAG-PPC bonding for tissue paper. The results show that the paper fibers can absorb decomposed PPC and PAG-induced acid, thus protecting the substrate. Keywords: temporary bonding; debonding; polypropylene carbonate Začasno bondiranje z uporabo s papirjem vnesene PPC plasti Izvleček: Prikazano je začasno bondiranje z vnosom plasti polipropilen karbonata (PPC) s pomočjo papirja. Vložena papirna plast lahko absorbira kislino generatorja fotokisline (PAG), s čimer zaščiti substrat. Uporaba PPC plasti omogoča velike izboljšave vezne trdnosti bonda. Zlasti je vezna trdnost precej višja kot pri uporabi PPC/PAG-PPC tkanine. Rezultati kažejo, da lahko papirna vlakna absorbirajo razgrajeno kislino, ki jo povzroča PPC in PAG, s čimer se zaščiti substrat. Ključne besede: začasno bondiranje; debondiranje; polipropilen karbonat * Corresponding Author's e-mail: xuzw@zju.edu.cn, 1 Introduction Silicon wafer is the fundamentals of semiconductor industry [1-3]. Particular, the application of thin silicon wafers is an enabling technology for modern electronics as reduced wafer thickness integration enables shorter processing times and less cost [4-6]. All of this is advantageous for a low package height for chip cards, the requirement for higher power, and the search for System-in-a-Package (SiP) using chip stack methods. Temporary bonding and debonding are essential for fabricating thin wafers [7, 8]. On the one hand, the bonding strength should be high in order to endure the mechanical polishing/thinning. On the other hand, debonding process is required to be simple, low cost and of high reliability. To achieve the above requirements, we propose photo acid generator (PAG) loaded polypropylene carbonate (PPC) debonding at room temperature without any solvent based or ultraviolet (UV) treatment [9]. Subsequently, PPC/PAG-PPC bonding structure is proposed [10]. The inserted PPC layer serve as the passivation layer, which can absorb the PAG-induced acid. The bonding layer loses adhesion to the substrate and automatic debonding is achieved when center region of the PPC layer is decomposed. The PAG-induced acid is separated from the bonding substrate, which improve the bonding strength and protect the substrate. Application of PPC as temporary adhesive for fabrication of sensor chip has also been demonstrated [11]. The main aim of this work is to develop a method to further increase the PPC temporary bonding strength. Herein, we propose temporary bonding using paper inserted PPC layer. Further improvement of bonding strength is achieved. 211 © MIDEM Society Pousia. S.et al; Informacije Midem, Vol. 48, No. 4(2018), 197 - 203 2 Experimental Temporary bonding and debonding using paper inserted PPC layer is proposed to protect the substrate and improve the bonding strength. The bonding structure is shown in Fig. 1a. The PPC polymers (QPAC 40) used in this work were obtained from Empower Materials and have a molecular weight of 196 kg / mol. The PPC solution was prepared by dissolving pure PPC in acetone under constant stirring to form a 20 wt% solution. Tetrakis(penta-fluorophenyl) borate-4-methyl-phenyl [4-(1-methylethyl)-phenyl] iodonium tetrakis (pentafluorophenyl) borate is used as the PAG and obtained from tokyo chemical industry Co. The PAG-PPC solution was prepared by adding PAG (about 1 wt% of the PPC) to the PPC solution. Printer paper, tissue paper and silicone paper are used as the paper insertion layer. The main chemical compositions of the paper insertion are cellulose, hemicellulose, lignin, calcium carbonate, etc. The paper fiber can interlace with PPC polymer and absorb PAG-induced acid. Silicon paper is fabricated by treating printer paper with silicone, so it is nonstick and heatproof. The glass substrates (10mmx10mm) are obtained from Dongsheng Corporation with density of 2.2 g/cm3, tensile strength of ~50 MPa and inflection resistance of 60-70 MPa. The PPC solution was poured onto the glass substrate facade. The acetone was then removed by baking the specimen for 10 min at 60 °C. Subsequently, paper layer is attached on PPC surface, followed by dropping of PAG-PPC solution and solvent evaporation. Bonding of the fabricated samples is achieved using a hot press (Carver, Inc.) at bonding pressure of 0.2MPa. The bonding temperatures for thermal bonding 1 and 2 are 100°c and 200°c, respectively. The morphology of the substrate surface is examined using Hitachi TM3000 scanning electron microscope (SEM). 3 Results and Discussions The decomposition products of PPC include cyclic propylene carbonate (cPC), propylene glycol, and CO2, which indicates that decomposed PPC is liquid at room temperature. The (SEM image of typical paper fiber is shown in Fig. 2. It is obvious that the cellulose fiber of paper can absorb decomposed PPC and PAG-induced acid. Thus, PPC is less consumed and there is PPC remained beneath the paper layer, the substrate is protected and the bonding strength is improved. Under high bonding temperature (>170°c, represent as thermal bonding 2 in Fig. 1a1), sufficient PAG-induced acid is produced, consuming the entire PPC layer between paper layer and achieving automatic debonding at room temperature without any solvent based or UV treatment. Under low bonding temperature (<130°c, represent as thermal bonding 1 in Fig. 1a2), a portion of PAG is activated and less PAG-induced acid is produced, and a considerable portion of acid is also absorbed by paper fiber. Thus, a subsequent UV irradiation or heating is required to achieve complete debonding. Thermal Bonding 2 Class PPC Paper PAG-PPC Glass Time Glass PPC PPC Paper Paper • * * * " ' > 1 ¿Strong at/d * • • » 1 Decomposed PPC Paper draper-' PPC PPC Glass Glass Bonded Debonded PAG-PPC Paper PPC Glass a1 ruv/ thermal Before bonding a Thermal Bonding 1 Glass Time Glass PPC PPC Paper &APaper •. » * 9 » * * Jitrong acid PPC+PAG+ Decomposed PPC Paper iv Paper- ' PPC PPC Glass Glass Bonded a2 Partially Debonded Figure 1: Schematic of temporary bonding and debonding process a PPC/Paper/PAG-PPC bonding structure a1 Bonding at high temperature(>170°c) and subsequent automatic debonding for PPC/Paper/PAG-PPC structure a2 Bonding at low temperature(<130°c) and subsequent debonding for PPC/Paper/PAG-PPC structure Figure 2: SEM image of typical paper fiber Glass substrates are used to demonstrate and compare the bonding results. The results are shown in table 1. It 212 M. Mojibi et al; Informacije Midem, Vol. 48, No. 4(2018), 217 - 227 can be seen from table 1 that large improvements of bonding strength are achieved using paper inserted PPC layer. This effect is especially obvious for tissue paper, which absorb more PAG-induced acid. For printer paper and tissue paper, the bonding strength decrease significantly when bonding temperature increases to 200°c, which is probably caused by damage of fiber structure. On the contrary, there is no significant decrease of bonding strength of silicone paper inserted PPC layer, which can be attributed to the heat resistance property of silicone paper. In order to adjust the debonding time, heating or UV irradiation processes after bonding is used. All the bonded samples fabricated in this work are successfully debonded. Table 1: Comparison of the bonding strength of different methods demonstrated using glass substrates The surface morphologies of debonded samples were observed by SEM. Fig. 3 shows the SEM image of typical surface morphology of debonded samples for PAGPPC bonding under thermal bonding 2. PPC residue was observed. The results correspond well with the bond mechanism which state that under high bonding tem- Figure 3: SEM image of typical surface morphology of debonded samples for PAG-PPC bonding under thermal bonding 2 perature, excessive PAG-induced acid is produced, consuming the PPC protection layer at multiple locations and and leaving PPC residue. The PAG-induced acid can cause damage to the substrate and decrease the reliability of circuit where PPC protection layer is consumed. Fig. 4 shows the SEM image of typical surface morphology of debonded samples for PPC/silicone paper/PAG-PPC under thermal bonding 2. The results show that the upper surface of paper is the debonding interface, which indicate that the PPC layer beneath paper insertion is hardly decomposed. This corresponds well with the bond mechanism which state that paper fibers can absorb decomposed PPC and PAG-induced acid. Thus, PPC is less consumed and there is PPC remained beneath the paper layer, the substrate is protected and the bonding strength is improved. The improvements of bonding strength have also been demonstrated in Table 1. Figure 4: SEM image of typical surface morphology of debonded samples for PPC/silicone paper/PAG-PPC under thermal bonding 2. 4 Conclusion This letter proposes temporary bonding and debond-ing using paper inserted PPC layer. The paper insertion can absorb PAG-induced acid and increase bonding strength. In order to adjust the debonding time, heating or UV irradiation processes after bonding is used. 5 Acknowledgments This work was supported by National Natural Science Foundation of China (Grant No. 61804132). The author would like to thank the Animal Science Experimental Teaching Center of Zhejiang University for SEM characterization. The author would like to thank Prof. Yufeng Jin and Prof. Min Yu from Peking University for their help in previous work. The author would also like to Ref. Bonding strength (MPa) Thermal bonding 1 Thermal bonding 2 Printer paper in this work 3.9±0.45 MPa 1.7±0.33 MPa Tissue paper in this work 4.1±0.29 MPa 2.3±0.12 MPa Silicone paper in this work 3.5±0.19 MPa 3.2±0.43 MPa PAG-PPC bonding in [9] 3.0±0.34 MPa 2.1±0.18 MPa PPC/PAG-PPC bonding in [10] 3.3±0.26 MPa 2.7±0.25 MPa 213 M. Mojibi et al; Informacije Midem, Vol. 48, No. 4(2018), 217 - 227 thank the anonymous reviewer for the valuable judgment of this paper. 6 References 1. B. Tunaboylu, Space transformer connector characterisation for a wafer test system, Informacije MIDEM, 47[4] (2017) 255-260. 2. B. Tunaboylu, Performance of Ni-alloy MEMS-probes coated with PdCo films in semiconductor wafer test, Informacije MIDEM, 46[2] (2016) 80-90. 3. X. S. Zhang, Fabrication and characterization of squama-shape micro/nano multi-scale silicon material, Science China Technological Sciences, 55[12] (2012) 3395-3400. https://doi.org/10.1007/ s11431-012-4853-2 4. S. L. Ma, et al., Fabrication and characterization of a tungsten icroneedle array based on deep reactive ion etching technology, Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, 34[5] (2016) 052002. https://doi.org/10.1116/1.4960715 5. R. N. Fang, et al., Characteristics of coupling capacitance between signal-ground TSVs considering MOS effect in silicon interposers, IEEE Transactions on Electron Devices, 62 [12] (2015) 4161-4168. https://doi.org/10.1109/ ted.2015.2494538 6. X. Sun, et al., Measurement-based electrical characterization of through silicon vias and transmission lines for 3D integration, Microelectronic Engineering, 149[5] (2016) 145152. https://doi.org/10.10167i.mee.2015.10.010 7. Y. Guan, et al., Fine-pitch through-silicon via integration with self-aligned back-side benzocyclobutene passivation layer, IET Micro & Nano Letters, 11 [10] (2016) 619. https://doi. org/10.1049/mnl.2016.0267 8. P.Garrou, Handbook of 3D integration (Wiley-VCH), 2008. 9. Z. Zhu, et al., Temporary Bonding/Debonding of Silicon Substrates Based on Propylene Carbonate, Journal of Electronic Packaging, 137[4] (2015) 044501. https://doi.org/10.1115/1.4031750 10. Z. Zhu, et al., PPC-based bilayer temporary bonding and debonding, Microelectronic Engineering, 180[5] (2017) 5-7. https://doi. org/10.1016/j.mee.2017.05.029 11. X. Xue, et al., Heat-Depolymerizable Polypropylene Carbonate as a Temporary Bonding Adhesive for Fabrication of Flexible Silicon Sensor Chips, IEEE Transactions on Components Packaging & Manufacturing Technology, 7[11] (2017) 1751-1758. https://doi.org/10.1109/ TCPMT.2017.2742554 Arrived: 27. 05. 2018 Accepted: 24. 10. 2018 214 Original scientific paper Informacije ímidem Journal of M https://doi.org/10.33180/InfMIDEM2018.404 Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 4(2018), 217 - 227 Reliability evaluation of buck converter based on thermal analysis Mohammad Mojibi, Mahdi Radmehr Electrical Engineering Department, Islamic Azad University, Sari branch, Iran Abstract: The design, which is based on the concept of reliability, is impressive. In power electronic circuits, the reliability design has been shown to be useful over time. Moreover, power loss in switches and diodes plays a permanent role in reliability assessment. This paper presents a reliability evaluation for a buck converter based on thermal analysis of an insulated-gate bipolar transistor (IGBT) and a diode. The provided thermal analysis is used to determine the switch and diode junction temperature. In this study, the effects of switching frequency and duty cycle are considered as criteria for reliability. A limit of 150°C has been set for over-temperature issues. The simulation of a 12 kW buck converter (duty cycle = 42% and switching frequency = 10 kHz) illustrates that the switch and diode junction temperature are 117.29°C and 122.27°C, respectively. The results show that mean time to failure for the buck converter is 32,973 hours. Keywords: Reliability; Mean time to failure; Buck converter; Junction temperature. Ocena zanesljivosti buck pretvornika na osnovi termične analize Izvleček: V prispevku je predstavljena ocena zanesljivosti buck pretvornika na osnovi termične analize bipolarnega tranzostorja z izoliranimi vrati (IGBT) in diode. Termična analiza je uporabljena za določitev temperature spoja diode in stikala. Kriterij zanesljivosti je vpliv frekvence preklopa in obratovalnega cikla. Zgornja temperaturna meja je 150 °C. Simulacije 12 kW buck pretvornika (obratovalni cikel = 41%, frekvenca preklopa = 10 kHz) pokažejo temperaturo stikala 117.29 °C in spoja diode 122.27 °C. Povprečen pričakovani čas do okvare je 32,973 ur. Ključne besede: zanesljivost; srednji čas do okvare; buck pretvornik; temperatura spoja. * Corresponding Author's e-mail: radmehr@iausari.ac.ir 1 Introduction In recent years, the use of renewable energy has become more popular because of the negative impacts of fossil fuels and the environmental pollution they cause. Nowadays, various methods and topologies for extracting energy from different renewable sources are being introduced. Solar energy, which can be harnessed using photovoltaic panels, is one of the alternative sources of energy and offers many advantages (such as less negative environmental effects and affordability) in comparison with other sources. As renewable energy sources continue to be used more often, more attention is now being paid to power electronics. A converter frequently used for photovoltaic panels in power electronics, as well as in several wind turbine energy conversion systems, is the dc-dc converter. In the last few decades, there have been many dc-dc converter topologies introduced, which have been generally classified based on the ratio of voltage output to input (also known as gain) into three fundamental groups: buck, boost, and buck-boost. This paper focuses on the buck converter type, often used in small or low power systems as a simple, remarkably efficient way to reduce the input voltage to a regulated dc voltage [1]. More efficient use of any device has always been a goal of manufacturers. In power electronics, the proper functioning of converters encompasses high output quality, a long lifespan, and less energy consumption. Due to the increase of power electronic converters in different devices, an especially important factor for optimizing converters is power quality, which can be described in terms of its thermal characteristics. Indeed, 215 © MIDEM Society M. Mojibi et al; Informacije Midem, Vol. 48, No. 4(2018), 217 - 227 previous researches have clarified the relationship of converter performance and quality in terms of heat loss [2-4]. Furthermore, Usui and Ishiko presented a simple approach for the thermal design of an IGBT module practised only in steady state operation [5]. In recent decades, different approaches for thermal analysis have also been introduced, including the highly accurate method of computational fluid dynamics (CFD), based upon how airflow conditions determine heat transfer coefficients [6]. Converter lifespan is another significant factor with a direct relationship to reliability, which represents the probability of failure in a system at a specific time [7]. The reliability of a system depends on various parameters; for this reason, identifying the indicators and calculation of the reliability parameters of the system's parts is required. Usually, two parameters are used to assess the reliability of the system. The first parameter is failure rate explained by failure distribution, and the next parameter is mean time to failure (MTTF) which presents the average operation time before the first failure of a component [8]. There are different researches related to the reliability assessment of various circuits and power converters. These circuits include multilevel inverters [9, 10], DC-DC converters [11], and AC-AC converters [12]. Khosroshahi et al. [13] evaluated the reliability of two conventional and interleaved DC-DC boost converters based on the MIL-HDBK-217 procedure. They found that the interleaved boost converter performs better in terms of reliability in comparison with the conventional boost converter. Perhaps, the most crucial weakness of this article is using approximate relations for calculating power dissipation in the switch and diode, which are based on their internal resistances. Rashidi-Rad et al. [14] performed a reliability analysis of modular multilevel converters (MMCs) with the presence of half and full-bridge cells. Their examination illustrated that the modular converters that used half-bridge cells have more reliable performance than other state. Arifujjaman and Chang [12] compared the reliability of three ac-ac converter namely intermediate boost converter (IBC), intermediate buck-boost converter (IBBC), and back-to-back converter (BBC) with the well-known matrix converter. They concluded that the intermediate boost converter exhibits more reliable than other ones. In [15], the reliability of a buck converter was assessed in the presence of N-channel and P-channel MOSFET drivers. They showed that the considered buck converter has more reliability when an N-channel MOSFET is used as switch. However, they ignored some portions of the power losses in switch and diode, thus the obtained results may not be referred. Ranjbar et al. [16] carried out a reliability assessment of single/two stage power factor correction (PFC) converters. The MIL-HDBL-217 was considered as reliability estimation procedure in this analysis. The outcomes demonstrated that the lifespan of a singlestage converter is about 1.6 times longer than the two-stage converter. In this study, for simplicity of calculations, the case temperature was intended to be a fix value of 35°C. This leads to an inaccuracy in the results. The main purpose of this paper is to estimate the reliability of a buck converter based on the MIL-HDBK-217 standard. Although this standard has been criticized for being obsolete, it is still extensively used in military and aerospace industries to provide a basis for comparison between two or more different circuits [17]. For this reason, several previous literatures have employed this standard for predicting the reliability of power electronic converters (e.g., [1822]). To investigate the reliability of semiconductor devices, there is a need for determining the junction temperature in these types of components, and in this study, the selected approach is based on information from manufacturer's datasheet. A one-cell Cauer thermal model was utilized in order to provide a precise relationship between the power losses and the junction temperatures in the presence of a heatsink. This approach has an acceptable result as well as suitable speed in calculations. Additionally, this is the first time that the simultaneous impact of switching frequency and duty cycle on the power losses and the junction temperature has been analyzed. The rest of this paper is structured as follows: Section 2 describes the buck converter as a case study. The reliability principals employed for the analysis are discussed in Section 3. In Section 4, the accurate thermal analysis for the buck converter is discussed. In Section 5, the results and reliability evaluation are presented. Finally, conclusions are drawn in Section 6. 2 The buck converter The buck converter circuit shown in Figure 1 is a highly efficient step-down dc-dc converter which is commonly used in switched-mode power supply circuits (SMPS). Generally, the dc input voltage of the buck converter 216 M. Mojibi et al; Informacije Midem, Vol. 48, No. 4(2018), 217 - 227 is derived from the output of a rectifier through a delink. In this paper, an IGBT is used as a switch for the converter. Also, the thermal analysis has been performed considering the effect of temperature on the voltage drop between the collector and emitter junctions of the diode and the transistor, because practically this voltage should be estimated by the means of both collector current and temperature, VCE(i(, T). The voltage drop for an IGBT can be experimentally measured by sensing the current of switch. Typically, a low-ohmic resistor is placed between the ground and emitter, and by flowing the current through this sensing resistor, the occurred voltage drop can be identified by another monitoring circuit. An improved sensing method is based on four external connection nodes for finding RDS(on) of the switching power MOSFET, or VCE(on) of an IGBT. The drawback of these methods is need for protection circuits and expensive discrete components against high voltage [23]. But, the employed approach in this paper will provide us the opportunity to identify the voltage drop indirectly. Figure 1: Topology of a buck DC-DC converter. Table 1: Rated parameters for the desired buck converter. Characteristic Rated output active power Po Input voltage Vin Output voltage Vout Switching frequency fs Inductor L Capacitor C 12 kW 300 V DC 125 V DC ± 1.2% 10 kHz 3 mH 1 mf A buck converter with parameters based upon Table 1 is simulated in MATLAB/Simulink. An open-loop controller is used for the simulation. Furthermore, a value of 42% is considered the duty cycle in this state. The results of the simulation are shown in Figure 2: Figure 2: The simulation results of basic characteristics of the converter. When the buck converter operates in continuous conduction mode (CCM), the current through the inductor (IL) will never fall to zero during the cycle. Assuming the steady state operation for this converter, it can be concluded that the energy stored in each of circuit components at the end of a cycle is equal to energy stored at the beginning of the cycle. Therefore, the input and output voltages in the buck converter have a direct relationship with the duty cycle of the pulses, which can be shown as follows: Vout = DVn (1) where Vout, Vn, and D are the output voltage, the input voltage, and the converter duty cycle, respectively. With regard to the value of 0 (11) where VS (S) is the ratio of applied collector-emitter voltage to rated voltage. Diodes are usually used as power rectifiers in power electronic converters. In the industry, the diodes with a reverse recovery rate of 500 nanoseconds or less (approximately 0.1 of standard rectifiers) are categorized as fast rectifiers. If this period is reduced to 100 nanoseconds or less, they will be named as super-fast rectifiers [39]. Given that the diodes within the IGBT modules are classified as fast recovery power rectifier, they must be set to the appropriate level according to the standard, and the base failure rate for the diodes will be equal to 0.025 failures/106 h. In the following equation, nS is the stress factor for diodes: ^S = (s (D) 2.43 (12) where VS(D) is the ratio of operating voltage to nominal voltage. nC explains the contact construction. Considering it is metallurgically bonded, the contact construction leads to the value of 1 for nC [35]. In the capacitor failure rate, nCV is the capacitor factor which can be calculated as follows: nCV = 0.34 x C0 where C is the capacitance in microfarad. (13) The inductor base failure rate can be expressed as follows: Xb (L) = 0.000335 x exp 'Ths + 273^156 329 (14) where T is the hot spot temperature in degree Celsius, which can be determined using Equation (15): Ths = Ta +1.1 XAT (15) In Equation (15), TA expresses the device ambient operating temperature in degree Celsius. Also, AT is the average temperature rise above the ambient [34, 35]. The inductor failure rate is much lower than other circuit components, so it can be omitted from the analysis. The capacitor failure rate can be described by the following equation: A, (c)= 0.00254 ' S ^ 0.5 + 1 exp 5.09 x fTA + 273 V 378 (16) where S is the ratio of operating voltage to nominal voltage. nT is the temperature factor that, for the switch and diode, can be expressed as follows [35]: n T (s ) exp nT (D) = eXP -2114: -3091: \\ v Tj + 273 T + 273 V j 298 J J w 298 (17) (18) J J where T. is the junction temperature. One of the major concerns regarding reliable power electronics is the operating temperature. Thus, it seems that the precise determination of the junction temperature results in a more accurate analysis of the reliability. There are five different approaches introduced by Reliability Analysis Center (RAC) to predict the junction temperature for semiconductor devices. In this study, Method IV was used. This method is utilized when a heatsink is mounted on the device, and the exact value of the case temperature is also available [40]. According to the used approach, the junction temperature can be calculated from Equation (19): T j = Tc + 0jc x PIoss (19) In Equation (19), TC is the heat sink temperature, djc is the thermal resistance of the diode or switch, and P, is ' loss the total power losses of switch or diode. 219 M. Mojibi et al; Informacije Midem, Vol. 48, No. 4(2018), 217 - 227 In fact, Equation (19) exhibits a scheme of the one-cell Cauer thermal network. Figure 3 shows this modeling. Figure 3: One-cell Cauer thermal network model. In Figure 3, Rth and Cth are the thermal resistance and capacitance from junction-to-case, respectively, and these indicators should be selected from the datasheet of the used IGBT module (both diode and IGBT). Also, by similarity of thermal modeling and electrical modeling, the junction temperature can be found easily from the total power losses. Foster and Cauer thermal network models are commonly used for dynamic thermal modeling, and both models use thermal resistance (R) and thermal capacitance (C), which are joined together as ladders and form multiple layers. Although many manufacturers of power modules typically offer the Foster model limited to four layers [41], the others only provide the transient thermal impedance curve (Zth) within the datasheet; and the values for each layer should be obtained by curve fitting tools [42, 43] or algorithms [44]. Here, the particle swarm optimization (PSO) algorithm was used [45] to identify four RCs related to the four different layers. Due to the need for a high number of simulations in this paper, a one-layer Cauer model has been employed for thermal analysis between junction and case. In addition to having the suitable precision, this model improves the simulation speed significantly. One issue for modeling thermal networks is the conversion of a Foster model to a Cauer model, and vice versa (for more details about these two thermal networks, refer to [46]). Considering that the four-layer Foster model is a four-order system, a circuit software is required to convert it to the first-order Cauer model. In this study, we used the LTspice software to find the values of Rth and Cth for the one-cell thermal model. The resistance of the single-layer model is equal to the sum of the four resistances of the four-layer model, which is the same as the peak of the thermal impedance curve. In order to determine the value of capacitance, a curve fitting on the outputs of the LTspice software was performed. Thus, the obtained values of the thermal resistance and capacitance for the Cauer network are 0.25 K/W and 0.18 J/K, respectively. Similarly, the extracted values for the diode are 0.46 K/W and 0.1 J/K, respectively. To complete the thermal model, the heat transfer from the case to the ambient through the heatsink should also be added. Modeling of this part is shown in Figure 4. Figure 4: Thermal modeling from case-to-ambient. In order to implement this part, the thermal and physical elements of MATLAB/Simulink have been used. The case-heatsink thermal resistance value (Rth(c_h) is driven from the datasheet, and is equal to 0.05 K/W for the module under study. A 10-inch aluminum heatsink manufactured by the Wakefield-Vette under forced air cooling (500 feet per minute) is considered as the cooling system. According to the described circumstances, the value of Rth(h_a) will be equal to approximately 0.1 K/W. For simplicity, we consider the case-heatsink thermal capacitance to be 0.25 J/K. The heatsink thermal capacitor is also assumed to be 0.01 J/K, based on [47]. Finally, as mentioned earlier, the determination of semiconductors' failure rate depends on their power losses. The utilized approach in this paper is based on calculating both conduction and switching losses for the diode and switch using lookup tables. Detailed explanation of this process is given in [48]. 4 Thermal analysis of buck converter In order to determine the thermal analysis of the converter, a Fuji 2MBI150U2A-060 600V/150A IGBT module is selected as the switch. The features of this module include high speed switching, voltage drive, and low inductance [49]. Figure 5 shows the IGBT on-state characteristics in 25°C and 125°C, based on Collector current versus Collector-Emitter voltage. The rated current distributions for the switch and diode are shown is Figure 6, which this figure clearly demonstrates the summation of switch and diode currents can produce the inductor current (when the switch is on, the diode is off). Conversely, when the diode is on, the switch is off. The inductor current will be a triangular waveform when its voltage analogue is pulsating in a rectangular form 220 M. Mojibi et al; Informacije Midem, Vol. 48, No. 4(2018), 217 - 227 Figure 5: IGBT's Collector current in terms of Collector-Emitter voltage [49]. Figure 6: Current distributions of the switch and diode. (a) (b) (c) Figure 7: 2D plots for showing effects of duty cycle and switching frequency on (a) the switch junction temperature, (b) the diode junction temperature, (c) the heat sink temperature. The most important factor in the evaluating converter reliability is temperature, which is directly related to power losses of the switch and diode. Thus, the calculation of the junction temperature is a sure way to assess reliability. Various elements can influence the junction temperature and its value will change with variations in component's power losses; increasing the switching frequency can lead to more power losses in the switch and diode. Another important factor for power losses in the buck converter is the modulation index or duty cycle. By setting a different duty cycle for the converter, the gain of the output voltage will change. An analysis is undertaken to show the effects of the switching frequency and the duty cycle on the junction temperature and the heat sink temperature. Figures 7 and 8 represent the items that can affect temperatures in the form of two-dimensional and three-dimensional diagrams. (a) (b) (c) Figure 8: 3D plots for showing effects of duty cycle and switching frequency on (a) the switch junction temperature, (b) the diode junction temperature, (c) the heat sink temperature. It is evident from Figures 7 and 8 that a lower duty cycle corresponds to a better performance in terms of temperature because of the decrease in the output voltage level. Therefore, it is possible to change the duty cycle to its desired value by changing the basic 221 M. Mojibi et al; Informacije Midem, Vol. 48, No. 4(2018), 217 - 227 characteristics of the converter. Increasing switching frequency from 1 to 10 kHz has a negligible impact on the temperature, but switching frequencies higher than 10 kHz will increase the temperature. The over-temperature is limited to 150°C, so the converter ceases to operate beyond this temperature. For duty cycles higher than 51%, the junction temperature of the switch rises beyond the over-temperature. This shows the weakness of heatsink for cooling the module under thermal pressure. Using a more efficient heatsink will result in a decrease in the junction temperature and the extension of authorized period for increasing the duty cycle. The calculated power losses for the switch and diode (based on the rated parameters) are 145.02 W and 89.69 W, respectively. Also, the results illustrate that the switch junction temperature for a duty cycle of 42% and f = 10 kHz is 117.29°C. The junction temperature of the diode is 122.27°C, and it has a higher value than the switch's temperature. Although the diode power losses are less than the switch, due to the greater diode thermal resistance in comparison with the switch (0.46 compared to 0.25 K/W), the diode junction temperature would be higher. This issue can also be deduced from the physical structure of the IGBT module, because the cross-section of the diode chip is smaller than the switch, and with the same heat flux applied to the both chips, the smaller chip will experience higher temperature increase. This shows that greater thermal resistance can produce higher junction temperatures. a stable value for the temperature of the heat sink [50]. However, the structure and design of the heat sink can affect its operating temperature. The simulation results showed that the heat sink temperature measured with the parameters rated was 69.32°C. 5 The reliability evaluation of buck converter Estimated failure rates for each component under identical conditions are shown in Tables 2-5. Due to the application of the switch, a value of 0.7 is considered to be the application factor. Values of nQ and nE were set for the components according to [34]. A value of 0.88 was considered to be the failure rate of the controller, similar to [35], and the failure rate of the converter can be estimated by summing all of the failure rates (we only have one from each component). The failure rate of the entire system was calculated at 30.328 (failures/106 h) by the following equation: N (20) By reversing the failure rate, MTTF can be calculated as follows: Typically, the heat sink temperature is much lower than that at the junction of other components, and in reliability designs, a temperature of 40°C is considered MTTF 1 106 V» 30.328 32,973 hours (21) Table 2: The estimated base failure rate for the switch. I PLoss (W) T (°C) nT "a nR ns nE no Ab Ap (failures/106 h) 1 145.02 117.29 5.35 0.7 10 0.22 6 5.5 0.1 27.188 Table 3: The estimated base failure rate for the diode. I PLoss (W) Tj (°C) nT nc ns He no Ab Ap (failures/106 h) 1 89.69 122.3 12.85 1 0.19 6 5.5 0.025 2.014 Table 4: The estimated base failure rate for the capacitor. I Value Ta (°C) ncv He no Ab Ap (failures/106 h) 1 1 if 40 0.34 2 10 0.029 0.197 Table 5: The estimated base failure rate for the inductor. Ta (°C) Ths (°C) 40 69.32 1 4 20 6.22X10-4 Ap (failures/106 h) 0.049 222 M. Mojibi et al; Informacije Midem, Vol. 48, No. 4(2018), 217 - 227 6 Conclusion A new approach to reliability assessment based on thermal analysis of the switch and diode was presented. The thermal analysis of a buck converter with the basic characteristics shown in Table 1 was conducted by calculating the temperature at the switch and diode junction. The total failure rate of the converter was expressed by summing the failure rate of the components using the parts count method. The procedure employed for the reliability analysis was that given in the MIL-HDBK-217F handbook. The results of the simulation using MATLAB Simulink showed that the buck converter analyzed will operate reliably for 3.8 years, which is an acceptable performance. 7 References 1. Huangfu Y, Ma R, Liang B, Li Y. "High power efficiency buck converter design for standalone wind generation system". International Journal of 12. Antennas and Propagation, 1, 1-9, 2015. https:// doi.org/10.1155/2015/751830 2. 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IEEE Transactions on Industry Applications, 50(1), 415-423, 2014. https://doi.org/10.1109/TIA.2013.2266391 Arrived: 27. 01. 2018 Accepted: 23. 11. 2018 225 226 Original scientific paper https://doi.org/10.33180/InfMIDEM2018.405 Informacije imidem Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 4(2018), 229 - 233 Elliptically polarized frequency agile antenna on ferroelectric substrate Vladimir Furlan12, Sebastjan Glinšek3, Tanja Pečnik4, Matjaž Vidmar5, Brigita Kmet4, Barbara Malic4 1Slovenian Centre of Excellence for Space Sciences and Technologies, Ljubljana, Slovenia 2Taoglas GmbH, Munich, Germany 3Materials Research and Technology Department, Luxembourg Institute of Science and Technology,, Belvaux, Luxembourg 4Jozef Stefan Institute, Ljubljana, Slovenia 5Faculty of Electrical Engineering, University of Ljubljana, Ljubljana, Slovenia Abstract: A low-profile, compact and frequency-tunable antenna made on ferroelectric substrate is presented. It is designed as a planar dipole antenna with an IDC varactor integrated in the signal line. Antenna is fed through a coplanar waveguide matched to 50 Q. The center frequency can be tuned from 6.895 GHz to 7.050 GHz. It exhibits elliptical polarization and omnidirectional radiation pattern. Keywords: Frequency-tunable antenna; ferroelectric thin films; (Ba,Sr)TiO3 Eliptično polarizirana in frekvenčno nastavljiva antena na feroelektrični podlagi Izvleček: Predstavljena je frekvenčno nastavljiva planarna antena z majhnim profilom izdelana na feroelektrični podlagi. Zasnova antene temelji na planarnem dipolu z interdigitalnim varaktorjem, ki je integriran v signalni liniji. Napajana je skozi koplanarni valovod z imedanco 50 Q. Resonančna frekvenca antene je prilagodljiva v območju med 6.895 GHz in 7.050 GHz. Antena ima eliptično polarizacijo in omni-smerni diagram sevanja. Ključne besede: Frekvenčno nastavljiva antena; feroelektrične tanke plasti; (Ba,Sr)TiO3 f Corresponding Author's e-mail: sebastjan.glinsek@list.lu 1 Introduction Nowadays Earth and space communication modules provide multiple services on different frequencies with constant demand for reduced dimensions of the communication devices. Reduced dimensions of the chassis often result in either compact antennas with narrow bandwidth or in complex multiband design. Frequency-agile antennas, on the other hand, are attractive as they are small and can at the same time seamlessly cover a wide frequency range [1, 2]. A simple way to tune antenna is to load it with varactors. In the past years thin-film ferroelectric varactors have been extensively studied for possible use in frequency-agile microwave devices [3, 4]. Lumped-element microwave circuits based on ferroelectrics are advantageous over the competing technologies, i.e., semiconductor varactors and micro-electro-mechanical systems (MEMS), in terms of space-radiation stability, reliability and their rapid response [5, 6]. High-density integrated circuits based on ferroelectric thin films with thicknesses below 1 ^m can be produced on a single substrate, which increases the fabrication output and reduces the cost. This paper presents a novel antenna architecture with integrated ferroelectric varactor, which was designed to manufacture a simple yet efficient tunable antenna 227 © MIDEM Society M. Mojibi et al; Informacije Midem, Vol. 48, No. 4(2018), 217 - 227 for satellite communications at frequencies between 6.875 and 7.050 GHz. In addition to tunable center frequency it is characterized also with elliptical polarization and good cosmic irradiation hardness [7]. Antenna is fed through a coplanar waveguide (CPW) loaded with an interdigital (IDC) varactor made on Ba03Sr07TiO3 thin-film substrate. Biasing of the varactor is achieved through the CPW signal line, with RF signal and bias separated with 1 MO resistor. 2 Antenna fabrication and design Resonant frequency of the antenna can be effectively changed by adding a variable capacitor (varactor) at its feed point. Polycrystalline ferroelectric film, with the composition of Ba03Sr07TiO3, was deposited by cost-efficient Chemical Solution Deposition on ~250 pm-thick polished polycrystalline Al2O3 substrate (CoorsTek Inc., Golden, USA, £ = 9.9). Thickness of the film was increased by several deposition-heating steps to 240 nm and the final annealing was performed at 900 °C [8]. Dielectric permittivity £ and losses tan5 of the films were measured at 9.6 GHz using split-post dielectric resonators (QWED, Warsaw, Poland) and were found to be 640 and 0.02, respectively. Dipole antenna fed by a coplanar waveguide with integrated BST varactor was found to give the best compromise between the requirements, i.e., working frequency range, and its characteristics, i.e., dimensions and efficiency. The structure was patterned by lift-off photolithography and top Cr/Cu electrodes with 15 nm of Cr and 2 pm of Cu were deposited by DC sputtering (Balzers Sputron, Oerlikon Balzers, Liechtenstein). Its configuration is shown in Fig. 1. Width and spacing of the 50 Q CPW feed line are 1050 pm and 250 pm, respectively. The IDC fingers are 185 pm long, 10 pm wide and have a 5 pm gap between them. Magnified view of the 12-fin-gered IDC varactor is shown in the inset of Fig. 1. To facilitate the measurement, an SMA connector was mounted at the edge of the CPW. The photography of the fabricated antenna and the optical micrograph of the IDC varactor are shown in Fig. 2(a) and (b), respectively. Figure 2: (a) fabricated tunable dipole antenna and (b) IDC varactor. 3 Measurement results and comparison with existing solutions Return loss Su of the tunable dipole antenna measured at applied bias voltage up to 50 V is shown in Fig. 3. The resonant frequency changes between 6.875 GHz for 0 V bias and 7.050 GHz for 50 V bias, which translates into tuning range of approximately 3 %. Higher voltages detune the antenna to the point where it is no longer viable for space communication. -2 4 -6 s -io S -12 -14 -16 -18 -20 6. -ov -25V -- -50V i V 1 1 i 6.9 7 7.1 Frequency (Hz} 7.4 7.5 x10B Figure 1: Configuration of the proposed tunable dipole antenna. Dimensions are given in mm. Figure 3: Measured return loss 5n of the tunable dipole antenna. Far-field radiation patterns were measured in the MVG Satimo StarLab (MVG Industries, Villebon-sur-Yvette, France) near field measurement chamber (Fig. 4). Currents flowing on the outside of the coaxial cable shield were suppressed as much as possible with the use of ferrite chokes, which can be seen as white cylinders near the antenna in Fig. 4. The radiation patterns at 6.875 GHz under 0 V bias are presented in Fig. 5, while the Axial Ratio (AR) is shown in Fig. 6. In X-Y plane antenna has an almost omnidirectional 228 V. Furlan et al; Informacije Midem, Vol. 48, No. 4(2018), 229 - 233 pattern. In the Z-X plane antenna has maximum gain in X axis and minimum in Z axis, which is typical for dipole antenna radiation pattern, although it is not perfect. It has a higher gain in -X direction compared to +X direction (Fig. 5a) and higher gain in X-axis compared to Y-axis. This can be explained with the current flowing on the antenna between the horizontal arms and ground plane shown in Figure 7. Maximum gain is 1.6 dBi. AR measurement shows that antenna is linearly polarized in Z-X plane but has a significantly lower AR in X-Y plane, i.e. it is elliptically polarized in Y axis (Fig. 6). Figure 4: a) Measurement set-up for far-field radiation measurements with mounted antenna. b) Detailed view of the same set-up. Elliptical polarization and irregular radiation pattern can be explained by examining the current distribution on the antenna, which was simulated with Sonnet Software 3D planar high-frequency electromagnetic software and is shown in Fig. 6. Vertical parts of the antenna between horizontal dipole and ground plane are electrically far apart. Consequently, currents flowing into the antenna though the signal line and out of the antenna through the ground plane do not cancel each other out. Antenna is therefore radiating not only from its horizontal parts, as could be expected for a dipole antenna, but also from its vertical parts. This induces vertical component into the radiated electromagnetic field. Compared to the existing literature data on tunable antennas based on BST-film varactors, the 3 % tuning of resonant frequency at 50 V exceeds the values reported for slot loop antennas, for which either 3 % or 1 % tuning was achieved with 200 [9] and 40 V bias z b) Y -6875 MHz (dBi) X (dBi) Figure 5: 2D radiation patterns measured at 6.875 GHz. a) Z-X plane, b) Z-Y plane and c) X-Y plane. 229 V. Furlan et al; Informacije Midem, Vol. 48, No. 4(2018), 229 - 233 [10], respectively. However, it is inferior to the 8 % tuning achieved with 10 V in Bowtie antenna with three IDC varactors integrated in the feed line [11]. a) x -6875 MHz (dB) Z (dB) X C) Y -$875 MHz (dB> Figure 6: Axial Ratio diagrams measured at 6.875 GHz. a) Z-X plane, b) Z-Y plane and c) X-Y plane. Figure 7: Tunable dipole antenna current distribution at 6.875 GHz. 4 Summary A low-cost and compact frequency agile antenna on ferroelectric substrate was made and measured. An IDC varactor integrated in the antenna can shift its resonant frequency by 3 % when bias voltage of 50 V is applied. In Y-axis antenna exhibits elliptical polarization with low axial ratio, which is desirable in Earth and satellite communication as it reduces fading of the signal. Design allows a compact, lightweight and low cost manufacturing, which is anticipated for space applications. 5 Acknowledgments This work was supported by European Space Agency as part of the Ferro-Patch project and the Slovenian Research Agency (ARRS, J2-5482, P2-0105). 6 References 1. J. M. Carrere, R. Staraj, G. Kossiavas, "Small Frequency Agile Antennas'; Electronics Letters, vol. 37, no. 12, June 2001, pp. 728-729, 2001. https://doi.org/10.1049/ek20010529 2. R. T. Cutshall, R. W. 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Jantunen, "Low-Sintering-Temperature Ferroelectric-Thick Films: RF Properties and an Application in a Frequency-Tunable Folded Slot Antenna", IEEE Antenna and Wireless Propagation Letters, vol. 7, pp. 461-464, 2008. https://doi. org/10.1109/LAWP.2008.2001120 10. H. Y. Li, H. P. Chen, S. C. Chen, C. H. Tai, J. S. Fu, "A tunable slot loop antenna using interdigitated ferroelectric varactors", IEEE Antennas and Propagation Society Symposium, 2012. https:// doi.org/10.1109/APS.2012.6348537 11. K. C. Pan, H. Jiang, D. Brown, C. H. Zhang, M. Patterson, G. Subramanyam,"Frequency tuning of CPW bowtie antenna by ferroelectric BST thin film varactors", Proceedings of the 2011 IEEE National Aerospace and Electronics Conference, 2011. https://doi.org/10.1109/NAEC0N.2011.6183066 Arrived: 31. 08. 2018 Accepted: 06. 12. 2018 231 232 Original scientific paper https://doi.org/10.33180/InfMIDEM2018.406 Informacije imidem Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 4(2018), 235 - 240 Electrochemical acetylcholinesterase biosensor for detection of cholinesterase inhibitors: study with eserine Nina Lokar1, Veno Kononenko2, Damjana Drobne2, Danilo Vrtacnik1 University of Ljubljana, Faculty of Electrical Engineering, Laboratory of Microsensor Structures and Electronics, Ljubljana, Slovenia 2University of Ljubljana, Biotechnical Faculty, Department of Biology, Ljubljana, Slovenia Abstract: Cholinesterase inhibitors are widely used as pesticides, as chemical warfare agents and as drugs to treat symptoms of Alzheimer's disease. Therefore, it is a high need to develop methods for their detection which are fast, sensitive, and reliable. This paper reports a preliminary work in the development of an electrochemical biosensor based on acetylcholinesterase (AChE) which is constructed by immobilization layers - cysteamine/glutaraldehyde/AChE on thin layer gold electrode for detection of cholinesterase inhibitors. Eserine (physostigmine) was used as a test inhibitor. The enzyme immobilization efficacy was evaluated by measuring activity of immobilized enzyme via Ellman's method. The enzyme activity of the initial reduction of 33% in five days remained after that stable for at least one week. Chronoamperometric response to substrate acetylthiocholine chloride (ATCl) was assumed to follow Michaelis-Menten kinetics. After exposure biosensor to 25 mM eserine for 10 min, 70% inhibition of enzyme was detected. Reactivation factor of inhibited AChE was determined as 0.016 min-1. Keywords: Electrochemical biosensor; Acetylcholinesterase; Eserine; Ellman assay; Chronoamperometry; Cyclic voltammetry Elektrokemijski acetilholinesterazni biosenzor za detekcijo holinesteraznih inhibitorjev: raziskava z eserinom Izvleček: Holinesterazni inhibitorji se pogosto uporabljajo kot pesticidi, kot kemična bojna sredstva ali kot zdravila za zdravljenje simptomov Alzheimerjeve bolezni, zaradi česar je razvoj hitrih, občutljivih in zanesljivih metod za njihovo zaznavanje izrednega pomena. Članek podaja rezultate začetnih raziskav v razvoju elektrokemijskega biosenzorja za detekcijo inhibitorjev acetilholinesteraze (AChE). Biosenzor je zgrajen na steklenem substratu, na katerem je strukturirana tankoplastna zlata elektroda. Na njej so imobilizirani cisteamin/glutaraldehid/AChE. Kot testni inhibitor je uporabljen eserin (fizostigmin). Učinkovitost imobilizacije encima smo spremljali z merjenjem aktivnosti imobiliziranega encima z Ellmanovo metodo. Po petih dneh od izdelave biosenzorja se je aktivnost encima stabilizirala. Kronoamperometrični odziv na substrat acetiltioholin klorid (ATCl) je predpostavljeno sledil kinetiki Michaelisa in Mentenove. Po 10 minutni izpostavljenosti biosenzorja 25 mM eserinu smo detektirali 70% inhibicijo encima. Reaktivacijski faktor inhibiranega AChE je bil 0.016 min-1. Ključne besede: elektrokemijski biosenzor; acetilholinesteraza; eserin; Ellmanova metoda; kronoamperometrija; ciklična voltametrija * Corresponding Author's e-mail: nina.lokar@fe.uni-lj.si 1 Introduction In 1962, Clark and Lyons proposed the initial concept of glucose enzyme electrodes which led to a powerful analytical instrument for the detection of glucose in samples from patients with diabetes. This resulted in popularization of biosensors [1, 2]. In comparison with the conventional analytical techniques (such as chromatography and mass spectrometry), biosensors are typically easy to use, suitable for in situ measurement, and low cost [3]. Biosensors are remarkably diverse, 233 © MIDEM Society N. Lokar et al; Informacije Midem, Vol. 48, No. 4(2018), 235 - 240 comprising a wide range of combinations of biorecog-nition and transduction elements [4, 5]. Enzymes are the most often used bio-recognition elements, whereas the most widely applied biosensors are based on electrochemical transduction method [6]. Enzyme-based biosensors are implemented in direct or indirect form [5]. One example of indirect form option is cholinesterase (ChE) biosensors which are based on enzyme inhibition [7, 8]. They are useful tools for detection of ChE inhibitors. The most widespread applications of such biosensors are detection of pesticides (organophosphates and carbamates) and warfare nerve agents (sarin) [6]. ChE inhibitors are also recognized as prevailing choice (galantamine, rivastigmine, donepezil) in the treating of Alzheimer's disease symptoms [9]. For these applications, the inhibitors detection and analysis are of great importance. Eserine has been used by many researchers as a reference standard in the evaluation of new ChE inhibitors [10]. Eserine can be found naturally in the Calabar bean. Eserine binds at both the anionic and esteric sites of acetylcholinesterase (AChE), forming a drug-enzyme complex. The mechanism is not completely reversible [11]. This paper reports construction of an AChE biosensor based on immobilization layers of cysteamine, gluta-raldehyde, and AChE, which are chemically bound to the thin gold electrode layer. Cyclic voltammetry (CV) and chronoamperometry (CA) were applied to demonstrate the fasibility of fabricated biosensor structure for the detection of one well-known and important neuro-transmitter inhibitor eserine. 2 Materials and methods 2.1 Chemicals Following compounds were purchased from Merck (Germany): 95-98% H2SO4, 30% H2O2, 100 mM cysteamine, glutaraldehyde 5% (v/v), AChE from electric eel (50 U/mL), 100 mM K-P buffer solution with pH = 8.0 (47 mL 1 M K2HPO4 + 3 mL 1 M KH2PO4 + 450 mL mi-liQ water), 5 mM (if not specified differently) substrate acetylthiocholine chloride solution (ATCl), and 10 mM eserine. 0.1 M KCl containing 2 mM ferri/ferro-cyanide were prepared and purchased from Merck and Fluka (Belgium), respectively. 2.2 Instruments Spectrophotometry was carried out by microplate reader Cytation 3 from BioTek (Germany). CV and CA measurements were carried out using po-tentiostat EmStat3+ Blue equipped with PSTrace 5.3 software from PalmSens BV (The Netherlands). Miniature Ag/AgCl, 3 M KCl reference electrode, model ET073 was from eDAQ Pty Ltd (Australia). 2.3 Biosensor structure Electrodes. Replaceable chip, containing an array of 6 thin layer gold working electrodes (Figurela) was manufactured. Gold electrodes were applied on glass substrate using microfabrication processes - sputtering of Cr/Au with thicknesses 30 nm/120 nm, photolithography patterning and wet etching. The diameter of the working electrodes was 0.3 cm, resulting in an apparent geometric area of 0.07 cm2. As counter (or auxiliary) electrode, platinum wire was used, and it was wrapped around the external reference electrode (Figure 1b). All three electrodes were installed in an originally designed electrochemical cell with reservoir volume of 5 mL (Figure 1c). Chip with working electrodes in electrochemical cell was connected to potentiostat (Figure 1d) with spring tips. Figure 1: Experimental setup of biosensor. AChE immobilization. Gold electrode chip was first cleaned with piranha solution (H2SO4:H2O2 in volume ratio 3:1), for 10 minutes. Thereafter, the electrode chip was well rinsed with ultrapure water and imme- Immobilization layers Electrode layers Figure 2: AChE immobilized gold electrode. AChE Glutaraldehyde Cysteamine Gold Chrome Pyrex 234 V. Furlan et al; Informacije Midem, Vol. 48, No. 4(2018), 229 - 233 diately immersed in cysteamine, glutaraldehyde aqueous solution and in AChE solution as described in [12]. Schematic description of resulting sample structure is shown in Figure 2. 2.4 Measurement procedure AChE activity measurement. AChE hydrolyses ATCl to acetate and thiocholine chloride (TChCl) which can be further measured spectrophotometrically [13]. Standard spectrophotometric Ellman colorimetric assay [14] was used to check the efficacy of the enzyme immobilization procedure on the gold surface. Test gold plated glass with 0.2 cm2 had AChE immobilized as described previously. The absorbance of yellow product 5-thio-2-nitrobenzoate (TNB) was measured after reaction time of 10 minutes and the product quantity was evaluated using the Lambert-Beer law as Eq. 1 [15]: Product quantity = AV el (1) where A is absorbance at 405 nm, V is volume of the sample (products TChCl, Ellman's reagent, K-P buffer), £ known molar extinction coefficient of TNB (£ = 14,150 M-1cm-1 [16] and l is the beam length in the sample, respectively. In our case parameters were: V = 250 ^L, l = 0.75 cm. CV and CA techniques [17] were applied to measure enzyme activity on immobilized gold electrode chip. In the case of measurement by CV, the input voltage was scanned from -0.1 V to +0.6 V, with potential step of 0.01 V and scan rate of 0.06 V/s. CA measurement was carried out at DC potential of 0.4 V. Measurements, if not specified differently, were performed 10 minutes after exposure substrate ATCl to AChE enzyme. Substrate was dissolved in K-P buffer and solution of ferri-cyanide with KCl. Sequence of reactions occurring at an AChE biosensor is shown schematically in Figure 3. The result of the ATCl hydrolysis is the electrochemically active TChCl, which exchanges an electron with an electrochemical mediator ferricyanide when passing from reduction to oxidation state. Mediator transfers the electron to the electrode via redox reactions. Oxidation and reduction process on cyclic voltammogram are referred to solid and dashed lines in Figure 3, respectively [18, 19]. Electrons on the electrode are detected by external electrical circuit (potentiostat). AChE inhibition measurement. AChE biosensor is based on enzymatic inhibition mechanism. Eserine as analyte inhibits the normal enzyme function. The enzyme inhibition is therefore determined by the difference in measured electric currents in the absence (0) and presence (i) of eserine. The inhibition is calculated as Eq. 2 [20]: Inhibition = (i0 - ) / i0 (2) Figure 3: Sequence of reactions occurring at AChE biosensor. Measuring protocol of AChE inhibition was performed in three steps. The biosensor was immersed in the substrate ATCl solution and solution of ferricyanide with KCl, for 10 min and the signal i0 was measured (step 1). Then, the AChE biosensor was rinsed three-times with the K-P buffer solution (step 2) and immersed in a new substrate and ferricyanide solution with eserine addition for reaction and incubation time of 10 min, then residual activity i. was measured (step 3). 3 Results and discussion Activity of the immobilized enzyme was evaluated spectrophotometrically by measuring the quantity of produced thiocholine chloride product. The activity was monitored in time period of 12 days (Figure 4). From Figure 4 it can be seen that after 33% initial decrease of enzyme activity in five days, the activity remained steady for at least one week. The reason for large initial loss of activity can be attributed to stabilization of biostructure or incomplete covalent binding of the enzyme, surface defects and impurity of enzyme. After confirming immobilized enzyme activity by Ellman's method, AChE biosensor performance was investigated by CV and CA measurements on biosensor 235 M. Kikelj et al; Informacije Midem, Vol. 48, No. 4(2018), 241 - 247 electrode structure. Figure 5 shows CV response obtained in absence and in presence of ATCl. Time (day) Figure 4: Spectrophotometrical measurement of time dependent AChE activity. Potential vs. Ag/AgCl, 3 M KCl reference (V) Figure 5: Cyclic voltammogram obtained in absence (solid line) and in presence of substrate ATCl (discontinuous line) in the presence of redox couple ferri/ferro-cyanide. The reaction with substrate refer to ATCl hydrolysis, catalysed by the enzyme AChE. Addition of ATCl causes an increase in concentration of TChCl and consequently of the ferrocyanide, resulting in an increase of the anodic peak current. On the contrary, the cathodic peak current is proportional to the amount of ferricyanide that decreases after the addition of ATCl. This can be seen in Figure 5, where anodic peak current I increases and cathodic peak current I decreases with pa 1 pc time of TChCl present. Therefore, we can determine a ratio I /I . The ratio of the peak currents is equal to one pa pc for reversible system of ferro/ferri-cyanide, shown by solid line in Figure 5. Larger peak current difference is obtained for reaction with ATCl, shown by dashed line in Figure 5, for the reaction time of 95 min. The corresponding ratio of the peak currents was therefore determined as 3.1. This confirms higher rate of oxidation and consequently concentration of produced TChCl. Figure 6 shows measured current by CA technique and fitted result (solid line) versus ATCl concentration. (a) __1 mM ATCl ____5 mM ATCl ........10 mM ATCl 2 3 4 5 6 7 Time (s) (b) 3 4 5 6 7 [ATCl] (mM) Figure 6: Selected chronoamperometric curves (a) from which (at 10 s) calibration plot of ATCl using the AChE biosensor is constructed (b). Relation between electrical current and concentration of substrate ATCl was assumed to follow MichaelisMenten kinetics (Eq. 3) [21], being aware that many other factors can affect the results [22]: V Vmax ] K +[5 ] (3) where V0 is initial velocity, V^ is maximum velocity, [S] is substrate concentration, and KM is Michaelis constant. According to the curve fit of measured points in Figure 6 (solid line), the calculated apparent Michaelis constant Km°pp = 2.6 ± 0.9 mM was determined. Finally, after determining production of TChCl by AChE biosensor, AChE inhibition was chronoamperometri-caly detected by using well-established commercially available AChE inhibitor eserine. The inhibition of AChE was determined by measuring the decrease of the CA signal, which is consequence of eserine addition to the ATCl substrate solution. Result of inhibition for 25 mM of concentration of eserine is presented in Figure 7. 1.0 4 2 E 6 4.5 4.C 3.5 30 3.C 25 3.2.5 20 2.C 15 a. 10 C.5 -15 236 M. Kikelj et al; Informacije Midem, Vol. 48, No. 4(2018), 241 - 247 < 6 3 c 5 0) 3 4 3 V Initial enzyme activity ■ no eserine ■ eserine inhibition â— Residual enzyme ■ ' activity ■ 0 10 20 30 40 50 60 70 80 Time (min) Figure 7: Study of AChE inhibition by eserine. Both, initial enzyme inhibition in value of 70% and recovery of AChE activity are presented in Figure 7. After 10 minutes of inhibition by eserine, samples were repeatedly rinsed and re-measured, noting the significant recovery of the signal. Note that each measurement, presented in Figure 7, lasted only 10 s, while time on x-axis shows the total time of experiment duration. It can be seen that recovery of AChE activity increases almost linearly with time (20 to 68 min) when system was not exposed to eserine, recovering to 59% and 39% of inhibition at 42 and 68 min, respectively. An important kinetic parameter of inhibited AChE is the reactivation factor Kreact. By applying Perola's equation (Eq. 4), the reactivation factor K „ was calculated ^ " " react from the inclination of the linear plot obtained by monitoring the inhibition as a function of time [23]: ln f Inhibition ^ v Inhibition0 y Kreactt (4) where Inhibition0 is the first measured current after inhibitor addition, which corresponded to t = 0 of the de-carbamoylation phase, and Inhibition( is the inhibition determined as a function of time during the enzyme activity recovery phase. Kreact of 0.016 min-1 was determined, and it is in good agreement with the literature data [24]. 4 Conclusions The AChE electrochemical biosensor is presented. It is successfully applied for detection of eserine as an example of choline inhibitor in water. Spectrophotometric measurements have shown that five days after AChE immobilisation on gold surface activity of an enzyme decreased for 33% and then remained stable an extended period of time. Biosensor was evaluated via CV and CA measurements. CV measurement of enzyme activity resulted in asymmetric cyclic voltammogram, i.e. increase of anodic peak current and decrease of cathodic peak current (ratio 3:1). This confirms higher rate of oxidation and consequently concentration of produced TChCl. Moreover, relation between electrical current and concentration of substrate ATCl up to 10 mM were assumed to follow Michaelis Menten kinetics. Apparent Michaelis constant was determined as 2.6 ± 0.9 mM. Our results have shown that 25 pM eserine inhibits the activity of AChE for 70%. Reactivation factor of 0.016 min-1 was determined, showing reversibility of AChE inhibition by eserine. Presented work is to be further extended to determine biosensor sensitivity, reliability and concentration dependent inhibition of eserine and other AChE inhibitors. 5 Acknowledgments The authors acknowledge the financial support from the Slovenian Research Agency (research core funding No. P2-0244 and contract No. 1000-18-0510 - with Faculty of Electrical Engineering). Work was partly financed by Mediterranean Institute for Monitoring in the frame of collaboration with Biotechnical Faculty. 6 References 1. 2. 3. 4. 5. A. P. F. Turner, 'Biosensors: sense and sensibility', Chemical Society Reviews, vol. 42, no. 8, p. 3184, 2013. https://doi.org/10.1039/c3cs35528d L. C. Clark and C. Lyons, 'Electrode systems for continuous monitoring in cardiovascular surgery', Annals of the New York Academy of Sciences, vol. 102, no. 1, pp. 29-45, Oct. 1962. https://doi. org/0.1111/j.1749-6632.1962.tb13623.x A. Amine, S. Cinti, F. Arduini, D. Moscone, and G. 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Brufani, 'Long chain analogs of physostigmine as potential drugs for Alzheimer's disease: new insights into the mechanism of action in the inhibition of acetylcholinesterase', Biochimica et Biophysica Acta (BBA) - Protein Structure and Molecular Enzymology, vol. 1343, no. 1, pp. 41-50, Nov. 1997. https://doi. org10.1016/S0167-4838(97)00133-7 Arrived: 31. 08. 2018 Accepted: 24. 10. 2018 238 Original scientific paper https://doi.org/10.33180/InfMIDEM2018.407 Informacije imidem Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 4(2018), 241 - 247 Orthodox Theory Monte-Carlo Simulation of Single-Electron Logic Circuits Miha Kikelj, Benjamin Lipovsek, Franc Smole University of Ljubljana, Faculty of Electrical Engineering, Ljubljana, Slovenia Abstract: In the past decades MOS based digital integrated logic circuits have undergone a successful process of miniaturisation eventually leading to dimensions of a few nanometres. With the dimensions in the range of a few atomic radii the end of conventional MOS technology is approaching. Amongst the prospective candidates for sub 10nm logic are integrated logic circuits based on single-electron devices. In our contribution we present the use of MOSES (Monte-Carlo Single-Electronics Simulator) as a method for simulation of complementary single-electron logic circuits based on the orthodox theory. Simulations of single-electron devices including a single-electron box, a single-electron transistor and a complementary single-electron inverter were carried out. Their characteristics were evaluated at different temperatures and compared to measurement results obtained at other institutions. The potential for room-temperature operation was also assessed. Keywords: single-electron logic circuits; single-electron transistor; Monte-Carlo; simulation; MOSES; voltage-state logic Monte-Carlo simulacija enoelektronskih logičnih vezij na podlagi Ortodoksne teorije Izvleček: V preteklih desetletjih je MOS tehnologija uspešno prestala proces miniaturizacije, kar je privedlo do dimenzij struktur v rangu nanometrov. Dimenzije, ki obsegajo le še nekaj atomski polmerov, bi lahko napovedovale konec konvencionalne MOS tehnologije. Kot eden izmed glavnih kandidatov za logična vezja, ki bodo delovala pri dimenzijah okoli 10nm in manj, se omenjajo logična vezja na osnovi enoelektronskih gradnikov. V našem prispevku bomo predstavili uporabo simulacijskega orodja MOSES (Monte-Carlo Single-Electronics Simulator), kot metode za simulacijo komplementarnih enoelektronskih digitalnih logičnih vezij na podlagi Ortodoksne teorije. Izvedli smo simulacije enoelektronskih struktur vključno z enoelektronsko škatlo, enoelektronskim tranzistorjem in komplementarnim enoelektronskim inverterjem. Njihove karakteristike smo ovrednotili pri različnih temperaturah in primerjali z izmerjenimi karakteristikami z drugih raziskovalnih ustanov. Ocenili smo tudi možnost delovanja enoelektronskih vezij pri sobni temperaturi. Ključne besede: enoelektronska logična vezja; enoelektronski tranzistor; Monte-Carlo; simulacija; MOSES; logika stanj napetosti * Corresponding Author's e-mail: miha.kikelj@fe.uni-lj.si 1 Introduction In the last 50 years since the invention of CMOS technology in 1963 the aforementioned technology has gained a huge advantage mainly due to its small power dissipation. Through the continuous process of miniaturisation the reduction of device dimensions from 5 ^m to 14 nm was achieved [1]. Conventional CMOS technology is bound to reach its limits in the near future and in order to sustain device miniaturisation other technological options should be employed. One of the prospective candidates for the implementation of sub-10 nm digital logic circuits are digital logic circuits based on single-electron Coulomb blockade devices [2]. The possibility to manipulate electrons one by one should reduce the power dissipation and enable higher integration densities. Up to this point two implementation abilities have been explored. Voltage-state logic as a direct transfer of CMOS topology to single-electron devices [3] and charge-state logic in the form of binary decision diagram - BDD [4] circuits and quantum cellular automaton - QCA [5][6] circuits. In our contribution we explore the possibility of voltage state logic circuits design and analysis using the MOSES [2] Monte-Carlo simulator. Our focus will be mainly on 239 © MIDEM Society M. Kikelj et al; Informacije Midem, Vol. 48, No. 4(2018), 241 - 247 the implementation of logic functions with means of complementary single-electron logic circuits based on the Orthodox theory briefly described in Section 2. mentary single-electron inverter. Wherever possible we compared our results to measurements of a physical device with similar parameters taken at other institutions. 2 Orthodox theory and monte-carlo simulation In order for single-electron charging effects to become observable and for orthodox theory to apply two conditions should be met. Firstly charging energy should be much greater than thermal energy as depicted in equation (1). (1) This condition requires either feature sizes to be in the range of nanometres to minimise capacitances of the structure, or the operating temperature to be near the absolute zero. The second condition to be met is the condition of tunnel resistance Rt in equation (2). Rt = At - 4.2 kn q (2) Satisfying these conditions, one can analyse single-electron circuits according to the orthodox theory. Applying the theory, the tunnel rate r through an individual junction can be expressed by means of equation (3). 3.1 Single-electron box A single-electron box is the simplest single-electron structure. It consists of a single tunnel junction, coupled through a capacitance to a voltage source. The circuit is shown in Fig. 1 and circuit parameters used for simulation are given in the Table 1 below. V C 1 3 2 • :::: V2 = 0 Figure 1: Circuit of a single-electron box used for simulation. Table 1: Single-electron box circuit parameters used for simulation. r = AE q2 R, 1 - exp AE v kBT J) (B) As the orthodox theory assumes independence between individual tunnelling events and only one tunnelling event possible at a certain time, it is possible to describe the macroscopic behaviour of such circuit through a stochastic series of such tunnelling events. The process takes into account probabilities that a tunnelling event will occur at a certain point in time and the probabilities are weighted by the tunnelling rate r. Such a process is suitable for implementation within the Monte-Carlo method and is implemented in the MOSES simulator. 3 Simulation of single-electron structures Within our work we have analysed circuits of a single-electron box, single-electron transistor and a comple- Element Value C 9 aF Ctj 1 aF Rtj 1GG kO Vg G-5G mV - 0 K lO K 20 K 40 K / / • // 1 1.5 2 2.5 Q(3)/q Figure 2: Simulation results of a single-electron box at 25 mK. 3 2 l 0 0 3 240 M. Kikelj et al; Informacije Midem, Vol. 48, No. 4(2018), 241 - 247 Varying the voltage Vg from 0 to 50 mV, we observed a characteristic response of the circuit - Coulomb staircase, predicted by the orthodox theory. Simulation results are shown in Fig. 2. We could not find a real structure measurement to compare the results to, but we have found them comparable to an identical structure simulated by MUSES [7], which is another Monte-Carlo simulator. The characteristic Coulomb staircase is temperature dependent, since the thermal energy should not exceed the charging energy. Simulation of the temperature dependence of a Coulomb staircase is depicted in Fig.3. -o K 10 K 2o K 40 K 0 0.5 1 1.5 2 2.5 3 Q(3)/q Figure 3: Temperature dependence of the Coulomb staircase. 3.2 Single-electron transistor A single-electron transistor (SET) is a modification of a single-electron box. Adding another tunnel junction and a supply voltage source, we get the circuit presented in Fig. 4. In Table 2 element values used for simulation are presented. Values for the simulation were chosen according to the measurements in [8]. Varying the gate voltage Vg and supply voltage V as given in Table 2, we were able to obtain a stability diagram for the given transistor. The simulation was performed at 25 mK and a background charge at the central island of 0.3 electrons as observed in [8]. The addition of background charge was necessary to achieve agreement between simulations and measurements, since it shifts the stability diagram of a single-electron transistor. The obtained stability diagram is given in Fig. 5. Fig. 6 presents a measured stability diagram of a real single-electron transistor [8] with the same parameters. Table 2: Single-electron transistor circuit parameters used for simulation. Element Value Ctji 57.14 aF CtJ2 53.94 aF Cg 3.2 aF Rtj1, Rtj2 1GG kO Vg G-SG mV V G-2 mV D 10 I 3 Figure 5: Simulation of a SET stability diagram at 25 mK. 3.2.1 Temperature dependence As a single-electron transistor is just a variation of a single-electron box, its characteristics should also be temperature dependent. Taking 114.28 aF as a cumulative capacitance of the circuit in Fig. 4 towards the environment C, we were able to estimate the temperature, up to which Coulomb oscillations would be noticeable, according to equation (4). Figure 4: Circuit of a single-electron transistor used for simulation. T « q k d CV 16 K (4) 3 2 1 2.5 0 2 1.5 K 1 0.5 O g 241 M. Gradisek et al; Informacije Midem, Vol. 48, No. 4(2018), 249 - 254 Figure 6: Mesurement of a SET stability diagram at 25 mK [8]. To get a sense of the relation 'far less' in equation (4), we made a simulation of Coulomb oscillations at different temperatures and a supply voltage V of 1 mV. It was observed, that Coulomb oscillations become negligible at temperatures 3 times smaller as calculated. The results of the simulations are given in Fig. 7. 0 K --1, 25 ----2, 5 K --------5 K 10 20 30 40 50 Figure 7: Simulation of Coulomb oscillations at different temperatures. V = 1 mV. As the temperature dependence of the observed Coulomb oscillations may not pose a serious problem at this point, their impact of the characteristics of complementary single-electron logic circuits is quite significant. 3.3 Complementary single-electron inverter A complementary single-electron inverter is comprised of two single-electron transistors much as a conventional CMOS inverter. The two identical SETs with an additional controlling capacitance at the gate, act as a p-MOS or n-MOS equivalent, depending on the operating point set by the controlling electrodes. The schematic of a single-electron inverter circuit is shown in Fig. 8. The elements' values were once again taken from a real implementation of the device from [8] for easier comparison of the results. The parameters are given in Table 3. 1 TJi a) b) Figure 8: Complementary single-electron inverter a) and an electron microscope image of the realisation from [9] b). Table 3: Single-electron inverter circuit parameters used for simulation. Element Value CTJ1 - CTJ4 100 aF Cgl, Cg2 800 aF Cs1/ Cs2 686 aF RtJ1 - RTJ4 100 kO Vg 0-80 |V Vs 65 |V The simulation was performed at 25 mK and with no background charge at any of the nodes, since none was reported originally. Fig. 9 shows simulation results of a DC transfer characteristics compared to the measurement and SPICE simulation results obtained in [8]. Our simulated characteristic shows some deviations from the measured one and more closely corresponds to the characteristics obtained by SPICE. The difference is thought to be due to second-order effects namely cotunneling, since it is not simulated by MOSES and could result in a steeper characteristic than in reality. Second-order effects are most prominent near or in the Coulomb blockade region [10], where standard tunneling is negligible. Additional electron transmission L C 4 3 2 1 0 V [mV] g 242 M. Gradisek et al; Informacije Midem, Vol. 48, No. 4(2018), 249 - 254 90 80 70 60 ? 50 40 30 20 10 0 Figure 9: Simulated SET inverter characteristics at 25 mK from MOSES, SPICE [8] and the measurement of the device [8]. through the single-electron transistor induced by the cotunneling effect in the Coulomb blockade region could account for the gentler slope, since it inhibits charging and discharging of the load capacitor. Nearly perfect agreement between simulations and measurements outside of the transition region of the inverter, on the other hand, lets us believe that simulations at higher temperatures should show similar or even better agreement with real structures, due to the diminishing of the cotunneling effect with increasing temperature as observed in [11-12]. 3.3.1 Temperature dependence of DC transfer characteristic The temperature dependence of the inverter's transfer characteristic was evaluated using equation (4) where the cumulative capacitance towards its surroundings 1686 aF was taken as the value of Cr Taking into account the factor'far less'derived in the previous section, -200 mK -400 mK 10 20 30 40 5C 60 70 80 the maximum operating temperature was estimated to be around 360 mK. The simulation of the temperature dependence of the inverter's DC transfer characteristic is shown in Fig. 10. From Fig. 10 one can clearly see a continuous degradation of logic levels with increasing temperature, as well as a decrease in the absolute differential gain at the switching point. An inverter with such characteristics is clearly an inappropriate building block for larger logic circuits even at temperatures close to absolute zero, let alone at room temperature. 3.3.2 Single-electron inverter at room temperature The main goal in developing single-electron circuits is room temperature operation. According to the simulations from previous sections we have proposed a structure that when implemented, should exhibit single-electron effects even at room temperature. Using equation (4) and a factor 1/5 for the criterion 'far less' we have estimated the value of Cz to less than 1.2 aF. To meet the criterion we have scaled the values in Table 3 2000 times. The element values of the scaled inverter are given in Table 4 and the simulation of the DC transfer characteristics at different temperatures is given in Fig. 11. Table 4: Single-electron inverter circuit parameters used for simulation. Element Value CïJl - CTJ4 0.05 aF Cql, Cq2 0.4 aF Cs1i Cs2 0.343 aF 0 0.02 0.04 0.06 0.08 0.1 0. Figure 10: Temperature dependence of SET inverter characteristics. Figure 11: Temperature dependence of SET inverter characteristics. From Fig. 11 it is clearly visible, that the inverter characteristic is still observable at room temperature, even Vg [ M V] 0 V [V] g V UV] 243 M. Gradisek et al; Informacije Midem, Vol. 48, No. 4(2018), 249 - 254 though the differential gain at the switching point is already below 1. A strong degradation of logic levels is also visible. Despite the observable inverter characteristics at room temperature, the inverter would still not be capable to drive further logic stages. For that to become possible, the dimensions of the features composing the inverter would need to drop into the sub-nanometre region as predicted in [13]. The dimensions of a fabricated device with parameters from Table 4, where each island is shaped as a cube for simplicity, are given in Table 5. Fig. 12 presents a simplified layout of the device. Table 5: Dimensions of the single-electron inverter structure for parameters in Table 4 and Table 3. Dimension Length Table 4 Length Table 3 a 1 nm 1 nm b 2.38 nm 106 nm c 0.12 nm 0.12 nm d 0.15 nm 0.15 nm VH, a c b d a c a d V out CT a Figure 12: Proposed simple layout of a room temperature operable single-electron inverter. 4 Conclusions From the performed simulations it is clear, that single-electron circuits could be the next step in the integration and miniaturisation of logic circuits. One of the setbacks of complementary single-electron logic is the small dimension of the features comprising the single-electron circuits to achieve room temperature operation. Another possible setback is the degradation of the logic levels and thus the inability to drive further stages. The solution of the problem could be found in single-electron charge state logic, which defines logic levels with the presence of an electron and not with the voltage level as do complementary single-electron circuits. Two of the possible approaches already in development are the use of QCA (Quantum Cellular Automaton [5][6] and the BDD (Binary Decision Diagram) [4]. 5 References 1. V. K. Khanna, "Single Electronics," in Integrated Nanoelectronics, Pilani, India, Springer, 2016, pp. 247-269. https://www.doi.org/10.1007/978-81-322-3625-2 2. A. N. Korotkov,"Single-electron logic and memory devices," International Journal of Electronics, vol. 86, no. 5, pp. 511-547, 1999. https://www.doi. org/10.1080/002072199133256 3. K. Uchida, J. Koga, R. Ohba, et al., Programmable Single-Electron Transistor Logic for Future Low-Power Inteligent LSI: Proposal and Room-Temperature Operation," IEEE T. Electron Dev., vol. 50, no. 70, pp. 1623-30, July 2003. https://www. doi.org/10.1109/ted.2003.813909 4. S. Kasai in H. Hasegawa, "A single electron binary-decision-diagram quantum logic circuit based on schottky wrap gate control of a GaAs nanowire hexagon," IEEE Electron Device Letters, vol. 23, no. 8, pp. 446-448, 2002. https://www.doi.org/10.1109/ led.2002.801291 5. A. N. Bahar, S. Waheed, N. Hossain in M. Asaduzzaman, "A novel 3-input xor function implementation in quantum dot-cellular automata with energy dissipation analysis," Alexandria Engineering Journal, 2017. https:// www.doi.org/10.1016/j.aej.2017.01.022 6. S. Banerjee, J. Bhattacharya, R. Chatterjee, P. Bagchi, S. Mondal, R. Bandyopadhyay, R. Dutta in P. Das, "A novel design of 3 input 8 output decoder using quantum dot cellular automata," in Information Technology, Electronics and Mobile Communication conference (IEMCON), 2016 IEEE 7th Annual, pp. 1- 6, IEEE, 2016. https://www.doi. org/10.1109/iemcon.2016.7746340 7. A. A. Elabd, A.-A. T. Shalaby in E.-S. M. El-Rabaie, "Monte carlo simulation of single electronics based on orthodox theory," in Radio Science conference (NRSC), 2012 29th National, pp. 581591, IEEE, 2012. https://www.doi.org/10.1109/ nrsc.2012.6208569 244 M. Gradisek et al; Informacije Midem, Vol. 48, No. 4(2018), 249 - 254 8. R. van de Haar in J. Hoekstra, "Spice simulation of single-electron electronics compared to measurement results," in STW-ProRISC-IEEE Workshop, pp. 190-194, 2003. 9. C. P. Heij, P. Hadley, and J. E. Mooji., "Single-electron inverter," Applied Physics Letters, vol. 78, no. 8, pp. 1140-1142, 2001. https://www.doi. org/10.1063/1.1345822 10. C. Wasshuber, Computational Single-Electronics. Springer-Verlag Wien, 2001. https://www.doi. org/10.1007/978-3-7091-6257-6 11. S. De Franceschi, S. Sasaki, J. M. Elzerman, et al., "Electron cotunneling in a semiconductor quantum dot," Physical review letters, vol. 86, no. 5, pp. 878-881, 2001. https://www.doi.org/10.1103/ PhysRevLett.86.878 12. R. Scheibner, E. G. Novik, T. Borzenko, et al., "Sequential and cotunneling behavior in the temperature-dependent thermopower of few-electron quantum dots," Phiysical Review B, vol. 75, no. 4, pp. 041301, 2007. https://www.doi. org/10.1103/PhysRevB.75.041301 13. K. K. Likharev, "Single-electron devices and their applications," Proceedings of the IEEE, vol. 87, no. 4, pp. 606-632, 1999. https://www.doi. org/10.1109/5.752518 14. R. H. Chen, D. M. R. Kaplan in O. Turel, Monte-Carlo Single-Electronics Simulator 1.2 USERS'S GUIDE, 2001. 15. MOSES. Monte-Carlo Single-Electronics Simulator, available from R. H. Chen (rchen@felix. physics.sunysb.edu) Arrived: 31. 08. 2018 Accepted: 24. 12. 2018 245 246 Original scientific paper https://doi.org/10.33180/InfMIDEM2018.408 Informacije imidem Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 4(2018), 249 - 254 Digitally Adjustable Differential Gain Stage Miha Gradisek, Drago Strle Laboratory for Microelectronic, University of Ljubljana, Faculty of Electrical Engineering, Ljubljana, Slovenia Abstract: Most ASIC's demand signal conditioning sub-circuits to modify various signal parameters; one of the important parameter is the gain. The presented configuration is based on the conventional R-2R structure which mainly suffers from the mismatch imperfections. The study shows possible approach to improve mismatch characteristic or enables us to take the advantage to increase bit resolution without mismatch deteriorations. The approach could be used to even further improve accuracy of the numerous previously described approaches [1], [2] which already eliminate high resolution mismatch imperfections. Paper presents the implementation of the gain stage with digital gain adjustment, in the range from 0.9 to 1.1 in 128 equidistant monotonous steps, nevertheless the approach could be implemented even for higher resolution stages. For robust design in terms of the fabrication process and harsh environment operation, a fully differential amplifier was designed in standard 0.18^m CMOS technology. Designed amplifier in combination with resistive network is presented together with simulation results including the parasitic capacitances. Keywords: digitally adjustable gain; resolution improvement; R-2R stage; deferentially balanced structure Digitalno nastavljiva diferencialna ojačevalna stopnja Izvleček: Večina namenskih integriranih vezij potrebuje podsklope vezij, ki skrbijo za obdelavo signalov in njihovih parametrov; pomemben parameter je ojačenje. Predstavljena konfiguracija bazira na konvencionalni R-2R strukturi, ki je znana po nezanemarljivem vplivu neidealnosti ujemanja elementov vezja. Študija predstavlja možen pristop za izboljšavo teh karakteristik oziroma nam omogoča povečanje ločljivosti ne da bi se pri tem poslabšale karakteristike ujemanja. Pristop se lahko uporabi na že znanih rešitvah za odpravo neidealnosti [1], [2] in tako še dodatno izboljša ločljivost. Delo predstavlja implementacijo ojačevalne stopnje z digitalno nastavljivim ojačenjem od 0.9 do 1.1 v 128 ekvidistančnih monotonih korakih, vendar bi se lahko podoben pristop uporabil tudi za stopnje z večjo ločljivostjo. Robustno delovanje glede na proces izdelave in obratovale pogoje je dosežen z diferencialnim ojačevalnikom dizajniranim v standardni 0.18^m CMOS tehnologiji. V članku je predstavljen načrtan ojačevalnik v kombinaciji z uporovnim vezjem skupaj s simulacijskimi rezultati vključujoč parazitne kapacitivnosti. Ključne besede: digitalno nastavljivo ojačenje; izboljšanje ločljivosti; R-2R stopnja; diferencialno uravnotežena struktura * Corresponding Author's e-mail: miha.gradisek@fe.uni-lj.si 1 Introduction Common part of numerous analog ASIC's (Application Specific Integrated Circuits) incorporate circuits for signal conditioning. Modification of signal amplitude through gain adjustment presents one of the most frequently used approach. Several implementations are possible. In analog implementations the gain is changed using some nonlinear element in the feedforward or feedback path; the problem of such implementations is large distortions of the signal. In narrow band systems, this is acceptable, however, in our case, the system is wide band and thus analog nonlinear gain adjustment is not acceptable because we would like to achieve the distortions in the range of 0.01%. Thus, the only possibility is digital gain adjustment [3]. Each approach has associated advantages and disadvantages shortly described above. The important characteristics of the digital gain adjustment stage are: the resolution of gain steps, the responsivity, the distortions, the bandwidth, the area, and the final product cost. The paper investigates a possible approach for digital gain adjustment using the similar circuit as known from the R-2R DA converters. The implementation is based on the conventional R-2R ladder structure to adjust the gain through the binary weighted currents. Com- 247 © MIDEM Society M. Gradisek et al; Informacije Midem, Vol. 48, No. 4(2018), 249 - 254 pared to other structures it has some advantages (for example small area and fast switching) and some disadvantages (for example non-monotonicity) [4], where non-monotonicity is more evident at higher number of bits. The monotonicity performance of a higher resolution stages could be improved by a numerous approaches as a resistor laser trimming procedure, binary LSB and unary MSB algorithmic segmentation [2], ordered element matching [1] and others. Some of them contributes to more complex digital logic with interconnection considerations taking into account wiring placement as a result of on-chip gradients, while some others enlarge inevitable die area as a result of inability of analog component accuracy at shrunk dimensions [2]. Mismatch suppression could be achieved with increased dimensions of the unit resistors as described with the Pelgrom's Law [5]. Nevertheless monotonicity could be improved even without increment of the resistor dimensions at the expense of additional R-2R structure presented in this work. Approach take the advantage of the fully-differential interconnection of both structures which yields higher robustness [6]. A method which maintains monotonicity of the gain stage with higher number of bits in the ASICs with two anti-phase shifted input signals is proposed. The paper is organized as follows. Section 1 introduces the problem and explains why the R-2R structure is preferable. Section 2 describes the principle of operation, while Section 3 presents simulation results. Section 4 presents the layout and Section 5 concludes the article. 2 Circuit description 2.1 Principle of operation The principle schematics of a fully differential, digitally adjustable gain stage is shown in the Fig. 1. It consists of a resistive network composed of two R-2R ladder structures and feedback resistors. The adjustable gain stage provides the gain in the range from 0.9 to 1.1. R-2R determined adjustable gain (Gain=±0.1) is super-positioned to the constant one (Gain=1) determined by feedback resistors RFB1 and RFB2. To take the advantage of the proposed approach of doubling gain range, input signals inp and inn should be anti-phase shifted as differential structure suppresses in-phase signals. In the case when multiplexer directly translates the portion, determined by the bits, of the signal inp to the upper amplifier feedback resistor RFB2, the absolute amplitude of the output signal outn is increased and in contrary decreased in a case when the portion of the inn is crossed through a multiplexer and tied to the upper resistor RFB2. In this manner multiplexer with its switches permutates in-between two R-2R ladder structures and thus control whether the gain is increased or decreased. The proposed approach with differentially connected R-2R structures yields higher resolution compared to single-ended structure at the expense of increased die area. The stage has gain resolution equivalent to 7 bits. According to the desired gain, determined by the six bits b. (/=0,1,...5) plus additional one b6 for multiplexer (sign bit), the portion of the current from the R-2R structure is connected either to the signal ground or to the summing point at the input node of a differential amplifier. Resistor RFB2 in combination with differential TIA (trans-impedance amplifier) serves as a current to voltage converter. Two differential output signals are kept around the signal ground with a help of common mode feedback circuit (CM block in the Fig. 1). Output common signals are assured by a help of additional amplifier which compares the voltage VCM to the reference voltage (i.e. signal ground) and provides error correction through the feedback biasing signal Vcmb (Fig. 2). Figure 1: Simplified schematic of a fully differential, balanced, R-2R adjustable gain stage. 2.2 Resistive network The gain of the stage is composed of two super-positioned contributions. The constant one is determined by the ratio f/n of resistors RFB1 and RFB2 while the variable one is based on the adjustable R-2R stage determined by binary weighted currents delivered to the virtual ground of the TIA from the R-2R stage. Values of resistors are determined in a way to achieve a desired gain range from 0.9 to 1.1 in 128 equidistant monotonous steps. Desired gain steps can be realized according to (1) by setting unit resistors multiplication factors to k=153, n=16 and f=16 (see (1)). ( 5 Gain = - R, l ' (k + l)R 25-ii 2R (-1)+-T (1) nR, u J Unit resistance is selected appropriately to provide on one side sufficient accuracy and bandwidth, and on the other side to maintain low noise and low current con- 248 M. Gradisek et al; Informacije Midem, Vol. 48, No. 4(2018), 249 - 254 sumption. The resistors should exhibit high linearity (low voltage coefficient), small temperature coefficient, acceptable noise, small parasitic capacitance and good matching properties. This is accomplished by appropriate size of the unit resistor and appropriate layout. Considering mentioned parameters, high resistive poly resistor is used [4]. Unit resistance RU is composed of foundry minimal recommendation of five squares. Used high resistive poly resistor with sheet resistance of approximately 350 Q/W yields RU = 1.836 kO. 2.3 Switches In order to realize high accuracy of gain adjustment, it is essential to properly construct the switches as well. Weighted currents in the R-2R branches call for scaled switches from the one with a minimum conduction resistance for b5 to the switch with maximum resistance for b0, which has 32 times larger resistance compared to the switch b5. Nevertheless, maximum resistance of each switch should be much smaller than the unit resistance RU. To meet the switch conduction requirements, they should be adequately dimensioned. For the same reason, multiplexer switches should be properly designed as well. In general, large switches have relative large parasitic capacitance that affects the speed and stability. However, R-2R switches in the proposed approach do not experience any voltage change as they are tied to the signal ground node. This is convenient in terms of the system bandwidth. R-2R and multiplexer switches are constructed as transmission gates with complementary MOSFETs with different dimensions to maintain approx. linear resistance over different voltages. In addition, dummy MOSFETs are added to the nodes, to reduce the clock feedthrough effect and off channel charge injection during switching and to ensure the same loading of all driving lines, thus to mitigate the gain transition glitches. Remaining imperfections during gain adjustment are empirically determined by simulations and solved with time delayed control lines through buffered inverters. 2.4 Differential trans-impedance amplifier Fully differential TIA with feedback resistances RFB2 converts currents out of the resistive R-2R network and RFB1 to two differential output signals. Since closed loop configuration impact overall system bandwidth and stability, the TIA is based on the folded cascode architecture (Fig. 2). Sufficient unity-gain bandwidth is needed to overcome the gain variations at the frequency of the signal. Poorly designed TIA, in terms of bandwidth, can at high frequencies cause large gain variations. TIA is composed of a PMOS differential pair (M3, M4) with tail current of 200^A, which is distributed between two NMOS transistors (M5, M6). Each of them drains additional current of 40 ^A from PMOS load (M7, M8). To clearly present configuration, additional cascode transistors for performance improvement are missing in the simplified schematic. Output stage is based on the common source configuration with Miller compensation. Figure 2: Transimpedance amplifier based on the folded cascade architecture. TIA must be stable under all conditions, therefore a differential and common mode stability is assured using appropriate frequency compensation circuitry. It should be properly designed using appropriate feedback capacitor CFB (Fig. 1), which implements low pass filtering characteristics. This capacitance compensates influence of the parasitic capacitance of the switches in the R-2R ladder structure. 3 Simulation results The circuitry is designed in TSMC 180nm CMOS technology and characterized using Cadence Virtuoso environment. Process verification includes all process corners: typical, low-slow, slow-fast, fast-slow, fast-fast and/or statistical variations: MC, MM; complete temperature range from -40°c to 150°c and supply voltage range from 3V-5V. Principle of operation of gain adjustment is presented in the Fig. 3. The gain is equal to 1 when the bits b5-b0 Figure 3: Gain adjustment: (a) signal at the output of the amplifier, (b) status of controlling bits b0 to b5, (c) status of multiplexer bit b6. 249 M. Gradisek et al; Informacije Midem, Vol. 48, No. 4(2018), 249 - 254 are set to low independently of the multiplexer bit b6. When b6 is low, enabled b0-b5 bits increase the gain up to 1.1 and when b6 is high the gain is decreased from 1 down to 0.9 in 127 equidistant steps. Figure 4 shows transient response to 500 kHz input square signal. The system settles 2^s after power-on. Figure 4: Transient response at gain: 0.9, 1 and 1.1 for 500 kHz square-wave input signal. Implementation with two 6-bit R-2R ladder structures yields better accuracy as one with single 7-bit R-2R structure. In the Fig. 5, the matching accuracy of two 7-bits R-2R ladder based structures are presented. Fig. 5(b) shows LSB gain variations for proposed approach with two 6-bit R-2R structures and multiplexer which implements the b6 compared to the previous design [4] with one 7-bit R-2R structure presented in Fig. 5(a). One 6-bit R-2R structure provides adjustable gain range of 0.1 which is doubled over constant gain of 1 with a help of an additional 6-bit R-2R and multiplexer, while 7-bit R-2R have to provide an adjustable gain range of 0.2 above the constant gain of 0.9. Distribution of the LSB gain shows improvement of the standard deviation of the proposed approach compared to the previous one for approximately 40%. Figure 5: LSB gain variation: (a) mismatch of the previous design and (b) mismatch for proposed approach. Closed loop AC characteristics of the amplifier with digital gain adjustments are presented in the Fig. 6, for gains set to 0.9, 1 and 1.1. At higher frequencies, the gain characteristics starts to distort as a result of process influence to the gain bandwidth of the TIA. Nevertheless, closed-loop gain characteristics at low frequencies are mainly affected by the mismatch contribution of the R-2R structure [7]. It is evident in the case when an ideal amplifier is used and R-2R mismatch is the main contributor to the overall gain variations, which are listed in the Table 1. Table 1: Influence of process and mismatch variations on the LSB gain using real and ideal TIA. Real amplifier Ideal amplifier Std. dev. Std. dev. Std. dev. Std. dev. @ 100kHz @ 500kHz @ 100kHz @ 500kHz Process 8.20E-05 1.83E-03 1.42E-07 3.46E-06 Mismatch 2.90E-04 4.58E-04 2.82E-04 2.82E-04 Figure 6: Closed-loop characteristic for the gain stage with gain variations 0.9, 1 and 1.1. Figure 7 shows open loop differential AC characteristics. Most critical phase margin of 53° is met at 12.7MHz for 3V power supply, fast-fast corner and at temperature of 150°C. Fig. 8 shows AC characteristics for common mode feedback signal (VCM). It shows stable behavior and provides the appropriate output common signal. Figure 7: Differential open-loop gain and phase characteristics. The offset of the complete gain stage is generated inside the TIA, as a result of the mismatch of the MOSFETs in the input differential stage. Offset distribution based on Monte-Carlo simulation is shown in the Fig. 9. The maximum input offset is 3mV and is included in the evaluation of the system performance. 250 M. Gradisek et al; Informacije Midem, Vol. 48, No. 4(2018), 249 - 254 4 Layout Figure 8: Open-loop gain and phase characteristics of the common mode feedback signal VCM. Figure 9: TIA input offset for mismatch variations. The CMRR behavior of the gain stage with added input offset voltage of 3mV is shown in the Fig. 10. The presented characteristics show that the amplifier input offset deteriorate CMRR performance as it is proportional to the invert value of the offset [8]. Figure 10: CMRR with and without added offset. The important parameter is also a phase shift at the highest frequency of 500 kHz. The worst phase shift of 14° happens as expected at the largest gain, for supply voltage of 5.5V, at 150°C and max process variation of the R-2R structure. This deviation could be trimmed in the separate process of the phase shifting. Typical power consumption is 660 ^A at 3.3V supply voltage, typical process parameters and 25°C. It is increased to 860 ^A at 5.5V supply voltage, fast-fast process parameters corner and at 150°C. The layout of the stage is presented in the Fig. 11. It is symmetrical. As already mentioned, the R-2R implementations are prone to glitches during gain switching. Appropriate control logic is realized in a way to equalize digital control signals delay. The resistors mismatch is improved by using the optimum width of the resistors (RU dimensions 4^mx20^m). In addition, the surrounding of all resistors must be the same, which is achieved using appropriate dummy resistors that reduce the edge effects. Analog inputs are shielded from the digital signals. For higher accuracy, sensitive current mirrors and differential stage of the TIA are protected with additional dummy devices. Signal ground tracks are wide enough to minimize voltage drops across the gain stage. Overall silicon area occupies approximately 0.2 mm2. Figure 11: Layout of adjustable gain ratio cell. 5 Conclusions This paper presents design, optimization and implementation of a digitally adjustable gain stage, based on R-2R structure. Proposed approach yields performance improvements in terms of the accuracy compared to the previous realizations. Designed TIA is implemented in a way to provide sufficient bandwidth of the system together with the parasitic contributions of the resistive network and switches. The characteristics of the amplifier are verified in terms of process and mismatch variations as well as supply voltage and temperature. 6 References You Li, Tao Zeng, and Degang Chen, 'A high resolution and high accuracy R-2R DAC based on ordered element matching', in 2013 IEEE 251 M. Gradisek et al; Informacije Midem, Vol. 48, No. 4(2018), 249 - 254 International Symposium on Circuits and Systems (ISCAS2013), Beijing, 2013, pp. 1974-1977. https:// doi.org/10.1109/ISCAS.2013.6572256 2. G. Radulov, P. Quinn, H. Hegt, and A. H. M. van Roermund, Smart and Flexible Digital-to-Analog Converters. Dordrecht: Springer Netherlands, 2011. https://doi.org/10.1007/978-94-007-0347-6 3. W. Xu, R. Zhang, and C. Shi,'Research of segmented 8bit voltage-mode R-2R ladder DAC, 2015, pp. 1-4. https://doi.org/10.1109/ASICON.2015.7517105 4. Miha Gradisek, Janez Trontelj, and Drago Strle, 'High precision adjustable gain stage', Conference proceedings 2017, pp. 102-107, 2017. 5. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, 'Matching properties of MOS transistors, IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989. https://doi.org/10.1109/ JSSC.1989.572629 6. A. Abba, A. Manenti, F. Caponio, and A. Geraci, 'High Performance Analog Front-End for Digital Spectroscopy', IEEE Transactions on Nuclear Science, vol. 57, no. 4, pp. 2173-2177, Aug. 2010. https://doi.org/10.1109/TNS.2010.2049658 7. M. P. Kennedy, 'On the robustness of R-2R ladder DACs', IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 47, no. 2, pp. 109-116, Feb. 2000. https://doi. org/10.1109/81.828565 8. Jian Zhou and Jin Liu, 'On the measurement of common-mode rejection ratio', IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, no. 1, pp. 49-53, Jan. 2005. https://doi.org/10.1109/ TCSII.2004.838332 Arrived: 31. 08. 2018 Accepted: 27. 12. 2018 252 Original scientific paper Informacije (midem lournal of M https://doi.org/10.33180/InfMIDEM2018.409 Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 4(2018), 255 - 261 Multiparameter miniature fiber-optic sensor: design and signal interrogation Simon Pevec1, Borut Lenardic2, Denis Donlagic1 1University of Maribor, Faculty of EE & Computer Science, Maribor, Slovenia 2Optacore d.o.o., Ljubljana, Ljubljana, Slovenia Abstract: Miniature, all-silica, fiber-optic sensors capable of independent measurement of at least two different parameters are presented. Sensors were produced by a micromachining process based on the selective etching of specially designed phosphorous-doped optical fibers and an assembly-procedure that included fiber cleaving, fiber splicing and etching of fiber-micro-assemblies. Furthermore, an efficient method for independent readout of parameters in sensors that are composed of multiple resonators was also developed. The method utilizes a discrete Furrier transform of sensor's optical spectrum and allows for simultaneous, crosstalk-free and highly sensitive readout of individual resonators' path length changes. Keywords: Optical sensors; micromachinin; microstructures; discrete Fourier transform. Večparametrični miniaturni optični vlakenski • • y , ... 7 7 y • senzorji: načrtovanje in signalno razločevanje Izvleček: V članku so predstavljeni miniaturni, optični, vlakenski senzorji, ki lahko neodvisno zaznavajo najmanj dva različna parametra. Senzorji so izdelani s postopkom mikroobdelave na osnovi selektivnega jedkanja posebnih z fosforjem dopiranih optičnih vlaken. Ti postopki so združeni s standardnimi postopki rezanja, varjenja in jedkanja. Poleg tega je predstavljena učinkovita metoda za neodvisno branje parametrov senzorja, ki združuje več zaporedno nanizanih resonatorjev. Metoda vključuje diskretno Fourierjevo transformacijo optičnega spektra, ki omogoča simultano in zelo občutljivo razločevanje sprememb posameznih optičnih dolžin resonatorjev. Ključne besede: Optični senzorji; mikroobdelava; mikrostrukture; diskretna Fourierjeva transformacija. * Corresponding Author's e-mail: simon.pevec@um.si 1 Introduction Optical fiber-based sensors have received a great deal of attention over the past several decades for increased sensitivity over existing techniques, geometric versatility, immunity to harsh environments, and inherent compatibility with optical fiber communication systems. The rising complexity of sensor systems, methods often require sensing of more than one physical or chemical parameter. In particular, multi-parameter fiber-optic sensors that monitor physical, chemical, and biological parameters are of great importance in numerous areas including structural health monitoring, environmental pollution control, biochemical and biomedical applications [1-4]. Miniaturization brings additional challenges in cases of small sensing devices designs, as those devices are more sensitive to oxidation and other degradation processes. A variety of multi-parameter sensors have been proposed recently including Fiber Bragg grating [5], Fabry-Perot interferometer (FPI) [6], higher-order-mode fiber based modal interferometer sensors [7], evanescent field sensors [8], surface plasmon resonance sensors [9] and combination between them [10]. Beside them, there are also some other techniques involving multicore fibers, that have high potential for multiparameter sensing [11]. In this paper we present all-silica multiparameter miniature fiber-optic Fabry-Perot (FP) sensors for measuring at least two parameters simultaneously. Sensor design, signal interrogation and achieved performance is presented and discussed for following multiparameter sensors: - sensor for pressure and temperature [12] - sensor for pressure and refractive index [13] 253 © MIDEM Society S. Pevec et al; Informacije Midem, Vol. 48, No. 4(2018), 255 - 261 - sensor for refractive index and temperature [14] - sensor for relative humidity and temperature [15] - sensor for pressure, temperature, thermal conductivity and refractive index [16] All sensors demonstrated high measurement resolution with negligible cross-talk among measured parameters. We successfully demonstrated simultaneous measurement up to four very different physical parameters. In addition, efficient method for independent readout of different parameters of multiple resonators was also presented. The method base on discrete Furrier transform of sensor's back reflected optical spectrum that allows simultaneous, crostallk-free and highly sensitive measurements of resonators' path length change. 2 Mathematical model and signal processing of fabry-perot multiparameter sensor The model of the multiparameter sensor, which was used in simulations to illustrate the cross-talk between different frequency components and effect of applied Gaussian window, will be presented below. Sensor is composed from three semi reflective surfaces, which forms three FP resonators. The first two are shown in the Fig.1 as Lt and L, while the third resonator L3 represents their sum. The basic principle of the operation of an individual FP resonator or interferometer can be explained by the light wave that enters the resonator, where it is reflected or interfered between the two surfaces. The magnitude of the light current or the shape of the spectral characteristic is effected by: the distance L between mirrors, the wavelength of light A and the refractive index n of the transmission medium. Because in our case we have several FP resonators in the series, we can use one-dimensional space, where the superposition of the optical wave can be presented with a trigonometric approach. Figure 1: Model of FPI. In general, the optical wavelength in some point can be described as a function of time: E = E0 sm{M ±qj) (1) This can be written in the complex space as: E = E0eJ (at ±f) (2) First, three waves overlapping in space of the same frequency and speed must be add together. The following waves are summed up after the reflection from the mirrors in the lead-in fiber: j (at p = p r . ejat 03 -^y' 3 ^ E02 — Ey '3 r^^l 0Č3 ' e E01 — Ef'3'2 -OjV1 ~a2 ' e (3) j (at+%) Where E03, E02, and E01 are individual components of the electrical field strength, that are reflected from individual semi-reflective surfaces, Ev is the input amplitude of the electric field strength, r is coefficient of reflectivity and t is transmission coefficient, and the coefficient a is reserved for describing the optical losses on the splice. The phase changes corresponded to the interferometer's optical path length variations: ^=kn=2nLn/A, in our case, we have already defined it as a phase change due to a reflection from a distant mirror, which doubling the optical path, and thus the phase of the wave. ft = 4nn2L2 A 4n(n2L2 + n,L,) < =—^—^ + n (4) When optical waves travels cross the glass / air boundary, or vice versa, an additional phase shift occurs for n / 2, so in our example, when we observe the reflected wave, this is taken into account with the phase delay n (equation 4). The current description covers only electric field strengths that do not include transmission coefficients t of individual mirrors on the way back. This is supplemented by the following terms: E — E — E r • j E2 — Eq2^3 O} — EJ3 r2 (1 ) • e E~i — Eoi?3?2^/l 1J1 aa — — Ejltl r (1 - a3 )(1 -a2) • eJ (at+*2) (5) 254 S. Pevec et al; Informacije Midem, Vol. 48, No. 4(2018), 255 - 261 Where E3, E2 and E1 represent the total electrical field strength, which is reflected from the individual semi-reflective mirror, as shown in Fig. 1. Furthermore, the total electrical field strength can be written as the sum of all three components: Er — E3 + E2 + El J61t Er — Evr3-e}61 + Evt32r2(1-a3) ■ei{at+n 2 + +Ef3tlr1 (1 - a )(1 - a2 ) ■ ei[m+