UDK 621.3:(53+54+621 +66)(05)(497.1 )=00 ISSN 0352-9045 Strokovno društvo za mikroelektroniko elektronske sestavne dele in materiale Strokovna revija za mikroelektroniko, elektronske sestavne dele in materiale Journal of Microelectronics, Electronic Components and Materials INFORMACIJE MIDEM, LETNIK 36, ST. 2(118), LJUBLJANA, junij 2006 Jûîei Stefan institute 4th European Microelectronics and Packaging Symposium with Table-Top Exhibition and Satellite Workshop on Ferroelectric Thin- & Thick-films Processing and Their Applications in MEMS May 21-24,2006 Terme Čatež, Slovenia Society tor Microelectronics, Electronic Compcnents and Materials UDK 621.3:(53+54+621 +66)(05)(497.1 )=00 ISSN 0352-9045 INFORMACIJE MIDEM 2 o 2006 INFORMACIJE MIDEM LETNIK 36, ŠT. 2(118), LJUBLJANA, JUNIJ 2006 INFORMACIJE MIDEM VOLUME 36, NO. 2(118), LJUBLJANA, JUNE 2006 Revija izhaja trimesečno (marec, junij, september, december). Izdaja strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale - MIDEM. Published quarterly (march, june, september, december) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Glavni in odgovorni urednik Editor in Chief Dr. Iztok Sorli, univ. dipl.ing.fiz., MIKROIKS d.o.o., Ljubljana Tehnični urednik Executive Editor Dr. IztokŠorli, univ. dipl.ing.fiz., MIKROIKS d.o.o., Ljubljana Uredniški odbor Editorial Board Dr. Barbara Malič, univ. dipl.ing. kern., Institut Jožef Stefan, Ljubljana Prof. dr. Slavko Amon, univ. dipl.ing. el., Fakulteta za elektrotehniko, Ljubljana Prof, dr. Marko Topič, univ. dipl.ing. el., Fakulteta za elektrotehniko, Ljubljana Prof. dr. Rudi Babič, univ. dipl.ing. el., Fakulteta za elektrotehniko, računalništvo in informatiko Maribor Dr. Marko Hrovat, univ. dipl.ing. kern., Institut Jožef Stefan, Ljubljana Dr. Wolfgang Pribyl, Austria Mikro Systeme Intl. AG, Unterpremstaetten Časopisni svet Prof. dr. JanezTrontelj, univ. dipl.ing. el., Fakulteta za elektrotehniko, Ljubljana, International Advisory Board PREDSEDNIK-PRESIDENT Prof. dr. Cor Claeys, IMEC, Leuven Dr. Jean-Marie Haussonne, EIC-LUSAC, Octeville Darko Belavič, univ. dipl.ing. el., Institut Jožef Stefan, Ljubljana Prof. dr. Zvonko Fazarinc, univ. dipl.ing., CIS, Stanford University, Stanford Prof. dr. Giorgio Pignatel, University of Padova Prof. dr. Stane Pejovnik, univ. dipl. ing., Fakulteta za kemijo in kemijsko tehnologijo, Ljubljana Dr. Giovanni Soncini, University ofTrento, Trento Prof. dr. Anton Zalar, univ. dipl.ing.met., Institut Jožef Stefan, Ljubljana Dr. Peter Weissglas, Swedish Institute of Microelectronics, Stockholm Prof. dr. LeszekJ. Golonka, Technical University Wroclaw Naslov uredništva Uredništvo Informacije MIDEM Headquarters MIDEM pri MIKROIKS Stegne 11,1521 Ljubljana, Slovenija tel.: + 386(0)1 51 33 768 fax: + 386 (0)1 51 33 771 e-mail: Iztok.Sorli@guest.ames.si http://www.midem-drustvo.si/ Letna naročnina znaša 12.000,00 SIT, cena posamezne številke je 3000,00 SIT. Člani in sponzorji MIDEM prejemajo Informacije MIDEM brezplačno. Annual subscription rate is EUR 100, separate issue is EUR 25. MIDEM members and Society sponsors receive Informacije MIDEM for free. Znanstveni svet za tehnične vede I je podal pozitivno mnenje o reviji kot znanstveno strokovni reviji za mikroelektroniko, elektronske sestavne dele in materiale. Izdajo revije sofinancirajo ARRS in sponzorji društva. Scientific Council for Technical Sciences of Slovene Research Agency has recognized Informacije MIDEM as scientific Journal for microelectronics, electronic components and materials. Publishing of the Journal is financed by Slovene Research Agency and by Society sponsors. Znanstveno strokovne prispevke objavljene v Informacijah MIDEM zajemamo v podatkovne baze C0BISS In INSPEC. Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™ Scientific and professional papers published in Informacije MIDEM are assessed into C0BISS and INSPEC databases. The Journal is indexed by ISI® for Sci Search®, Research Alert® and Material Science Citation Index™ Po mnenju Ministrstva za informiranje št.23/300-92 šteje glasilo Informacije MIDEM med proizvode informativnega značaja. Grafična priprava in tisk BIRO M, Ljubljana Printed by Naklada 1000 izvodov Circulation 1000 issues Poštnina plačana pri pošti 1102 Ljubljana Slovenia Taxe Perçue UDK621.3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 36(2006)2, Ljubljana ZNANSTVENO STROKOVNI PRISPEVKI PROFESSIONAL SCIENTIFIC PAPERS U.Kač: Načrtovanje preizkusljivosti mešanih analogno-digitalnih integriranih vezij 71 U.Kač: Design for Test of Mixed-signal Integrated Circuits J.Olenšek, J.Puhan, A.Burmen, S.Tomažič, T. Turna: Optimizacija integriranih vezij z algoritmom simuliranega ohlajanja 79 J.Olenšek, J.Puhan, A.Burmen, S.Tomažič, T. Turna: Optimization of Integrated Circuits by Means of Simulated Annealing Mohd S Sulaiman: Metodologija za doseganje optimalne zakasnitve, porazdelitve signala in porabe moči urinega omrežja vezij FPGA 85 Mohd S Sulaiman: A Methodology for Optimum Delay, Skew, and Power Performances In an FPGA Clock Network A.Assim, M.B.I.Reaz, M.Ubrahimy, A.F.Ismail, F.Choong, F.Mohd-Yasin: Pametni dom na osnovi umetne inteligence 91 A.Assim, M.B.I.Reaz, M.l.lbrahimy, A.F.Ismail, F.Choong, F.Mohd-Yasin: An Al Based Self-Moderated Smart-home G.Modrijan, M.Petkovšek, P.Zajec, D.Vončina: Merjenje lastnosti mehkomagnetnih materialov pri visoki stopnji magnetnega nasičenja 95 G.Modrijan, M.Petkovšek, P.Zajec, D.Vončina: Precise Characterization of Soft-magnetic Materials at High Saturation G.Bizjak: Meritve svetlobno-tehnlčnih veličin 102 G.Bizjak: Measurement of Photometric Quantities R.Zorko: 0 merilni tehnologiji z vidika podjetniškega mikrookolja 110 R.Zorko: About Metrology from Entrepreneurial Microenvironment Point of View POROČILA S KONFERENC 116 CONFERENCE REPORTS Simpozij EMPS2006 Symposium EMPS2006 NOVICE 119 NEWS MIDEM prijavnica 120 MIDEM Registration Form Slika na naslovnici: Konferenca EMPS2006 se je odvijala v Termah Čatež Front page: EMPS2006 was held in Terme Čatež VSEBINA CONTENT Obnovitev članstva v strokovnem društvu MIDEM in iz tega izhajajoče ugodnosti in obveznosti Spoštovani, V svojem več desetletij dolgem obstoju in delovanju smo si prizadevali narediti društvo privlačno in koristno vsem članom.Z delovanjem društva ste se srečali tudi vi in se odločili, da se v društvo včlanite. Življenske poti, zaposlitev in strokovno zanimanje pa se z leti spreminjajo, najrazličnejši dogodki, izzivi in odločitve so vas morda usmerili v povsem druga področja in vaš interes za delovanje ali članstvo v društvu se je z leti močno spremenil, morda izginil. Morda pa vas aktivnosti društva kljub temu še vedno zanimajo, če ne drugače, kot spomin na prijetne čase, ki smo jih skupaj preživeli. Spremenili so se tudi naslovi in način komuniciranja. Ker je seznam članstva postal dolg, očitno pa je, da mnogi nekdanji člani nimajo več interesa za sodelovanje v društvu, seje Izvršilni odbor društva odločil, da stanje članstva uredi in vas zato prosi, da izpolnite in nam pošljete obrazec priložen na koncu revije. Naj vas ponovno spomnimo na ugodnosti, ki izhajajo iz vašega članstva. Kot član strokovnega društva prejemate revijo »Informacije MIDEM«, povabljeni ste na strokovne konference, kjer lahko predstavite svoje raziskovalne in razvojne dosežke ali srečate stare znance in nove, povabljene predavatelje s področja, ki vas zanima. O svojih dosežkih in problemih lahko poročate v strokovni reviji, ki ima ugleden IMPACT faktor.S svojimi predlogi lahko usmerjate delovanje društva. Vaša obveza je plačilo članarine 25 EUR na leto. Članarino lahko plačate na transakcijski račun društva pri A-banki : 051008010631192. Pri nakazilu ne pozabite navesti svojega imena! Upamo, da vas delovanje društva še vedno zanima in da boste članstvo obnovili. Žal pa bomo morali dosedanje člane, ki članstva ne boste obnovili do konca leta 2006, brisati iz seznama članstva. Prijavnice pošljite na naslov: MIDEM pri MIKROIKS Stegne 11 1521 Ljubljana Ljubljana, junij 2006 Izvršilni odbor društva UDK621,3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 36(2006)1, Ljubljana NAČRTOVANJE PREIZKUSLJIVOSTI MEŠANIH ANALOGNO-DIGITALNIH INTEGRIRANIH VEZIJ Uroš Kač Institut Jožef Štefan, Ljubljana, Slovenija Kjučne besede: načrtovanje preizkusljivosti, mešana analogno-dlgitalna vezja, vgrajen samodejni preizkus, oscilacijska metoda Izvleček: V članku je obravnavana problematika načrtovanja preizkusljivosti mešanih analogno-digitalnih integriranih vezij. Predstavljeni so osnovni principi načrtovanja preizkusljivosti, ki jih je možno vgraditi v računalniška načrtovalska orodja preko takolmenovanlh nadzornikov pravil načrtovanja (ang. design rule checker). Omenjene so metode, ki temeljijo na meritvah parametrov Integriranega vezja, kot na primer meritev mirovnega napajalnega toka. Sledi opis tehnik, ki zagotavljajo dostop do globoko vgnezdenlh podsklopov. Obravnavani sta tudi problematika generlranja in vrednotenja analognih signalov v vezju ter zasnova vgrajenega samodejnega preizkusa. Zadnji del prispevka povzema osnovne značilnosti oscllacijske preizkusne metode. Design for test of mixed-signal integrated circuits Key words: design for test, mixed-signal Integrated circuits, built-in self-test, oscillation based test Abstract: The proliferation of consumer electronics increasingly determines the course of development of semiconductor technology. In this context analog and mixed-signal integrated circuits and systems are regaining Importance as electronic devices heavily rely on analog signal processing techniques. The semiconductor industry follows market demands by developing Increasingly complex application specific integrated circuits and systems. This introduces new challenges In the process of circuit design and results In numerous difficulties in assuring adequate product quality. The latter is becoming a severe problem as the established analog test procedures already represent one of the bottlenecks in the development of complex mixed-signal systems. Consequently, research of new techniques supporting a structured approach to the design of testable analog integrated circuits is increasing steadily. Due to the diversity of analog and mixed-signal designs various solutions are being explored. The main trends are described in the paper. The problem of circuit testing is tightly related to the circuit design process. The implementation of fast structures can be simplified and the quality of the ■ test procedure can be increased by applying design rules and procedures or design for testability (DfT) techniques. Numerous DfT techniques for mixed-signal Integrated circuits have been proposed in recent years. Although the basic concepts of various techniques can differ substantially, we can roughly classify them into design of support structures for implementation of external analog measurement methods and the design of structures for the implementation of analog built-in self-test (BIST). The second group of DfT techniques is expected to play a crucial role in future complex integrated circuits and systems as It eliminates some limitations related to the use of conventional automated test equipment and increases product reliability throughout its life cycle. The oscillation based test method (OBT) described in the last part of the paper belongs to the second group of DfT techniques. The method is based on the assumption that the tested circuit can be reconfigured into an oscillator. Faulty circuits can then be Identified by simply measuring the oscillation frequency and comparing it to a reference value obtained from a fault-free (i.e., "golden") circuit under the same operating conditions. The method assumes that the oscillation frequency is sensitive to those component parameters which determine the relevant characteristics of the tested circuit. The main issue in oscillation based circuit testing is the design of testability structures and circuit reconfiguration schemes, which provide for an efficient test implementation. In the paper, general principle of OBT is described and some more details are given on its application In analog filter testing. 1 Uvod Z naraščanjem kompleksnosti ter vse težjim dostopom do globoko vgnezdenih analognih podsklopov postaja preizkušanje integriranih vezij vse večji problem, zato jih je potrebno načrtovati tako, da jih bo možno učinkovito preizkušati. V industriji in akademskih ustanovah narašča število raziskav, katerih cilj je razvoj ustreznih tehnik in postopkov strukturiranega načrtovanja preizkusljivih analognih vezij. Pristope v grobem razdelimo na realizacijo struktur za izboljšanje vodljlvosti (angl. controllability) in spremljivosti (angl. observability) notranjih vozlišč analognih podsklopov ter na načrtovanje struktur, ki omogočajo izvedbo vgrajenega samodejnega preizkusa v integriranem vezju. Zaradi obsežnosti področja ne gre iskati splošne rešitve za vsa analogna vezja, temveč je bolj smiselno iskati učinkovite tehnike preizkušanja za posamezne razrede analognih vezij. V tem prispevku uvodoma povzemamo osnovne principe načrtovanja preizkusljivosti (angl. Design for Testability, ali okrajšano D1T), v nadaljevanju pa opisujemo izbrane pristope preizkušanja mešanih analogno-digitalnih vezij, ki so dosegli ustrezno pozornost v strokovni javnosti in se uveljavili v praksi. Zadnji del prispevka je namenjen oscilacijski preizkusni metodi, pri kateri smo tudi sami prispevali teoretske rezultate in jo uspešno uporabili v praksi. 2 Tehnološki izziv Pomanjkanje strukturiranih DfT tehnik načrtovanja analognih podsklopov postaja ena poglavitnih ovir nadaljnjemu razvoju mešanih integriranih sistemov. Ker jih proizvajalci praviloma preverjajo s funkcionalnim preizkušanjem, je optimizacija postopkov težavna in zahteva izkušene inženirje z odličnim poznavanjem problematike. Hkrati je zelo težko 345 U. Kač: Informacije MIDEM 36(2006)2, str. 71-346 Načrtovanje preizkusljivosti mešanih analogno-digitalnih integriranih vezij oceniti kvaliteto postopka, saj se funkcionalni preizkusi ne nanašajo neposredno na strukturne napake. Raziskovalci iz industrije in akademskih ustanov so si zato enotni, da je potrebno razviti ustrezne DfT tehnike, ki bi omogočile struk-turiran pristop k problemu preizkušanja analognih podsk-lopov že od začetnih faz načrtovanja proizvoda, /1 /, /2/, /3/, /4/. Nadalje bi razvoj učinkovitih analognih BIST struktur omogočil uporabo popolnoma digitalnih avtomatskih preizkuševalnih naprav (ang. Automatic Test Equipment -ATE), kar bi bistveno poenostavilo in pocenilo postopke proizvodnega preizkušanja. Iz napovedi Združenja industrije polprevodnikov/5/, lahko razberemo predvidene trende razvoja mešanih analogno-digitalnih DfT tehnik ter njihovo uporabo v bodočih kompleksnih SoC vezjih. V skladu z naraščajočimi potrebami industrije se je v preteklih nekaj letih občutno povečalo število raziskav na tem področju. V znanstveni in strokovni literaturi lahko tako zasledimo številne prispevke, ki obravnavajo različne analogne oziroma mešane DfT tehnike. Predlagani pristopi se medsebojno precej razlikujejo, kar izhaja predvsem iz lastnosti ciljne aplikacije, vendar pa je njihov skupni cilj izboljšanje preizkusljivosti kompleksnih mešanih integriranih vezij. Slika 1 skuša povzeti nekatere najbolj pogoste DfT tehnike in primere njihove uporabe. 3 Načrtovanje preizkusljivosti mešanih analogno-digitalnih vezij 3.1 Splošna DfT pravila Večina splošnih DfT pravil izhaja iz uveljavljenih tehnik načrtovanja analognih vezij oziroma iz predhodno pridobljenih načrtovalskih izkušenj. Osnovna pravila so: vezja delimo na podsklope (makro celice), zagotovimo vodljivost vhodov podsklopov, zagotovimo spremljivost izhodov podsklopov, omogočimo izključitev povratnih zank v analognih pod-sklopih, vgradimo digitalne spominske celice v stičišča analognih in digitalnih podsklopov, uporabimo standarden digitalni preizkusni vmesnik za izbiro načina delovanja vezja (normalno obratovanje ali preizkušanje). Tovrstna pravila je možno vgraditi v računalniška načrtoval-ska orodja, kjer lahko njihovo upoštevanje spremljamo preko t.i. "nadzornikov pravil načrtovanja" (ang. design ruie checker). Poleg splošnih DfT pravil lahko v to skupino uvrstimo tudi ukrepe, kot je upoštevanje pravil oziroma omejitev pri fizičnem razvrščanju elementov vezja. S tem lahko zmanjšamo verjetnost pojava določenih napak in tako izboljšamo preizkusljivost vezja /6/. 3.2 Podpora zunanjim merilnim metodam Drugo skupino DfT tehnik predstavljajo strukture za podporo postopkom preizkušanja, ki temeljijo na zunanjih meritvah parametrov integriranega vezja. Meritev mirovnega napajalnega toka (Iddq preizkušanje) je uveljavljena tehnika proizvodnega preizkušanja digitalnih vezij /7/. Njegova uporaba v mešanih integriranih vezjih zahteva upoštevanje ustreznih strategij delitve vezja na podsklope ter možnost ločene izključitve analognih jeder. To zagotavlja minimalen vpliv le-teh na mirovni tok vezja med preizkušanjem digitalnih podsklopov. Po drugi strani je možno meritve toka uporabiti tudi za preizkušanje analognih podsklopov vezja. Ker so nekatere analogne strukture, kot so tokovna zrcala ali generatorji prečnega (ang. bias) toka ali napetosti, posebej občutljive na naključno spreminjanje parametrov proizvodnega procesa, lahko pride tudi pri pravilno delujočih vezjih do občutnih odstopanj v velikosti električnih tokov v vezju. Posledica je maskiranje napak v vezju, čemur se lahko izognemo s ponovitvami meritev napajalnega toka ob vhodnih signalih nasprotne polaritete. Možna rešitev je tudi realizacija dodatnih strukturv nekaterih tipičnih analognih podsklopih. Avtorji v /8/in /9/tako predlagajo izvedbo dodatnih tokovnih zrcal v transkonduktančnih operacijskih ojačevalnikih (OTA), slika 2, s katerimi omogočimo meritev mirovnega toka analognega vezja z zunanjimi merilnimi instrumenti ali z vgrajenimi tokovnimi senzorji. Razvrstitev Primeri uporabe Hierarhični nivo uporabe Fizični opis vezja DfT tehnike za mešana vezja Shematski opis Opis na nivoju podsklopov Opis na nivoju sistema -► Pravila načrtovanja z upoštevanjem preizkusljivosti -i : —i—> Optimizacija razmestitve -► Načrtovanje struktur za lddx preizkušanje Strukture za podporo specifičnim merilnim postopkom --> —» Sw- Opamp strukture Postopki za izboljšanje vodljivosti / spremljivost! —► i— IEEE 1149.4 vodilo Naknadne spremembe vezja ADCbist, PLLb,st, AGC ---» Delni / popolni samodejni preizkus —► Rekonfiguracija vezja Sočasni preizkus 1- i —► —► Samodejno preverjanje Slika 1: DfT tehnike za mešana analogno-digitalna integrirana vezja 76 U. Kač: Načrtovanje preizkusljivosti mešanih analogno-digitalnih integriranih vezij Informacije MIDEM 36(2006)2, str. 71-78 jtM= cp v V,-h f......Vo! A J'n Preizkus: K,\b- ap,lnVt 'V.H 1 jI" Slika 3: operacijski ojačevalnik z možnostjo rekonfiguracije (sw-opamp) Podobno rešitev, ki temelji na rekonfiguraciji posameznih stopenj analognega filtra v navadne ojačevalne stopnje, predlagajo tudi avtorji v /13/. Ker je vtem primeru rekon-figuracija izvedena s stikali v osnovni poti signala, je lahko vpliv nelinearnih upornosti in parazitnih kapacitivnosti stikal na prenosno funkcijo sistema precejšen. Takšna rešitev zato zahteva podrobno analizo in upoštevanje vpliva stikal že med postopkom načrtovanja osnovnega analognega vezja. Med pogosteje uporabljane tehnike sodi realizacija namenskih preizkusnih analognih vodil. Načrtovalci z realizacijo le-teh omogočijo vodljivost in spremljivost analognih vozlišč na nivoju integriranega ali tiskanega vezja oziroma na nivoju sistema. Čeprav je osnovni princip uporabe preprost, pa je dejanska izvedba precej zahtevna. Pri načrtovanju tovrstnih struktur zato uporabljajo različne tehnike, kot so diferencialna vodila, vgrajeni gonilniki signalov (prilagoditev naimpedancooz. kapacitivno obremenitev vodila), ločevanje vodil za različne analogne podsklope (NF, RF) ter ozem-Ijene oklopne plasti nad in pod vodili, ki lahko pripomorejo k zmanjšanju motenj v merilnem postopku. Pri načrtovanju paje pomembna tudi uporaba standardnega preizkusnega vmesnika, ki lahko precej olajša pripravo potrebnega merilnega okolja in prenosljivost obstoječih preizkusnih programov na nove aplikacije. 3.4 Standard IEEE 1149.4 Konec leta 1999 je bil dokončno potrjen industrijski standard IEEE 1149.4 za mešano preizkusno vodilo (ang. Mixed-Signal Test Bus, /14/), ki se navezuje na že obstoječi in v praksi uveljavljeni standard za načrtovanje digitalnih vezij z robno preizkusno linijo (IEEE 1149.1 - Test Access Port and Boundary-Scan Architecture). Standard določa lastnosti analognega preizkusnega vodila in predpisuje osnovno preizkusno infrastrukturo sistema (slika 4). Bistvena značilnost standarda so t.i. analogne robne celice (ang. Analog Boundary Module - ABM), ki so nameščene med funkcionalne priključke analognega jedra in vhodne/ izhodne sponke vezja ter omogočajo povezavo analognih vozlišč z zunanjimi merilnimi instrumenti brez uporabe občutljivih merilnih sond. Standard poleg analogne infrastrukture predpisuje tudi obvezno krmilno logiko in osnovne načina delovanja analognih robnih celic. Poleg tega dopušča tudi različne razširitve infrastrukture, npr. z vgradnjo struktur za izvedbo analognega samodejnega preizkusa. 73 U. Kač: Informacije MIDEM 36(2006)2, str. 71-348 Načrtovanje preizkusljivosti mešanih analogno-digitalnih integriranih vezij Robni register Vth Vh VL Vq n n n Digitalna celica Analogno vodilo AB1 Analogni robni modul Digitalna celica izTDI jedro Nadzor stikal sponka vTDO Slika 4: arhitektura IEEE 1149.4 mešanega preizkusnega vodila Upoštevanje standarda omogoča bolj strukturiran pristop k načrtovanju preizkusljivih mešanih analogno-digitalnih vezij, vendar pa ima predlagana infrastruktura tudi nekatere slabosti. Med temi sta relativno omejeno frekvenčno in im-pedančno merilno območje, ki sta določeni predvsem z načinom izvedbe vgrajenega analognega vodila in pripadajočih analognih stikal v robnih celicah. Izbira najustreznejše tehnike je zato prepuščena načrtovalcu, ki mora pri tem upoštevati vpliv dejavnikov, kot so končne upornosti in parazitne kapacitivnosti MOS stikal, ali pa enosmerna odstopanja (offset) ojačevalnikov, tako na natančnost meritev kot na osnovne parametre analognega vezja. 3.5 Generiranje in vrednotenje analognih signalov v vezju Generiranje in vrednotenje analognih signalov z zunanjo merilno opremo vnaša nekatere omejitve v postopek preizkušanja vezij. Te so posledica omejenega frekvenčnega ali amplitudnega območja signalov, ki jih lahko prenašamo med merilnimi napravami ter integriranim vezjem (oziroma vhodi in izhodi vgnezdenih analognih podsklopov), občutljivosti prenosnih poti signalov na motnje ipd. Možno rešitev tega problema predstavlja generiranje oziroma vrednotenje analognih signalov v samem integriranem vezju. V tem primeru poteka prenos preizkusnih podatkov in merilnih rezultatov med vezjem in zunanjo preizkuševalno napravo v digitalni obliki. Ceno za možnost uporabe preprostejših digitalnih preizkuševalnih naprav plačamo z dodatno površino polprevodnika, ki je potrebna za realizacijo ustreznih analognih preizkuševalnih struktur v samem integriranem vezju. Izbira generatorja signala je odvisna od vrste preizkusa, ki ga želimo opraviti. Medtem, ko za preizkus določenih tipov vezij, kot so npr. analogno/digitalni (A/D) pretvorniki zadošča en sam vhodni signal, pa pri vezjih, kot so analogni filtri, običajno uporabljamo postopek preizkušanja z večfrekvenčniml vhodnimi signali. Haurie in Roberts sta v /15/predstavila izvedbo sinusnega oscilatorja, ki temelji na LDI (ang. Loss-less Discrete Integrator) rezonatorju in A2 modulatorju (slika 5). Oscilatorje možno skoraj v celoti realizirati z relativno preprostimi digitalnimi elementi, kot so registri, seštevalniki, multiplekserji in pomikalni registri, medtem ko je uporaba analognih struktur omejena na 1-bitni digitalno/analogni (D/ A) pretvornik (zadrževalnik ničtega reda) in preprost nizko-prepustni filter. Predlagano strukturo odlikuje visoko razmerje signal/šum (ang. Signal to Noise Ratio - SNR) kot tudi možnost generiranja večtonskih signalov. .........(*> *2 AE MUX - k<) k0 Slika 5: Generator sinusnega signala na osnovi DS modulatorja Preizkus A/D pretvornikov običajno obsega določitev integralne (INL) in diferencialne nelinearnosti (DNL) ter napake 76 U. Kač: Načrtovanje preizkusljivosti mešanih analogno-digitalnih integriranih vezij Informacije MIDEM 36(2006)2, str. 71-78 ojačanja in enosmernega odstopnaja pretvornika. Te parametre lahko določimo z analizo v frekvenčnem ali v časovnem prostoru kar vpliva tudi na izbiro oblike vhodnega signala. Pri meritvah v časovnem prostoru želimo na vhodu pretvornika uporabiti počasen, linearno naraščajoči signal. Primer realizacije generatorja tovrstega signala je predstavljen v /16/. Pri histogramskem (frekvenčnem) preizkusu /17/beležimo število ponovitev posameznih digitalnih kod na izhodu pretvornika ob periodičnem vhodnem signalu z znano amplitudno distribucijo, npr. sinusnemu ali trikotnemu signalu /18/. Vrednotenje odziva analognega vezja otežuje vsebovana nenatančnost analognih signalov. Zaradi tega moramo pri analizi odziva vezja na dani vhodni signal upoštevati vplive šuma in odstopanj v generatorju signala kot tudi dopustnih odstopanj parametrov preizkušanega vezja. Včasih lahko pri vrednotenju odziva preizkušanih podsklopov izkoristimo obstoječe D/A pretvornike in DSP jedra v Integriranem vezju /19/, /20/. Kadarto ni možno, je potrebno realizirati namenske preizkusne zmogljivosti, pri čemer pa skušamo čim bolj omejiti potrebno površino polprevodnika /21/. Realizacija A/D pretvornika visoke časovne in amplitudne resolucije je običajno v nasprotju z zahtevo po majhni površini: na eni strani poznamo hitre a velike flash A/D pretvornike, na drugi pa počasne pretvornike na osnovi sukcesivne aproksimacije, ki sicer zasedejo manjšo površino polprevodnika. Pod določenimi pogoji pa je možno realizirati pretvornike, pri katerih resolucija ni obratno sorazmerna hitrosti pretvorbe. Avtorji v /22/in /23/tako izkoriščajo periodičen odziv analognega vezja, ki tudi počasnim sukcesivnim A/D pretvornikom omogoča doseganje časovne resolucije, ki je primerljiva tistim pri veliko višjih frekvencah vzorčenja. Poleg klasičnih A/D pretvornikov lahko za analizo preizkušanega vezja uporabimo tudi druge strukture. Eno izmed možnosti predstavljajo t.i. analogni nadzorniki (ang. analogue checker). S pomočjo le-teh preverjamo določene parametre vezja glede na znan vhodni signal. Nadzorniki iz odziva vezja izločijo vrednost iskanega parametra in jo primerjajo z dvema referenčnima vrednos-tima (Pmin , PM« ), ki ustrezata zgornji in spodnji meji dopustnega odstopanja parametra od željene vrednosti, rezultat pa je preprost digitalni signal, ki javi prisotnost napake (go/no-go preizkus). Analogni nadzorniki običajno sestojijo iz vezja za izločanje iskanega parametra in pripadajočega primerjalnika, vendar pa se dejanska izvedba nadzornika razlikuje glede na vrsto obravnavanega analognega vezja, /24/, /25/, /26/. Ker je v praksi nemogoče ločeno primerjati vsako vzorčeno vrednost izhodnega signala z željeno vrednostjo, uporabljamo postopke komprimiranja analognih signalov. Želje-na lastnost struktur za komprimiranje analognih signalov je, da za dva različna vhodna signala ustvarijo dve različni signaturi, hkrati pa za dopustna odstopanja vhodnega preizkusnega signala tudi signatura ostaja v mejah pričakovanega območja, čeprav je mogoče signatura določiti s klasično A/D pretvorbo izhodnega signala in uporabo digitalnih tehnik komprimiranja z večvhodnimi signaturnimi registri (ang. Multiple Input Signature Register - MISR), so se nekatere druge strukture, /27/, /28/, izkazale za učinkovitejše glede na potrebno površino polprevodnika. V /29/so avtorji predstavili izvedbo generatorja analogne signature, v SC (ang. Switched-Capacitor) tehnologiji, ki lahko hkrati služi tudi kot generator preizkusnih signalov (slika 6). Potrebno površino polprevodnika lahko dodatno zmanjša souporaba funkcionalnih elementov vezja v preizkusni shemi. Slika 6: ABILBO - vgrajen observator analognih blokov 3.6 Vgrajen samodejni preizkus Z vgradnjo ustreznih zmogljivosti v integrirano vezje lahko omogočimo popolnoma avtonomno izvajanje preizkusnega postopka, ki ne zahteva nobene dodatne podpore s strani zunanje merilne opreme, z izjemo proženja začetka in spremljanja končnega rezultata preizkusa. Prednost takšnega pristopa je v zmanjšanju kompleksnosti (in cene) zunanje preizkuševalne naprave in možnosti sočasne izvršitve več ločenih vgrajenih preizkusov ter posledično skrajšanju časa celotnega preizkusa. Slabost je vsekakor povečanje polprevodniške površine vezja zaradi dodatne preizkusne infrastrukture ter omejena možnost obdelave analognih signalov. Pristopi k izvedbi vgrajenega samodejnega preizkusa analognih podsklopov se razlikujejo predvsem glede na njihov vpliv na funkcionalne elemente vezja ter glede na tehniko generiranja preizkusnih signalov in vrednotenja odziva preizkušanega analognega vezja. Razlikujemo lahko tudi med bolj ali manj strukturiranimi pristopi k načrtovanju BIST struktur. Prvi so bolj splošne narave in pripomorejo k skrajšanju načrtovalskega časa, običajno na račun večje potrebne površine polprevodnika. Nestrukturi-rani pristopi so prilagojeni specifičnim analognim vezjem in lahko ob manjši dodatni površini polprevodnika občutno izboljšajo preizkusljlvost vezja. Prilagoditev struktur specifičnemu vezju po drugi strani zahteva daljši čas načrtovanja. Največ pozornosti je bilo do sedaj posvečene izvedbi BIST struktur za A/D in D/A pretvornike, /31/, /32/, /33/, saj gre za pogosto uporabljane mešane analogno-digitalne podsklope s širokim naborom parametrov (ojačanje, INL, DNL, enosmerno odstopanje), ki po drugi strani zahtevajo obsežen in drag postopek preizkušanja. Primer strukturi-ranega pristopa k preizkušanju vezij, ki vsebujejo tako A/D kot D/A pretvornike je t.i. hibridni BIST(HBIST), ki gajev/ 30/predlagal Ohletz. Samodejni preizkus se izvede z vz- 73 U. Kač: Informacije MIDEM 36(2006)2, str. 71-78 Načrtovanje preizkusljivosti mešanih analogno-digitalnih integriranih vezij postavitvijo povezave med izhodom D/A in vhodom A/D pretvornika, medtem ko vhode D/A pretvornika vzbujajo vzorci iz vgrajenega LFSR (ang. Linear Feedback Shift Register) generatorja psevdo-naključnih vrednosti. Sočasno se v digitalni domeni izvaja analiza signature na izhodih A/D pretvornika. Med analognimi BIST pristopi velja posebej omeniti komercialne rešitve podjetij LogicVision ter Fluence Technology. Avtorja Sunter in Nagi iz podjetja LogicVision sta razvila adcBIST tehniko namenjeno preizkušanju A/D pretvornikov /34/, ki zahteva uporabo nekaterih dodatnih elementov: analognega multiplekserja na vhodu pretvornika, R-C vezja za glajenje vhodnega signala ter digitalnega bloka za generiranje preizkusnih vrednosti in procesiranje rezultatov pretvorbe. Elemente vključujemo v načrtovano vezje na nivoju blokov, zato pristop ne zahteva posegov v strukturo A/D pretvornika (slika 7). Digitalno vezje skrbi za generiranje vhodnega preizkusnega signala in za izračun koefi-centov polinoma tretjega reda. Slednji so določeni na podlagi najmanjše vsote kvadratov tako, da zagotavljajo prile-ganje polinoma dani sekvenci izhodnih vrednosti pretvornika. Koeficienti vsebujejo vso potrebno informacijo za določitev enosmernega odstopanja, ojačanja ter harmoničnega popačenja drugega in tretjega reda. Izračun parametrov se izvede digitalno in lahko poteka v ali izven integriranega vezja. Prednost pristopa je njegova odpornost na šum, variacije v proizvodnem procesu in nelinear-nosti na vhodu pretvornika, med slabosti pa sodi predvsem ne-izračunavanje dinamične in integralne nelinearnostl pretvornika. Poleg adcBIST ponujajo pri LogicVision tudi rešitev za preizkušanje digitalnih in analognih PLL struktur pod imenom pllBIST /35/. h __adcBIST ........ Preizkusni vmesnik Slika 7: Shematski prikaz adcBIST pristopa Podjetje Fluence Technology trži skupino analognih BIST rešitev pod skupnim imenom BISTmaxx. Skupina proizvodov obsega strukture za preizkušanje A/D (ADCBIST) in D/A (DACBIST) pretvornikov ter PLL struktur (VCOBIST). Medtem ko ADCBIST temelji na vgradnji namenskih zmogljivosti, ki omogočajo izvedbo klasičnega histogramske-ga preizkusa, pa DACBIST uporablja t.i. oscilacijsko tehniko za določitev pomembnih parametrov preizkušanega vezja. Oscilacijska tehnika temelji na možnosti pretvorbe preizkušanega vezja v oscilator, /36/, /37/, in na pred- 76 postavki, da napake v vezju vplivajo na frekvenco oscilacij. Naravna frekvenca transformiranega vezja je tako odvisna od dodanih zunanjih komponent ter od večine parametrov, ki določajo frekvenčno karakteristiko oziroma časovni odziv vezja. DACBIST predvideva transformacijo D/A pretvornika poljubne resolucije v eno-bitni D/A pretvornik ter priključitev negativne regulacijske povratne zanke na preizku-šano vezje. Frekvenco oscilacij določimo s preprostim vezjem, ki obsega eno-bitni A/D pretvornik (primerjalnik) In digitalni števec, preizkusna infrastruktura pa vključuje še Integrator analognega signala in ustrezno krmilno logiko (slika 8). Nekaj dodatnih besed namenjamo oscilacijski metodi in njeni uporabi pri preizkušanju analognih filtrov v naslednjem poglavju. Pri uporabi tehnik vgrajenega samodejnega preizkušanja analognih vezij lahko na koncu ugotovimo, da se s selitvijo preizkusnih zmogljivosti v samo integrirano vezje ustrezno povečuje tudi potrebna površina polprevodnika, kljub temu pa je za določene aplikacije to ena izmed ugodnejših rešitev, predvsem zaradi povečanja učinkovitosti preizkusnega postopka, skrajšanja časa preizkušanja vezja in pogosto tudi možnosti izvajanja preizkusov med obratovanjem sistema. Hkrati tudi trenutni trendi razvoja čedalje bolj nakazujejo potrebo po uporabi tovrstnih tehnik pri načrtovanju zanesljivih a cenovno ugodnih mešanih integriranih vezij in sistemov. 1-bitni O/A pretvornik Slika 8: Primer izvedbe DACBIST strukture 3.7 Oscilacijska metoda Oscilacijsko metodo /36/, /37/, /38/je možno uporabiti za preizkušanje različnih razredov analognih vezij. Pri tej metodi vzpostavimo pogoje, da vezje, ki ga želimo preizkusiti, zaoscilira. Izmerimo frekvenco oscilacij in jo primerjamo s frekvenco izmerjeno pod enakimi merilnimi pogoji na referenčnem vezju, za katerega vemo, da je brez napak. Ob predpostavki, da se morebitne napake v vezju odražajo v frekvenci oscilacij, tako lahko odkrivamo vezja z napakami. Splošni pristop k uporabi oscilacijske preizkusne metode je podan na sliki 9. Prelzkušano vezje običajno delimo na manjše podsklope, znotraj katerih izvedemo ustrezne ukrepe za vzpostavitev nestabilnega stanja in posledično oscilacij na izhodu podsklopa. Oscilacijska metoda je posebej privlačna za realizacijo vgrajenih samodejnih preizkusov saj običajno zahteva relativno Negativna povratna zanka Cg "h \rll.....r 4-flL ..r*. 1-bitni A'0 pretvornik šttvec 2"R"j ' i Rezultat U. Kač: Načrtovanje preizkusljivosti mešanih analogno-digitalnih integriranih vezij Informacije MIDEM 36(2006)2, str. 71-78 omejene posege v strukturo preizkušanega vezja, hkrati pa se izognemo potrebi po realizaciji namenskih struktur za generiranje preizkusnih signalov. Za vrednotenje odziva vezja pa zadošča že zelo preprosta struktura, ki jo lahko realiziramo z detektorjem nivoja analognega signala in digitalnim števcem. Preizkušeno veije fr„, reset Slika 9: Splošni pristop k uporabi oscilacijske metode Preizkušanje analognih filtrov pogosto temelji na dinamičnih meritvah frekvenčnega odziva vezja na vhodni signal spremenljive frekvence. Učinkovitost takšnega postopka je v veliki meri odvisna od izbire ustrezne oblike vzbujanja ter načina vrednotenja odziva. V primeru načrtovanja vgrajenega samodejnega preizkusa zahteva realizacijo ustreznih namenskih struktur, ki lahko občutno povečajo potrebno površino polprevodnika, poleg tega večina aplikacij zahteva uporabo generatorjev analognih signalov visoke stabilnosti in možnost generiranja večfrekvenčnih signalov. V zadnjih letih je bilo objavljenih več prispevkov, ki obravnavajo uporabo oscilacijske metode pri preizkušanju aktivnih analognih filtrov/38/. Predstavljene so bile nekatere rešitve za izbrane razrede aktivnih R-C filtrov, ki temeljijo na pretvorbi preizkušanega vezja v oscilatorsko strukturo s pomočjo vgrajenih stikal in dodatnih pasivnih elementov /39/, ali pa z uporabo zunanjega vezja, /40/. Poleg tega naletimo tudi na nekatere rešitve, ki obravnavajo specifična aktivna R-C vezja, /41/, /42/, in dokazujejo praktično uporabnost postopka v proizvodnem preizkušanju integriranih analognih filtrov. Uporaba oscilacijske metode je še posebej smiselna v primeru preizkušanja SC vezij, saj le ta že v osnovi vključujejo analogna stikala, torej je vezje pogosto možno trans-formirati brez večjih posegov v strukturo samega vezja oziroma že z zagotovitvijo ustreznih (digitalnih) krmilnih signalov. Huertas et al. so v /43/in /44/predstavili preizkusni postopek za specifično SC filtrsko vezje, ki temelji na uporabi oscilacijske metode. Oscilacijska struktura je zasnovana z uporabo dodatnega zunanjega vezja, ki v preizkusnem načinu zagotavlja obratovanje preizkušanega pas-ovnoprepustnega SC filtra v mejno stabilnem območju. Na podlagi analize pokritosti napak so tudi ugotovili, da lahko kakovost preizkusa izboljšajo z dodatnim preverjanjem am- plitude izhodnega signala. V /45/je predlagana rekonfi-guracijska shema oscilacijskega preizkusa pasovnopre-pustne SC stopnje, ki se nanaša na univerzalno Fleischer-Laker-jevo stopnjo drugega reda. Delo predstavlja posplošen pristop k načrtovanju struktur za izvedbo oscilacijskega preizkusa v tipičnih topologijah SC filtrskih stopenj. 4 Zaključek Reševanje problema preizkušanja je tesno povezano s postopkom načrtovanja vezja. Z upoštevanjem pravil, postopkov in tehnik načrtovanja, ki jih skupno označujemo kot načrtovanje preizkusljivosti, lahko bistveno olajšamo izvedbo in povečamo učinkovitost preizkusnega postopka. Na področju načrtovanja preizkusljivosti v mešanih ana-logno-digitalnih integriranih vezjih so bile v preteklih letih predstavljene številne rešitve, vendar pa so se le redke uveljavile v praksi. Posamezne tehnike se po svoji zasnovi precej razlikujejo, vendar jih lahko v grobem razdelimo na načrtovanje struktur za podporo zunanjim merilnim metodam in na načrtovanje struktur za izvedbo vgrajenega samodejnega preizkusa vezja. Cilj našega prispevka je bil predstaviti glavne sodobne že uveljavljene preizkusne metode, hkrati pa pokazati tudi na nekatere zanimive ideje in izhodišča za razvoj novih učinkovitih rešitev. 5 Literatura /1/ G.W. Roberts, "Metrics, Techniques and Recent Developments in Mixed-Signal Testing", Proc. IEEE/ACM Int'l Conference on Computer Aided Design, San Jose, CA, USA, 1996, pp. 514-521 /2/ G.W. Roberts, "Improving the Testability of Mixed-Signal Integrated Circuits", Proc. IEEE Custom Integrated Circuits Conference, Santaclara, CA, USA, 1997, pp. 214-221 /3/ R. Spina, and S. Upadhyaya, "Test Time Versus Design-for-Test Resources in Mixed-Signal Systems", Proc. IEEE International Mixed-Signal Testing Workshop (IMSTW96), CuebecCity, Canada, 1996, pp. 173-180 /4/ A. Lechner, M. Burbridge, A. Richardson, B. Hermes, "3DB Challenge for DfT, DfM, DOT & BIST Integration into Analogue and Mixed Signal ICs", Proc. IEEE Latin-American Test Workshop, Cancun, Mexico, 2001, pp. 194-199 /5/ Semiconductor Industry Association, International Technology Roadmap for Semiconductors, Edition 2003 /6/ J .A. Prieto, A. Rueda, I. Grout, E. Peralias, J.L. Huertas, A.M. Richardson, "An Approach to Realistic Fault Prediction and Layout Design for Testability in Analogue Circuits", Proc. Design, Automation and Test in Europe Conference (DATE'98), Paris, France, 1998, pp. 905-912 /7/ J.M. Soden, "IDDQ Testing: A Review", Journal of Electronic Testing: Theory and Applications, No. 3, 1992, pp. 291-303 /8/ I. Baturone, J.L. Huertas, S.Sanchez Solano, and A.M. Richardson, "Supply Current Monitoring for Testing CMOS Analog Circuits", XI Congreso de Diseño de Circuitos Integrados y Sistemas, Barcelona, Spain, 1996, pp. 231-236 /9/ I. Baturone, S. Sanchez Solano, A.M. Richardson, and J.L. Huertas, "Current-Mode Techniques for Self-Testing Analogue Circuits", Proc. IEEE International Workshop on IDDQ Testing, Washington D.C., USA, 1997 /10/ J.S. Matos, A.C. Leao, J.C. Ferreira, "Control and observation of analog nodes in mixed-signal boards", Proc. IEEE Int'l Test Conference (ITC'93), Baltimore, USA, 1993, pp. 323-331 73 U. Kač: Informacije MIDEM 36(2006)2, str. 71-78 Načrtovanje preizkusljivosti mešanih analogno-digitalnih integriranih vezij /11/ A.H. Bratt, A.M.D. Richardson, R.J.A. Harvey, and A.P. Dorey, "A design-for-test structure for optimising analogue and mixed signal IC test", Proc. European Design & Test Conference (ED&TW95), Paris, France, 1995, pp. 24-32. /12/ D. Vasquez, A. Rueda, J.L. Huertas, "A DfT methodology for active analogue filters", Proc. IEEE Mixed Signal Test Workshop (IMSTW'95), Grenoble, France, 1995 /13/ M. Renovell, F. Azais, Y. Bertrand, "A Design-for-Test Technique for Multi-Stage Analog Circuits", Proc. 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Roberts, "A BIST Scheme for a SNR, Gain Tracking and Frequency Response Test of a Slgma-Delta ADC", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 42, No. 1, 1995, pp. 1-15 /20/ E.K.F. Lee, "Reconflgurable Data Converter as a Building Block for Mixed-Signal Test", Proc. European Design & Test Conference (ED&TW97), Paris, France, 1997 /21/ M. Renovell, F. Azais, S. Bernard, Y. Bertrand, "Hardware Resource Minimization for Histogram-based ADC BIST', Proc. VLSI Testing Symposium (VTS'00), Montreal, Canada, 2000, pp. 247-252 /22/ K. Lofstrom, "Early Capture for Boundary Scan Timing Measurements", Proc. of the IEEE International Test Conference (ITC'96), Washington D.C., USA, 1996, pp. 417-422 /23/ A. Hajjar, G.W. Roberts, "A High Speed and Area Efficient On-Chip Analog Waveform Extractor", Proc. of the IEEE International Test Conference (ITC'98), Washington D.C., USA, 1998, pp. 688-697 /24/ R. Hajranl, B. Vinnakota, "Analog Circuit Observer Blocks", IEEE Trans, on Circuits a 100 000 16122 FE until cost < 50 124(1) 58 FE until cost < 10 2483 (2) 33595 2 best cost 8.07 7.37 FE until best cost 96912 (69) 47605 final FE > 100 000 47768 FE until cost < 10 3672 (3) 32014 FE until cost < 1 26688 (21) 34248 3 best cost 0.282 0.088 FE until best cost 41131 (32) 43877 final FE > 45 000 44164 Fig 3: Topology of the second circuit. . « outn CD- A bias o-00 j ¿Il Ti! If 6 Ob it Inpl Inn2 innl 11 c ilû [T Inp2 cml Ht 3H ¿rrt 1 qu pr ■ll~ Oütp -o Fig. 4: Topology of the third circuit. Table 3: Summary of the optimization cases: number of optimization parameters, number of design goals, and number of corner points. case K design goals corner points 1 12 7 1 2 15 14 14 3 17 32 17 ner points to account for different environmental conditions (supply voltage, temperature, process parameter variations, ...). Since every CF evaluation requires a separate circuit simulation for each corner point, a large number of simula- Since the modified COMPLEX method uses restarts and can explore several local solutions within the given number of CF evaluations, the number of the run in which a solution was found is given in brackets. The number of CF evaluations after which the COMPLEX method was manually stopped, is also given. The OSA method stopped automatically when the temperature reached its final value. Both tested methods were compared in terms of the solution quality and the number of CF evaluations (FE). The first case is the most simple of the three cases considered. It only has a few design goals and does not include corner points. It also has the least optimization variables. All this makes the solution space smaller and the CF less complex. For this case the modified COMPLEX method performed considerably better than OSA. It did however require more CF evaluations and several restarts to reach a good solution. In the second case multiple corner points and more design goals were considered. OSA outperformed the modified COMPLEX method in terms of solution quality and number of required CF evaluations. The third case has the largest number of optimization variables, design goals, and corner points, in this case OSA was also more successfull than the modified COMPLEX method. These results show that for simpler cases the modified COMPLEX method clearly Is a better choice. But when it comes to complex circuits, many design goals, and, above all, a large number of corner points, it does not perform as good as OSA. Not even restarts helped the COMPLEX method to find a better solutions than the one OSA found in a single run. 83 J. Olenšek, J. Puhan, A. Burmen, S. Tomažič, T. Turna: Informacije MIDEM 36(2006)2, str. 79-84 Optimization of Integrated Circuits by Means of Simulated Annealing 6 Conclusions A recently developed optimization method called Orthogonal Simulated Annealing (OSA) is described and compared against a version of the simplex algorithm (COMPLEX method). Both methods are first tested on a set of mathematical test functions. The results showed that OSA performs better when the CF has many local minima. On the other hand, the COMPLEX method is a good choice when finding a local minimum quickly is more important than finding a global minimum. OSA and modified COMPLEX method were then tested on three IC design cases. The results showed that on the simpler case the modified COMPLEX method using restarts outperformed the OSA method. As the problem complexity increased, the ability of the OSA to explore the search space more thoroughly resulted in better performance (compared to the modified COMPLEX method). But in order to obtain a good solution in a reasonable amount of time, probabilistic global convergence of the algorithm had to be sacrificed (modified generation mechanism and cooling schedule). Therefore there is no guarantee as to when and if the global minimum will actually be found. Nevertheless OSA is well suited to IC optimization and design, particularly for problems with many variables and corner points. 7 Acknowledgment The research has been supported by the Ministry of Higher Education, Science and Technology of Republic of the Slovenia within programme P2-0246 - Algorithms and optimization methods in telecommunications. 8 References /1/ Li-Sun Shu, Shinn-Ying Ho, A Novel Orthogonal Simulated Annealing Algorithm for Optimization of Electromagnetic Problems, IEEE transactions on magnetics, Vol. 40, No. 4, pp. 1790-1795, July 2004. /2/ M.J. Box, A new method of constrained optimization and a comparison with other methods, Computer Journal, Vol. 8, pp. 42-52, 1965. /3/ S. Kirkpatrick, C.D. Gelatt, M.P. Vecchi, Optimization by simulated annealing, Science, Vol. 220, pp. 1277-1292,1983. /4/ Yiu-Wing Leung, An orthogonal Genetic Algorithm with Quantization for Global Numerical Optimizaion, IEEE transactions on evolutionary computation, Vol. 5, No. 1, pp. 41-53, 2001. /5/ R.L.Yang, Convergence of simulated annealing algorithm for continuous global optimization, Journal of optimization theory and applications, Vol. 104, No. 3, pp. 691-716, 2000. /6/ SPICE OPUS circuit simulator homepage: URL: http://www.fe.uni-lj.si/spice/ , Faculty of Electrical Engineering, Electronic Design Automation Laboratory: URL: http://www.fe.uni-lj.si/edalab/\hspace{1 mm). /7/ PuhanJ, Bürmen A, TumaT. Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points, Canadian journal of electrical and computer engineering, Vol. 28 (3-4): pp. 105-111 JUL-OCT 2003. /8/ Bürmen A, Strle D, Bratkovic F, Puhan J, Fajfar I, Tuma T. Automated robust design and optimization of integrated circuits by means of penalty functions, AEU- International journal of electronics and communications, Vol. 57 (1), pp. 47-56,2003. univ. dipl. ing. el. Jernej Olenšek Univerza v Ljubljani, Fakulteta za elektrotehniko Tržaška 25, SI-1000 Ljubljana E-mail: jernej.olensek@fe.uni-lj.si Tel: (01) 4768 724 doc. dr. Janez Puhan Univerza v Ljubljani, Fakulteta za elektrotehniko Tržaška 25, SI-1000 Ljubljana E-mail: janež. puhan@fe. uni-lj. si Tel: (01) 4768 322 doc. dr. Arpad Burmen Univerza v Ljubljani, Fakulteta za elektrotehniko Tržaška 25, SI-1000 Ljubljana E-mail: arpadb@fides. fe. uni-lj. si Tel: (01) 4768 322 prof. dr. Sašo Tomažič Univerza v Ljubljani, Fakulteta za elektrotehniko Tržaška 25, SI-1000 Ljubljana E-mail: saso.tomazic@fe.uni-lj.si Tel: (01) 4768 432 izr. prof. dr. Tadej Tuma Univerza v Ljubljani, Fakulteta za elektrotehniko Tržaška 25, SI-1000 Ljubljana E-mail: tadej.tuma@fe.uni-ij.si Tel: (01) 4768 329 Prispelo (Arrived): 20. 02. 2006; Sprejeto (Accepted): 29. 05. 2006 80 UDK621,3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 36(2006)1, Ljubljana A METHODOLOGY FOR OPTIMUM DELAY, SKEW, AND POWER PERFORMANCES IN AN FPGA CLOCK NETWORK Mohd S Sulaiman Faculty of Engineering, Multimedia University, Selangor, Malaysia Key words: FPGA clock network, High performance, IC design, Low power design, CMOS Abstract: A methodology for FPGA clock network optimisation is presented. The algorithms for optimisation of clock skew, delay, and power considering slew rate constraint for an FPGA fixed-clock network are implemented and verified on SX 32 FPGA chip. Measurements indicated a 60% reduction in clock slew rate and a 22% improvement in power dissipation when compared to the results of the initial, un-optimised chip. Metodologija za doseganje optimalne zakasnitve, porazdelitve signala in porabe moči urinega omrežja vezij FPGA Kjučne besede: CMOS, FPGA, urina vezja, načrtovanje integriranih vezij, načrtovanje vezij z majhno porabo, CMOS Izvleček: V prispevku predstavljamo metodologijo za doseganje optimalnega delovanja urinega omrežja znotraj vezij FPGA. Algoritmi za optimizacijo zakasnitve, popačenja signala in porabe moči so bili uvedeni in preverjeni na vezju SX 32 FPGA. Meritve pokažejo 60% zmanjšanje v popačenju signala in 22% zmanjšanje porabe moči v primerjavi z rezultati pred optimizacijo. 1 Introduction Modern high performance VLSI systems are designed to work at a specific maximum clock frequency depending on their applications and the process technology used. One of the constraints in achieving maximum clock frequency is clock rise time {slewrate). The longest rise time in the clocking network limits the clock frequency (clock period) /1/. A clock network is responsible for distributing clock signal from an input pad to the clock input of each block in an IC (sink). The clock net should be able to maintain the clock signal integrity. The distribution of clock signal on the chip must be done while minimizing the clock delay, clock skew, and slew rate /3/. Clock delay is defined as the maximum delay from the clock source to the input of any logic block. Maximum clock skew is defined as the difference between the longest clock delay and the shortest clock delay in the system. To achieve minimum slew rate while maintaining clock signal integrity, minimum number of buffers are added into the clock tree. This technique also helps to reduce clock delay and clock skew. Proper buffer placement and buffer sizing minimizes the slew rate. Capacitive load of the driven gates/logic blocks (gate load) and parasitic loads of signal line (wiring load) are among the factors that affect clock slew rate, delay and power dissipation. Since power consumed by the clock network contributes a major portion of the total chip's power consumption /4/, reducing the clock net power consumption will have tremendous effect in system's overall power consumption. Research works in the buffered clock network mainly focused on the minimization of clock delay and clock skew. As far as this work is concerned, previous works have not addressed the problem of clock delay, skew, and power optimisation with slew rate constraint. Work in /1 / emphasized on generating a clock network and optimising clock delay and skew without considering power performance while work in /3/ focused on inserting minimum number of buffers in clock trees with skew and slew rate constraints. The latter assumes that the clock tree will be buffered by a single type CMOS buffer. No doubt, this strategy helps to reduce clock skew and skew sensitivity to process variation. It, however, requires a balanced tree network, which is not applicable to FPGAs. The simultaneous change of buffer size and wire width to optimise performance and power in /5/ assumes that buffer locations are already given; i.e. clock tree Is already buffered. This technique is useful in minimizing delay and power but it does not consider any slew rate constraint. Although the work done, in /6/ can significantly reduce the clock delay and clock skew, it does not consider the effect buffer insertion has on slew rates and power dissipation. Additional capacitive loading imposed by adding buffers into the clock tree will increase the slew rates and power dissipation, which is not desirable, especially for high-speed mobile applications. Based on these observations, this paper proposes an optimisation methodology for optimum clock delay, skew, and power performances for a given slew rate constraint. For this work, several constraints are considered and a few assumptions are made: Buffers can be inserted at tree nodes only due to the FPGA physical layout constraint. 359 Informacije MIDEM 36(2006)2, str. 85-90 M. Sulaiman: A Methodology for Optimum Delay, Skew, and Power Performances in an FPGA Clock Network The maximum clock slew rate Is 0.5 ns, and the maximum allowable clock delay is 2.5 ns for CMOS 0.35-um technology. The clock tree will be buffered by buffer of different sizes due to loading considerations. The outline for the remainder of this paper is as follows. Problem formulation is discussed in Section 2. In Section 3, the algorithm that solves the initial buffer insertion problem Is presented. Algorithm for delay and slew rate optimisation by changing buffer position is discussed in Section 4. Section 5 discusses the buffer sizing strategy for simultaneous clock delay, skew, slew rate, and power optimisation. Section 6 explains the wire width sizing technique for delay reduction. Section 7 contains the simulation results and comparisons. Conclusions are presented In Section 8. 2.1 Definitions The definitions of the terms that will be used in the later sections are as follows: Unbuffered Clock Tree (UBT): a clock tree T(V,E) consisting of wires (edges) E and nodes V with no buffers between the source and sink nodes (initial clock tree). Buffered Clock Tree (BFT): a clock tree T(V,E) after buffer insertion. Wire (E): an internal signal line connecting logic block's input to its output. Node (V): a point that connects two logic blocks together An FPGA is made up of z number of logic blocks (x rows x y columns, where x x y = z, input-output (I/O) blocks, and programmable Interconnects (see Fig. 1 ). Logic blocks can be either logic modules or flip-flops (see Fig. 2 (a) and (b), respectively). The circuit models for this work are as shown in Fig. 3 and Fig. 4. Each clock tree branch (vertical column) consists of logic blocks and a driverto drive the clock signal to all the logic blocks in the column (see Fig. 4). Logic blocks are modelled as a series RC-circuit while the vertical wires are modelled as a tc-RC circuit (see Fig. 3). The resistance R for the two models (series 7t-RC and RC) is given by the following formula: The capacitance in the RC-circuit that models the logic block for CMOS 0.35-um technology is 21.2 fF (calculated based on the 3D modelling technique described in /7/). mmmmm LOGIC BLOCKS PATH 3 PATH I Fig. 1. FPGA Building Blocks Horizontal wires are modelled as a PI-RC circuit (see Fig. 3). Wire resistance is calculated as follows: R = - h Wt p +R mt erconnect (2) h where Lh = horizontal length of logic module Wh = horizontal width of logic module r = sheet resistance of signal line Rinterconnect= resistance of interconnect The capacitance is found to be 23 fF (based on the method described in /7/). R = (1) where L = length of Logic Module W= width of vertical track for the path of clock signal inside the logic block r = sheet resistance of signal path Figure 5 shows the sketch of the proposed technique for simultaneous optimisation of clock delay, skew, and power with slew rate constraint. The overall algorithm is shown in TABLE 1. /'. Initial Buffer Insertion: Inserts different number of buffers in each source-to-sink for a UBT depending on the slew rates of that path. 86 M. Sulaiman: A Methodology for Optimum Delay, Skew, and Power Performances in an FPGA Clock Network Informacije MIDEM 36(2006)2, str. 85-90 DO O D1 O D2 O D3 O DB -a Y A Q- A0 BO Al B1 (a) (b) Fig. 2. FPGA Logic Blocks: (a) Logic Module; (b) Flip-flop Fig. 3. RC Model for Logic blocks and wire /'/'. Delay & Power Optimisation (Slew Rate Constraint) - modified /6/ Buffer locations are optimised to minimize clock delay. Buffer sizes in the BFT are changed accordingly to minimize slew rate, should there be a need to do so. iii. Delay & Skew Optimisation by Buffer Sizing - proposed by /5/ and /6/, modified to consider slew rate constraint Fig. 4. Column model Path by path, buffer sizes are changed to change the delay of each path/column. iv. Wire sizing approach to optimise power, skew, and delay Wire widths are changed to see the effect on clock delay, skew, and optimisation. Table 1 - Overall optimization algorithm Get slew rates and delay of every path Do Initial Buffer Insertion while flag = TRUE Do Delay and Power Optimization (Buffer Positions) if slew rates < tmax. Do Delay & Skew Optimization (Buffer Sizing) flag = FALSE else flag = TRUE Do Slew Rate Minimization (change size of Bk.[) end end Do Skew & Power Optimization (Wire Sizing) 87 Informacije MIDEM 36(2006)2, str. 85-90 M. Sulaiman: A Methodology for Optimum Delay, Skew, and Power Performances in an FPGA Clock Network Initial Buffer Insertion In this section, Initial Buffer Insertion problem is discussed. Initial Buffer Insertion Problem: Given a UBT and a maximum clock delay, clock skew, and slew rates, determine the number of buffers to be inserted in each path (source to sink) such that slew rate is less than tma* of 0.5 ns. That is, number of buffers in each path = f(slew rate) To solve the initial buffer insertion problem, given a slew rate constraint, the paths are first sorted in ascending order according to the maximum path clock delay, i.e. tdeiay_pi (tpathjmn) < tdelay_P2 < ■ ■■ < tdelay_P20 < tdelay^P21 (tpath_max). Next, the size of column driver is reduced by a factor of two. We then measure the maximum slew rate of every path, starting with the shortest delay path, i.e. path 1. If the slew rate is less than tmax, no buffer is inserted in that path. However, if the slew rate is greater than tmax, one buffer is inserted right In the middle of the clock path. The maximum slew rate for the path is then measured. If it is still greater than tmax or if the rise time improvement is less than 15%, we remove the buffer and start increasing the size of column driver until the goal is achieved. If there is at least 15% improvement in path slew rate but it is still greater than tmax,, another buffer is inserted. This time the two buffers are placed such that they divide the clock path in three equal-length sections. The buffer insertion step is repeated until the slew rates for all paths are less than tmax. In general, if we have k buffers in a path, they should be arranged such that they divide the path in k+1 equal sections. For instance, consider three paths in the FPGA chip shown in Fig. 1. Initially, the slew rates for paths 1, 3, and 21 are 482 ps, 583 ps, and 940 ps, respectively. After the size of column driver has been reduced by a factor of two and one buffer has been inserted in path one, the slew rate is reduced by only 5%. Therefore, we remove the buffer in path 1 and start increasing the size of column driver (see Fig. 4). The final result for path 1 is that the slew rate is less than 0.5 ns. Path 3 needs one buffer while path 21 (the longest path, not shown in Fig. 1) needs two buffers. We, then, continue the optimisation process with the simultaneous optimisation of clock delay, slew rate, and power by changing buffer positions. The algorithm selects a buffer from source to sink (depth-first) and move its position to reduce the clock delay. If the delay is reduced, the buffer is moved to the new location, otherwise it stays at its original position. After all buffer Fig. 5. Optimisation Approach positions have been optimised, we check the slew rate. A buffer is selected from sink to source (bottom-up). If the slew rate at Input of buffer Bk is greater than 0.5 ns, we increase the size of buffer Bk-i until the slew rate is less than tmax. TABLE III displays the Buffer Positioning Algorithm for simultaneous optimisation of clock delay and power with slew rate constraint. The original algorithm developed by /6/ was modified to consider the slew rate constraint. 88 M. Sulaiman: A Methodology for Optimum Delay, Skew, and Power Performances in an FPGA Clock Network Informacije MIDEM 36(2006)2, str. 85-90 Table 5 displays the algorithm used for optimising clock delay and skew. This original technique was developed by /6/, and then was modified to take into account the slew rate constraint. Step 1: The algorithm arranges the path according to its delay in ascending order; tdeiay_pi (tpathjnin) < tdeiay„P2 < ... < tdelay_P20 < tdelay_P21 (tpath_max)- Step 2: Starting with tpath_min, it selects a bufferfrom source to sink (depth-first). Step 3: The buffer size is changed by As. If the delay is reduced, we then check the slew rate. We stick with the new size should the slew rate be less than tmax,- Otherwise, the buffer size is not changed. Step 4: If delay is reduced and slew rate is less than tmax, repeat step 3 until there is no further improvement. Wire width sizing strategy for delay, skew and power optimisation is as described below: Step 1 : Given a maximum wire width due to chip area constraint, vertical and horizontal wire widths are increased. Step 2: If clock delay, and skew are reduced, then change the widths. Step 3: Otherwise, reduce wire widths. If delay and skew is decreased, keep reducing the wire widths. Else stop. The results of the algorithms developed were verified on an FPGA chip where the clock tree is neither balanced nor of equal length. All the logic blocks in the FPGA chip have fan-out of one for worst-case capacitive loading imposed on the clock tree. Table 4 presents the results of clock delay, skew, slew rates, and power before and after the clock tree is optimised. Chip area savings of 765 jam2 is achieved with the new optimised clock tree. Power dissipation is improved by 22%. For all paths, the slew rates are reduced to within the scope of 500 ps (tmax)- These values range from 366 ps to 463 ps. Table 2 - Delay & Power optimization algorithm Input: Buffered Clock Tree (BFT) with n paths and kj level of buffers in path i. n = no. of paths Ax: buffer moving step (single-node step) Output: Optimized clock path (position-wise) Procedure: PathDelayMinimization (Path i, kp Ax, n) for path = 1 to n // optimize delay (move buffer position) for buffer level i = 1 to k (depth-first approach) move buffer i, Bj up Ax check path clock delay if delay is reduced stay at new location keep moving up Ax until no further improvement else go back to old location move buffer i, B; down Ax check path clock delay if delay is reduced stay at new location keep moving down Ax until no improvement else back to old location end end end // minimize slew rate for buffer j = k to 1 (bottom-up) if slew rate at input of Bj > 500 ps increase size of B^ end end end 89 Informacije MIDEM 36(2006)2, str. 85-90 M. Sulaiman: A Methodology for Optimum Delay, Skew, and Power Performances in an FPGA Clock Network Table 3 - Delay and skew minimization with slew rate constraint Input: BFT with optimized buffer position As: buffer size increase n = no. of paths Output: Optimized buffer sizes for delay, skew, slew rate and power. Procedure: BufferSizing (Path i, k;, As, n) for path = 1 to n (i.e. r for buffer level i = 1 to k path_min ^^ ^pathmax) In this paper, a methodology for optimisation of clock delay, clock skew and power with slew rate constraint is presented. This method is effective especially when dealing with trade-offs among delay, skew, power, and slew rate for an FPGA chip. The results presented in this paper have shown convincingly that the method developed yields sharper rise and fall edges and reduces power dissipation with practically no penalty in the clock delay. max new size // increase buffer size while increase_buffer_size = TRUE increase size of buffer i, Bj by As if delay is reduced if slew rate < t„ buffer size : inerease_buffer_size = TRUE else buffer size = old size increase_buffer_size = FALSE end end // reduce buffer size while reducebuffer size = TRUE reduce size of buffer i, Bj by As if delay is reduced if slew rate < tmax buffer size ~ new size reduce buffer size = TRUE else buffer size = old size reduce__buffer_size = FALSE end end end // end of 2nd for loop // need additional buffers? if delay >2.5 ns (tmax) add another buffer in the path go to PathDelayMinimization end end // end of main for loop /1/ l-Min Liu, T.L. Chou, A. Aziz, and D.F. Wong, "Zero-Skew Clock Tree Construction by Simultaneous Routing, Wire Sizing and Buffer Insertion", Proc. 2000 Int'l Symposium on Physical design, pp. 33-38, 2000. /2/ M.Afghani and C.Svensson, "Performance of synchronous and asynchronous schemes for VLSI systems", IEEE Trans. Corn-put., vol. 41, no. 7, pp. 858-872, 1992. /3/ G.E. Tellez, "Minimal Buffer Insertion in Clock Trees with Skew and Slew Rate Constraints", IEEE Transactions on CAD of IC and Systems, vol. 16, pp. 333 - 342, April 1997. /4/ J.W. Chung, D.Y. Kao, C.K. Cheng, and T.T. Lin, "Optimization of Power Dissipation and Skew Sensitivity in Clock Buffer Synthesis", ISLPED 95, pp. 179 - 184, 1995. /5/ J.Cong, C.K.Koh, and K.S.Leung, "Simultaneous Bufferand Wire Sizing for Performance and Power Optimization", ISPLED 96, pp. 271 - 276, 1996. /6/ X. Zheng, D. Zhou, and Wei Li, "Buffer Insertion for Clock Delay and Skew Minimization", ISPD99, pp. 36 - 41, April 1999. /7/ T.Stohr, et al, "Analysis, Reduction and Avoidance of Crosstalk on VLSI Chips", iSPD 98, pp. 211 - 218, 1998. Mohd S Sulaiman Faculty of Engineering, Multimedia University, 63100 Cyberjaya, Selangor, Malaysia E-mail: shahiman@mmu.edu.my Prispelo (Arrived): 30. 01. 2006; Sprejeto (Accepted): 29. 05. 2006 Table 4 - Comparison of clock delay, skew, slew rate, power dissipation, and buffer area between the unoptimised design and the optimized design Initial Clock Tree Optimised Clock Tree % Improvement Shortest Path (1) Longest Path (21) Shortest Path (1) Longest Path (21) Overall (Path 21) Rise Time (ps) 481.1 939.5 463.5 362.8 61.4 Fall Time (ps) 493.0 842.9 456.3 385.7 54.2 Clock Delay (ns) 1.43 2.35 1.38 2.26 3.8 Maximum Clock Skew (ns) 0.92 0.88 4.3 Power (mW) 112.7 87.4 22.4 Area occupied by Buffers & Column Drivers (|J.m2) 5145 4380 14.9 90 UDK621,3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 36(2006)1, Ljubljana AN Al BASED SELF-MODERATED SMART-HOME AwssAssim1, M. B. I. Reaz1, M. i. Ibrahimy1, A. F. Ismail1, F. Choong2, F. Mohd-Yasin2 1Dept. of Electrical and Computer Engineering, International Islamic University Malaysia, Kuala Lumpur, Malaysia 2Facultyof Engineering, Multimedia University, Selangor, Malaysia Key words: Smart-Home, VHDL, Multiagent, FPGA, Prediction. Abstract: Smart-home conception has emerged in recent years and played a very important part in the formation of future houses. Making our current homes more adaptable and self-directed is the main focus of smart home research. Achieving these goals won't be possible without giving our today's home enough intelligence to make rational decisions to operate itself which usually we as inhabitants of the home make these decisions in our everyday life to manage our home and achieve comfort that we desire. In this paper we present prototype of a system that overcomes this problem by giving the home enough intelligence to adapt to its inhabitants life style without the need for the inhabitants to exercise authority. The system makes use of multi-agent and prediction techniques to provide intelligent smart-home appliances automation. The final prototype will be downloaded into FPGA chip. Pametni dom na osnovi umetne inteligence Kjučne besede: Inteligentni dom, VHDL, večagentni sistemi, FPGA, napoved Izvleček: Koncept inteligentnega doma se je pojavil v zadnjih letih in je odigral pomembno vlogo pri načrtovanju bodočih hiš. Glavni cilj raziskav na področju inteligentnega doma je ustvariti bolj prilagodljiv In samo-upravijiv dom. Takega cilja ne bo mogoče doseči brez, da bi domu dali določeno mero inteligence, s pomočjo katere se bo lahko odločal in se upravljal, kar je do sedaj bila izključno domena stanovalcev. V prispevku predstavimo prototip sistema, ki domu omogoča dovolj inteligence, da se prilagodi življenskemu slogu stanovalcev brez potrebe po njihovem avtoritativnem posredovanju. Sistem uporablja večagentne tehnike in tehnike napovedi za avtomatizacijo delovanja naprav znotraj inteligentnega doma. Končni prototip bo izveden kot vezje FPGA. 1. Introduction Smart-home is a structure that is equipped with technology that makes it possible for the home Inhabitant to operate the house using special techniques. These techniques might include programming an array of home appliances or by using remote control schemes. Recently many high profiled researches discrete such as IBM, MIT and Microsoft started to setup smart-homes to be used as test beds by researchers /1/. The Artificial Intelligence (Al) designation; is the ability of a computer to perform rational tasks, such as reasoning and learning that human intelligence is capable of doing /2/. The aim of Al is to utilize the abilities of the human brain into computer powered devices. One of these devices is the smart-home appliance that can automatically adjust itself to the desire of the home inhabitants. The physical picture of a home being rational Is very plausible. A home that is capable of making coherent decisions could possibly offer a level of self-sufficiency that is not available in the current home environment. By automating the home many residents prefer that home tasks such as security and power consumption can be carried out by the smart-home systems automatically with out their need for exercising authority. The essence of smart-home study lies in the creation of smart environment saturated with computing and communication capability, yet gracefully enhanced integrated with the human users The com- plexity of a Smart Home solution lies in the variety of different protocols and media involved, and the requirements of the various services provided such as automation, security and power management etc. During the past years many home appliances automation projects has emerged /3, 4, 5/. Although previous systems achieve the required home mechanization needs but on the other hand most of previous systems were software based and expensive to be implemented and commercialized and that's probably the main reason why previous systems were not used by the general public. In this paper we present a portable, low cost and fast hardware prototype of a multi-agent system that is designed to provide home automation without the need to be programmed. In the next section we will look into the detail of the techniques used in our system and at the end we will illustrate the expected performance of the system and furthermore future work will be discussed. 2. Research methodology The system main goals are to achieve high operational speed and efficiency and at the same time making it cost effective and portable. Due to the mentioned goals the system is implemented on hardware rather than software. The system makes use of multi-agent techniques; each agent will be responsible to control a section of the home 365 A. Assim, M. B. I. Reaz, M. I. Ibrahimy, A. F. Ismail, Informacije MIDEM 36(2006)2, str. 91-94 F. Choong, F. Mohd-Yasin: An AI Based Self-moderated Smart-home and automate the devices appliances usage according to the life style of the inhabitants. The agents are homogeneous and non-communicative; the only communication that the agents can perform is to share the overall environment state of the whole smart-home so as to make better predictions and device automations. To correspond with the outside world the system makes use of X10 protocol to send and receive messages from and to the home appliances. The system has two modules; one of the modules is used to generate X10 packet and the other is responsible to receive and translate an X10 packet. Based on the information contained in the packet, the unit generates a message to each agent environment state maintainer. When the device state maintain-er receives the message it updates the local view of the agent devices state. The system is event driven. The events are themselves time driven and are controlled by a system clock. The time frame of the events is adjustable by the home occupants. Each time an event trigger is generated the agents will issue a device command based on their learned knowledge that were gathered by monitoring the users everyday device interactions. The agent consists of three main units; prediction unit, decision unit and communication unit. The prediction unit is designed by using Active-Lezi algorithm /6/, the unit is responsible for predicting the future environment state based on the current environment state. On the other hand the decision unit is modeled using techniques of Reinforcement learning, the algorithm used for modeling the unit is Q-Learning. The use of prediction unit with the decision unit makes better system performance since it is sometimes undesirable to directly predict and operate a particular home appliance. That's why we need the reinforcement learning techniques to be used so that the agent learns from previous experience and not letting the prediction unit perform unnecessary action. Finally the communication unit is responsible to handle the communication between the agents as illustrated in Fig.1 Before putting the system into operation the system needs to be trained. The training is done by collecting devices usage patterns of the home inhabitants, after data gathering phase the data is fed to the system. The system performance is improved by using more accurate training data. For detailed system superficial overview refer to Fig.2. 3. Decision unit The decision unit of the system is responsible for performing rational decision. The unit is modeled according to Q-Learning algorithm. Q-learning is a reinforcement learning technique where action value function is used to assign values to actions that the system performs at a given state. Fig. 1 The agent illustration diagram i Agitu i I j Environment Stats Update rK; X !0 Recievcr ! Bufftr Agent Trauicr if rl« Ö •> jV as Environ«!« Fig. 2 Superficial illustration diagram of the system Given the environment devices states as [S], and the device actions that can be taken on a given environment state as [A], we can form the Q value array of reinforcement learning as shown in equation 1. Q - Sx A (1) According to Q-Learning algorithm the Q value array is used to store the rewards the agent has received by performing a particular action at a given environment state. Each time the agent makes a correct decision; the agent is given a positive reward or a negative reward. The reward is calculated based on the user feedback to the agents performed action, which can be sensed by the system through monitoring the devices state constantly. The Q value function will be calculated as shown in equation 2. Q*(x,a) = (l-a)Q*(x,a) + a(r + yFt(y)) (2) where Q* is the Q-learning value function, x is the environment states, a is the action that can be taken, a is the 92 A. Assim, M. B. I. Reaz, M. I. Ibrahimy, A. F. Ismail, F. Choong, F. Mohd-Yasin: An AI Based Self-moderated Smart-home Informacije MIDEM 36(2006)2, str. 91-94 learning rate, y is the value of future reinforcement and V* is the future Q-learning value function. 4. Prediction unit The prediction unit is very important unit; due to the reason that it can minimize the error rate by predicting the future environment state, thus allowing the decision unit to take actions based on the predicted future state. The unit is modeled using an online predictor Active-Lezi. Active-LeZi algorithm is an enhancement of both LZ78 and LeZi-Update algorithms /6/. It incorporates a sliding window approach to address the drawbacks of both LZ78 and LeZi-Update. This approach also demonstrates various other desirable characteristics given below. The core model of Active-Lezi algorithm is Growing-Order-Markov model based on LZ78 algorithm, therefore Active-Lezi accomplish optimal predictability. Active-Lezi stores more information, which implies that as the input sequence (the experience) grows, the algorithm performs better. This is a desirable characteristic of any learning algorithm. After simulating Active-Lezi algorithm by using input data pattern with high noise. We can see that the result gained from the simulation is very desirable since the algorithm achieves prediction of 100%. The simulation result is shown in Fig.3. 100 § 50 -140-?30- EL X 20 -10 - o J-,-,-,-, 0 500 two 1600 200Q Number Training instances Fig. 3 Graph showing the prediction accuracy of Active-iezi 5. Results and discussion The purpose of the research is to implement a home appliances automation system by using multi-agent techniques. The system will be later hardware synthesized. At the moment our system is still under development, so the testing of the system that we have so far performed has been done using software simulation. During our testing phase we have implemented a synthetic data generator to generate training data to train the system. The synthetic data generator is used to produce devices usage pattern that accurately symbolize an actual home occupant devices usage routine. The data simply include the time, place and action of the event that is hy-pothetically performed by a particular home resident as shown in Table 1. After the data is generated it is converted into an accurate X10 protocol packets and then is fed to the system using the system training unit. Table 1 Sample Synthetic Data Used To Train The Multi-Agent System Date and Time Action Device Location 2006-03-03 /09:21 On Lampl Living Room 2006-03-03 / 10:26 Off Fanl Bedroom 2006-03-03 / 10:29 On Tvl Living Room 2006-03-03 / 18:21 Off Lampl Living Room 2006-03-03 /20:22 Off Tv2 Bedroom The system has been simulated and tested using our synthetic data generator. Since the system is hardware based we have used Model-Sim VHDL simulation software to simulate the design. Based on our simulation results we realize that the system can perform accurately and the error rate is reduced by using more training data as shown in Fig.4. Fig. 4 Graph Illustrate The Simulation Results Since the system is modeled using the techniques of reinforcement learning, there are few some important point need to be mentioned. In orderto accommodate the home inhabitant preferences and learn accurately form the interaction of inhabitant devices, we decided to give a small reward value to every accurate action that the decisionmaking unit performs and a larger value to a particular action that the user performs. These make the system to adapt the inhabitant preferences faster and more accurate. Since the actions are increased according to the number of home appliances, thus more the appliances installed in the home, the more complicated the decision making process becomes. The simulation results shows that the system without prediction unit has a dramatically fall in the performance. This proves that the prediction unit is highly important to minimize the number of actions to be performed on the predicted next environment state. 93 Informacije MIDEM 36(2006)2, str. 91-94 A. Assim, M. B. I. Reaz, M. I. Ibrahimy, A. F. Ismail, F. Choong, F. Mohd-Yasin: An AI Based Self-moderated Smart-home 6. Conclusion The purpose of this research is to implement a revolutionary home automation system that automates the home devices appliances usage based on the inhabitant's life style. The methodology used in this system is based on techniques of Al in particular multi-agent techniques. This system will be realized on hardware to overcome problems faced by other systems such as cost and portability. Moreover making use of muti-agnet techniques will make the system performs faster than previous home automation systems due to the fact that parallelism of multi-agent can help deal with limitations imposed by time-bounded reasoning requirements. References /1/ M. Coen, 'Design principles for Intelligent Environments', AMI Spring Symposium, Stanford, 23rd -25th March 1998, pp. 36-43. /2/ Edwin O. Heierman, III Diane J. Cook, "Improving Home Automation by Discovering Regularly Occurring Device Usage Patterns", Data Mining, 2003. ICDM 2003. Third IEEE International Conference on, 19-22 Nov. 2003, pp. 537- 540. /3/ R, Hamabe, M. Murata, and L. Namekawa, 'Home Bus System (HBS) Interface LSI and its Standard Protocol Example,' IEEE Trans. Consumer Electronics, vol. 36, no. 4. November 1990, pp. 949-953. /4/ Kashiwamura. H. Koga, and Y. Murakami, "Telecommunications Aspects of Intelligent Building." IEEE Comm. Mag., vol. 29, no. 4, April 1991, pp. 28-40. /5/ C. K. Lim et al., "Development of A Test Bed for High- Speed Power Line Communications," Int'l. Conf. Power Sys. Tech., 2000, vol. 1, Perth, WA., 4th -7th December 2000, pp. 451-56. /6/ KarthikGopalratnam, Diane J. Cook, "Active LeZI: An Incremental Parsing Algorithm for Sequential Prediction", FLAIRS Conference. St. Augustine, Florida, 12th -14th May 2003, pp. 38-42. /Awss Assim, M. B. I. Reaz, M. I. Ibrahimy, /4. F. Ismail Dept. of Electrical and Computer Engineering, International Islamic University Malaysia, Gombak, 53100 Kuala Lumpur, Malaysia Tel: +603-61964435, Fax: +603-61964488, Email: mamun.reaz@iiu.edu.my F. Choong, F. Mohd-Yasin Faculty of Engineering, Multimedia University, 63100 Cyberjaya, Selangor, Malaysia Prispelo (Arrived): 19. 05. 2006; Sprejeto (Accepted): 29. 05. 2006 94 UDK621,3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 36(2006)1, Ljubljana PRECISE CHARACTERIZATION OF SOFT-MAGNETIC MATERIALS AT HIGH SATURATION Gorazd Modrijan, Marko Petkovšek, Peter Zajec, Danijel Vončina University of Ljubljana, Faculty of Electrical Engineering, Ljubljana, Slovenia Keywords: ring core, soft-magnetic material, measuring system, DSP, low-distortion, form factor, B-H curve Abstract: The presented paper deals with a computerized measuring system for evaluating magnetic properties of soft-magnetic ring cores (in compliance with the IEC60404-2 standard). A measuring set-up with a feedback power amplifier is introduced. Its basic operation is explained and an upgraded version Is presented. Its main feature Is a superior control loop based on a repetitive action control method which assures an accurate and stable secondary Induced sinusoidal voltage waveform without voltage zero-crossing distortion caused by a large magnetizing current. Two variants of the repetitive method are presented which provide more realistic measurements of magnetic field strength H at the specified amplitude of the secondary induced voltage. Measurements done without and with the repetitive action corrector are presented and discussed. Reasons for choosing one variant are given and results that confirm the improvement over a conventional approach without the repetitive controller are shown. Merjenje lastnosti mehkomagnetnih materialov pri visoki stopnji magnetnega nasičenja Kjučne besede: toroldno jedro, mehkomagnetni material, merilni sistem, DSP, nizko popačenje, faktor oblike, B-H krivulja Izvleček: V članku je predstavljen mlkrokrmilnlško nadzorovan merilni sistem za merjenje parametrov mehkomagnetnih jeder z zaključeno magnetno potjo (po predpisih, ki jih določa standard IEC60404-2). Opisano je osnovno merilno vezje, ki temelji na linearnem močnostnem ojačevalniku z negativno povratno zanko. Razloženi so temelji njegovega delovanja. Predlagana je nadgradnja merilnega sistema z nadrejeno regulacijsko zanko z regulatorjem, ki temelji na repetltivnl korekcijski metodi. Slednji je posebno primeren za zagotavljanje stabilne sinusne oblike sekundarne inducirane napetosti brez popačenja pri prehodu skozi ničlo, ki ga povzroča velik magnetilni tok. Predstavljeni sta dve različici repetitivne korekcijske metode, ki omogočata realnejše posredno merjenje magnetne poljske jakostl H. Obe različici učinkovito zmanjšujeta konico magnetilnega toka ter posledično magnetne poljske jakosti, pri tem pa ohranjata amplitudo sekundarne inducirane napetosti nespremenjeno. Predstavljene so primerjalne meritve, opravljene na opisanem merilnem vezju brez in z uporabo nadrejene regulacijske zanke z repetitivnim regulatorjem. Podani so razlogi za izbiro ene od izvedb ter pridobljeni rezultati. Opravljene meritve potrjujejo izboljšave, ki jih doprinese regulirani sistem v primerjavi z nereguliranlm. Introduction In the field of soft-magnetic cores manufacturing the measurement of magnetic field strength H at a predefined magnetic flux density B is of outmost importance to determine the quality of assembled magnetic cores. The measurement deviations, set by the standards regulating this field /1 - 2/, are relatively tolerant and allow various methods or power supply assemblies for achieving them. Nonetheless, the common denominator of all such devices is that they should keep the secondary induced voltage waveform sinusoidal even when the device undertest (D.U.T.) requires high flux density. Such a device should be able to: perform B-H curve measurement of soft-magnetic cores which are used in low and medium- frequency applications such as voltage and current transformers, yokes for motors or line filters, perform hysteresis loss measurement, which is crucial for minimizing core losses and so enabling reduction in size of magnetic devices. The accurate measurement of magnetic field strength H becomes especially Important when estimating cores that are measured in high saturation region. A couple percents deviation of the measured value from the actual value can mean all the difference when considering the material to choose. To obtain magnetic parameters of soft-magnetic materials, measurements are usually done using standard 25 cm (Epstein) test core assemblies /3-5/ consisting of several steel strips. In practice, however, it is desired to perform magnetic measurements not only on magnetic strips, but also to perform production quality control tests on ring cores after they have been assembled /6/. The standards that regulate the field of magnetic measurements demand a secondary induced voltage of stable amplitude and accurate shape. During measurements, the voltage and frequency variations should not exceed + 0.2 % of the required value. For the determination of: the specific total losses, the specific apparent power and the rms value of the magnetic field strength, the form factor FFu (which is the ratio of the rms value of the signal to its average rectified value) of the secondary voltage us must be maintained in a range of 1.111 ± 1% otherwise the above measurements (and other derivate quantities) are not valid. The given requirements can be 369 G. Modrijan, M. Petkovšek, P. Zajec, D. Vončina: Informacije MIDEM 36(2006)2, str. 95-101 Precise Characterization of Soft-magnetic Materials at High Saturation met in two different ways: solely with a feedback power amplifier and by using a superior digital control loop. Both cases are presented in this paper. Theory Parameters of a soft-magnetic ring core are usually measured in a well known measurement set-up, where the D.U.T. is magnetized by an alternating primary current ip, causing a magnetic field strength /2/: H = ip-Np/Ife, (1) where Np is the number of primary turns and Ife the effective magnetic path of the D.U.T., which can be calculated from the dimensions (the outer and inner ring diameters) of the ring core. As a consequence of the magnetic flux density B, voltage is induced in a secondary winding: us = -Ns- Sfe ■ dB / dt, (2) where Ns and Sfe stand for a number of secondary turns and cross-sectional area of the D.U.T., respectively. To minimize the impact of the shape of the primary current i'p to the measurement of the specific apparent power and the rms value of H, the international standard implies that the measurement should be made with a sinusoidal magnetic polarization B /1, 2/. In this case, the rms value of the induced voltage us, becomes proportional to the maximum value of B: Us = 4.44 ■ § ■ f ■ Sfe ■ Ns, (3) where f is the frequency of the induced voltage. The main problem when measuring a B-H curve is actually the deviation of the secondary induced voltage (or magnetic flux density B) from an ideal sinusoidal waveform, which is caused by a high (peak) current flowing when the soft-magnetic core is in a magnetic saturation. A deformed secondary induced voltage yields a higher peak current and consecutively declines the secondary voltage waveform from the optimal one, so corrupting the measurement of magnetic field strength. By correcting the shape of the induced voltage us, the peak current can be diminished and measurement of H improved! System Description One possible method to fulfill the required voltage shape criteria (FFu) involves a power amplifier with an attached primary winding of the D.U.T. to its output, while the secondary voltage is fed back to its negative input in order to instantaneously control the secondary voltage waveform (Figure 1). Figure 1: Principle of the power amplifier assisted measurement set-up The voltage drop in the primary winding of the above setup is compensated through the control of a power amplifier. Unfortunately, the DC offset voltage of the power amplifier (resulting in the pre-magnetized magnetic core) causes incorrect measurement results. Another potential problem is the power amplifier instability appearing at low impedance loads. The problem of DC offset voltage can be successfully solved with the measurement set-up shown in Figure 2 /7/. Its main idea Is to use an additional matching transformer (Tr.) placed between the power amplifier (PA) and the D.U.T. The matching transformer prevents the D.U.T. from being pre-magnetized with the remaining DC voltage offset at the PA output, which is left uncompensated through the use of a low-pass (LP) filter (fc = 2 Hz). Since the transformer is a part of the control loop, no special requirements have to be met during its design stage, except that the possible pre-magnetization has to be taken into consideration. To keep the matching transformer size in reasonable limits, the primary feedback loop of the PA is upgraded with a low-pass filter. Due to its low cut-off frequency, it forces only the DC component of the PA output voltage into the summation point, thus reducing the DC pre-magnetization of the D.U.T. In addition, the matching transformer with a proper turn ratio adjusts the low impedance of the device's primary winding to the PA and therefore provides its nominal burden in spite of the primary turns Np as well as secondary turns Ns reduction. A request for the measurement set-up is that it must cover a wide range of ring core assortments with the possibility of the secondary voltage as well as primary magnetizing current swinging in wide dynamic ranges. Attempts to fulfill this demand can lead to PA instability or to measurement inaccuracy due to the insufficient signal to noise ratio. In order to raise the measurement accuracy, depending basically on the sensitivity of the magnetic flux evaluation that is obtained by means of numerical integration of the induced secondary voltage /3/, and expand the measurement range, programmable gain amplifiers (PGA) were installed in both measurement paths terminated with 12-bit analog-to-digital converters (ADCs) as well as in the negative feedback control loop. 370 G. Modrijan, M. Petkovšek, P. Zajec, D. Vončina: Precise Characterization ot Soft-magnetic Materials at High Saturation Informacije MIDEM 36(2006)2, str, 95-101 Figure 2: The proposed experimental set-up Upon the given core data (outer diameter (O.D.), inner diameter (I.D.), height (H) and filling factor) and the preferred magnetization level, the appropriate gain is set by a digital signal processor (DSP). The same DSP also cares for data capturing and the generation of a sinusoidal reference voltage Uin- Because the described system already comprises a DSP controller, an additional superior control loop is implemented in it, which further improves the overall accuracy of the secondary induced voltage us- Superior Control Loop Design The superior control of the described system is comprised of two successive controllers which are not active at the same time. The first is an ¡-like fuzzy logic controller (FLC) which oversees the magnitude of the reference voltage Uin necessary to achieve the desired amplitude of the induced secondary voltage us. It is activated every time the reference voltage is changed and deactivated when the secondary voltage us reaches the desired value. The second controller (enabled when the FLC is deactivated) is based on a repetitive (integral) action method which corrects the shape of the generated reference signal Ujn in order to achieve a sinusoidal induced secondary voltage with a THD as low as possible. The requirement for minimal THD is a consequence of the desired form factor FFu. The corrector basically adds a correction waveform uCor to the sine reference voltage effectively forming the input waveform Uin. Fuzzy Logic Controller Because of the design of the system it is impossible to accurately predict the amplitude of the secondary induced voltage in relation to the voltage applied on the primary winding. This is made worse by the DSP not knowing what kind of soft-magnetic material is being analyzed. The only known fact is that the ratio of the secondary Induced voltage to the primary applied voltage (k) varies from almost 1 to approximately 0.8, in dependence oftheD.U.T., number of primary and secondary winding turns and gain factor of the power amplifier's feedback control loop. Because of stated reasons behind the uncertainty of the amplitude of secondary voltage an l-Iike FLC is used to control the amplitude of the primary voltage Uin. There are two demands it must fulfill: it must convey the secondary induced voltage to its predestined value in at least ten periods and it must not overshoot. The first demand is based on the maximum measurement time allowed, while the second is inherent of the measurement method itself: because the D.U.T. is in an unknown state (usually pre-magnetized) it must be demagnetized before the first measurement could take place. This is achieved by bringing the device close to saturation and then back down to zero. The problem arises if/when the D.U.T. enters deep Into the saturation region and the current exceeds all anticipated values. At this point the induced secondary voltage is not sinusoidal any more and amplitude measurement/calculation becomes impossible thus hindering the functioning of the FLC. The l-like FLC is of SISO type: the (single) input is the degree of deviation of the amplitude of the secondary induced voltage us from the desired value usrei (which is an internal DSP value send by the PC). The deviation is calculated as: where: Usref- Us, Us = k • Uin. (4) (5) The (single) output of the FLC (Uin) is the scaled (internal) sinusoidal reference waveform uref. Uin = a ■ Uref. (6) The gain a of the l-like FLC is altered until the voltage u,n produces the desired secondary induced voltage Us (e = 0) in which case the attenuation of the system k is completely compensated. The action of the FLC is divided in dependence of the error e in four regions: L, M, S and Z. If the deviation e is very large (region L), the increase (or decrease) of the reference voltage Uin is large (meaning a small integral constant) and if the deviation is small (region S), the increase (or decrease) of the reference voltage is small (large integral constant). When the amplitude of the secondary induced voltage coincides with the desired value, the FLC sets the integral constant to zero and so effectively disabling itself and starting the repetitive action controller (see next chapter). The cross points of the five regions are calculated from the known parameters of the source and the D.U.T. and their values are set to bring the secondary voltage to Its final value in about ten periods. The initial integral constant of the FLC is calculated approximately and is chosen in a way to cause a change of secondary voltage of not less then about 12.5 % (taking into account an approximation of the 97 G. Modrijan, M. Petkovšek, P. Zajec, D. Vončina: Informacije MIDEM 36(2006)2, str. 95-101 Precise Characterization of Soft-magnetic Materials at High Saturation system attenuation). All the subsequent incrementations (or decrementations) can be only equal to or smaller than the initial value. Repetitive Control Method The proposed control method for the pertinent system is a variant of a repetitive action control method /8/, which is especially suitable for correcting periodic signals (of voltage and/or current). In the past, repetitive control methods have seen extensive application where correction of a periodic waveform is required /9-12/ (e.g. motor control applications and PWM switching power supplies like UPS devices), mainly because of their reliable operation, low cost and ease of implementation. In our case, we chose an integral repetitive action control method since the output waveform of the amplifier and the disturbance are always periodic, even when a nonlinear load is supplied by the voltage power amplifier/8, 13/. The control principle moreover does not depend on internal control loops of the voltage power amplifier nor does it require any special knowledge about its parameters. Besides the periodic occurrence of disturbances, the only condition that must be met for the implementation of the control principle is the stability of the amplifier. A simplified representation of the voltage power source is shown in Figure 3. The periodic disturbances causing output voltage distortions are summarized in a load-dependent disturbance signal d, which is chosen intentionally to simplify the analysis. It is especially appropriate when analyzing the impact of periodic disturbances and nonlinear distortion of output voltage of a power supply with a nonlinear load. Figure 3: Described system in z domain with disturbance signal d. Regardless of the type of repetitive control mechanism, they all rely on operation of a discrete number of period-based correctors. Figure 4 shows a plug-in repetitive controller/14/ processing the error e, which is (at least in the first correction period) the difference between the input reference waveform u/n and the actual output waveform us. The calculated and stored values of the error £(nj) are used to form a periodical correction waveform uCor, which is added to the original (in most cases a sine wave) reference waveform Um, thus effectively reducing the error of the output waveform of the amplifier/compensating the disturbance d. The basic idea of the repetitive controller is that a period T of the reference (and sampled output) voltage is divided in N discrete intervals of duration r(where T = N ■ z). In each interval n, the acquired sample of the amplifier output voltage us(n.T) is subtracted from the reference value Uintn). The calculated error S(nj) at the present discrete interval n in a particular period T is then stored twice: unmodified in a table of correction values (which has N different positions) at the position corresponding to the discrete interval n, and scaled by G(Z> in a second correction table (with N positions) at position n too. The same procedure is applied to all the intervals in a given period of the generated waveform. In the next period (T + 1), the unmodified value of the error of a particular interval n (of the previous period) is scaled by the factor Kr and added to the other (already scaled) value of error of the previous period interval n. The sum of both values form a quant of the correction waveform: Ucorln.T) ~ Kr ■ £(n,T) + X G(z) ■ £(n,j), (7) which is summed up to the reference voltage u-min) and the result Is a new input waveform: Uin'(n,T+ V - Ujn(n) + UCor(n,T). (8) The output voltage us(n,T+-\> of the amplifier is meanwhile sampled again and the new error £(nj+ u in a specific interval is recalculated. It is stored unmodified in the first table and scaled by G(Z>, summed to the previously scaled and stored error £(nj) of the n-th interval and stored again at the corresponding position in the (second) table of correction values for subsequent use in the following period (T+ 2). Owing to the repeating execution of the correction procedure, the (second) table of scaled errors contains the sums of all past errors £(n) of all specific correction intervals n independently. Consequently, the correction waveform Figure 4: Block diagram of a classic repetitive action control method in z domain. 372 G. Modrijan, M. Petkovšek, P. Zajec, D. Vončina: Precise Characterization of Soft-magnetic Materials at High Saturation Informacije MIDEM 36(2006)2, str. 95-101 Ucor(nj) behaves as if it Is formed with the help of N correctors, each correcting the value of one Interval n. Due to the nature of the control method, a sub-cycle response is impossible, meaning that the error detected in a certain period can be suppressed at best in the following period. Figure 4 shows a block diagram of the described control method in z domain, where the time delay unit z'N delays the computed correction waveform for one entire period T (composed of N samples). Similarly, a time delay unit z"1 delays the execution for one sample. The key element of the repetitive action controller is the inner loop with the internal model G(Z>-z'N. Its closed loop transfer function is: 1 -n , (9) where G(Z> can be a constant or a function of z, e.g. a low-pass filter /15/ or a second order filter. In the time domain, this internal model is an integrator (if G/Zj = 1) summing up the error e of the n-th correction interval from the first to all successive periods. As explained before, this sum is used to correct the n-th interval of the reference waveform. While the implemented correction method was tried out and found to be good, at some point it aroused concerns linked with the usage of data memory space of the DSP in which the calculations where executed. Consecutively, a modified version of the correction method was implemented (Figure 5), which required one memory table less then the previous method and had some other modifications: the function G(Z) of the closed loop model l(Zj was chosen to be/set to one so effectively making the closed loop model l(Z) a proper integrator, an additional proportional model Q, used before the closed loop model l(Zj was introduced, which regulates the export of the error e which is added to the already stored errors, the constant Kr was dropped, two time advance units (z q and z h) were added. Although it was later found out, that the memory concerns were groundless, the correction method was retained. Its advantages were shorter calculation time and reduced data memory usage while having better stability and roughly the same ability to suppress waveform distortions (or lower THD). Repetitive Action Control Method Implementation Both described control methods (classic and adapted) were implemented in the described B-H analyzer and tested. They work well, although with some distinctions in speed and accuracy. While the first is a little better in terms of the ability to reduce THD, the second allows for a wider deviation of the parameters of the regulator from the optimal value with minimal deterioration of THD. The reference signal L//n in both implementations consists of 1000 samples per period. This was also the sampling rate of the AD converter, meaning that the correction waveform Ucor is also formed of the same number of intervals. Taking into account the Nyquist theorem, frequencies up to 50 kHz were sampled and corrected. The Implemented correction method has also two time advance units: zq in the direct path, which Is used for correcting the various time delays (caused by the sampling time of the ADC, the conversion time of the digital-to-analog converter (DAC) and other time delays) and without which the actual realization of the correction method would not work, zh in the feedback branch, which implementation is not necessarily required, but it is useful to reduce the amplitude of the correction waveform uCOr caused by the phase shift between the input and output of the system. Measurements All the following measurements were made on an experimental model of the described B-H analyzer. The frequency domain analyses were made by means of a dynamic signal analyzer HP35665A. The measured frequency range was 0 to 3.2 kHz and a flat top windowing method was selected. For the THD calculation the harmonic components up to the 64th were observed and averaged over 30 measurements. The D.U.T. was a thin metal M0 silicon-iron toroidal core O.D./I.D./H.: 53/39/18 mm with two primary and two secondary winding turns. Figure 6 shows test conditions without and with the repetitive action control method enabled and after the desired value of the secondary voltage amplitude has been set by h nz) Figure 5: Block diagram of the implemented repetitive action control method in z domain. 99 G. Modrijan, M. Petkovšek, P. Zajec, D. Vončina: Informacije MIDEM 36(2006)2, str. 95-101 Precise Characterization of Soft-magnetic Materials at High Saturation the FLC. Shown are the secondary induced voltages, which are proportional to magnetic flux density B (3), and currents, which are proportional to magnetic field strength H (1). The voltage waveform uscor is shifted up by 0.2 of a division because off a better visual distinction from the us waveform, while currents /> are not. The voltage was set to 120 mV peak, which for the D.U.T. corresponds to a magnetic flux density of 1.600 T. The D.U.T. was clearly in magnetic saturation. In the case of uncorrected secondary voltage the calculated form factor FFu was 1,113 % (which is well within the parameters prescribed by the standard). The effective value of magnetic field strength in this instance was 28.3 A/m. harmonics can be observed which were preliminary absent. :US / dB 20 10 0 -10 -20 -30 -40 -50 -60 -70 500 1000 1500 2000 2500 3000 fl dB Figure 6: Secondary voltages us, corrected secondary voltage uscor, primary currents ip and correction waveform ucor (kus = 200 mV/div, kip = 2 A/div, kucor =■ 2 mV/div, t = 2 ms/div) In the second case, with the correction enabled and the same reference magnetic flux density, the calculated form factor was 1.1108 %. The measured effective value of magnetic field strength was 27.7 A/m. From the given values we can calculate, that a 0.2 % change in the form factor contributes to a 2.16 % decrease in the magnetic field strength. Figure 6 shows also a fifth signal which is the correction waveform uCor needed to achieve the low-distortion secondary induced voltage uscor■ The waveform is again shifted down by 2.5 divisions because of clarity. Both secondary voltage waveforms were analyzed in the frequency domain and their relative frequency spectra are shown in Figures 7 and 8. The first figure shows the frequency spectrum of the uncorrected and corrected voltage waveform of Figure 6 when the gain factor (Z) of the power amplifier's feedback loop was set to 1. The gray curve is the frequency spectra of the uncorrected voltage Us- The measured THD is about 1.656 %and it was caused mainly by odd higher harmonics components between the 3rd and the 23rd. The black curve represents the conditions of the corrected system. The measured THD was 0.04 %. A slighter increase in the 52th and 53th higher 100 Figure 1: Frequency spectrum of an uncorrected and corrected system (Z = 1) Another set of the same measurements was done, but with the gain of the power amplifier's feedback loop (Z) set to 4. The THD was in overall lower: 0.408 % with the correction disabled and 0.017 % with the correction enabled. us/dB* 20 - 10 - 0 - -10 - -20 - -30 -[ -40 -1 -50 - ! : | -60 | 1 -70 ' , -80 J 'i'^-,-,-,-,-► 0 500 1000 1500 2000 2500 3000 fldB Figure 8: Frequency spectrum of an uncorrected and corrected system (Z = 4) As can be seen from the figure above, the use of the gain factor in the power amplifier's feedback loop can greatly improve the THD factor because it forces a larger input voltage u-m, which can be set with greater accuracy. On the other hand, the gain factor must be used with care because of system stability concerns. The following figure shows a B-H curve of the D.U.T. used for the presented measurements measured with the described system and with the repetitive action controller enabled. As stated before, the same measurements were also done on a system controlled with a classical correction method (as seen in Figure 4). The acquired figures are not recorded in this paper because they deviate only minimally from the already presented. The measured form factor was the same while the calculated THD with correction enabled was actually a bit better: 0.016 %. G. Modrijan, M. Petkovšek, P. Zajec, D. Vončina: Precise Characterization of Soft-magnetic Materials at High Saturation Informacije MIDEM 36(2006)2, str. 95-101 i.2-f 0,2-: I o.G-y- -0,6 -0,8 -1,0 -¿0 -50 "Jo -30 -20 -!0 0 10 20 30 40 50 60 Hef Figure 9: B-H curve of the D.U.T. Conclusion The aim of the presented paper was the comparison between an uncorrected measurement set-up suitable for measuring magnetic field strength H, which was based on a feedback power amplifier and was already compliant with the tolerances imposed by the standard defining magnetic measurements, with the same supply set-up, but upgraded with a superior digital control loop. Two repetitive action control methods were implemented. Their goal was to achieve a better, more faithful reproduction of a sinusoidal waveform secondary Induced voltage. The first tested was a classical repetitive action correction method. Its use proved to be very effective in reducing the THD level of the secondary induced voltage us■ The drawback was the fine tuning of parameters that it required for achieving the best results and possible problems with system stability if they were mismatched. The second correction method was a modified version of the previous one, which required less parameters optimization. It yielded slightly worse error correction (greater THD), but it was much more robust. Nonetheless, the achieved results of form factor improvement were very good and at the end it was the chosen one because of ease of implementation and usage. The slightly greater THD it produced was so small, thet it did not weigh up its other advantages. With the use of the repetitive action control method improvement on magnetic field strength H measurements are more than perceivable. Although a couple of percents improvement (reduction) of H can not seem much, it can aid the end user's decision making process when choosing a soft-magnetic core. References /1/ International standard IEC60404-2, Methods of measurement of magnetic, electrical and physical properties of magnetic sheet and strip, 1996. /2/ Deutsche Norm DIN 50 460, Bestimmung der magnetischen Eigenschaften von weich-magnetischen Werkstoffen, 1988. /3/ E. Carminati, A. Ferrero, A Virtual Instrument for the Measurement of the Characteristics of Magnetic Materials, IEEE Trans. Instrum. Meas., vol. 41, pp. 1005 -1009, Dec 1992. /4/ A. Boglietti, P. Ferraris, M. Lazzari, M. Pastorelll, F. Profumo, New Power Supply Method for Soft Magnetic Material Characterization at High Flux Density Values, IEEE Trans. Magn., vol. 28, pp. 2459-2461, Sep 1992. /5/ L. D'Alessandro, A. Ferrero, A Method for the Determination of the Parameters of the Hysteresis Model of Magnetic Materials, IEEE Trans. Instrum. Meas., vol. 43, pp. 599-605, Aug 1994. /6/ J. Buck J, Automatic Hysteresisgraph Speeds Accurate Analysis of Soft Magnetic Materials, PCIM, February 2000, on-line version at: http://www.walkerldjsclentific.com/buck.pdf /7/ M. Petkovsek, J. Nastran, P. Zajec, F. Pavlovcic, D. Voncina, Soft-magnetic ring core measuring system with a decreased number of primary and secondary winding turns, IEEE Trans. Instrum. Meas., vol. 53, No. 2, 2004, pp. 444 - 447. /8/ N. M. Oldham, O. B. Laug, B. C. Waltrip, Digitally Synthesized Power Calibration Source, IEEE Trans. Instrum. Meas., vol. IM-36, No. 1, pp. 341 -346, June 1987. /9/ H. Lavric, D. Voncina, P. Zajec, F. Pavlovcic, J. Nastran, A precision hybrid amplifier for voltage calibration systems, Inf. MIDEM, vol. 34, No. 1, 2004, pp. 37-42. /10/ T. Yokoyama, A. Kawamura, Disturbance Observer Based Fully Digital Controlled PWM Inverter for CVCF Operation, IEEE Trans. Power Electron., vol. 9, No. 5, pp. 473 - 480, Sep.1994. /11/ C. G. Anwar, M. Tomizuka, Plug in Repetitive Control for Industrial Robotic Manipulators, Proc. IEEE Int. Conf. Robot. Automat., pp. 1970-1975, May 1990. /12/ A. Gubisch, P. L. Lualdi Jr., P. N. Miljanlc, J. L. West, Power Calibrator Using Sampled Feedback for Current and Voltage, IEEE Trans. Instrum. Meas., vol. 46, No. 2, pp. 403 - 407, Apr. 1997. /13/ C. Rech, H. Pinheiro, H. A. Gründling, H. L. Hey, J. R. Pinheiro, Comparison of Digital Control Techniques With Repetitive Integral Action for Low Cost PWM Inverters, IEEE Trans. Power Electron., vol. 18, No. 1, pp. 401 - 410, Jan. 2003. /14/ K. Zhang, Y. Kang, J. Chen, Direct Repetitive Control of SPWM Inverter for UPS Purpose, IEEE Trans. Power Electron., vol. 18, No. 3, pp. 784 - 792, May 2003. /15/ Y. Ito, S. Kawauchi, Microprocessor Based Robust Digital Control for UPS with Three-Phase PWM Inverter, IEEE Trans. Power Electron., vol. 10, No. 2, pp. 196-204, Mar. 1995. mag. Gorazd Modrijan, univ. dipl. inž. el. as. dr. Marko Petkovšek, univ. dipl. inž. el. doc. dr. Peter Zajec, univ. dipl. inž. el. izr. prof. dr. Danijel Vončina, univ. dipl. inž. el. Laboratorij za močnostno elektroniko in regulacijsko tehniko Univerza v Ljubljani, Fakulteta za elektrotehnko Tržaška cesta 25, 1000 Ljubljana, Slovenija e-mail: gorazd.modrijan@fe.uni-lj.si, marko.petkovsek@fe.uni-ij.si, peter.zajec@fe.uni-lj.si, voncina @fe. uni-lj. si tel: +386 1 47 68 466, fax: +386 1 47 68 487 Prispelo (Arrived): 14. 02. 2006; Sprejeto (Accepted): 29. 05. 2006 101 UDK621,3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 36(2006)3, Ljubljana MERITVE SVETLOBNO-TEHNICNIH VELIČIN Grega Bizjak Univerza v Ljubljani, Fakulteta za elektrotehniko, Laboratorij za razsvetljavo in fotometrijo, Ljubljana, Slovenija Kjučne besede: fotometrija, svetlobni tok, svetilnost, svetlost, osvetljenost, meritev svetlobe Izvleček: Svetloba je fizikalno gledano elektromagnetno valovanje. Je pa tudi medij, ki omogoča naš vid in dojemanje sveta. Pri tem sodelujejo naše oči, živčni sistem in možgani in pokaže se, da ta sistem ni enako občutljiv za vse valovne dolžine. Zaradi tega je bilo poleg radiometrije, ki se ukvarja z merjenjem elektromagnetnega valovanja, vpeljati tudi fotometrijo, ki pa svetlobo meri tako, kot jo dojema naš vidni sistem. V članku so zato najprej opisane osnove dojemanja svetlobe in osnovne fotometrične veličine. V nadaljevanju pa sledi opis fotometrlčnih merilnih priprav torej fotometrov. Podana je tudi kratka zgodovina fotometričnih normal, predvsem normale za svetilnost. Na koncu pa je dodan še kratek opis Laboratorija za razsvetljavo in fotometrijo, ki že skoraj 80 let deluje v sklopu Fakultete za elektrotehniko na Ljubljanski univerzi. Measurements of Photometric Quantities Key words', photometry, luminous flux, luminous intensity, illuminance, luminance, measurement of light Abstract: Light is part of the electromagnetic radiation and therefore a physical quantity. On the other hand, light is also a human sensation in similar fashion to sound, taste, smell and warmth. Light can so be considered as a radiation or as our response to it. As a radiation, light can be measured with the help of radiometry and radiometric quantities like radiant flux, radiant intensity, irradiance or radiance. But light as a response to this EM radiations involves also the behavior of our visual system (eye, nerves, brain). Our visual system, like other physical detectors of radiation, reacts only to a certain part of the spectrum. Moreover the sensitivity of the human eye to radiation is not the same for each of the wavelengths of the light. So the photometry was Introduced to measure light in such a way that the results correlate with visual sensation that would be experienced by a human observer exposed to the same radiation. In order to fulfill the mentioned aim of photometry, a special function V(l) was introduced, which describes the relative spectral sensitivity of the (average) human eye. This function enables us, to calculate the photometry quantities like luminous flux, luminous intensity, illuminance and luminance from the radiometry ones. In the paper first the photometry quantities and units are presented. Further the development of photometer, the device for measuring photometrical quantities, is described. Both visual and physical photometers are mentioned. At the end of chapter 3 the modern photometers, based on semiconductor photo-voltaic cell are Introduced and its use for measurement of illumination, luminous intensity, luminous flux and luminance are described. Chapter 5 deals with definitions of photometric units, especially with candela, the unit for luminous intensity. In this chapter also the photometric standards are introduced. The history of candela standard is described from use of candle to the realization of candela with a high accuracy cryogenic radiometer. Also the luminous flux standards and luminance standards are mentioned. In the last chapter some information about the Laboratory of lighting and photometry are given. The Laboratory, which has a 80 years long tradition, is part of the Faculty of Electrical Engineering at the University of Ljubljana, Slovenia. 1. Uvod Svetloba je elektromagnetno valovanje. Svetlobo lahko torej fizikalno obravnavamo enako, kot vsa elektromagnetna valovanja in jo enako lahko tudi merimo. Torej s pomočjo radiometrije. Vendar pa je svetloba tudi medij, ki nam posreduje preko 80% informacij iz našega okolja. Dojemanje svetlobe vključuje človeške oči, živčne povezave in možgane. Pokaže se, da se naš vidni sistem ne odziva na vse valovne dolžine svetlobe (elektromagnetnega sevanja) enako. Zato pri opisovanju oziroma merjenju svetlobe za potrebe vida ne moremo uporabiti radiometrije. Vpeljana je bila fotometrija, ki pri vrednotenju svetlobe upošteva tudi občutljivost človeškega vidnega organa na posamezne valovne dolžine svetlobe. 2. Fotometrija in fotometrične veličine Fotometrija je torej znanost, ki se ukvarja z merjenjem svetlobe. Kot rečeno, svetlobo lahko opišemo fizikalno kot del elektromagnetnega sevanja. In kot tako jo lahko tudi ustrezno merimo s pomočjo radiometrije in radiometričnih enot: sevalnega toka, jakosti sevanja, obsevanosti in seval-nosti. Človeške oči se ne odzivajo na vse valovne dolžine elektromagnetnega valovanja, ampak samo na valovne dolžine, ki so (grobo) omejene z 380 nm in 780 nm. Pravzaprav lahko le elektromagnetno valovanje s temi valovnimi dolžinami imenujemo svetloba. Pokaže pa se, da se človeške oči tudi ne odzivajo na vse valovne dolžine svetlobe enako. S poskusi in meritvami je bilo dokazano, da rumeno-zelena svetloba v možganih izzove večji občutek svetlosti kot recimo rdeča ali modra svetloba z enako energijo. Na podlagi teh raziskav je bila določena krivulja spek- 102 G. Bizjak: Meritve svetlobno-tehničnih veličin Informacije MIDEM 36(2006)2, str. 102-109 Koznučm žarki Gama žarki X - žarki Ultravijolična svetloba Vidna s\ elloba Infrardeča svetloba Mikro valovi Televizijski valovi Radijski valovi X(m) X(nm) ..... 10-M l«) Ultravijolična Vijolična -MI )0-s Modra : — 1V< "i g 10 - ........... Zelena . ..... sisu 7 7 10" ............ Rumena : •¡m lO-1 Oranžna (ni . \ Rdeča , .......'770 Infrardeča ; ..... 1400 I O'5 Slikal: Delitev spektra elektromagnetnega valovanja tralne občutljivosti človeškega očesa, ki jo običajno označujemo z V(A,). m o > 1.0 = 3 y-j £¡ 0.8 skotopski . o es C (nočni) vid / 0.6 / "cS e sevalni tok in Km konstanta z vrednostjo 683 Im/W. Svetlobni tok (angleško: luminous flux) je merilo za količino energije, ki jo vir seva v prostor. Je ekvivalent moči v "Wattih" vendar z upoštevanjem občutljivosti oči na svetlobo posameznih valovnih dolžin. Enota za svetlobni tok je lumen z oznako Im. Za primerjavo: navadna 100W žarnica ima približno 1300 Im, fluorescenčna sijalka moči 58 W oddaja približno 5200 Im, 90 W nlzkotlačna natrijeva sijalka pa kar 13500 Im. 2.2 Svetilnost Svetilnost (angleško: luminous intensity) odgovarja v radi-ometriji jakosti sevanja. Predstavlja torej delež svetlobnega toka v določeni smeri oziroma v določenem prostorskem kotu. 1 = d& dO, (2) dfl, . Slika 3: Predstavitev svetilnosti s pomočjo svetlobnega toka in prostorskega kota Vsota (integral) svetilnost v vseh smereh okoli vira, oziroma v polnem prostorskem kotu, je torej enaka svetlobnemu toku. Enota za svetilnost je kandela (oznaka: cd), kije tudi ena od osnovnih enot SI merskega sistema. Zadnja definicija kandele je iz leta 1979 in pravi: 1 kandela (cd) je svetilnost v določeni smeri vira z monokromatsko svetlobo frekvence 540 x 1012 Hz, ki ima jakost sevanja v tej smeri 1/683 W/sr. 103 Informacije MIDEM 36(2006)2, str. 102-109 G. Bizjak: Meritve svetlobno-tehničnih veličin Svetilnost je odvisna od izbrane smeri, zato jo največkrat podajamo v polarnih diagramih. Nekaj karakterističnih vrednosti: sveča ima svetilnost 0,6 do 1,1 cd, navadna žarnica približno 110 cd, sonce zunaj atmosfere pa kar 3 x 1027 cd. Slika 4: Prikaz kotne porazdelitve svetilnosti v polarnem diagramu 2.3 Osvetljenost Osvetljenost (angleško: illuminance) je podana kot količina svetlobnega toka, ki konča na določeni ploskvi in je torej ekvivalent obsevanosti v radiometriji. Enota za osvetljenost je torej lm/m2 oziroma luks (lx). E cKD dA (3) Osvetljenost pa je možno določiti tudi s pomočjo svetilnosti. Zvezo podaja fotometrlčni zakon oddaljenosti, ki ga lahko, ob predpostavki, daje ploskev, na kateri opazujemo osvetljenost, pravokotna na smer širjenja svetlobe, zapišemo kot: 7-1 Z E = — (4) r Osvetljenost je fotometrična veličina, ki jo je najlaže Izmeriti, zato se jo tudi največ uporablja. Standardi, priporočila in predpisi podajajo tako na primer minimalne vrednosti osvetljenosti na delovnem mestu. Še nekaj karakterističnih vrednosti: osvetljenost poletnega travnika pri jasnem nebu opoldne je okoli 100.000 lx, v senci drevesa pa okoli 10.000 lx, osvetljenost pisalne mize v pisarni je 500 lx, osvetljenost pločnika ponoči pri uporabi ustrezne cestne razsvetljave doseže do 20 lx, na travniku v mesečini pa bi izmerili 0,05 lx. 2.4 Svetlost Svetlost (opazovane točke) je definirana s pomočjo svetlobnega toka, ki ga točka na izbrani ploskvi oddaja v izbran prostorski kot. Določimo jo lahko po enačbi: L = • d20 dA • cosy • dO. (5) Pri tem je d

(Im) I : A j Osvetljenost E(lx) Q : r u Svetilnost I (cd) j : A Svetlost L (cd/m2) Slika 6: Prikaz povezav med osnovnimi fotometričnimi enotami 104 G. Bizjak: Meritve svetlobno-tehničnih veličin Informacije MIDEM 36(2006)2, str. 102-109 3. Fotometer Inštrument, s katerim lahko izmerimo katero od fotometričnih veličin, v splošnem imenujemo fotometer. Prvi opis fotometra se pojavi v letu 1729 v delu "Essai d'optique sur la gradation de la lumiere" Pierra Bouguera (1698-1758), profesorja v Havre. Fotometer, ki je prikazan na spodnji sliki, je temeljil na primerjavi svetlosti dveh površin, ki ju osvetljujeta dva različna svetlobna vira. Na podlagi enakih svetlosti obeh površin je možno sklepati o enaki osvetljenosti, ki ju je, s pomočjo znanih (kvadratov) oddaljenosti od enega in drugega vira, možno preračunati v svetilnost neznanega vira. Seveda ob poznavanju svetilnosti drugega vira. Neznani vir svetlobe „ Referenčni ' vir svetlobe Prosojen > papir Slika /; Slika prvega Bouguerjevega totometra, objavljena leta 1760 Opisani princip subjektivne fotometrije se je kasneje pojavil še v mnogih drugih znanstvenih delih znanih avtorjev s tega področja kot so Lambert, Thompson, VVedge Trotter in drugi. Zaradi lažjega in točnejšega določanja razdalje so v merilni postopek vpeljali še fotometrično klop, tako da ja priprava za meritev svetilnosti neznanega vira izgledala tako, kot je prikazana na spodnji sliki. Slika 8: Fotometrična klop (A) s subjektivnim fotometrom (B), neznanim in referenčnim svetlobnim virom (C) in zaslonkami (D). Vendar pa opisane subjektivne merilne metode, kljub natančnosti izdelave optičnih inštrumentov, kmalu niso več zagotavljale ustrezne točnosti. Danes govorimo o objektivni fotometriji, ki temelji predvsem na optoelektronskih pretvornikih, kot so fotocelica, fotopomnoževalka, fotoupor in fotodioda. Vendar pa se v zadnjem času uporabljajo skoraj izključno le še silicijeve fotodiode. S pomočjo posebnih optičnih filtrov je možno njihovo spektralno občutljivost ustrezno prilagoditi spektralni občutljivosti človeških oči. Ob ustrezni povezavi fotodiode z merilnikom toka tako dobimo merilnik osvetljenosti aH lux-meter. Slika 9: Laboratorijski lux-meter razreda točnosti L Ostale tri osnovne fotometrične veličine je prav tako možno meriti s fotodiodo oziroma luks-metrom. Seveda ob upoštevanju določenih fizikalnih povezav in zakonov. Svetilnost merimo običajno na fotometrični klopi ob upoštevanju razdalje med virom in fotoelementom, kot je to že bilo opisano pri subjektivni fotometriji.. V kolikor pa nas zanima kotna porazdelitev svetilnosti, lahko uporabimo gonlofotom-eter. Slika 10:Goniofotometer z zrcalom 105 G. Bizjak: Informacije MIDEM 36(2006)2, str. 102-109 Meritve svetlobno-tehničnih veličin Svetlobni tok se prav tako da izmeriti z goniofotometrom in integracijo svetilnosti po celotnem prostorskem kotu. Hitrejša metoda pa je uporaba integrirne (Ulbrichtove) krogle. Opazovani svetlobni vir se namesti v sredino integrirne krogle. Premaz notranje stene krogle z ustreznimi refleksijski-mi lastnostmi zagotavlja, daje notranja površina enakomerno osvetljena. Če del notranje površine krogle nadomestimo z fotodiodo oziroma lux-metrom, lahko iz izmerjene osvetljenosti in poznavanja velikosti krogle izračunamo svetlobni tok vira. Lahko pa meritev opravimo tudi primerjalno z virom, katerega svetlobni tok poznamo. "A Slika 11 ilntegrirna krogla Slika 12:Merilnik svetlosti Z fotodiodo lahko izmerimo tudi svetlost, in sicertako, da z ustrezno optično napravo omejimo kot, pod katerim svetloba pada na površino fotodiode. Taki merilni pripravi rečemo merilnik svetlosti. Izvedba je lahko enostavnejša, tako da optični objektiv samo nataknemo za glavo lux-me-tra. Lahko pa je merilnik svetlosti izdelan tudi z ustreznim okularjem, ki omogoča, da skozi objektiv tudi vidimo področje, katerega svetlost merimo. Opazovani kot je pri merilnikih svetlosti običajno velik 1 ° ali 3 Za meritve svetlosti na področju cestne razsvetljave pa se uporabljajo tudi merilniki z manjšimi koti opazovanja (20 ' (ločnih minut) ali tudi samo 6 '). Zares prenosna fotometra sta samo merilnik osvetljenosti (lux-meter) in merilnik svetlosti. Zaradi tega standard DIN 5032, ki podaja osnove merjenja svetlobe, navaja samo Razred inštrumenta oznaka Pogrešek (po DIN 5032) L A B C prilagoditev V(X.) krivulji f> 1,5% 3 % 6% 9% UV občutljivost u 0,2 % 1 % 2% 4% IR občutljivost r 0,2 % 1 % 2% 4% prilagoditev cos ep krivulji Í2 1,5% 1,5% 3 % 6% vrednotenje Eq f2.0 10% 10% 15% 20% vrednotenje Ez Í2.z 5% 5% 10% 15% vrednotenje E2h /¡.h 5 % 5% 10% 15% pogrešek linearizaeije^ h 0,2 % 1 % 2% 5% pogrešek kazalnika f* 0,2 % 3 % 4,5 % 7,5 % utrujenost /5 0,1 % 0,5 % 1 % 2% temperaturni koeficient 01.0, a25 0,1 %/K 0,2 %/K 1 %/K 2 %/K modulirana svetloba /7 0,1 % 0,2 % 0,5 % 1 % pogrešek odklona fu 0,1 % 0,5 % 1 % 2% skupni pogrešek .fses 3 % 5% 10 % 20% spodnja frekvenčna meja fu 40 Hz 40 Hz 40 Hz 40 Hz zgornja frekvenčna meja fo lO5 Hz 105 Hz 104 Hz 10J Hz Tabela 2: Dovoljeni maksimalni pogreški za posamezne razrede točnosti pri merilnikih osvetljenosti po standardu DIN 5032 106 G. Bizjak: Meritve svetiobno-tehničnih veličin Informacije MIDEM 36(2006)2, str. 102-109 Tabela 3: Dovoljeni maksimalni pogreški za posamezne razrede točnosti pri merilnikih svetlosti po standardu DIN 5032 Razred inštrumenta oznaka Pogrešek (po DIN 5032) L A B C prilagoditev V krivulji fi 2% 3 % 6% 9% UV občutljivost u 0,2 % 1 % 2% 4% IR občutljivost r 0,2 % 1 % 2% 4% prostorsko vrednotenje fi(z) 2% 3 % 6% 9% vpliv svetlosti okolice m 1 % 1,5 % 2% 4% pogrešek linearizacije h 0,2 % 1 % 2% 5% pogrešek kazalnika ¡4 0,2 % 3% 4,5 % 7,5 % utrujenost h 0,1 % 0,5 % 1 % 2% temperaturni koeficient a o, a 25 0,1 %/K 0,2 %/K 1 %/K 2 %/K modulirana svetloba /7 0,1 % 0,2 % 0,5 % 1 % pogrešek zaradi polarizacije fs 0,2 % 1 % 2% 4% pogrešek odklona fll 0,1 % 0,5 % 1 % 2% pogrešek izostritve f,2 0,4 % 1 % 1 % 1 % skupni pogrešek fs.es 5 % 7,5 % 10% 20% spodnja frekvenčna meja fu 40 Hz 40 Hz 40 Hz 40 Hz zgornja frekvenčna meja fo 105 Hz 105 Hz 104 Hz 10J Hz se je z razvojem fotometrov tudi pri svetilkah pokazala ista slabost torej slaba ponovljivost svetlosti plamena. Zato so ob koncu devetnajstega stoletja začeli razmišljati o drugačni vrsti normale, ki bi temeljila na črnem sevalu znane površine in temperature. Pojavila so se prva sevala s staljeno platino, imenovana tudi Violla normale. Vendar pa so se tudi pri teh sevalih pojavljale težave zaradi nečistoč v platini, ki so povzročale razlike v svetlosti površine in s tem tudi v svetilnosti normale. Vzačetku dvajsetega stoletja so nekaj časa razmišljali, da bi normalo za svetlost izdelali v obliki električne žarnice. Vendar pa se je pokazalo, da ni možno dovolj natančno opredeliti in izdelati žarnico, ki bi lahko služIla kot absolutna normala. So se pa žarnice uveljavile kot sekundarne normale za svetlost. Leta 1909 so raziskovanja pripeljala do prvega standarda "mednarodne kandele", ki je temeljil na sevalu iz čistega torija, potopljenega v platino pri temperaturi trojne točke (2042 K). Platino so segrevali v visokofrekvenčni peči moči 7 kW. To normalo je leta 1921 sprejela tudi mednarodna komisija za razsvetljavo (CIE), leta 1948 pa tudi Mednarodna konferenca za mere in uteži. Ob tem so tudi spremenili ime enoti iz candle v candela. Leta 1979 pa je Mednarodna komisija za mere in uteži sprejela novo definicijo kandele. Ta pravi, da je kandela svetilnost v dani smeh vira z monokromatskim sevanjem frekvence 540x1012 Hz, ki ima v tej smeri jakost sevanja 1/683 W/sr. Frekvenca 540x1012 Hz odgovarja valovni dolžini 555,016 nm v standardnem zraku, to pa je svetloba, na katero so človeške oči najbolj občutljive. Tako danes enota za kandelo nI več predstavljena s sevalom, pač pa na podlagi absolutne občutljivosti ustreznega detektorja (npr. visoko-točni kriogeni radiometer). Še vedno pa je kandelo možno predstaviti tudi z črnim sevalom. 107 razrede točnosti za ta dva inštrumenta. Tako za merilnik osvetljenosti kot za merilnik svetlosti so v standardu navedeni štirje razredi točnosti: L, A, BinC. Dovoljeni skupni pogreški so za posamezne razrede podani v tabeli 2. Normale fotometričnih enot Zgodovina normal v fotometriji se začne v začetku devetnajstega stoletja, ko so začeli uporabljati plamen sveče kot normalo za svetilnost. Od tod tudi ime enote za svetilnost (kandela), ki izhaja iz angleške besede candle za svečo. Taka normala je zadoščala le kratek čas, saj so z izboljšanimi fotometri kmalu odkrili, daje svetilnost plamena sveče zelo težko reproducirati, pa čeprav se predpisali sestavo, obliko in hitrost gorenja sveče. Slika 13:Hefnerjeva svetilka Zato so svečo kmalu nasledile svetilke s plamenom, ki so uporabljale različne vrste goriva. Poznanih je bilo več vrst, med bolj znanimi pa je bila Hefnerjeva svetilka. Vendar pa Informacije MIDEM 36(2006)2, str. 102-109 Slika 14:Električna žarnica kot riormala za svetilnost Poleg normal za svetilnost uporabljamo v fotometrijl še normale za svetlobni tok ter normale za svetlost. Normale za svetlobni tok so večinoma Izvedene v obliki žarnic. Lahko pa uporabimo tudi druge električne svetlobne vire, na primer fluorescenčne sijalke. Vendar pa moramo v tem primeru uporabiti tudi ustrezno umerjeno predstlkalno napravo. Normale za svetlobni tok se uporabljajo pri primerjalnem merjenju svetlobnega toka v integrlrni krogli. Sicer pa slednja omogoča tudi absolutno merjenje svetlobnega toka, tako da normala ni vedno potrebna. Na podobnem principu kot integrirna krogla deluje tudi normala za svetlost. Sestavljena je Iz manjše krogle v kateri je nameščen vir svetlobe, običajno žarnica. Notranja stena je obdelana s premazom, z visoko odsevnostjo z Lambertovo kotno porazdelitvijo, zaradi česar je osvetljenost notranje površine krogle enakomerna. Nato manjši del stene krogle nadomestimo okencem, ki je lahko prekrito s prosojnim materialom. Površina okenca ima zaradi enakomerne osvetljenost tudi enakomerno svetlost. Tako normalo se da umeriti s pomočjo merilnika osvetljenosti pri znani razdalji med njima in njuni geometriji. Ne poznamo pa normale za osvetljenost. Merilnike osvetljenosti (lux-metre) zato umerjamo s pomočjo normale za svetilnost in znane razdalje med njima v skladu s fotometričnim zakonom oddaljenosti (enačba 4). Laboratorij za razsvetljavo in fotometrijo Laboratorij za razsvetljavo In fotometrijo se nahaja na Fakulteti za elektrotehniko Univerze v Ljubljani. Je eden od slovenskih merilnih laboratorijev z najdaljšim stažem. G. Bizjak: Meritve svetlobno-tehničnih veličin Slika 15:Normala za svetlost Ustanovljen je bil že jeseni leta 1921, ko se je Elektrotehniški oddelek takratne Tehniške fakultete preselil v nove prostore na Aškerčevi. Laboratorij se danes sicer nahaja v drugih prostorih, vendar je še vedno tako kot takrat "ves v črnem, ne le stene ampak tudi pod in oknice, ki zastirajo svetlobo, so črne" (citat iz knjige Zgodovina slovenske univerze v Ljubljani do 1929, izdane 1929). Slika 16:Notranjost laboratorija Vse od takrat se laboratorij uspešno razvija. Danes lahko v laboratoriju izvajamo praktično vse fotometrične meritve. Za merjenje svetlobnega toka je na voljo več normalnih žarnic in integrirna krogla. Meritev svetilnosti je možna na 108 G. Bizjak: Meritve svetlobno-tehničnih veličin Informacije MIDEM 36(2006)2, str. 102-109 fotometrični klopi dolžine 2 m ob uporabi različnih normalnih žarnic. Izdelali smo tudi preprost goniofotometer, ki omogoča osnovno merjenje kotne porazdelitve svetilnosti. Merjenje osvetljenosti je možno s precizijskim luks-metrom razreda L ter z različnimi prenosnimi luks-metri. Svetlost pa lahko izmerimo s pomočjo kombiniranega merilnika svetlosti, ki je hkrati tudi spektroradiometer. Torej nam omogoča tudi meritve spektralne vsebine svetlobe, barve svetlobe in indeksa barvnega videza. Na voljo so tudi stabilizirani viri enosmerne in izmenične napetosti ter merilni inštrumenti električnih veličin. Z opremo v laboratoriju (normalnimi žarnicami in fotometrično klopjo) je možno umerjati merilnike osvetljenosti. V laboratoriju izdelane normale za svetlost pa omogočajo tudi umerjanje merilnikov svetlosti. Z uporabo normalnih žarnic, fotometrične klopi in integrirne krogle je možno umerjanje delovnih normal za svetlobni tok in svetilnost. Poleg z meritvami, se v laboratoriju ukvarjamo tudi z razvojem merilne opreme. Eden zadnjih projektovje razvoj merilnika svetlosti na osnovi digitalne kamere. Prednost takega merilnika je, da omogoča tudi merjenje svetlosti majhnih površin, na primer presvetljenih piktogramov na stikalih. Del dejavnosti pa predstavlja tudi projektiranje razsvetljave in izračuni osvetljenosti in svetlosti v notranjih in zunanjih prostorih. Laboratorij za razsvetljavo in fotometrijo trenutno še ni akreditiran za kallbracijo fotometričnih inštrumentov, se pa trudimo, da bi ta korak čim prej opravili. Literatura Casimer DeCusatis, Handbook of Applied Photometry, American Institute of Physics, 1997 Hans-Jürgen Hentschel, Licht und Beleuchtung, Hütnig Verlag Heidelberg, 2002 Jahn W. T. Walsh, Photometry, Dover Publications Inc., 1958 Joseph B. Murdoch, lluminating Ingineering, Visions Communications, 2003 Dietrich Gall, Grundlagen der Lichtechnik, Pflaum Verlag, 2004 Arne Valberg, Light vision color, Wiley, 2005 Katalog izdelkov LMT, LMT Berlin, 1998 Grega Bizjak, Meritev svetlobno-tehničnih veličin, Posvet o meritvah TC Semto, Ljubljana, 2005 Doc. dr. Grega Bizjak, univ. dipl. inž. el. Univerza v Ljubljani, Fakulteta za elektrotehniko Laboratorij za razsvetljavo in fotometrijo Tržaška 25, Ljubljana tel.: 01 - 4768 446 fax.: 01 - 4768 289 e-mail: grega. bizjak@fe. uni-lj. si Prispelo (Arrived): 10. 05. 2006; Sprejeto (Accepted): 29. 05. 2006 109 UDK621,3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 36(2006)3, Ljubljana O MERILNI TEHNOLOGIJI Z VIDIKA PODJETNIŠKEGA MIKROOKOLJA Rudi Zorko Metrel d,d., Horjul, Slovenia Kjučne besede: meritev, inovacija, metrologija, podjetje, globalnost, dodana vrednost, strošek, povezovanje, strategija, mikrookolje, makrookolje Opisani so vidiki položaja podjetja v panogi merilne tehnike in v obdobju globalizacije.Posebej so poudarjeni notranji poslovni procesi v podjetju,položaj podjetja v globalnem okolju in pomen povezav in sodelovanja.Izraziteje so opredeljene spremembe v vsebini in delovanju mikrokolja v podjetju. About metrology from entrepreneurial microenvironment point of view Keywords: measurement, innovation, metrology, globalisation, added value, cost,price, interconnection, strategy, microenvironment, macroenviron-ment Era of globalisation at one hand and possibilities of positioning of the hightech company in the field of measurement technology on other hand is described. Integration of measurement in sophisticated engineering solutions is present in new produts and services. Therefore, there are more and more equipment with analysing and diagnostics perfornamance present on the market. Industry metrology is driving force for new products and services. Quality should be measured and it is done by measurement of parameters and characteristics. A company on global market is affected by different pressure like dangers and opportunities. Technology itself is not enough for the succes of the company. Management of the intellectual property in the company is a key issue to the success. Open innovation circle is very important to realise most competitive solutions with best inputs and resources. Innovations portfolio in the company shows the presence of various innovation steps like continuous, by leaps and radical, Innovation. All the time Business Opportunity Evaluation is part of decision making process. Collaboration of the company with the partners is very important but it must be parí of core stratey, vision and goals. Analysig of mistakes in cooperation is very useful to improve relatioships. Only 30% business relationships are succesful, nearly 70% are finished premature. Microenvironment of the company is most oriented to this categories of creations: - permanet innovating - cell manufacturing - strategyc planning - standartisation activities - customer is first - products placing - R&D processes - purchasing marketing - Manufacturing process - management of reductions - Total predictive maintenance - continuously improvements - six sigma quality criteria - measurement of succes Uvod Poslovno udejstvovanje na področju ustvarjanja dodane vrednosti v povezavi z Izdelki in storitvami merilne tehnologije sodi v področje takoimenovanih »visokih tehnologij«. Tudi zato in ne samo zato je to področje, ki je v intenzivnem razvoju in kot tako tudi zelo razširjena strokovna disciplina v večini področij človekovega ustvarjanja in projektiranja naprav moderne dobe. Temeljne zakonitosti metrologije povezane z novimi tehnologijami in merilnimi metodami ob uporabi mikroprocesorjev in druge proračunalniške koncepcije nudijo vsak dan nove naprave pa tudi nove do včeraj še neaktualne storitve. Nekatera podjetja delujejo tudi alternativno na povsem novih principih lahko bi rekli nadkukorenčno. To pomeni iskanje še neodkritih priložnosti za določeno skupino uporabnikov. 384 Danes opažamo, da se je meritev sama, kot fizikalna operacija enostavno skrila v celovitost rešitve inženirskega izziva na določenem pojavu. Čeprav je meritev večkrat prektrita z procesiranjem, obdelavo signala in drugimi tehnološkimi danostmi še vedno nastopa v svojem bistvu ko je merjenje skupina eksperimentalnih postopkov, ki imajo za cilj določitev ene veličine. Merjenje je tudi proces primerjave vrednosti neznane veličine z veličino, ki je vzeta za enoto mere. Znanstvena disciplina, ki tudi podpira gospodarske učinke podjetništva v področju merilnih tehnologij je Metrologija. Metrologija je znanost, ki se ukvarja: z metodami merjenja veličin realizacijo in vzdrževanjem etalonov fizikalnih veličin razvojem in izdelavo merilnih naprav obdelavo, analizo, pomnjnejm in prenosom merjenih rezultatov R. Zorko: O merilni tehnologiji z vidika podjetniškega mikrookolja Informacije MIDEM 36(2006)2, str. 110-115 Merjenje je nastalo kot rezultat potrebe za ugotavljanje količinskih (kvantitativnih) karakteristik naravnih pojavov in je neposredno rezultat potrebe po primerjavi. Od samega opažanja naravnega pojava na merjenje letega se je prišlo ravno zaradi razvoja znanosti v 17. stoletju/R Bekon/. Metrologija je razvejana na zakonsko, industrijsko in znanstveno metrologijo. Zakonska metrologija je področje, ki ga določa država z zakoni in predpisi. Zakonska metrologija zagotavlja :mer-sko enotnost v državi, razvoj metrologije v skladu s tehnološkim razvojem države, povečanje kakovosti izdelkov in storitev, zaščito potrošnikov v kupoprodajnih odnosih in nadzor zaščite človekove bivalne in delovne sredine. Industrijska metrologija je področje, ki omogoča, da se industrijski in drugi proizvodi izdelujejo v skladu z mednarodnimi standardi/SIST, IEC, VDE, ISO, CE,. . . /Kakovost izdelka predstavljajo lastnosti s katerimi se ustvarja kakovost dela In življenja. Ocenjevanje kakovosti se opredeljuje z meritvami karakteristik parametrov oziroma veličin. Znanstvena metrologija je področje, ki povezuje razvojno in raziskovalno delo, ki vključuje merjenje največje točnosti in natančnosti v metroloških laboratorijih. Nekater ključne besede za področje merilne tehnike so predvsem:točnost, preciznost, ločljivost, linearnost, občutljivost, prag delovanja, stabilnost, ponovljivost, histereza, vhodna in izhodna impedanca. Podjetje v globalnem okolju Položaj podjetja iz dejavnosti merilne tehnologije je vezano tako na nevarnosti kot tudi na priložnosti na tržišču. Med nevarnosti lahko štejemo zasičenost trga, vojna cen, konkurenca, nova zakonodaja, itd. Ključno je, da podjetje vedno znova preverja in ugotavlja pretok denarja, dohodkovnost oziroma dodano vrednost. V globalnem prostoru tudi za panogo merilne tehnologije obstojijo izzivi in priložnosti a seveda tudi nevarnosti. Tehnologija sama po sebi še ne določa uspeha manage-menta upravljanja inovacij. Za uspeh je potrebnih še več parametrov. Predvsem stalna inovacija v podjetju je zelo pomembna za uspešnost plasmana izdelkov. Svoje mesto v razvojnem procesu ima stalna, skokovita pa tudi radikalna inovacija. Kupci pravzaprav niso pretirano zainteresirani za tehniške lastnosti izdelka, več jim pomenjo prodajni argumenti v katere so preoblikovne tehniške lastnosti, ki prepričljivo kažejo na vrednost izdelka v vrednostni verigi kupca. Izdelki in storitve (instrumenti, testerji, umerjanje) v panogi merilne tehnologije so del poslovnih modelov, ki so zazanamovani predvsem z: naravnanim tržnim segmentom vrednoto za uporabnika vezano na aktualno zasnovo in tehnologijo Mnogo podjetji se znajde v zanki (toda tega se še ne zavedajo) Staine nevarnosti H Zasičenost trga ^ • Zasičenost cen pretok denarja Podjetje X Si#» ??? ^ Motnje v sistemu r - ' Konkurenca • Nova zakonodaja • etc. Slika 1: Nevarnosti in motnje, ki prežijo na podjetje usmeritvijo na ključno vrednoto ponudbe definiranjem verige vrednosti za oblikovanje ponudbe vzdržnim modelom dospetja plačil računov vzpostavitvijo prilagajanja vrednot za obstoj poslovnega modela Portfolio inovacij v podjetju je slejkoprej vezano na presek dejavnikov med tržiščem oziroma uporabnikom in tehnologijo oziroma izdelkom Zaprt inovacijski sistem Tehnologija •*.«.**•* * ► Raziskave Razvoj Novi izdelki in tržišče Slika 2: Proces inoviranja v industrijskem okolju Narava dela in stalnih izboljšav zahteva v inovativnem podjetju vse vidike stalnega optimiranja programa: lijak idej novih poslov zametki novih poslov atraktivnost inovacij in izboljšav ustvarjanje projektov novih poslov ustanovitev novih podjetij ustanavljanje poslovnih enot Sestavni del portfolia inoviranja so tudi naslednje situacije ter ukrepi: hitrost inovativnega procesa soočenje s tveganjem in stroški izločanje nezanesljivih trgov in tehnologij odločitev o vlaganju in številu projektov priprava poslovnega načrta 111 Informacije MIDEM 36(2006)2, str. 110-115 R. Zorko: O merilni tehnologiji z vidika podjetniškega mikrookolja Poslovne priložnosti naj bi bile predmet stalne evaluacije predvsem z vidika merljive atraktivnosti za uporabnika na eni primerljivosti za podjetje na drugi strani. Opredelitev podjetja do inovacije je običajno ena od naslednjih odločitev: izločitev ideje podpora ideje odprodaja inovacije na določeni stopnji oblikovanje partnerstva na inovaciji ali ustanovitev podjetja formiranje nove dejavnosti v podjetju izogniti uničevalni tekmi s konkurenco za vsako ceno na enakih ali podobnih izdelkih. Klasičen RR krog Oosežki leitiiilnjih tehnologij Večanje vlaganj v RR Novi izdefki in odlike Portfolio inovacij pri razvoju izdelkov in storitev Večanje prodaje tn dobička na obstoječem poslovnem modelu —i prilagajanje j skokovitost Hf rizično področje sedanjost obnova novo Trg / uporaba Slika 3: Stopnje inovativnosti v odnosu na razmerje med izdelkom in njegovo uporabnostjo Ob klasičnem notranjem razvojno-raziskovalnem krogu se v podjetju uveljavlja tudi razvojno-raziskovalni krog, ki je obrnjen navzven. Pri navznoter naravnanem inovacijskem krogu obstoje nekakšne skrite predpostavke izvajalcev in sicer: v kolikor to odkrijem bom sam našel tržišče vkolikor to odkrijem prvi bo to moja last predvidevam, da je pomembna tehnologija, ki je potrebna tudi na voljo predvidevam da najboljši ljudje na tem področju delajo za nas In kaj se je spremenilo z ozirom na povedano? vedno več je na voljo mobilnih strokovnjakov in delavcev z vrhunskimi sposobnostmi vedno več je kvalitetnih centrov znanja predvsem univerz manjši je tehnološki vpliv velesil prisotno je tržno prerazporejanje največjih dobaviteljev več je na voljo startnega in tveganega kapitala Povedano pa narekuje potrebo , da podjetje podvzame ukrepe in reagira na zlom klasičnega inovacijskega kroga. Predvsem je to odnos do uvajanja odprte inovativnosti tudi z zapolnitvijo vrzeli z zunanjo tehnologijo oziroma znanjem. Le tako je možno ustvarjati vrednostno inovacijo, ustvarjati nove izdelke in storitve za nova tržišča in se vsaj nekolko Slika 4: Razvojno raziskovalni krog v industrijskem podjetju Logika odprte inovacije pomeni predvsem spoznanje, da so danes dobre ideje zelo razširjene in da ni monopola nad uporabo znanja. Posebej je treba gospodariti oziroma upravljati z industrijsko lastnino ter blagovno znamko. Za plemenitenje lastnega poslovnega modela potrebujemo tudi vzpostavitev odnosa z zunanjo industrijsko lastnino. Na drugi strani pa moramo iskati priložnosti, da se ustvarja dobiček tudi v drugih poslovnih modelih z našo industrijsko lastnino. Vedno pa moramo vedeti da ne delajo najpametnejši ljudje samo za nas. Evaluacija poslovnih priložnosti Ustreznost podjeiju Slika 5: Shema upravljanja s poslovnimi priložnostmi Vse to je potrebno zaradi iskanja novih neodkritih a obetavnih trgov in tehnologij za stopnjevanje poslovnega portfelja podjetja. Prav tako moramo ustvarjati verigo vrednosti s katero vsopamo v strateška poslovna zavezništva. Odprta inovativnost nam omogoča tudi ustvarjanje zunanjih in notranjih zametkov dejavnosti na različnih stopnjah razvoja in tehnologij. Tudi dejavnosti, ki (še) niso v jedru poslovne dejavnosti podjetja morajo ustvarjati prihodek od rezultatov dejavnosti. V Evropi naj bi nastala najbolj konkurenčna družba, temelječa na znanju na svetu. Veliko pobud in politik poskuša delovati v tej smeri a zaenkrat so makro kot tudi mikro gospodarski parametri pod težo bremen družbe, ki išče svojo priložnost. 112 R. Zorko: O merilni tehnologiji z vidika podjetniškega mikrookolja Informacije MIDEM 36(2006)2, str. 110-115 Dejstvo je, da tehnologija sama po sebi še ne določa uspešnosti inovacij, dogaja se tudi da velik del dobičkonosnih inovacij ni vezan na znanje temelječe na znanosti. Vprašanje ali nizkozahtevne tehnološke inovacije temeljijo na znanju dobi odgovor na tisti strani, ko je znanje tudi podjetništvo, inovacija izdelka, iznajdljivost, prodornost in manj zanstveno pogojeno kreativnost. Za inovativnost v nizkozahtevnih tehnoloških panogah pa je značilen tisti del inovativnosti, ki se odraža s povezavo podjetij in izobraževalnega sistema (ne samo univerz). Take povezave pa bistveno spreminjajo odnos do uporabnega znanja. Povezovanje podjetja s subjekti zunanjega okolja je zelo bistveno za doseganje poslovnih učinkov. Seveda mora podjetje imeti poslovno naravnanost, cilje, smotre, vizijo in strategijo. Da bi bili pripravljeni na kvalitetna partnerstva pa moramo posebno pozornost nameniti pripravi na sklepanje takih povezav. Te priprave pomenijo opredelitev naslednjih pojmov: strategija poslov podjetja strategija predvidene povezave stranke v povezavi način delovanja povezave pogoji za stalno napredovanje povezave identifikacija kompetenc v povezavi spremljanje razvoja in poslanstva razvoja povezave dopolnjevanje strategije povezave Da bi bile povezave čimbolj kakovostne je smiselna analiza na način kot kaže slika 6 Odprta inovativnost v podjetju: Rast novega posia in dobička ter dobiček iz licenc Poiniiev vrzeli z zunanjo tehnologijo TehnoloSki proboj Notranja tehnološki! 1)3 ta tehnološka l>a*a Zunanji raziskovalni projekti Licenca za tehnologijo Viri tehnologije Notranji razvoj Realizacija tehnologije Slika 6. Proces inoviranja v poindustrijskem okolju Pri vzpostavljanju poslovnopartnerskih povezav je zelo pomembno: priprava, izbira poslovnega partnerja, vzajemni strateški cilj, pogajanja, vodenje sodelave pa tudi stalno preverjanje dosežkov poslovnega partnerstva. V Evropi so še posebej aktualne povezave, ki so razvojno naravnane. Sem sodi lahko vstopanje podjetja v Tehnološke platforme, Tehnološke parke, 7. Evropski okvirni razvojni program, Eureko in tudi druge. Analiza napak Povezave-kooperacije Rslativni faktorji Odnosi med ljudmi, kultura prizadevanj Pozicioniranje, ; strategija ; 60-70% vseh povezav se konča predčasno Slika 7; Nujnost povezovanja podjetij in analiziranje težav v povezovanju Na svetovnem trgu uveljavljeno podjetje iz programa merilne tehnologije naj bi svoj, poslovni proces snovalo na najsodobnejših principih delovanja In med ključne besede sodijo naslednje aktivnosti: Inovacija kot stalnica Strateško načrtovanje Planiranje kooperacij Upoštevanje kupca Razvojno inovacijski sistem Proizvodni proces Celovito vzdrževanje Kakovost po»six sigma« Modeliranje proizvodnih celic Tehnike usposabljanja Poudarjanje vrednot Delo na standardih Vodenje redukcij Lansiranje izdelka Strategija nabavne verige Proces izboljšav Obvladovanje sprememb-KAlZEN Sprotno ugotavljanje uspešnosti Materialni tokovi Izvajanje poslovnega sistema podjetja Poseben poudarek pripada naslednlm dejavnostim: *Procesu razvoja talentov v podjetju *Organizaciji planiranja "Usposabljanju za vrhunsko voditeljstvo *Vzodbujanju šampionskega navdiha voditeljev 'Upravljanju z blagovno znamko "Upravljanju industrijsko lastnino Seveda pa moramo vedeti, da je hrbtenica poslovnosti v podjetju pogojena z: LJUDMI, NAČRTOVANJEM, UČINKI, KUPCI, KAKOVOSTJO, STROŠKI IN INOVACIJO Seveda moram posebej poudariti pomen najvišjih vodilnih v podjetju in s tem v zvezi pomen menedžmenta v podjetju. Ob tem velja v razmislek citirati Fredmunda Malika (menedžerski svetovalec in profesor na Univerzi v St. Gal-lenu). 113 Informacije MIDEM 36(2006)2, str. 110-115 R. Zorko: O merilni tehnologiji z vidika podjetniškega mikrookolja »Neoliberalnemu polovičnemu znanju je treba pripisati, da je gospodarstvo v svojih temeljih ogroženo. Pravi liberalizem ne zahteva, da so vsi cilji podrejeni gospodarstvu. Tisto kar liberalizem res zahteva pa je, da je vsak odgovoren za svoje ravnanje. To mora veljati tudi za menedžerje. Številna načela liberalizma so bila preobrnjena v svoje nasprotje. . Zmotno je ljudem pridigati, da je tržno gospodarstvo čudovit sistem. Tržno gospodarstvo je slab sistem, tudi zato, ker ga ljudje iz dneva v dan kot takega doživljajo. Doživljajo ga kot brutalnega, neusmiljenega, nečloveškega in nepravičnega. Menedžerji bi morali tržno gospodarstvo sicer braniti, ne pa ga hvaliti. Tudi oni vedo da je tržno gospodarstvo slabo in neučinkovito. Vedo pa tudi, da so vsi drugi sistemi še veliko slabši in manj učinkoviti. Naivno je reči, da bo vse uredil trg. Ta namreč ne prinaša nobenega gospodarskega učinka, ne prepreči nobene napake, temveč jih kaznuje potem, ko so se že zgodile. Da bi lahko popravili slabosti in škodo, ki jo prinaša trg, potrebujemo dobre menedžerje, ki poslanstva podjetij ne bi reducirali na intersese delničarjev in maksimiranje dobička. « Podlaga za dinamične inovacije je prav gotovo znanje in sposobnost dojemanja temeljnih raziskav in še posebej aplikativnih raziskav po tehnološki in tržni strani. Inovacija je vedno časovno opredeljena, okvirom dodane vrednosti in tudi geografski namembnosti. Poudariti moramo še pomen oblikovanja (designa), patentov pa tudi standardov in tehnične regulative ter s komercialnega vidika ceno in predprodajno pa tudi poprodajno podporo uporabnikom. Izvedljivost razvojnega projekta v globaliziranem podjetju merilne tehnologije je vezana na izvedljivost tehnologije, ekonomike in pravne regulative. S pravnega vidika so pomembne tudi nacionalne zakonodaje, patenti pa tudi predpisi o eventuelnih nekomercialnih barierah. Študija izvedljivosti projekta je ključna za izvedbo glavne faze razvojnega projekta. Seveda je bistveno, da pridemo do izdelka z dobro tržno pozicijo, le tako se lahko nadejamo dobri prodaji. Parametrov, ki vplivajo na tržno pozicijo je seveda več, prav gotovo pa ne moremo mimo funkcionalne vrednosti izdelka ali storitve, cene, uveljavljenosti blagovne znamke pa tudi obsega ponudbe drugih proizvajalcev (konkurence). V visoko tehnološki dejavnosti kar merilna tehnika zagotovo je, je pomembno tudi posredovanje aplikativnega znanja za izdelek do uporabnika. Organiziranje pred in popro-dajne podpore je zelo bistveno za penetracijo izdelka na trgu. Posredovanje znanja na seminarjih in tudi preko elektronskega medija pa je stalna praksa za tekoči program in še posebej za nove izdelke. Merilna tehnika sodi v visokotehnološko tržno nišo in faktor časa v procesu inovacije še posebej pomembno vlogo. Posebej moramo poudariti estetske in ergonomske vidike pravočasnega oblikovanja izdelka. Poleg oblikovanja se tudi v Industriji merilne tehnike realizira tehnični razvoj na določenih programskih vsebinah, kijih opredeljuje poslovni načrt podjetja. Pri tehničnem razvoju v panogi merilne tehnike so pomembna znanja predvsem eksaktnih ved fizike, mehanike, elektrotehnike in elektronike, kemije, programske opreme, aparaturne opreme in drugih. V samem tehničnem razvoju so RR (raziskovalno-razvojne) aktivnosti realizirane v simbiozi inženirjev v Tehničnem razvoju in tudi inženirjev v Marketingu. Faze razvoja so predvsem: priprava in izdelava tehničnega zahtevnika, eksperimentalni razvoj, funkcionalno modeliranje, izdelava prototipa, izvajanje preskušanja, razvojna serija in poskusna serija. Področja uporabnosti končnih izdelkov v Merilni tehniki so največkrat opredeljene z naslednjimi ključnimi besedami: instrument, tester, analizator v povezavi z diagnostiko mon-itoringom, testiranjem, merjenjem, analiziranjem, preskušanjem, primerjanjem, presojanjem in drugimi možnostmi, ki jih merilna tehnika nudi. Analiza napak Priprava Izbira partnerja Organiziranost na strateški cilj Pogajanja Ni bilo jasnih ciljev; j ; Manjka wi