ISSN 0352-9045 Informacije i MIDEM Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 3(2018), September 2018 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 48, številka 3(2018), September 2018 V /V UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 3-2018 Journal of Microelectronics, Electronic Components and Materials VOLUME 48, NO. 3(167), LJUBLJANA, SEPTEMBER 2018 | LETNIK 48, NO. 3(167), LJUBLJANA, SEPTEMBER 2018 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2018. All rights reserved. | Revija izhaja trimesečno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale - Društvo MIDEM. Copyright © 2018. Vse pravice pridržane. Editor in Chief | Glavni in odgovorni urednik Marko Topič, University of Ljubljana (UL), Faculty of Electrical Engineering, Slovenia Editor of Electronic Edition | Urednik elektronske izdaje Kristijan Brecl, UL, Faculty of Electrical Engineering, Slovenia Associate Editors | Odgovorni področni uredniki Vanja Ambrožič, UL, Faculty of Electrical Engineering, Slovenia Arpad Burmen, UL, Faculty of Electrical Engineering, Slovenia Danjela Kuščer Hrovatin, Jožef Stefan Institute, Slovenia Matija Pirc, UL, Faculty of Electrical Engineering, Slovenia Matjaž Vidmar, UL, Faculty of Electrical Engineering, Slovenia Editorial Board | Uredniški odbor Mohamed Akil, ESIEE PARIS, France Giuseppe Buja, University of Padova, Italy Gian-Franco Dalla Betta, University of Trento, Italy Martyn Fice, University College London, United Kingdom Ciprian Iliescu, Institute of Bioengineering and Nanotechnology, A*STAR, Singapore Malgorzata Jakubowska, Warsaw University of Technology, Poland Marc Lethiecq, University of Tours, France Teresa Orlowska-Kowalska, Wroclaw University of Technology, Poland Luca Palmieri, University of Padova, Italy International Advisory Board | Časopisni svet Janez Trontelj, UL, Faculty of Electrical Engineering, Slovenia - Chairman Cor Claeys, IMEC, Leuven, Belgium Denis Donlagic, University of Maribor, Faculty of Elec. Eng. and Computer Science, Slovenia Zvonko Fazarinc, CIS, Stanford University, Stanford, USA Leszek J. Golonka, Technical University Wroclaw, Wroclaw, Poland Jean-Marie Haussonne, EIC-LUSAC, Octeville, France Barbara Malič, Jožef Stefan Institute, Slovenia Miran Mozetič, Jožef Stefan Institute, Slovenia Stane Pejovnik, UL, Faculty of Chemistry and Chemical Technology, Slovenia Giorgio Pignatel, University of Perugia, Italy Giovanni Soncini, University of Trento, Trento, Italy Iztok Šorli, MIKROIKS d.o.o., Ljubljana, Slovenia Hong Wang, Xi'an Jiaotong University, China Headquarters | Naslov uredništva Uredništvo Informacije MIDEM MIDEM pri MIKROIKS Stegne 11, 1521 Ljubljana, Slovenia T. +386 (0)1 513 37 68 F. + 386 (0)1 513 37 71 E. info@midem-drustvo.si www.midem-drustvo.si Annual subscription rate is 160 EUR, separate issue is 40 EUR. MIDEM members and Society sponsors receive current issues for free. Scientific Council for Technical Sciences of Slovenian Research Agency has recognized Informacije MIDEM as scientific Journal for microelectronics, electronic components and materials. Publishing of the Journal is cofi-nanced by Slovenian Research Agency and by Society sponsors. Scientific and professional papers published in the journal are indexed and abstracted in COBISS and INSPEC databases. The Journal is indexed by ISI® for Sci Search®, Research Alert® and Material Science Citation Index™. | Letna naročnina je 160 EUR, cena posamezne številke pa 40 EUR. Člani in sponzorji MIDEM prejemajo posamezne številke brezplačno. Znanstveni svet za tehnične vede je podal pozitivno mnenje o reviji kot znanstveno-strokovni reviji za mikroelektroniko, elektronske sestavne dele in materiale. Izdajo revije sofinancirajo ARRS in sponzorji društva. Znanstveno-strokovne prispevke objavljene v Informacijah MIDEM zajemamo v podatkovne baze COBISS in INSPEC. Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madic Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana Informacije imidem Journal of Microelectronics, Electronic Components and Materials vol. 48, No. 3(2018) Content | Vsebina Original scientific papers Izvirni znanstveni članki I. E. Sacu, M. Alci: Low-power OTA-C Based Tuneable Fractional Order Filters 135 I. E. Sacu, M. Alci: Nastavljiv filter frakcijskega reda nizkih moči na osnovi OTA-C V. Erginer, O. Girgin: A Novel Space Vector Modulation Based Control Strategy for Z-Source Inverter 145 V. Erginer, Ö. Girgin: Kontrolna strategija inverterja na osnovi modulacije prostorskega vektorja T. Svete, A. Pletersek: Digital implementation of a demodulator for HF RFID reader device 155 T. Svete, A. Pleteršek: Digitalna implementacija demodulatorja za HF RFID izpraševalnik A. Kamaraj, P. Marichamy: Design of Fault-Tolerant Reversible Floating Point Division 161 A. Kamaraj, P. Marichamy: Načrtovanje proti napakam odpornega reverznega deljenja s plavajočo S. Thamphiwatana, T. Phairatana, S. Chirasatitsin, M. Samae, G. V. Casquillas, H. Al-Salami, S. Kojic, G. M. Stojanovic: A microfluidic micromixer fabricated using polydimethylsiloxane-based platform for biomedical applications 173 S. Thamphiwatana, T. Phairatana, S. Chirasatitsin, M. Samae, G. V. Casquillas, H. Al-Salami, S. Kojic, G. M. Stojanovic: Mikrofluidični mikro mešalnik z uporabo platforme na osnovi polidimetilsiloksana za biomedicinske aplikacije V. Dj. Vukic: Computer Simulation Model for Evaluation of Radiation and Post-Irradiation Effects in Voltage Regulator with Vertical PNP Power Transistor Front page: Microfluidic micromixer (S. Thamphiwatana et al.) 181 V. Dj. Vukic: Računalniški simulacijski model za ocenjevanje sevalnih in post sevalnih vplivov na napetostni regulator z vertikalnim močnosnim tranzistorjem PNP Naslovnica: Mikro mešalnik tekočin (S. Thamphiwatana et al.) 133 134 Original scientific paper /midem Journal of M Informacije | Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 3(2018), 135 - 144 Low-power OTA-C Based Tuneable Fractional Order Filters Ibrahim Ethem Sacu1, Mustafa Alci2 institute of Natural and Applied Sciences, Erciyes University, Kayseri, Turkey 2Department of Electrical and Electronics Engineering, Erciyes University, Kayseri, Turkey Abstract: In this study, a low-voltage low-power, simple operational transconductance amplifier (OTA) based fractional order low-pass and high-pass filters of order (n+a) are designed and simulated with CADENCE-PSPICE where 01. The employed transconductance amplifier operates at ±0.75 V. To simulate designed filters, 0.35 ^m TSMC CMOS technology parameters are used. The simulation results verify theoretical statements. The power dissipations of simulated low-pass filters of orders 1.3, 1.5, 2.3 and 2.5 are 14.6 nW, 13 nW, 17 nW and 15.3 nW, respectively. For the same filter orders, the corresponding dissipation values of high-pass filters are respectively 45.2 nW, 42.7 nW, 47.5 nW and 45 nW. In addition to the low-power low-voltage operation, another significant advantage of the proposed circuit topologies is that the OTA based low-pass and high-pass topologies provide electronic tuning capability of the orders and frequency responses of the filters without any structural change on these topologies. Therefore, same circuit topology can be used for the different orders of the same filter by just changing the biasing currents of the used OTAs. Additionally, OTA-C based filters offer usage of the grounded capacitors as well as resistorless realization. Keywords: Fractional filter; fractional circuit; low power Nastavljiv filter frakcijskega reda nizkih moči na osnovi OTA-C Izvleček: Članek predstavlja nizko in visoko pasovne filtre nizkih napetost in majhne moči na osnovi transkonduktančnega operacijskega ojačevalnika (OTC). Filtri reda (n+a) so načrtani in simulirani v CADNECE_PSPICE okolju, pri čemer je 01. Transkonduktančni ojačevalnik deluje pri napetosti ±0.75 V. Filtri so simulirani v 0.35 ^m TSMC CMOS tehnologiji. Poraba moči simuliranih nizkopasovnih filtrov reda 1.3, 1.5, 2.3 in 2.5 so 14.6 nW, 13 nW, 17 nW in 15.3 nW. Visokopasovni filtri enakih redov porabijo 45.2 nW, 42.7 nW, 47.5 nW in 45 nW moči. Nizko napetostno delovanje pri nizki porabi moči omogoča možnost elektronske nastavitve reda filtra brez spreminjanja topologije. Ista topologija tako omogoča izvedbo filtra različnega reda le s spreminjanjem mirovnega toka OTA. Filti na osnovi OTA-C omogočajo ozemljitev kondenzatorjev in izvedb o brez uporabe uporov. Ključne besede: frakcijski filter; frakcijsko vezje; nizka moč * Corresponding Author's e-mail: malci@ erciyes.edu.tr 1 Introduction Fractional calculus is a branch of mathematics that considers differential equations of arbitrary order in contrast to classical calculus. It eliminates the requirement that the order of differential equations has to be integer. Therefore, it generalizes conventional differential and integral equations and helps the modelling of the real world phenomena better [1, 2]. Fractional calculus has found applications in engineering, biology, control, viscoelasticity, electromagnetism, diffusion theory etc. [3]. By applying fractional calculus to electronics, sinusoidal oscillators, multi-vibrator circuits, phase locked loops, analogue fractional order controllers, differentiators-integrators and fractional order filters have emerged [3-23]. In the literature, several definitions of fractional derivatives have been proposed. One of them is the Riemann and Liouville fractional derivative, which is given as -f (t) = Da f (t) =--— (1) dta r(1 -a) dt {(t -T)a 135 © MIDEM Society I. E. Sacu et al; Informacije Midem, Vol. 48, No. 3(2018), 135 - 144 where T(.) is the Gamma function and fractional order a is 0) = G2 t1t2...t„ Gi Gn -s + - TiT2-T„+i TT2-T„+2 sn+2 + — S-+1 + 1 (16) Ti S +.....+- T1T2 TiT2...T„+2 2.4 Fractional high-pass filters of order (n+a) As following the similar procedure carried out in the section of the (n+a) order fractional low-pass filters, the developed BD diagram and design equations for their high-pass counterparts are depicted in Fig.4 and expressed as H FHPF (s) H FHPF 1+a (s) BHP(s) (19) where HUaFHPF(s) is the fractional high-pass filter given by (10) and BniHP(s) is the Butterworth high-pass polynomial derived by writing 1/s instead of s in Bn1LP(s). Substituting (10) into (19), the general IFLF form of fractional high-pass filters is obtained as By equating (15) with (16), it can be obtained that HT (s) = X 3 s2 + X 2 s + X j Yfl+2 s n+2 + Yn+js n+j +.....+ Yjs + Y0 (20) where the coefficients Xi (/=1,2,3) and Y.t (/=n+2, n+1,...0) can be derived using k (/=0,1,2,3) in (11) and m s (/=0,1,2) Cim2 1 138 I. E. Sacu et al; Informacije Midem, Vol. 48, No. 3(2018), 135 - 144 in (6) and the coefficients of the Butterworth high-pass polynomial BHPnJ(s). From Fig.4b, the transfer function of this topology is found as G3 sn+2 + 20 subcarrier periods). Figure 3 shows the basic structure of the proposed subcarrier demodulator. The symbol recognition algorithm (SRA) block tracks the demodulator output signal and performs symbol recognition and start of packet detection for BPSK coded protocols or collision detec- 157 T. Svete et all; Informacije Midem, Vol. 48, No. 3(2018), 155 - 160 tion for Manchester coded protocols. The numerically controlled phase (NCP) block controls the phase of the I and Q subcarrier clocks. Only the signs of the multi-bit signals from the filter outputs are used, as only one phase correction of fixed size is possible per subcarrier period. As such, the time in subcarrier periods the loop takes to achieve phase lock (or approximate phase lock), depends on the phase correction resolution. In the case of ISO/IEC 14443 type B f/128 kbit/s, a main clock frequency of f=13.56 MHz is used. The subcarrier frequency is f/16 or 847.5 kHz. This means that there are 16 samples for every subcarrier period. The size of the phase correction is one sample, or 1/16 of the subcarrier period, which means that the phase corrections are coarse, but sufficient for successful demodulation of the subcarrier signal. Ideally, it takes 4 phase corrections at most to align the I subcarrier clock phase to the input subcarrier phase. With excessive noise it can take longer. Phase corrections are disabled when a phase change is occurring on the subcarrier signal so a false phase correction does not occur. Figure 4: Measurement setup block diagram 5 Packet error rate theoretical limits To have an absolute benchmark to compare with measurement results a theoretical limit of the bit error rate (BER) or packet error rate (PER) for HF RFID protocols is needed. We derive the theoretical limit from [8]. Figure 3: Block diagram of the proposed demodulator The architecture can easily be scaled if size is a limitation, at the cost of performance. For example, the area of the IIR low pass filters can be reduced by reducing the filter order or increasing the ratio between the filter sampling frequency and cutoff frequency. The cost for this is worse noise attenuation and, as a result, worse noise performance. 4 Hardware implementation The demodulator was implemented on a field-programmable gate array (FPGA) development board for debugging and testing purposes. Since only the digital part of the receiver could be implemented on a FPGA, the analog front end (AFE) and ADCs were implemented with separate ICs, as shown in figure 4. For the AFE, the reader IC ST25R3911 was used. The IC was configured into a test mode, where the AFE outputs were available on its output pins. ADCs were used to sample the AFE outputs and relay their data to the FPGA. This way, a direct comparison between the proposed demodulator and ST25R3911 was possible. F = V T ^b Y Srms1b V2 N _ Nrms BW berbpsk = 2 erfc PER = l-(l-BER)' (2) (3) (4) (5) Equation 2 describes the energy per bit Eb in relation to the signal rms voltage VSrms and the bit duration Tb. Equation 3 describes the noise power spectral density Ng in relation to the noise rms voltage VNmms and the bandwidth of the noise BW. Equation 4 shows the ideal performance of BPSK coded protocols, such as ISO/IEC 14443 type B. Equation 5 shows the relation between the bit error rate and packet error rate for a given packet length of l bits. Bit length l needs to hold the number of all bits that need to be received successfully in order for the packet to be received successfully, as standard HF RFID data packets do not include error correcting codes. Special symbols, start, stop, parity, and CRC bits all need to be included. The longer the data packet, the less likely it will be received correctly in its entirety in a noisy environment. This limit only takes into account the errors that arise from bit errors in the presence of noise, but not the errors that occur when packet start or end are not detected due to noise. However, the limit is very useful since it represents an absolute marker unrelated to demodulator architecture, against which demodulator 158 T. Svete et all; Informacije Midem, Vol. 48, No. 3(2018), 155 - 160 performance can be compared. The smaller the difference between the measured and the theoretical limit, the better the performance of the demodulator is. code and BPSK result is 6.02 dB, as can be seen when comparing ISO/IEC 14443 type A f/128 kbit/s and f/64 kbit/s (same data structure, different bit coding). A similar formula can be written for Manchester coded protocols: 6 Measurement results Manchester = ^ ^^ J8 Nv (6) Equation 6 describes the ideal performance of Manchester coded protocols, such as ISO/IEC 14443 type A for a data rate of f/128 kbit/s. Compared to equation 4, we have a factor of 8 present in the denominator of the fraction inside the square root. This factor is the result of differences between Manchester code and BPSK. It stems from the need to correctly recognize both bit halves and a smaller distance between bit symbols in the constellation diagram for Manchester coded signals. Interestingly, ISO/IEC 14443 type A f/128 kbit/s has the same theoretical PER as type A f/16 kbit/s (type A data rates larger than f/128 kbit/s are BPSK coded), which demonstrates the superior robustness of BPSK compared to Manchester code with regards to noise. Table 1 shows the Eb/N0 (energy per bit to noise power spectral density ratio or SNR per bit) values in dB for 10 % PER for all protocols and data rates for data packets 10 bytes long (8 data and 2 CRC bytes). Table 1: Theoretical 10 % PER limits for a 10 byte long data packet for various HF RFID protocols and data rates. Protocol Data rate [kbit/s] 10 % PER Eb/N0 [dB] ISO/IEC 14443 type A* fc/128 12.69 ISO/IEC 14443 type A fc/64 6.67 ISO/IEC 14443 type A fc/32 6.67 ISO/IEC 14443 type A fc/16 6.67 ISO/IEC 14443 type B fc/128 6.91 ISO/IEC 14443 type B fc/64 6.91 ISO/IEC 14443 type B fc/32 6.91 ISO/IEC 14443 type B fc/16 6.91 ISO/IEC 15693* fc/2048 12.68 ISO/IEC 15693* fc/512 12.68 FeliCa fc/64 6.78 FeliCa fc/32 6.78 When comparing different protocols from table 1, one can observe the difference in E./N„ the data structure b0 and bit coding make. Protocols marked with an asterisk * have Manchester coded bits, whereas the rest are BPSK coded. The difference between Manchester The testing of the performance of the demodulator was done with PER measurements. For each SNR value a number of noisy packets were sent and the success rate of reception measured. Figure 5: Sketch of the test pattern generation procedure. Figure 5 shows the three steps in test pattern generation. First, a modulation signal with the correct packet structure was created, as shown in a). Then, band limited additive white Gaussian noise (AWGN) was added, as shown in b). The noise BW was 5 MHz while N0 was determined by the desired SNR value (equation 3). The noise BW was selected so it encompassed the entire BW of the data spectrum and usable frequency range of the AFE. The noisy modulation signal was then scaled and used to modulate a 13.56 MHz carrier, as shown in c). The test pattern generation was done in a Python script and uploaded to the signal generator to be fed into the device under test. An external clock source supplied a clock signal synchronous to the carrier field. The gain of the AFE was reduced to avoid adding more noise to the packets by any other noise sources (thermal and 1/f noise in the receiver, oscillator phase noise in the waveform generator). This was done to ensure the artificially generated noise was indeed the dominant noise source. The modulation signal was appropriately scaled, so that the signal levels at the ADC inputs were at nominal levels. Each packet had length of 8 data bytes, 2 cyclic redundancy 159 T. Svete et all; Informacije Midem, Vol. 48, No. 3(2018), 155 - 160 check (CRC) bytes, and packet structure as defined in ISO/IEC 14443 for type B at a data rate of f/128 kbit/s. Two sets of measurements were done, first on the FPGA development board with the proposed demodulator and later on the HF RFID reader IC ST25R3911. Figure 6: Packet error rate measurement results and the theoretical 106 kbit/s BPSK PER limit. Figure 6 shows the PER versus the Eb/N0 value in dB for both sets of measurements. For each data point 500 packets were sent. Figure 6 also shows a 3.1 dB difference between the theoretical limit and measured results at the 0.1 PER mark (10 % fail rate). Also shown is an almost 11 dB improvement compared to the HF RFID reader IC ST25R3911. Similar results were obtained with other protocols at their base data rates as shown in table 2. Table 2: PER measurement comparison for various protocols. Protocol Data rate [kbit/s] 10 % PER Eb/N0 [dB] Diff. to limit [dB] ISO/IEC 14443 type A fc/128 15.7 3.0 ISO/IEC 14443 type B fc/128 10.2 3.1 ISO/IEC 15693 fc/512 19.1 6.4 FeliCa fc/64 9.2 2.4 kbit/s, FeliCa f/64 kbit/s, and ISO/IEC 15693 single subcarrier f/512 kbit/s along with theoretical limits were presented. PER measurement results for ISO/IEC 14443 type B f/128 kbit/s showed good performance in noisy environment compared to theoretical f/128 kbit/s BPSK PER limit, where a 3.1 dB difference was observed. The difference between the theoretical limit and measurement results can be explained by the fact that the theoretical limit does not include the probability of errors in packet start or end detection, but only the probability of bit errors. Improvements in demodulator design reduce this difference. The theoretical limit serves as an absolute marker against which demodulator performance can be compared. Additionally, an almost 11 dB improvement was observed compared to HF RFID reader ST25R3911 for protocol ISO/IEC 14443 type B f/128 kbit/s. 8 References 1. 2. 3. 4. 5. 6. 7. 8. J. Costas, "Synchronous Communications," Proceedings of the IEEE, vol. 44, p. 1713-1718, 1956. B. Shamla, K. G. Gayathri Devi, "Design and Implementation of Costas loop for BPSK Demodulator," India Conference (INDICON), 2012 Annual IEEE, Kochi, 2012. P. Shachi, Rahul Mishra, Ravi Kumar Jatoth, "Coherent BPSK Demodulator using Costas Loop and Early-Late Gate Synchronizer," 2013 Fourth International Conference on Computing, Communications and Networking Technologies (ICCCNT), 2013. STMicroelectronics, "ST25R3911 NFC/HF Reader IC." Available: http://www.st.com/en/nfc/ st25r3911.html. Y.-H. Kim, M.-W. Seo, Y.-C. Choi, H.-J. Yoo, "A 13.56 MHz Receiver SoC for Multi-Standard RFID Reader," Electron Devices and Solid-State Circuits, 2008. H. Min, Y. Liu, C. Huang, "Digital Correlation Demodulator Design for RFID Reader Receiver," Wireless Communications and Networking Conference, 2007. C. Angerer, "A Digital Receiver Architecture for RFID Readers," Symposium on Industrial Embedded Systems, 2008. John G. Proakis, M. Salehi, Digital Communications, Fifth edition. McGraw-Hill, 2008. 7 Conclusion This paper presented a HF RFID demodulator based on a Costas loop for reception of protocols defined in ISO/IEC 14443, ISO/IEC 15693 and JIS X 6139. Demodulator design and operation were described. PER measurement results for ISO/IEC 14443 type A and B f/128 Arrived: 31. 05. 2018 Accepted: 26. 06. 2018 160 Original scientific paper /midem lournal of M Informacije | Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 3(2018), 161 - 171 Design of Fault-Tolerant Reversible Floating Point Division A. Kamaraj1, P. Marichamy2 department of ECE, Mepco Schlenk Engineering College, Sivakasi, India 2Department of ECE, PSR Engineering College, Sivakasi, India Abstract: In semiconductor industries power dissipation and the size of the computational devices are playing a major role. Size of a single transistor may limit the scaling of semiconductor devices. In turn, an alternative technology is needed for computational devices; one such technology is Reversible Logic. In this paper, a new set of reversible gates named as KMD Gates are proposed, they are capable of producing many logical functions compared to the conventionally available reversible gates. The proposed gates satisfy the reversibility and universality properties of reversible logic. In addition, these gates are having parity preservation, so they are fault-tolerant. A n-bit fault-tolerant reversible floating point division unit (FTRFPD) is designed in IEEE 754 single precision standard using the proposed fault-tolerant KMD reversible gates. This FTRFPD has parallel adder, latch, multiplexer, shift register, rounding and normalization register. All the functional blocks are fault-tolerant in nature as they are, they are constructed from the Fault-Tolerant Gates. The FTRFPD is capable of dividing two numbers using the non-restoring algorithm. Quantum Cellular Automata (QCA) is incorporated for validating the functionality of the reversible logic gates and division unit. The QCA based simulation results confirm that the designed unit is having reduction in Quantum Cost by 9.85%, in Delay by 29.63% and in Number of Gates by 33.54 % over the existing designs. Keywords: Reversible Logic; Quantum Cost; Delay. Načrtovanje proti napakam odpornega reverznega deljenja s plavajočo Izvleček: Poraba moči in velikost računskih elementov igrajo pomembno vlogo v polprevodniški industriji. Velikost posameznega tranzistorja lahko omejuje velikost poprevodniške naprave, zaradi česar je potrebna drugačna tehnologija za računske elemente, kot na primer reverzibilna logika. Članek predlaga nov set reverzibilnih vrat kot KMD vrat, ki omogočajo več logičnih operacij kot klasična vrata. Vrata zagotavljajo reverzibilnost in univerzalnost reverzibilne logike. Poleg tega predlagana vrata ohranjajo polariteto, kar pomeni, da so odporna proti napakam. Enota za deljenje s plavajočo vejico (FTRFPD) je načrtana v IEEE 785 standardu z enojno natančnostjo z uporabo predlaganih KMD vrat. FTEDPD ima paralelni množilnik, zapah, miltiplekser, pomikalni regiter ter zaokroževalni in narmalizacijski register. Vsi funkcijski blogi so odporni na napake saj vrebujejo proti napakam odporna vrata. FTEDPD lahko deli dve števili brez algoritma obnovitve. Za validacijo vrat in deljenja je uporabljen QCA (Quantum Cellular Automata). QCA simulacije potrjujejo zmanjšanje stoška kvanta za 9.85%, zakasnitve za 29.63% in števila vrat za 33.54% glede na obstoječe dizajne. Ključne besede: reverzibilna logika; strošek kvanta; zakasnitev. * Corresponding Author's e-mail: kamarajvlsi@gmail.com 1 Introduction In modern VLSI technology, size and power dissipation are the major challenges to computational devices. The size reduction of a transistor scaling has its own physical limits. Also, smaller transistors dissipate more power, and it has other second-order effects, which affect the functionality of the circuits. Landauer has proved that the irreversible computing devices dissipates heat energy in the order of KTln2 Joules for the loss of a single bit of information (where K is Boltzmann's Constant = 1.3807 x 10-23 J, T is room temperature) [1]. However, Benett has shown that the reversible computation using reversible gates is the solution to this issue [2]. It has two approaches physical and logical reversibility. Logical reversibility is the ability of the device to retrieve its input and output from each other logically; 161 © MIDEM Society A. Kamaraj et all; Informacije Midem, Vol. 48, No. 3(2018), 161 - 171 whereas Physical reversibility is provision to reverse the input and output in electronic or quantum circuits [3]. Parity checking is one of the common mechanism adapted to detect the error in the transmission and data logic. During the computation, if the parity of the input data is preserved, then there is no need for checking the intermediate stages. Thus, the parity-preserving functional units can be constructed with parity-preserving reversible gates [4]. The division is one of the most complicated functions of computer arithmetic. In this paper, we have proposed fault-tolerant reversible logic gates to construct division unit. n-bit fault-tolerant reversible floating point division (FTRFPD) circuit is constructed with these gates. The proposed design is vulnerable to errors, and it is better than the existing ones in terms of quantum costs, garbage outputs and constant inputs. The entire paper is organized as follows: in Section II, the basic definitions and performance measuring parameters are discussed. Section III discusses the relevant work previously done by various researchers in the same field. Section IV & V deal with the proposed new fault-tolerant reversible gates and fault-tolerant reversible floating point division unit. Finally, in Section VI the results obtained for the proposed division unit are being discussed. (a) 2 Basic definitions In this section basic definition of QCA, QCA clocking and performance measures commonly used are discussed. 21 QCA Basics The basic element of QCA is a cell, which represents a bit of information as in Fig.la. Each cell has four metal islands known as quantum dots. In quantum dots, two electrons occupy the four dots in "diametrically opposite" positions to polarize the dot. Logic '0' or Logic'1' is represented by the polarization position of dots as shown in Fig.1b[5]. The polarization can be computed as, P= ((P1+P3)-(P2+P4))/(P1+P2+P3+P4), where P= Charge in the ith quantum dot. 2.2 QCA Clocking QCA circuit's information flow is controlled by the Bennett Clocking scheme. It has four phases to process the (b) Logic '0' (P= -1) Logic 'l'(P=+l) Figure 1: (a) QCA cell; (b) QCA cell polarized with logic '0' and logic '1' information which is a switch, hold, release and relax as in Fig. 2. Each clock zone is 90-degree phase-shifted, which enables the computation to be carried out in a sequential manner [6]. Clock Zone 0 Clock Zone 3 Hold Hold S y V/ y Hold Relaxed A/ y Xcv NÂ> X Relaxed y Hold Hold Relaxed & / Figure 2: QCA Clocking with four phases 2.3 Performance measures Four Performance measures encountered in this work are listed below: - Quantum Cost: Quantum cost is calculated as the total number of 2*2 primitive gates required to derive the given reversible logic function [7]. Here the primitive gates refer to the conventional gates. They are Feynman, Toffoli, Fredkin and Peres gates. 162 A. Kamaraj et all; Informacije Midem, Vol. 48, No. 3(2018), 161 - 171 - Garbage output: The unwanted output of the reversible circuit is known as garbage output [7]. - Constant inputs: The input set to a stable value throughout the computation of the reversible circuit is known as constant inputs [7]. - Number of gates: It is defined as the total number of reversible gates that are utilized to obtain the desired reversible logic [7]. - Delay: The delay of the reversible circuit is equal to the total number of gates in the circuit. [8]. In other words, the maximum number of gates between the input to the output of the function is the delay of the reversible circuit. - Simple Reversible Gates: Fredkin, Feymann (CNOT), Toffoli and Peres are the most popularly used reversible gates. Toffoli is known as universal reversible 3 input gate, from this any reversible circuit can be derived [9]-[12]. - Other reversible gates: There are many other authors who proposed their own reversible gates such as D KG gate, MRG gate [13], NFT gate, TR gate and BVF gate [14]. Since, except NFT other gates are not fault-tolerant and the circuits derived from those gates are not fault-tolerant. 2.4 Fault-tolerant reversible logic A Gate is said to be fault-tolerant reversible logic gate only when it satisfies the following three properties: - Reversibility: In reversibility, input and output functions are uniquely derived from each other and vice versa for a reversible gate [15]. - Input OOutput - Universality: When a reversible gate is able to realize NOT, NAND / AND & NOR / OR functions in the output, it satisfies universality property [15]. - Fault Tolerance: Nowadays, a reversible circuit is expected to be reliable under all environmental conditions. In other words, it should be vulnerable to the fault occurrence. A gate having the same parity as in equation (1) in its input and output is said to be a fault-tolerant gate [4]. I10I20I3.....0In = O10O2^.0On _ (1) where, I. = Inputs and o. = Outputs of a gate 3 Related reversible logic works A new reversible Half adder, Full Adder, Ripple carry Adders are being built using the proposed reversible logic gates. These gates satisfy the universality and reversibility conditions as a fundamental requirement for a reversible gate [16]. Fault-tolerant full adder (FTFA) is proposed using two Islam Gates (IG) which have 3 garbage outputs and 2 constant inputs. A carry skip BCD is designed with the proposed FTFA functional unit [17]. A fault-tolerant reversible adder (FTRA) is proposed in [18] and ripple carry adder (RCA), carry skip adder (CSA) and n-bit ALU are constructed using FTRA, which are fault-tolerant [18]. Low-cost parity-preserving reversible adders such as Carry look ahead adder (CLA), Carry skip adder (CSA) and BCD adder are constructed with less quantum cost and garbage output using LCG gates [19]. A fault-tolerant reversible decoder (n to 2n) is constructed using Double Fredkin and RDC gates [20]. A signed multiplier is designed with MNFT gate which is fault-tolerant. The operating speed of the multiplier is improved using Wallace tree structures [21]. A reversible single precision floating-point square root is proposed using a modified non-restoring algorithm with Reversible Controlled-Subtract-Multiplex [22]. As an initial step towards the sequential circuit design, the latches have been designed with reversible gates. RS Flipflop is proposed in [23] with reversible gate BME and Peres. Also, D, RS and JK latches and flip-flops have been designed using MFG, FG and Toffoli reversible gates in [24]. Two approaches are proposed for n-bit fixed point division unit. Here, fault-tolerant reversible gates are utilized to make the entire division unit fault-tolerant. Both the approaches utilize nearly equal number of resources (quantum cost, garbage output etc.) [25]. A reversible floating point division is carried out with two different approaches which are conventional division and high-speed division. The results confirm that this approach is better than the previous [22] architectures in terms of quantum cost, garbage output [26]. A new fault-tolerant reversible RR gate is proposed to design a reversible division unit with fault-tolerance of n-bit. The module is constructed to meet the IEEE 754 format, which includes rounding register and normalization unit. Also, the division unit consumes less number of quantum cost, garbage output and number of gates than the previously available designs [8]. 4 The proposed logic gates A new reversible gate is introduced in two different methods: one is heroic act on the existing reversible gates and another is the creation of new gate to perform the desired operation. Fault tolerant 3*3 reversible gates are proposed to obtain the full adder function using Feynman and Fredkin gates [19]. These gates may not satisfy the universality property of a reversible gate. 163 A. Kamaraj et all; Informacije Midem, Vol. 48, No. 3(2018), 161 - 171 Here, we propose 4 reversible gates, namely KMD gate 1, KMD Gate 2, KMD Gate 3 and KMD Gate 4 as shown in Fig. 3 (a-d). These gates satisfy the fundamental requirements (reversibility and universality) of a reversible gate [15]. In addition, they are fault-tolerant in nature, i.e. EXOR function of the inputs and the outputs are equal (parity preservation). (a) (b) (c) (d) Figure 3: Block diagram (a) KMD gate 1 (b) KMD gate 2 (c) KMD gate 3 and (d) KMD gate 4 Table 1: Universality property of KMD gates 4.1 Fault-Tolerance, reversibility, and universality The fault-tolerant (parity preservation) and reversibility characteristics of the proposed gates are satisfied for the proposed gates. The inputs and the outputs of KMD Gates are having the same priority. So, the EXOR of Inputs and Outputs gives always zero for a fault-tolerant gate. Reversibility can be defined in two ways; one is, the computation overwriting the input vector with the output vector, and the other is, an unmodified copy of the input vector available elsewhere in the design [15]. For universality, a reversible gate must be able to produce NOT, AND & OR functions of 2-input format or it must be able to generate NOT, NAND / NOR functions of 2-input format [15]. The universality property of KMD Gates is represented in Table 1. From the above table, it is evident that all KMD Gates satisfy the universality property as stated in [15]. The proposed reversible gates can be constructed with fewer cells and occupy less area as shown in Table 2. Moreover, DKG and MRG are not fault-tolerant gates [13] [14]. But KMD Gates are fault-tolerant reversible gates. Thus, the construction of reversible circuits using these gates will have efficient fault-tolerant reversible circuits. 5 The Proposed methodology In arithmetic operations, the basic operations are addition, subtraction, multiplication, and division. Of them, the division is the most challenging arithmetic S. No. Reversible Gate Constant Input Logic Function Expression A=1; C=0 / 1 Q=NOT (B) Q = R' KMD Gate 1 C=1 Q = NAND (A,B) Q = A' + AB' C=0 R = OR (A, B) Q = A + A'B B=C=0 R = NOT (A) R = A' KMD Gate 2 C=0 Q = NOR (A,B) Q = A'B' = (A+B)' C=1 R = AND (A,B) R = AB B=D=0; C=1 S = NOT (A) S = A' KMD Gate 3 B=1 R = OR (A, C) R = A + A'C C=0 R = AND (A, B) R = AB B=C=1;D=0 Q = NOT(A) Q = A' KMD Gate 4 B=1 Q = NAND (A,C) Q = A' + AC' B=1; D=0 C=0 T = OR (A,C) Q = OR(A,C) T = AC' + C Q = AC' + C 164 A. Kamaraj et all; Informacije Midem, Vol. 48, No. 3(2018), 161 - 171 Table 2: Comparison of the proposed gates Gates Number of Cells used Quantum Cost Area (in ^m2) Fredkin gate [13] 187 5 0.19 DKG gate [13] 752 6 1.24 MRG GATE [13] 456 6 0.52 NFT gate[14] 128 - 0.142 KMD Gate 1 169 10 0.19 KMD Gate 2 121 10 0.13 KMD Gate 3 116 6 0.19 KMD Gate 4 244 12 0.42 operation in computer architecture design. A dedicated hardware module is incorporated into the division as part of the processor. It is a fundamental issue to identify the efficient division algorithm as per the IEEE 754 standard [27]. A complete division operation is a compound of sequential basic operations. A proposed fault tolerant floating point division unit consists of the following elements: multiplexer, Parallel In Parallel Out (PIPO) left shift register, adder/subtrac-tor unit, and rounding and normalization registers. All these functional units are designed as fault-tolerant. There are two possible methods available for the division of integer numbers. They are restoring and non-restoring divisions. In both the methods, the base operations are addition/subtraction and shifting the variables [28]. For n bit D is a dividend (2n bits to store remainder and quotient after division), V is divisor, and Q is quotient register, Restoring Division: 1. 2. 3. Shift the D (2n) to left one position. Subtract V (n) from D(V-D) and place the result back in D. If the Sign of D is 1, set MSB of Q0 to 0 and add V back to D (Restore); otherwise, set Q0 to 1. Non-Restoring Division: Step 1: (n times) 1. If the sign of D is 0, shift D left to the one-bit position and subtract V from D; otherwise, shift D and add V to D (V+D). 2. Now, if the sign of D is 0, set Q0 to 1; otherwise, set Qo to Step 2: 1. If the sign of D is 1, add V to D (V+D). In the restoring division, the left shift and subtract operation are equivalent to 2D-V. If D is negative, restore D and left shift, then subtract V which is equivalent to 2D+V. The latter case is used in the non-restoring division; which reduces the number of logical operations. The following significant changes are made in the above algorithm and flow diagram which are shown in Fig.4: - In the normal division, the dividend is shifted to the right side, here in the proposed method, it is left shifted. - The shifting is advanced to the first place rather than after the subtraction. - The remainder and quotient register are combined to form a single dividend register. The complete flow diagram of restoring division is shown in Fig.4; in the case of non-restoring, and the path is slightly changed as combining 3a and 3b of Fig.4 without restoration. In addition, to meet the IEEE 754 standard of floating point representation, the rounding and normalization are carried out. Algorithm: Inputs: D (Dividend); V (Divisor) and Sel=0. Outputs: R (Remainder) and Q (Quotient) Steps: 1. Initial: Clk=High; SP=0; Sel=0; Count=0; D=0; V=0 (Registers are Initialized) 2. If (Clk) If (SP= =0) n-bit Inputs are parallel loaded in operand registers(D & V). 3. Else if (SP= =1 & Hold = = 0& Count =n) If the result is negative; restore D and do rounding and normalization. 7. Dividend register MSB = Remainder; LSB = Quotient. 8. End. 5.1 Working Principle The complete data path of fault-tolerant floating point division is shown in Fig.5. The significant units are multiplexers, registers (F2G), parallel adder, rounding and normalization units. The necessary control signals are 165 A. Kamaraj et all; Informacije Midem, Vol. 48, No. 3(2018), 161 - 171 Figure4: Flow Diagram of floating point division Clk, load, sel, SP, set q0, shift and hold. These signals are released from the control unit at the appropriate time based on the Clk timing. Figure 5: Fault-tolerant floating point division unit When Clk is available and load & SP signals are high, the multifunctional registers are parallel loaded with '0' in 'A' register, and dividend in the Q register and divisor register are already loaded. In the next Clk, the dividend and divisor are loaded into (n+1) parallel adder. The adder performs the 2's complement addition, and the partial results are again stored back to higher order bits of the multifunctional register. In the meantime, left shifted (via F2G register) dividend is loaded back through the multiplexer and the MSB bit is serially shifted to the 'SO' of A register. Here, non-restoring division is followed in order to reduce the number of computations [28]. So, it is not necessary to restore the dividend after an unsuccessful subtraction (ie. the partial result is negative). Instead, the partial result is 2's complemented via F2G register bank and an FRG register during the next cycle. The sign bit of the partial result decides the Q0 value (ie. Q0=0, if sign =1; 1, otherwise). The same procedure is repeated for 'n' Clk cycle. After n-cycle, if the result is negative, restoration takes place; otherwise, register Q contains the quotient and 'A' register contains the remainder of the successful division. 5.2 Key elements of reversible fault-tolerant division unit The major functional units of reversible fault-tolerant division unit are multiplexers, operands registers, ad-der/subtractor, PIPO register, rounding and normalization registers. These functional units are being constructed using fault-tolerant gates; thereby the circuit becomes a fault-tolerant one. Multiplexer: KMD Gate 3 can be configured as a multiplexer with 'A' input as select line and others (B & C) are input data. The 3rd output provides the selected data. Fig.6 represents the 2 input multiplexer; when Sel=0; then C is selected; otherwise B is selected. The n-bit multiplexer can be derived by cascading the single bit structure. Here, the input D=0 provides 'sel' to be passed on to the next stage. The quantum cost of the n-bit Mux is 7n, and it has 2n garbage outputs. Figure 6: 2-input n-bit multiplexer Reversible Parallel In Parallel Out (PIPO) Shift Register: D latch can be derived from KMD Gate 3 as shown in Fig.7a. The 3rd output of the gate generates the necessary Q for the latch. A n-bit Parallel in Parallel Out (PIPO) is constructed by cascading the D-latches as shown in Fig.7a. The quantum cost of the n-bit PIPO is 7n, and it has 'n' garbage outputs. A multifunctional register is designed using D-latch and multiplexers. It acts as a left shift register; PIPO register, SISO register, and normal storage register according to the control signal. Fig.7b shows the multifunctional register with control signals hold & SP and data signals SI (Serial Input) & PI (Parallel Input). The symbol of the register is shown in Fig. 7c. n-bit register has the quantum cost of 21n, number of gates 3n and 4n garbage outputs. 166 A. Kamaraj et all; Informacije Midem, Vol. 48, No. 3(2018), 161 - 171 (a) (b) (c) CLK HOLD SP SI PI PIPO Multifunctional Register CLK HOLD SP Qi Q¡+ Figure 7: (a) n-bit PIPO Register (b) Construction of Multifunctional Register and (c) Symbol of Multifunctional Register The output behavior of the multifunctional register is tabulated in Table 3 which is derived from equation (2). Here, the parallel load operation selects the external input, and the serial input transfers the previously computed data to the next register. Q + = Hold'SP'I. + Hold'SP.Q., + Hold.Q. (2) The proposed D-latch using KMD Gate is having less of quantum cost, garbage output and gate count compared to the available latches as from Table 4. From the table, it is observed that the number of reversible gates used to construct D-latch in [8] is 7 which lead to high quantum cost and more garbage output, whereas the proposed design consists of one gate and least quantum cost of 9. Table 3: Truth table for multifunctional register Qi+ (Next Output) 0 0 Ii (Input Loaded to Register in Parallel) 0 1 Qi-1 (Left Shift & LSB receiving input from Serial Input) 1 X Qi (Maintaining Previous Value) Fault Tolerant Reversible Adder: The reversible fault-tolerant adder is being constructed using KMD Gate 4 with the quantum cost of 24 as shown in Fig.8. So, an n-bit adder consists of 21n quantum cost, 2n constant inputs, and 3n garbage outputs. Figure 8: n-bit Fault-Tolerant Reversible Adder Table 4: Performance analysis of D-latch Parameters [221 [231 [81 Proposed design Improvement % w.r.t [81 Quantum cost 14 10 47 9 35% 10% 80.8% Garbage outputs 4 2 6 1 75% 50% 83.3% Gate Count 3 3 7 1 66.6% 66.6% 85.7% Number of Cells - - - 116 - - - Area - - - 0.52pm2 - - - Clock Zone - - - 4 - - - 6 Results and Discussion To perform the comparison between different reversible division logic circuits, few chosen parameters are, A) (n+1)-bit Multiplexer B) n-bit Multiplexer C) (n+1)-bit Shift Register d) n-bit Shift Register E) Rounding Register F) Normalization Register G) Parallel Adder Figure 9: 2-bit fault tolerant reversible divider circuit 167 A. Kamaraj et all; Informacije Midem, Vol. 48, No. 3(2018), 161 - 171 quantum cost, garbage outputs, number of gates and constant inputs. The QCA realization of the above functional units and entire division unit is done using QCADesigner 2.0.3 tool as shown in Fig.9. The structure consists of multiplexer, registers, adders, normalization and rounding off units. All those modules are integrated to form the fault-tolerant reversible floating point division unit. Single bit multiplexers are combined to form the 2-bit and 3-bit multiplexers which receives dividend and zeros. At the same time, divisor register receives another divisor. The operands are then forwarded to the multifunctional register. This register is constructed using D-latch and multiplexer as in Fig.7. Then the operands are forwarded to the reversible adder. In the adder after every clk signal, the partial output is shifted one bit left. After n (number of bits) clk pulses, the adder output is forwarded to the rounding and normalization register to normalize the division as per the IEEE 754 single precision standard. The cost and other parameters calculated for individual units of the n-bit division unit is shown in Table 5a. The major components are derived from KMD Gate 3, F2G, and KMD Gate 4. Since KMD Gate 3 is utilized to construct the multiplexer and multifunctional register, the uniformity of the divider is majorly improved. Table 5b-e shows the comparison of quantum cost, number of gates, delay, and constant inputs of the division unit for 2 bits to 256 bits. From those tables, it is observed that the conventional and high-speed division array is exponentially increasing of Quantum Cost, Delay, and Constant Inputs with respect to a number of bits. But the proposed methodology is having linear relationship with the number of bits. So, proposed division unit can be utilized in any of the processor design. It is inferred that quantum cost, number of gates and delay are improved on a significant level compared to [25, 26]. For example, for the 256-bit division unit, the best available method has 3346 number of gates and delay [8]; while the proposed method has only 3076. The pictorial representation of the consumption of quantum cost, number of gates, delay and constant inputs are shown in Fig. 10a-d. It is evident that the proposed method is having linear relation with number of bits, while the existing methods having quadratic relation with number of bits. Table 5a: Performance measure calculations of individual modules of the division unit S. No. Module Number of Bits Gates Used Number of Gates Delay Quantum Cost Garbage Output Constant Input Multiplexer n KMD Gate 3 n n 6n 2n n n+1 n+1 n+1 6n + 6 2n+2 n+1 Multifunctional Register n 3n 3n 18n 5n 3n n+1 3n+1 3n+1 18n+18 5n+5 3n+3 Divisor Register n F2G n n 2n 2n n Parallel Adder n+1 KMD Gate 4 n+1 n+1 12n+12 3n+3 2n Register n F2G n n 3n - n n+1 n+1 n+1 3n+3 n+1 n+1 Other Gates 1 Fredkin 1 1 5 2 1 Total Cost 12n+4 12n+4 68n+44 20n+13 13n+6 Table 5b: Comparison of quantum cost for the existing and the proposed division unit. Number Of Existing [25] Existing [26] Proposed Bits Restoring Non-Restoring Conventional Division Array High Speed Division Array 2 210 203 33 82 180 4 360 353 74 165 316 8 660 653 204 415 588 16 1260 1253 656 1251 1132 32 2460 2453 2328 4267 2220 64 4860 4853 8744 15675 4396 128 9660 9653 33864 59995 8748 256 19360 19253 133256 234651 17452 168 A. Kamaraj et all; Informacije Midem, Vol. 48, No. 3(2018), 161 - 171 Table 5c: Comparison of number of gates for the existing and the proposed division unit. Number Of Bits Existing [25] Existing [26] Existing [8] Proposed Restoring Non-Restoring Conventional Division Array High Speed Division Array 2 59 57 13 34 44 28 4 95 93 33 69 70 52 8 167 165 79 175 122 100 16 311 309 251 531 226 196 32 599 597 883 1819 434 388 64 1172 1173 3299 6699 850 772 128 2327 2325 12739 25675 1682 1540 256 4631 4629 50051 100491 3346 3076 Table 5d: Comparison of delay for the existing and the proposed division unit. Number Of Bits Existing [25] Existing [26] Existing [8] Proposed Restoring Non-Restoring Conventional Division Array High Speed Division Array 2 54 52 24 12 43 27 4 88 86 54 27 69 51 8 156 154 150 85 121 99 16 292 290 486 297 225 195 32 564 562 1734 - 433 387 64 1108 1106 6534 - 849 771 128 2196 2194 25350 - 1681 1539 256 4372 4370 99846 - 3345 3075 Table 5e: Comparison of constant inputs for the existing and the proposed division unit. Number Of Bits Existing [25] Existing [26] Proposed Restoring Non-Restoring Conventional Division Array High Speed Division Array 2 36 34 5 20 32 4 58 56 13 39 58 8 102 100 41 95 110 16 190 188 145 279 214 32 366 364 545 935 422 64 718 716 2113 3399 838 128 1408 1406 8321 12935 1670 256 2830 2828 33025 50439 3334 Table 6: Comparison of performance measures for n-bit division unit Parameters Existing [25] Existing [26] Proposed Restoring Non-Restoring Conventional Division Array High Speed Division Array No. of Gates 18n+23 18n+21 3(n+2)2+2n/4 (n+2)(3n+11)/2 12n+4 Delay 17n+20 17n+18 3(n+2)2/2 - 12n+3 Garbage outputs 12n+18 12n+16 (n+2)2/2 (n+2)(3n+22)/4 20n+13 Quantum Cost 75n+60 75n+53 4(n+2)2+n/2 (n+2)(7n+27)/2 68n+44 Constant Input 11n+14 11n+12 (n+1)2+1/2 (n+2)(3n+14)/4 13n+6 169 A. Kamaraj et all; Informacije Midem, Vol. 48, No. 3(2018), 161 - 171 (a) (b) (c) (d) Figure 10: a. Number of bits vs Quantum cost; b. Number of bits vs Number of gates; c. Number of bits vs Delay; d Number of bits vs Constant inputs The estimated performance measurement of n-bit division unit is tabulated in Table 6. It is observed that the dependency factor 'n' - the number of bits is greatly reduced by the proposed method with respect to the existing [25, 26]. For example, conventional and highspeed division array have exponential relation with 'n', whereas the proposed method has a linear relationship. Moreover, the additional constant cost involved in 'n' is also reduced for the proposed method. From the last column of Table 6, it is observed that, the worst case additional cost is 44, but in the existing method, it is up to 60. 7 Conclusion In this paper, we have proposed a new n-bit fault-tolerant reversible floating point division unit (FTRFPD) which functions according to the non-restoring algorithm. The proposed division unit is being constructed by the fault-tolerant reversible KMD Gates. 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Arrived: 09. 04. 2018 Accepted: 13. 07. 2018 171 172 Original scientific paper /midem Journal of M Informacije | Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 3(2018), 173 - 179 A microfluidic micromixerfabricated using polydimethylsiloxane-based platform for biomedical applications Soracha Thamphiwatana1,2, Tonghathai Phairatana1, Somyot Chirasatitsin1, Mahdee Samae1, Guilhem Velve Casquillas3, Hani Al-Salami4, Sanja Kojic5, Goran M. Stojanovic5 institute of Biomedical Engineering, Faculty of Medicine, Prince Songkla University, Hatyai, Songkhla, Thailand 2Drug Delivery System Excellence Center, Prince Songkla University, Hatyai, Songkhla, Thailand 3Elvesys SAS company, Paris, France 4Biotechnology and Drug Development Research Laboratory, School of Pharmacy and Biomedical Sciences, Curtin University, Perth WA, Australia 5University of Novi Sad, Faculty of Technical Sciences, Novi Sad, Serbia Abstract: Personalised dosing microfluidic devices have great potential in transforming current biomedical treatment into more efficient and patient-tailored using lab-on-chip designs. One of the current challenges in manufacturing microfluidic devices is designing suitable mixers, at the microscale level, with intricate geometrical dimensions. The study aimed at designing micromixers using polydimethylsiloxane-based platform and investigated their performance and potential applications in biomedical devices. New microchip-like structure was fabricated and consisted of two inlets and one outlet. A mould was fabricated based on polydimethylsiloxane platform and the new design was examined in terms of mixing patterns. The flow-mixing process was tested for efficiency and robustness. The novel design showed consistent intricate dimensions suggesting fabrication method was robust and precise. The mixing ability of the micromixers showed semi-circular flow with efficient mixing at low liquids pressure (< 50 mbar) suggesting ability to mix fluids with various viscosities. Accordingly, the newly designed micromixers using polydimethylsiloxane-based platform with two inlets and one outlet have promise in biomedical fluid-mixing applications. Keywords: Micromixer, PDMS; Mixing efficiency Mikrofluidični mikro mešalnik z uporabo platforme na osnovi polidimetilsiloksana za biomedicinske aplikacije Izvleček: Mikrofluidične naprave s poosebljenim doziranjem imajo velik potencial pri spremembi trenutnega biomedicinskega zdravljenja v bolj učinkovito zdravljenje s pacientu prilagojenim dizajnom lab-on-chip naprav. Trenutni izziv je načrtovanje ustreznih mešalnikov na mikro nivoju. Članek predstavlja načrtovanje mikro mešalnikov z uporabo platforme na osnovi polidimetilsiloksana in njihovo integracijo v biomedicinske naprave. Nova mikročip struktura ima dva vhoda in en izhod. Kalup je izdelan na osnovi polidimetilsiloksana. Nov dizajn je bil opazovan s strain različnih mešalnih vzorcev. Proces pretočnega mešanja je bil preizkušen na osnovi učinkovitosti in robustnosti. Mešalna sposobnost kaže semi-cirkularni pretok z učinkovitim mešanjem pri nizkih tlakih (< 50 mbar) in različnih viskoznostih tekočin. Ključne besede: mikro mešalnik, PDMS; izkoristek mešanja * Corresponding Author's e-mail: sgoran@uns.ac.rs 173 © MIDEM Society S. Thamphiwatana et all; Informacije Midem, Vol. 48, No. 3(2018), 173 - 179 1 Introduction The proper mixing of reagents is an important process in biochemical experiments, which aims to incorporate various fluids as a way to detect concentrations of biological molecules. Microfluidic devices have attracted a huge attention due to a wide range of potential applications such as in diagnostics and pharmaceutical and biological applications [1-3]. The purpose of microfluidic mixing is to obtain a complete and fast mixing of numerous samples in microscale devices, by employing the diffusion effect at low Reynolds number in microfluidic systems [4]. Microfluidic technologies can be used to produce micromixers in order to make the whole process more efficient and reliable, minimizing cross-contamination and reducing the time and labour costs. Mixing in microchannels is a principle applied in many modern biomedical devices. Active and passive mixing approaches can be found in microfluidic chips [5]. Active micromixers require external energy sources (electro-kinetic [6], [7], ultrasonic [8], electrostatic or magnetic fields [9, 10] to generate perturbations in fluid flow. These devices provide a very good mixing characteristics and flow control. However, they are expensive for fabrication and cannot be easily integrated into complete microfluidic systems. Passive micromixers depend on diffusion process [11]. A smart geometric design is a key enabler of efficient mixing process in this type of micromixers. They can be manufactured in a simple way, using low-cost fabrication techniques and can be easily integrated with other functional components in Lab-on-chip [12] or Organ-on-chip [13] concepts, which are very popular nowadays. Taking into account above-mentioned advantages, this paper analyses fabrication process and testing of performances of a passive micromixer with innovative design. Various technologies can be used for manufacturing passive micromixers such as: printed circuit board (PCB) [14], low temperature co-fired ceramics (LTCC) [15], xu-rographic PVC foils-based technique [16], silicon-based or glass-based microfabrication [17], polydimethylsi-loxane (PDMS) technology [18]. An integrated microfluidic chip for rapid mixing of multiple liquids which requires few manipulations of pipettes has been developed in [19]. That microfluidic chip was fabricated by PDMS casting, integrated a micromixer among four other components. The lost-wax casting technique was used in [20] for fabrication of 3D PDMS microfluidic devices, but with very simple design. The fabrication of PDMS microfilters, which were chemically bonded to polyimide (PI), polyethylene-naphthalate (PEN), and polyethylene-terephthalate (PET) substrates, was demonstrated in [21]. With regard to different geometrical shape of microchannels as a main constituent of passive micromixers, the following structures have been reported: lamination mixer [22], rotational-type mixer or spiral microchannels [23], groove micromixer [24], staggered herringbone mixer [25] and splitting and re-combining the flow mechanism [26]. Manufacturing of high-performance microfluidic devices can be challenging, in particular when utilising complex structures of versatile and inconsistent shapes. This study investigates innovative and complex designs of micromixer and their fabrication using PD-MS-based platforms. PDMS is chosen for the fabrication of the micromixer due to its biocompatibility, transparency and mechanical flexibility. Design is based on semi-circular shapes of barriers creating disturbances aiming to achieve better mixing performances. The experimental testing of the fabricated microfluidic chip has been also performed. 2 Design, simulation and fabrication of micromixer 2.1 Design of micromixer The proposed innovative design of the microfluidic micromixer, including its dimensions is presented in Figure 1. The chip is composed of two inlets and one outlet. Internal structure of the chip consists of semicircular barriers which could provide the chaotic advec-tion with diffusion and enable efficient mixing of fluids from inlets. The calculation of the Reynolds number in the mixing area of 2000 ^m width and 60 ^m depth was between 0.2 - 3.0, therefore the chaotic advection with diffusion takes place. A design of microchannels was created in CleWin 4.0 software tool. Figure 1: Design and dimensions of microfluidic chip showing the positions of the inlets, the mixing chamber and the outlet 2.2 Simulation results for the proposed micromixer The proposed micromixer performances have been analysed through simulation results. Numerical simulation was carried out by software tool COMSOL mul-tiphysics, using two modules Laminar Flow and Transport of Diluted Species. The Laminar Flow module has been used for determination of the speed field vector which then transferred into the Transport of Diluted Species module which calculates the concentration of fluid in the designed micromixer. In order to provide 174 S. Thamphiwatana et all; Informacije Midem, Vol. 48, No. 3(2018), 173 - 179 evidence that proposed mixer operates properly we started simulation with the following parameters: the fluid pressure at inlets equal to 50 mbar, concentration of the red fluid (on one inlet) was 500 mol/m3, and on another inlet (blue fluid) 0 mol/m3. The obtained results of simulation are presented in Figure 2. Figure 2: Simulation results of the micromixer design From the presented simulation results it can be concluded that around internal semi-circular barriers good mixing of two fluids from inlets is performed. 2.3 Fabrication of micromixer There are two main steps to manufacture a microfluidic chip in PDMS technology: (1) fabrication of a mould and (2) replica moulding. To fabricate a mould, photolithography was used to form a pattern of the designed channels as a moulding master on a glass substrate (75 mm x 50 mm size, 0.96 mm thickness, Corning, USA). A glass substrate was cleaned with isopropanol and heated at 120 °C for 15 minutes. A dry film photoresist (30 ^m thickness, ORDYL) was covered and laminated on the glass substrate using a laminator. Using cutting-edge technologies and in-house built in systems, the first protective film was removed and then the resist was exposed for 10 seconds with an UV light (UV-KUB2) using the photomask. After exposing, the second protective film was removed. To etch the pattern, the resist was developed with agitated manually for 2 minutes in a bath containing commercial developers. Then it was rinsed with the commercial chemical, following with isopropanol. Finally, the mould was dried with compressed air. The process of mould fabrication is shown in Figure 3. Once the mould was created, the microchannels were built using chemically integrated polymer-copolymer matrices, namely polydimethylsiloxane (PDMS), by replica moulding. Using soft lithography, PDMS was used to replicate the patterned glass substrate served as a master. A mixture of PDMS base and curing agent (Sylgard 184, Dow Corning, USA) was prepared in the ratio of 10:1 by weight, and was stirred vigorously until well mixed. The mixture was degassed using a vacuum Figure 3: The process of mould fabrication using photolithography process chamber in order to eliminate air bubbles for 30 minutes. Next, the mixture was cast onto the master. The master filled with PDMS was cured in an oven at 80 °C for 2 hours. Then the replica was cut along the edge of the mould using a scalpel blade and was peeled off from the master. To access holes for the fluidic inlets and outlet insertion point, the PDMS chip were punched using a biopsy punch (1 mm in diameter, Ted-pilla). The surface of the punched PDMS chip was exposed to oxygen plasma for 2 minutes, and was placed as soon as possible against a clean glass slide to form a permanent bond. The process of PDMS replication is illustrated in Figure 4. Figure 4: The process of PDMS replication using soft lithography 3 Experimental method After microfluidic chips were fabricated, the pattern of microfluidic chip was examined under microscope. The size of microfluidic chip was comparable to one-euro coin as shown in Figure 5A. The measurements were 175 S. Thamphiwatana et all; Informacije Midem, Vol. 48, No. 3(2018), 173 - 179 performed in a mixing channel with a cross-section of 2 x 6 mm2. The first part of the channel was divided into two small inlets, and the shape of semi-circular was used as barriers in the mixing channel (the middle part) as shown in Figure 5B. Figure 5: (A) Prototype of the fabricated microfluidic chip, (B) Microscope images showing the pattern inside microfluidic chip The goal of microfluidic mixing is a thorough mixing of two or more samples in microfluidic devices. In order to achieve that goal, microchannel was designed with barriers to create the chaotic advection with diffusion (Reynolds < 10). Herein, the mixing pattern of the proposed microfluidic chip was studied with microfluidic flow controller (OB1) from Elveflow®. The experimental set-up of microfluidic system is shown in Figure 6. \ / Figure 6: (A) Schematic illustration of experimental set-up for microfluidic mixing study. (B) Photo of experimental setup. (C) Zoom-in version of microfluidic chip under microscope The flow controller was connected with vacuum pump, which is the pressure supply to the system. Pressure or flow was monitored by the Elveflow Smart Interface on computer. Microfluidic valves controllers were used to quickly start/stop flow. Flow/pressure sensor was also connected to the system for automatically adjusting the pressure in order to reach the set flow rate value. With this set-up, the pressured liquids from samples were smoothly and precisely flowed into microfluidic chip at desired rate. Flow in the chip was then observed under microscope. 4 Results and discussion 4.1 Testing of mixing performances at various pressures In this study, liquid pressure was varied from 40-200 mbar. The pressure for each channel was set at desired value. Two channels were set at same pressure flows. One channel represented the drug, which was in blue solution and another channel contained just water, which represented normal saline solution using to dilute the drug. At the first stage, the accuracy of the system was verified. At predetermined pressure, we collected samples at each pressure for 6 minutes. The representative of samples collected in each set of experiment is shown in Figure 7A. The measured volumes and appropriate flow-rates are presented in Figure 7B. Figure 7: (A) Representative photos of samples collected at various pressure flows. (B) Volume and flow rate at studied pressure range The flow-rate results were consistent with controlled pressured as expected. The obtain results indicate that the flow was precisely tuned and controlled as it was desired in this experiment. This precise flow control is important for flow transition into microchannel in order to simulate controlled drug injection into the microfluidic system. 176 S. Thamphiwatana et all; Informacije Midem, Vol. 48, No. 3(2018), 173 - 179 4.2 Evaluation of mixing efficiency To investigate the mixing performance, the standard deviation of the concentration of the colouring solution was calculated by a custom JavaScript in ImageJ. Briefly, the captured images were split into 8-bit images of red, green, and blue components. The red component was only used for measuring the intensities pixel-by-pixel via the detection zone. A standard curve relating intensities and concentrations was established. After converting the intensities to the concentrations, the homogeneity was represented by the standard deviation of the concentration over the detection area. The standard deviation can be normalized by the mean concentration to calculate the mixing index (MI): that was defined as in Eq. (1): MI 1 N - £ Nt! (c-cy c (1) Where Ci is the concentration of pixel i, N is the number of pixel over detection zone, and C is the ideally average concentration at well-mixing which is equal to 50% of the initial concentration. The standard deviation will be 0 for well-mixing. The mixing efficiency was defined as in Eq. (2): n= 1- MI = 1- 1 £ (C - C)2 N i=i C (2) The efficiency is therefore between 0 < n <1. When n =0 means the highest variation of concentration, i.e. no mixing. While n =1 is well-mixing. To relate the intensity with the corresponding concentration, the standard curve was evaluated. The preparation was used the concentration of 10 % (V/V) liquid food dye red in water solution. To cover the concentra- Figure 8: Mixing efficiency and enlarged images of outlet are representatives of the fluid flow within micromixer at different pressure flows tion, range from 0 - 100%, the standard curve was fit by a polynomial. In addition, the mixing was investigated with different pressure set-ups. The liquid 1 (red colour) and liquid 2 (water), at room temperature, entered the inlets from separated channels. The flow in the proposed microflu-idic chip was observed under microscope. The mixing efficiency was performed and mixing was quantified using above-mentioned equations. The results are illustrated in Figure 8. The mixing efficiency of is 72% at 40 mbar. It can be observed that at lower pressure (<50 mbar), two solutions were mixed thoroughly inside microfluidic chip as shown in Figure 9. The proposed micromixer efficiency around 72 % for low pressure, is comparable with the already reported mixing efficiency. For example, in paper [27], authors reported the following maximum efficiency 69, 75, and 79 % for three types of configurations of meander types of microchannels. Additionally, in the paper [28], authors presented T-micromixer's with efficiency around ~20% at similar pressures. Figure 9: Microscopic images (4x) obtained by mixing experiment in micro-mixer device at various pressure flows At high-pressure flow (>75 mbar), the mixing did not occur efficiently, because the high velocity flow rate along channel was generated, resulting in fluid could not travel across the channel by the chaotic advec-tion at a very short period of time. Even though, the mixing was not efficient at high flow rates, the diffusion area was larger when flow rate was slower. However, design of a passive micromixer is dictated by its intended application. For example, for chemical reactors and for biosensing application, the flow rate and applied pressure of the tested liquid should be small. That means, the mixing effect in the microfluidic chip should be performed by diffusion. We proposed semicircular barriers in one row 3 and in the next row 2, shifted in the space. In this way, it is achieved that fluid going between these barriers and diffusion effect are pronounced and chaotic mixing realized. Having one and the next rows close to each other, the good mixing efficiency can be reached only for low flow and small 177 S. Thamphiwatana et all; Informacije Midem, Vol. 48, No. 3(2018), 173 - 179 pressures, which is appropriate for intended (above-mentioned) applications of the proposed microfluidic chip. 5 Conclusion Findings of this study showed that the new design of micromixers exhibits preferable features with promising efficacy in biomedical and fluid-mixing applications. The use of PDMS has enhanced the performance of the micromixers and enables improved flow-mixing properties, which has significant implications in biomedical sensors and molecular-based detection capabilities. The ability of the newly designed micromixers to mix fluids of solution at a significantly low pressure (<50 mbar) is indicative of its potential biomedical applications, and thus, future work will aim to enable further development and testing of the device in biological setting such as in vivo analyses. 6 Acknowledgement Results presented in this paper received funding from the European Union's Horizon 2020 research and innovation programme under the Marie Sktodowska-Curie grant agreement no 690876, as well as partly through the TR32016. Authors thank to Mr. Mihailo Drljaca for help with some simulations. 7 References 1. Yong Hwang S, Jae Seo I, Yong Lee S, Ahn Y. Microfluidic multiplex biochip based on a point-of-care electrochemical detection system for matrix metalloproteinases. Journal of Electro-analytical Chemistry 2015, doi: 10.1016/j.jelech-em.2015.08.015. 2. Huang Y, Cai D, Chen P. Micro- and Nanotechnolo-gies for Study of Cell Secretion. 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Cabello M, Aracil C, Perdigones F, Quero JM. Conditioning Lab on PCB to Control Temperature and Mix Fluids at the Microscale for Biomedical Applications. Spanish Conference on Electron Devices (CDE), 2017. 15. Malecha K, Golonka LJ, Baldyga J, Jasinska M, So-bieszuk P. Serpentine microfluidic mixer made in LTCC. Sensors Actuators B Chem. 2009; 143(1): 400-413. 16. Chirasatitsin S, Kojic S, Stojanovic G. Optimization of microchannel fabrication using xurographic technique for microfluidic chips. Scientific conference ETIKUM'2017, Novi Sad, Serbia, December 06-08, 2017. 17. Silverio V, Cardoso S, Gaspar J, Freitas P, Moreira ALN. Design, fabrication and test of an integrated multi-microchannel heatsink for electronics cooling. Sensors and Actuators A: Physical. 2015; 235: 14-27. 18. He W, Xiao J, Zhang Z, Zhang W, Cao Y, He R, Chen Y. One-step electroplating 3D template with gradient height to enhance micromixing in micro- 178 S. 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Arrived: 20. 03. 2018 Accepted: 30. 07. 2018 179 180 Original scientific paper /midem journal of M Informacije | Journal of Microelectronics, Electronic Components and Materials Vol. 48, No. 3(2018), 181 - 193 Computer Simulation Model for Evaluation of Radiation and Post-Irradiation Effects in Voltage Regulator with Vertical PNP Power Transistor Vladimir Dj. Vukic University of Belgrade, Institute of Electrical Engineering "Nikola Tesla", Belgrade , Serbia Abstract: The aim of the presented research was to develop a faithful SPICE simulation model of radiation and post-irradiation effects in a low-dropout voltage regulator with a vertical serial PNP transistor. The main parameters for the analysis of the circuit's radiation response were the voltage regulator's maximum output current and the minimum dropout voltage, as well as the serial transistor's excess base current. All the data, comprised of the old irradiation and new annealing results, were unified and normalised, in order to enable a broad insight in the radiation tolerance of the examined circuits. Initial radiation effects, as well as the late post-irradiation effects, were successfully simulated using the variations of the maximum forward emitter current gain and knee current of the serial PNP power transistor. Ten-year room temperature annealing led to a significant recovery of the serial transistor's excess base current, yet the maximum output current and minimum dropout voltage, in most cases, expressed further degradation. On the other hand, two short-term, high-temperature annealing periods led to the tremendous recovery of all of the irradiated voltage regulators, reducing the circuit degradation down to the level perceived after absorption of nearly 10% of the total ionising dose. Keywords: vertical PNP transistor; excess base current; forward emitter current gain; computer simulation; voltage regulator, ionising radiation. Računalniški simulacijski model za ocenjevanje sevalnih in post sevalnih vplivov na napetostni regulator z vertikalnim močnosnim tranzistorjem PNP Izvleček: Cilj raziskave je bil razvoj zanesljivega SPICE simulacijskega modela sevalnih vplivov na low-drop napetostni regulator z vertikalnim serijskim tranzistorjem PNP. Glavni parametri analize odziva regulatorja na sevanje je bil največji izhodni tok in najnižja napetostna razlika med vhodom in izhodom (dropout napetost) ter bazni tok tranzistorja. Vsi podatku skupaj z rezultati starega sevanja in toplotne obdelave, so bili poenoteni in normalizirani za lažji vpogled v sevalno odpornost vezij. Začetni sevalni vplivi, kakor tudi post-sevalni vplivi, so bili uspešno simulirani s spreminjanjem ojačenja emitorskega toka in kolenskega toka tranzistorja PNP. Deset letna temperaturna obdelava pri sobni temperature je vodila k očitni ozdravitvi tranzistorskega baznega toka. Največji izhodni tok in najnižja dropout napetost je v večini primerov pokazala dodatno degradacijo. Po drugi strani pa sta dve kratkotrajni visokotemperaturni obdelavi pokazali občutno ozdravljenje obsevanih napetostnih regulatorjev, pri čemer je bila degradacija vezja ob 10% sevalni dozi zanemarljiva. Ključne besede: vertikalni tranzistor PNP; bazni tok; ojačenje emitorskega toka; simulacije; napetostni regulator; ionsko sevanje. f Corresponding Author's e-mail: vvukic@ieent.org 1 Introduction Despite the increasing use of switching power supplies, linear voltage regulators still have a wide area of use in electronic devices, particularly in battery-pow- ered systems [1]. This also applies to radiation-tolerant electronic devices, used in radiation environments such as satellites, nuclear and medical facilities as well as in the military environment. Bipolar transistors [2-5] 181 © MIDEM Society V. Dj. Vukic; Informacije Midem, Vol. 48, No. 3(2018), 181 - 193 and analogue integrated circuits [6, 7] (including voltage regulators [8-11]) have been extensively examined in the radiation fields, particularly following the discovery of the enhanced low-dose-rate sensitivity (ELDRS) in bipolar transistors [12, 13]. Since the cost of dedicated radiation-tolerant integrated circuits is very high, in recent years extensive efforts have been made to identify commercial off-the-shelf (COTS) integrated circuits (and related technology processes) suitable for application in radiation environments [14]. Among the tested circuits is the low-dropout voltage regulator STMicroelectronics' L4940V5, a circuit with a vertical PNP pass transistor [15], founded on the complementary BiCMOS process [16]. The circuit demonstrated unexpectedly high radiation tolerance [17-21], qualifying itself as a serious COTS candidate for use in moderate-dose radiation environments [17, 18]. Nevertheless, there were not enough data to create a faithful computer simulation model. Also, there were no detailed experiments that could quantify the circuit's post-irradiation response. In order to provide a wider picture on the radiation and post-irradiation effects in the L4940V5 voltage regulator, various isothermal annealing procedures were implemented. After long-term room temperature annealing, two short-term isothermal annealing procedures were performed. Also, a computer simulation model was developed in order to model the response of the vertical serial PNP power transistor. These combined efforts should enable the acquisition of comprehensive knowledge on the L4940V5 voltage regulator's radiation response. 2 Theory 2.1 Radiation effects Ionising radiation affects silicon bipolar junction transistors mainly through the mechanisms of charge-trapping, both in the oxide and on the semiconductor-oxide interface [14, 22]. The excess base current is the most important measure of the radiation-caused degradation of the bipolar junction transistor. It represents the difference between the base current measured after irradiation (/B) and the base current prior to irradiation (/J [14]: = >B - Bo (1) The base current has two components, the ideal one (IBi), affecting the transistor's current gain, and the recombination component (IJ, being the current of only the internal recombination processes in the base area [8, 23]: Ib = Ib,+ I Br = IsenVT + I^ (2) where: IS - transport saturation current [24], ISe - emitter-base leakage current, VEB - emitter-base voltage, VT -thermal voltage (being 26 mV at the room temperature of 20°C), n - ideality factor of the ideal base current, ne - ideality factor of the recombination base current (or, in SPICE models, emitter-base leakage emission coefficient [24]). Excess base current may be presented as the difference between the pre-irradiation and post-irradiation base currents. The detailed relation for the excess base current is [25]: aib =1 qnipE S XdBe 2Vt s'Wde 2Vt (3) where: s' - pre-irradiation surface recombination velocity, s" - post-irradiation surface recombination velocity, Wd - width of the depletion area in the base-emitter area prior to irradiation, q - elementary electron charge (1.6-10-19 C), n. - intrinsic carrier concentration in silicon, xdB - location of the depletion region at the surface of the base, PE - emitter perimeter, Veff - effective voltage (used in place of VEB, in order to include the influence of the oxide-trapped charge on the total voltage on the emitter-base junction) [25]. The excess base current rises proportionally to the difference of the surface recombination velocities existing prior to and after the exposure to ionising radiation. For a heavily-doped emitter and low emitter-base voltage (up to 0.6 V) [26], the excess base current may be considered to be directly proportional to the increase of the concentration of interface traps [26, 27]. Nevertheless, the excess base current cannot be affected only by the interface traps. The influence of the oxide-trapped charge is particularly important in the cases when the emitter was not heavily doped. Build-up of the oxide-trapped charge will increase the surface potential of the P-type emitter area [25]. Therefore, the surface recombination velocity depends on both the interface traps and the oxide traps. The ideality factor for the ideal base current is n = 1, but its value is not constant for the recombination current. Usually, the ideality factor of the recombination current is considered to be ne = 2, the same as during the normal operation of the transistor with a high emitter injection level [22]. Nevertheless, in reality, the re- EB EB EB 182 V. Dj. Vukic; Informacije Midem, Vol. 48, No. 3(2018), 181 - 193 combination current ideality factor has variable values between 1 and 2. Despite the long-known fact that the ideality factor is dependent on the applied baseemitter voltage [26], this fact is neglected in standard computer simulation models. In NPN bipolar transistors, the P-type base, right beneath the isolation oxide, is the most sensitive area. The reason is the relatively low doping concentration of the P-base, in comparison with the N-type collector and emitter. Both oxide-trapped charge and interface traps would negatively affect the P-type base, causing a rise in the excess base current [23]. On the other hand, in PNP transistors, the N-type base is not so endangered, since the positive oxide-trapped charge will cause the electrons to accumulate in the base area, suppressing the negative effects of the interface traps during the initial phase of irradiation [25]. If the emitter area is not heavily implanted, it will be the area most affected by the influence of radiation, experiencing the negative influence of both interface traps (increasing the surface recombination in silicon) and oxide traps (causing the depletion of the emitter area beneath the oxide) [28]. Mutually, these effects cause the depletion region on the base-emitter junction to spread deep into the emitter area, affecting the rise in the excess base current [28]. The mentioned effects depend on many factors, such as doping concentrations, the geometry of the transistors, the quality of oxides and passivation layers, etc. During the exposure to radiation of the silicon bipolar junction transistors, the initial phase will be dominated by the influence of the oxide-trapped charge [25]. At the same time, the concentration of the charge trapped at the interface between the silicon and silicon-dioxide will rise much more slowly, affecting the rise in the excess base current almost proportionally to the total absorbed dose [25]. Yet, after some time has elapsed in the ionising radiation field, the surface recombination velocity will reach its limit and the excess base current will enter the saturation phase. 2.2 Annealing Stability of defects in semiconductors and oxides, caused by radiation, depends on time, electric field and temperature [22]. Thus, a concentration of defects in materials may significantly change after irradiation, with tendency to substantially reduce in high-temperature ambient [22]. Depending on the nature of radiation and trapped charge (both in oxide and a semiconductor-oxide interface), bipolar transistors may partially recover or even further degrade its characteristics. Analysis of post-irradiation, time-dependent effects should provide a more detailed insight into the radiation response of the circuits exposed. Thermal excitation usually leads to a significant defect annealing at temperatures of 100°C and greater, while the tunneling is a dominant effect at a room temperature [22]. Several procedures were usually used, based either on isothermal [14] or isochronal [22] annealing. Isothermal annealing procedures are performed at a constant temperature (either room or elevated) [14], and this approach often enables a qualitative evaluation of the radiation-induced defects. On the other hand, isochronal annealing is performed with constant, successive time intervals [22], usually much shorter than the ones used for isothermal examinations. Isothermal annealing is a more realistic test procedure, since it may simulate a real exploitation conditions, in periods from one day up to several years. On the other hand, isochronal annealing procedures may involve high temperatures, yet in much shorter time intervals (in order of minutes). According to the published data [29], some integrated circuits showed annealing of the trapped holes from the oxide after the end of the elevated temperature (100°C) isothermal annealing, without a significant effect on the interface traps. Therefore, it would be possible for some devices to express radiation-induced degradation originating only from the influence of interface traps [29]! 3 Materials and methods Analysis of irradiation and isothermal annealing effects was performed on integrated 5-volt, positive voltage regulators STMicroelectronics® L4940V5. Samples were irradiated in the 60Co ionising radiation field in the Vinča Institute of Nuclear Sciences, Belgrade, Serbia, in the Metrology-Dosimetry Laboratory [17-19]. The devices absorbed total Y-radiation doses of 500 Gy(SiO2), at a dose rate of 4 cGy(SiO2)/s [20, 21]. For nearly ten years, the irradiated samples were kept in the office locker, at a room temperature always kept in the range 15-25°C. After 85,000 hours, all the samples of voltage regulators were tested in the same conditions as immediately after the irradiation, with a room temperature of 20°C. Shortly afterwards, the L4940V5 voltage regulators were examined to see if it would be possible to recover most of the oxide-trapped charge after one-week's annealing at the temperature of 100°C, with a negligible effect on the interface traps. Consequently, another one-week annealing at 150°C should lead to the complete recovery of all the radiation-induced oxide-trapped charge and most of the interface traps. The primary examined parameters were the voltage regulator's maximum output current, the serial transis- 183 V. Dj. Vukic; Informacije Midem, Vol. 48, No. 3(2018), 181 - 193 tor's minimum dropout voltage and the total circuit's quiescent current. Measurement of the quiescent current enabled the calculation of the serial transistor's base current and, consequently, the serial transistor's forward emitter current gain [18, 20, 21]. Voltage and current vaweforms were recorded using the oscilloscope Fluke' 196C. Several days after completion of the room-temperature annealing experiment, the circuits were annealed in the thermal chamber, at a temperature of 100°C, uninterruptedly for 168 hours. After the seven-day annealing, a new round of experiments was performed, with the same electrical parameters recorded. Finally, a day after the completion of the second round of electrical measurements, a final isothermal annealing sequence was performed, for another 168 hours with the same samples in the thermal chamber, yet this time at a temperature of 150°C. After the completion of the last annealing phase, the final data set on annealed voltage regulators was recorded. The presented sequence of isothermal annealing procedures, with the various temperatures and durations, should enable better insight into the influence of interface traps and the oxide-trapped charge on the radiation and post-irradiation response of a complex integrated circuit. Ten years should be a typical exploitation period for the electronic components in aerospace applications [22]. Since the manufacturer of the circuit L4940V5 did not provide the schematic circuit diagram of this voltage regulator, many efforts were made to gather the necessary data on the internal structure of this device. Using the published papers [30, 31] and patents [16, 32], the author created a basic computer simulation model in the program "LTspice IV" [33]. The created model was rigorously examined and improved until it enabled a pretty good recreation of a wide ensemble of experimental results. There was no intention to recreate all the details of the integrated circuit as made by its manufacturer, so it is not a straight replica of the particular circuit design. Yet, the presented simulation model was good enough to describe the circuit's response to the influence of Y-radiation. In order to present the circuit's response for various bias and load conditions, previously published results were unified with the data from new experiments. The data on the mean values of the maximum output current [17, 18], minimum dropout voltage [20, 21] and on-line parameters [19, 34], procured immediately after the exposure of the L4940V5 devices, were extensively presented in previous years. However, new experiments on the isothermal annealing of the voltage regulator were done on the same samples, yet this time ten years later. So, in order to avoid the unnecessary repetition of the old data, mostly results normalised to the data on virgin devices are now presented. Yet, the creation of the computer simulation model, as well as in-depth analysis of the perceived radiation effects, was not possible without unification of all the experimental data obtained. Descriptions of the experiments performed, the radiation sources, and the procedures implemented for procurement of the circuit's electrical parameters are in the detail provided in the references [17-21, 34, 35]. 4 Results Table 1 summarises the results on maximum output current and minimum dropout voltage (for load currents of 100 mA and 400 mA), obtained in the Y-radiation field with various biases and loads during irradiation. From the data on the quiescent current in the examined circuits, as well as from data on unloaded voltage regulators, the values of the serial transistor's base current and the internal control circuit's consumption were calculated (in a positive voltage regulator with the PNP pass transistor, total quiescent current represents the sum of these two currents [18, 21]). Consolidated results were presented, showing, firstly, data on unexposed circuits, then the data procured after absorption of total doses from 50 Gy up to 500 Gy, and, finally, the data procured during the isothermal annealing (long-term room-temperature, followed by short-term 100°C and 150°C annealing). Only the most important data necessary for the circuit response analysis are presented in the table, and all data were normalised to the values of virgin devices. Therefore, since the data on unloaded voltage regulators had basically the same trends in all three cases, only data obtained during the examination of the maximum output current are presented. As previously reported on its radiation response [1721], and being valid also following the implemented annealing of the tested circuits, the voltage regulator kept stable output voltage in all the examined operating points, regardless of the bias conditions during previous irradiation. The voltage reference circuit suffered negligible degradation, since the variations of the output voltage in unloaded devices could be measured in millivolts [21, 34]. The waveforms of the input voltage, output voltage and quiescent current, recorded on the laboratory setup, were presented in Fig. 1. Despite the high alternate current components, measured values of direct current enabled successful evaluation of the voltage regulator's radiation response. 184 V. Dj. Vukic; Informacije Midem, Vol. 48, No. 3(2018), 181 - 193 Table 1: Relative values of serial transistor's dropout voltage (VEC12; for tests with load current of 100 mA and 400 mA), maximum output current (Imax) and no-load quiescent current (IQ0), as well as the accompanying data on the absolute values of the serial transistor's excess base current (AIBJ2) in voltage regulator STMicroelectronics' L4940V5. Values were based on data recorded on virgin devices, during the exposure, and after irradiation, for the specified periods and types of isothermal annealing. Experimental results were extended with parameters of the serial transistor (maximum forward emitter current gain (PFmax) and knee current (IkF)), defined in the SPICE simulation models. Simulation models with serial PNP power transistors, having the parameters specified in the last two columns, were ones that reached high agreement with the data procured through all three types of experiment. Successive periods of isothermal annealing were marked as follows: annealing 1 (Qa = 20°C, t = 85,000 hours); annealing 2 (Qa = 100°C, t = 168 hours); annealing 3 (Qa = 150°C, t = 168 hours). Basic values of serial transistor's dropout voltage, base current and no-load quiescent current, experimentally procured on unexposed (D = 0 Gy) L4940V5 voltage regulators, for various bias and load conditions: a) 0 V, 0 A: VEa2 (100 mA) = 0.355 V [20], IB12 (100 mA) = 0.545 mA [20], VEa2 (400 mA) = 1.766 V [21], IB12 (400 mA) = 4.627 mA [21], lmax = 835.9 mA [18], IQ0 = 3.753 mA [18], IB12 (max) = 20.397 mA [18]; b) 8V, 1 mA: VEa2 (100 mA) = 0.394 V [20], IB12 (100"mA) = 0.703 mA [20], VECU (400 mA) = 1.736 V [21], IB12 (400 mA) = 3.824 mA [21], Im(a = 855.1 mA [18], IQ0 = 3.772 mA [18], IB12 (max) = 19.028 mA [18]; c) 8 V, 100 mA: VfC2 (100 mA) = 0.392 V [20], IB2 (100 mA) 0.734 mA [20], VEC.2 (400 mA) = 1.763 V [21], IB.2 (400 mA) = 4.417 mA [21], Imax = 852.5 mA [18], IQ0 = 3.806 mA [18], EC.2 IB12 (max) = 25.304 mA [18]; d) 8 V, 500 mA: VEC12 (100 mA) = 0.378 V [20], IB12 (100 mA) : 1.793 V [21], IB12 (400 mA) = 5.638 mA [21], Inua = 820.5 mA [18], IQ0 = 3.806 m A [18], I. -- 0.731 mA [20], VEC12 (400 mA) : (max) = 25.304 mA[18]. STMicroelectronics® L4940V5 Type of experiment Simulation Operation during irradiation and annealing Vec12 (100 mA) Vec12 (400 mA) Imax Parameters of serial PNP power transistor, Q12 Bias and load during irradi- Dose, Vec12 Ib12 AIb12 Vec12 IB12 AIB12 Imax Iq0 Ib12 AIB12 ßFmax IkF D [Gy] [p.u.] [p.u.] [mA] [p.u.] [p.u.] [mA] [p.u.] [p.u.] [p.u.] [mA] [A] ation 0 1 1 0 1 1 0 1 1 1 0 270 0.225 50 1.161 2.422 0.78 1.153 1.813 3.76 0.995 0.981 1.44 8.98 115 0.375 0 V 0 A 100 1.144 4.128 1.71 1.208 3.395 11.08 0.956 0.959 1.760 15.49 500 1.631 75.43 40.57 1.298 7.478 29.98 0.966 0.874 1.997 20.34 Annealing 1 1.27 3.996 1.63 1.265 3.127 9.84 0.862 0.933 2.118 22.8 Annealing 2 1.087 3.486 1.36 1.067 2.669 7.72 0.916 0.965 1.567 11.56 67 0.49 Annealing 3 1.234 2.312 0.64 1.08 1.659 1.82 0.898 0.967 1.28 5.71 125 0.38 0 1 1 0 1 1 0 1 1 1 0 340 0.225 50 1.023 1.55 0.39 1.11 1.349 1.34 0.999 0.986 1.089 1.7 180 0.375 100 0.990 2.119 0.79 1.139 1.938 3.59 0.993 0.976 1.435 8.27 115 0.425 8 V, 1 mA 200 1.000 3.599 1.83 1.127 3.894 11.07 0.980 0.954 1.785 14.94 45 1.1 300 1.003 5.747 3.34 1.242 6.859 22.41 0.974 0.938 1.870 16.55 500 1.251 27.89 18.91 1.347 8.567 28.94 0.958 0.917 1.904 17.2 Annealing 1 1.071 5.334 3.05 1.395 7.377 24.39 0.894 0.936 2.27 17.2 Annealing 2 1.071 3.115 1.49 1.187 2.712 6.55 0.937 0.962 1.904 11.71 60 0.7 Annealing 3 1.198 1.508 0.36 1.181 1.42 1.61 0.946 0.973 1.616 2.57 150 0.39 0 1 1 0 1 1 0 1 1 1 0 340 0.225 50 1.028 1.88 0.65 1.132 1.607 2.68 0.992 0.983 1.377 6.82 127 0.375 8 V, 100 mA 100 0.987 3.011 1.48 1.161 2.719 7.59 0.968 0.967 1.723 13.08 55 0.75 200 1.031 6.131 3.77 1.243 7.19 27.34 0.961 0.941 2.027 18.57 500 1.372 57.96 41.81 1.284 8.021 31.01 0.954 0.899 2.202 21.73 Annealing 1 1.372 11.38 7.62 1.336 7.63 29.28 0.891 0.922 2.065 19.26 Annealing 2 1.092 3.856 2.1 1.221 3.337 10.32 0.967 0.951 1.829 14.99 45 1 Annealing 3 1.115 1.703 0.52 1.188 1.535 2.36 0.934 0.967 1.326 5.9 120 0.4 0 1 1 0 1 1 0 1 1 1 0 240 0.2 50 0.971 1.929 0.68 1.085 1.591 3.33 1.007 0.98 1.164 4.15 100 0.375 8 V, 500 mA 100 1.011 3.010 1.47 1.153 2.914 10.79 0.999 0.962 1.289 7.32 500 1.704 54.56 39.15 1.267 6.297 29.86 1.01 0.909 1.427 10.8 Annealing 1 1.235 13.42 9.08 1.35 5.692 26.45 0.932 0.943 1.432 10.42 Annealing 2 1.103 3.844 2.08 1.25 3.663 15.01 0.969 0.956 1.368 9.32 Annealing 3 0.997 1.696 0.51 1.161 1.453 2.55 0.942 0.967 1.148 3.76 105 0.375 185 V. Dj. Vukic; Informacije Midem, Vol. 48, No. 3(2018), 181 - 193 Basic data on the vertical serial PNP power transistor, obtained using the SPICE simulations, are also included in Table 1. Since the previous research concluded that the control circuit did not have a significant influence on the voltage regulator's radiation response [20, 21], the focus of the computer simulation analysis was on the serial power transistor. The primary influence on the L4940V5 voltage regulator's radiation hardness was the interdigitated structure of its serial PNP transistor [17, 19]. Therefore, the serial power transistor's excess base current was the best measure of the circuit's radiation response. After careful examination, the results from Table 1 may provide much information about the L4940V5 circuit's radiation and post-irradiation response. All the irradiated circuits expressed lower recovery (from deposition of the total dose of 500 Gy) during the ten-year room-temperature annealing than during the two seven-day high-temperature annealing sequences. Recovery of the circuits after two-week isothermal annealing was not complete, yet the main parameters pointed to circuit damage comparable to the state recorded after the absorption of the total ionising dose of 50 Gy. Variations of the serial power transistor base current, presented in Table 1, may lead to the identification of two different circuit responses, for the irradiation and post-irradiation periods. The first category of results comprises the initial period of irradiation (up to 50 or 200 Gy, depending on the bias and load conditions), as well as the final periods of high-temperature isothermal annealing. The second category of results comprises the data procured after absorption of higher total doses, as well as the initial annealing periods (particularly the long-term, room-temperature annealing). The main means of identification of these categories is the saturation of the serial transistor's base current, in either of the three data ensembles. The threshold value of the base current, when overcurrent protection is activated, is approximately 35 mA. This value corresponds to the total voltage regulator's quiescent current of nearly 40 mA. When the serial transistor base current is always less than 35 mA, the radiation response of the PNP bipolar power transistor can be modelled with the standard Gummel-Poon model, with variations of only the maximum forward emitter current gain and the knee current. On the other hand, whenever the base current exceeded this threshold voltage, the SPICE model, successfully describing the circuit response for all three types of experiment, could not be made. In some cases, the power transistor base current was higher in control points with the collector current being 100 mA, than in the case when the collector current was 400 mA! Figure 1: Waveforms of input and output voltage (left) and quiescent current (right), recorded on the unexposed L4940V5 voltage regulator during the examination of the maximum output current The bias conditions had a great influence on the radiation response of the irradiated circuits. Data from Table 1 show opposite trends of the radiation response of the power transistor, on the one hand, and the rest of the circuit, on the other. While the serial transistor's base current increased, increasing also the voltage regulator's quiescent current, the quiescent current of the control circuit (IQ0) declined [21]. Yet, the primary focus was on the examination of the characteristics of the vertical power transistor, since it had the most obvious effect on the voltage regulator radiation response. So, analysing the variations of the excess base current, shown in Table 1, the clear scale of the radiation sensitivity of exposed circuits may be defined. Gamma-radiation inflicted the greatest damage on biased and heavily loaded voltage regulators (Vn = 8 V, I = 500 mA). Lower degradation was seen in unbiased devices, followed by even lower degradation in biased and moderately loaded voltage regulators (V ,n = 8 V, I = 100 mA). The least damage was expressed by biased and negligibly loaded devices (Vn = 8 V, I = 1 mA). The waveforms of the quiescent current and output current recorded on the laboratory setup are presented in Fig. 1. 5 Discussion 5.1 Computer simulation Fig. 2 presents a simplified computer simulation model of the L4940V5 voltage regulator, created in the program tool "LTspice IV" [33]. As can be seen from Fig. 2, the voltage reference and the error amplifier were represented only by general models. On the other hand, 186 V. Dj. Vukic; Informacije Midem, Vol. 48, No. 3(2018), 181 - 193 the simulation model of the serial PNP power transistor, Q12, was very complex. The main reason is the negligible radiation degradation of the control circuit elements, in opposition to the serious degradation of the serial power transistor. Due to its strong influence on the results obtained, the model included many details on the power supply circuit and the accompanying cables. Due to the low value of the main filter capacitor (nominally 330 ^F), the examined voltage regulators operated in two periods: with the constant output voltage and with its decreased value, falling below the nominal value of 5 V (see Fig. 1). Therefore, the integrated circuit's quiescent current had very rapid variations in these two operation sequences. Also, since the local ground of the examined voltage regulator was separated from the power supply ground by a cable, 10 m long, it also increased the alternating current component of the voltage regulator's quiescent current. In the period of 10 ms, matching the inherent frequency of the single-phase diode bridge, there was, de facto, operation of the voltage regulator with the dominant alternating current superimposed on its direct current component. Relatively low values of the maximum output current (being 720- 850 mA), as well as high values of the minimum dropout voltage, are a direct consequence of the low capacity of the main filter capacitor. Nevertheless, the experimental configuration was not changed, in order to enable mutual comparison of all the obtained and presented data, dating back to 2006 [17]. Yet, even in these circumstances, measurement of the mean values of quiescent currents led to the correct calculation of the serial power transistor's base current and its forward emitter current gain. Despite the high alternate current components, the computer simulation proved that the measured values of direct current, presented in tables 1 and 2, enabled successful evaluation of the voltage regulator's radiation response. The reaction of the anti-saturation circuit was also important, since it had a substantial influence on the quiescent current response. Whenever the dropout voltage on the pass PNP transistor fell below the threshold level, the anti-saturation circuit reacted in order to prevent the flow of excessive current from the serial transistor to the substrate and, consequently, to the ground contact. Therefore, the anti-saturation circuit was modelled in great detail. Another important element was the overcurrent protection of the driver NPN transistor, Q13. In order to prevent the voltage regulator's quiescent current rising above its upper limit of 50 mA [15], the transistor Q15 activates and takes the excessive collector current of the driver transistor, indirectly limiting the base current of the serial transistor. The consequence of this protection is the reduction of the voltage regulator's maximum output current. This was exactly the circuit response that was recorded in numerous experiments, particularly after the absorption of the higher total doses of Y-radiation. As the basic element for modelling the serial vertical PNP power transistor, the SPICE model of discrete transistor BC808-25 was used [36]. This is a discrete PNP transistor with the following nominal parameters: collector-emitter breakdown voltage BVCE0 = 25 V, nominal collector current IC = 500 mA, cut-off frequency fT = 100 MHz, with the maximum value of the forward emit- Figure 2: Schematic circuit diagram of L4940V5 voltage regulator 187 V. Dj. Vukic; Informacije Midem, Vol. 48, No. 3(2018), 181 - 193 ter current gain being in the range fiF = 160-400 [37]. These data are close to the specified characteristics of the vertical PNP power transistor in device L4940V5 (fT = 80 MHz, PF = 50 for the load of 1 A, BVao = 20 V) [15, 30]. Table 2 enables mutual comparison of simulation and experimental data on the serial transistor's base current. Simulation data on parameters variations of the vertical serial PNP power transistor are also included in Table 1. Transistor parameters were selected in order to enable the highest possible agreement with the results for all three types of experiments. In the initial period of irradiation, for total ionising doses from 0 Gy up to 200 Gy, the simulation model reproduced the experimental results very well. In the initial phase, a sharp decline of the forward emitter current gain was seen for all the tested operation conditions [17-21]. This decline was successfully modelled in the computer simulation using just the variations of the maximum forward emitter current gain (PFmax) and the forward knee current (IkF). Variations of the current gain and the excess base current were most successfully modelled for the biased and negligibly loaded voltage regulators. For other devices, both unbiased or biased and loaded with higher currents, procuring a faithful simulation model was much more difficult. Without exception, when the devices reached saturation of the excess base current, precise modelling was impossible. Unbiased and heavily loaded circuits L4940V5 entered this phase after the absorption of low total doses (50 Gy), while the biased and negligibly loaded devices experienced saturation after longer exposure (200 Gy). Table 2: Mutual comparison of absolute values of serial transistor's base current (IB12) in voltage regulator STMicro-electronics' L4940V5, obtained both with SPICE simulation and experiment. Experiments were executed on variations of dropout voltage (VEC12; for tests with load current of 100 mA and 400 mA) and maximum output current (Imax), for absorption of total ionising doses up to 500 Gy(SiO2). The results were extended with parameters of the serial transistor (maximum forward emitter current gain (PFmax) and knee current (IkF)), defined in the SPICE simulation models. Only experimental results that reached high agreement with simulation models were presented. Successive periods of isothermal annealing were marked as follows: annealing 2 (Qa = 100°C, t = 168 hours); annealing 3 (Qa = 150°C, t = 168 hours). STMicroelectronics® L4940V5 Simulation and experiment Simulation Operation during irradiation and annealing Vcei2 (100 mA) Vce12 ( 400 mA) Imax Parameters of serial PNP power transistor, Q12 Bias and load during Dose, Simulation Experiment [20] Simulation Experiment [21] Simulation Experiment [18] ßFmax IkF irradiation D [Gy] Ib12 [mA] Ib12 [mA] Ib12 [mA] Ib12 [mA] Ib12 [mA] Ib12 [mA] [A] 0 V 0 A 0 0.72 0.55 4.67 4.63 20.77 20.4 270 0.225 50 1.18 1.32 7.72 8.39 27.77 29.38 115 0.375 Annealing 2 1.88 1.9 11.39 12.35 32.44 31.96 67 0.49 Annealing 3 1.1 1.18 7.06 6.45 21.57 26.1 125 0.38 8 V, 1 mA 0 0.89 0.7 4.03 3.82 19.06 19.03 340 0.225 50 1.08 1.09 5.17 5.16 21.53 20.73 180 0.375 100 1.36 1.49 7.33 7.41 27.73 27.3 115 0.425 200 2.5 2.53 12.39 14.89 34.39 33.97 45 1.1 Annealing 2 1.98 2.19 10.85 10.37 31.11 30.74 60 0.7 Annealing 3 0.94 1.06 5.8 5.43 20.67 21.6 150 0.39 8 V, 100 mA 0 0.89 0.73 4.03 4.42 19.06 18.07 340 0.225 50 1.09 1.38 7 7.1 26.32 24.89 127 0.375 100 2.14 2.21 11.51 12.01 33.87 31.15 55 0.75 Annealing 2 2.52 2.83 12.72 14.74 35.21 33.06 45 1 Annealing 3 1.13 1.25 7.14 6.78 24.22 23.97 120 0.4 8 V, 500 mA 0 0.79 0.73 5.7 5.64 23.23 25.3 240 0.2 50 1.35 1.41 8.86 8.97 30.62 29.45 100 0.375 Annealing 3 1.29 1.24 8.42 8.19 26.31 29.06 105 0.375 188 V. Dj. Vukic; Informacije Midem, Vol. 48, No. 3(2018), 181 - 193 Partially unexpected were data on the long-term room-temperature annealing. Initial checks of several irradiated samples led to the assumption that, in the long-term perspective, irradiated L4940V5 voltage regulators would mostly recover [21]. Nevertheless, data obtained after 85,000 hours of room-temperature annealing did not support this hypothesis [34]. Despite the recovery of the serial transistor current gain and reduction of its excess base current, the maximum output current in most cases significantly declined. Yet, two successive one-week, high-temperature annealing sequences (100°C, followed by the 150°C exposure) led to the expressed circuit recovery. In all the examined cases, high-temperature annealing of devices irradiated until absorption of the total dose of 500 Gy led to nearly the same parameters as those recorded after absorption of 50-200 Gy. More important, these conditions could be again successfully modelled only with variations of the current gain and knee current of the serial transistor, just as in the initial period of irradiation. 5.2 Radiation effects As can be expected from the theory [38], unbiased devices suffer the most obvious damage, while bipolar intergated circuits with a high positive bias voltage during irradiation show much less degradation from the influence of radiation. On the one hand, this could be expected, since the high positive bias voltage injects the electrons in oxide, causing the trapped holes to recombine and consequently reducing the total oxide-trapped charge concentration. Yet, unbiased irradiation cannot enhance the hydrogen ions transport and, therefore, will have less influence on the build-up of interface traps. A sharp initial decline of the forward emitter current gain, presented in Table 1, points to the dominant influence of the oxide-trapped charge. The current gain declined rapidly, as presented in Table 1 and the maximum value of the forward emitter current gain decreased from 340 down to 55 (for biased and moderately loaded devices), following exposure to only 100 Gy. Also, at the same time the serial PNP power transistor's knee current significantly increased, rising from 0.225 A to 0.75 A. The emitter-base leakage emission coefficient, used in the simulation model of the transistor BC808-25 and, therefore, of the power vertical PNP transistor used in the present simulation, was a constant with a value ne = 1.568 [36]. Other voltage regulator elementary circuits were not seriously affected by ionising radiation, so the remaining elements of the simulation model were not changed. This initial rapid degradation of the serial transistor current gain clearly points to the main negative influence of the oxide-trapped charge. Yet, in the previous research it was calculated that the emitter area has a surface doping concentration equal to 3.3-1017 cm-3 [21]. This is a relatively high value for a PNP power transistor, and it was therefore assumed that the emitter should not be so much affected by the influence of the oxide-trapped charge, particularly since the emitter crowding was not perceived [21]. Nevertheless, despite such a high impurities concentration for a power device, this value was not so high, particularly in comparison with a small-signal PNP transistor, having an emitter doping concentration up to 1020 cm-3 [28]. Also, the interdigi-tated structure of the pass element, with 40 elementary PNP power transistors [30], was another reason for its lower radiation tolerance. Therefore, the main reason for such an obvious rise in the excess base current was certainly primarily related with the emitter, rather than the base area. After the initial phase of radiation exposure, the next phase showed saturation in the serial PNP transistor's excess base current, particularly after exposure of the samples to 500 Gy [18, 20, 21]. These results point to the reaction of the overcurrent protection of the NPN driver transistor Q13 (Fig. 2), preventing the rise of the voltage regulator's quiescent current above the foreseen maximum of 50 mA [15]. Saturation in the oxide-trapped charge build-up was always perceived for high total doses, being 500 Gy (with the exception of the biased and negligibly loaded samples). Yet, the problem is that it was not possible to create an adequate computer simulation model of the PNP power transistor for higher total doses! Whatever was implemented in the SPICE model of the serial transistor, it was not possible to get mutually faithful results for either the maximum output current (Iout = 720 - 850 mA) or the minimum dropout voltages (recorded for 100 mA and 400 mA) using the basic Gummel-Poon models. There were earlier attempts to simulate the increased recombination current in the base area, with the ideality factor of 2 [8]. Other tools, such as additional resistors, current sources, variations of the surface recombination currents or the other power transistor parameters did not help much. The most successful attempt was made with the implementation of a significantly increased base-emitter saturation leakage current (IJ. Yet, even in these cases, it was not possible to alter one simple fact: regardless of the output current (100 mA, 400 mA or 800 mA), for a dose of 500 Gy, the base currents were, in most cases, nearly the same, being 35-40 mA. Nevertheless, even with this saturation of the base current, the experiment indicated that the voltage regulator operated correctly, without significant degradation of its output voltage and with only a moderate decline of the maximum output current at some control points. The exponential dependence of the base current on 189 V. Dj. Vukic; Informacije Midem, Vol. 48, No. 3(2018), 181 - 193 the emitter-base voltage, accompanied by the successful simulation of the voltage regulator response with high output currents, could not be realised. So, despite the variations of either the emitter-base leakage current (Ise) or the emitter-base leakage emission coefficient (ne), a satisfactory simulation model suitable for the description of the high total-dose response could not be created. 5.3 Post-irradiation effects Data on the ten-year room-temperature annealing, presented in Table 1, point to a significant recovery of the serial transistor's excess base current, hand in hand with further degradation of the maximum output current and, in some cases, minimum dropout voltage. More important, saturation of the excess base current remained present during the examination with higher currents, making it impossible to create faithful SPICE models of the first phase of annealing. Tremendous recovery of the excess base current may be observed particularly in unbiased devices, reducing the serial transistor's base current nearly twentyfold! Also, in this, the most obvious case, the maximum output current, i.e. the serial transistor collector current, significantly declined. Various previous studies emphasize that, at room temperature, oxide-trapped charge anneals with time, contributing to the recovery of current gain [25], while interface traps in the field oxide often do not anneal [39]. Thus, it may be assumed that, following the ten-year room temperature annealing of the L4940V5 voltage regulators, the oxide-trapped charge partially recovered, while the interface-trapped charge continued to build up. Therefore, the power transistor's current gain recovery was primarily affected by the positive influence of the recovery of the oxide-trapped Fig. 3. Variations of the power PNP transistor current gain as a function of the collector current in: a) unbiased circuits (Vn = 0 V, V0ut = 0 A); b) biased and negligibly loaded (Vln = 8 V, Vout = 1 mA); c) biased and moderately loaded (V ln = 8 V, Vout = 100 mA); d) biased and heavily loaded circuits during irradiation (V|n = 8 V, Vout = 500 mA). Diagrams were created for constant collector-emitter voltage, being VCE = 3.3 V. Data were obtained from computer simulation models of the irradiated and annealed voltage regulators, which demonstrated high agreement with the experimental results presented in Table 1. 190 V. Dj. Vukic; Informacije Midem, Vol. 48, No. 3(2018), 181 - 193 charge. The negative influence of further interface traps build-up, causing the serial transistor's collector current to decline, had a much less obvious effect on its forward emitter current gain. The first high-temperature annealing sequence, including one-week at 100°C exposure, reduced the radiation damage to a level slightly above the one observed following the 100-Gy irradiation. The second sequence, involving 168-hour annealing at 150°C, further reduced the radiation damage down to the degradation caused by the total ionising dose of 50 Gy. With the exception of the samples that were heavily loaded during the irradiation, the voltage regulators' characteristics, following the high-temperature annealing sequences, could be successfully modelled, in the same way it was done in the initial phase of irradiation, using the variations of only the current gain and knee current. No sign of heavy saturation was observed in the forward emitter current gain after exposure to higher total doses of Y-radiation. Data on the short-term, high-temperature annealing pointed to a substantial recovery of the irradiated circuits, bringing them close to their pre-irradiation characteristics. Nevertheless, the data in Table 1 show that PFmaxrecovered only to 40-50 % of their pre-irradiation values. Yet, even this was enough for a nearly complete recovery of the voltage regulator's output parameters. Fig. 3 presents diagrams of the serial transistor's forward emitter current gain variation as a function of its collector current, in the range from 1 mA to 800 mA. For the specified collector currents, values of the serial transistor base-emitter voltage were in the range from 620 mV to 830 mV. Diagrams were produced from computer simulation models for all four types of bias and load conditions, briefly described in Table 1. The vertical PNP power transistor operates with output current being at least 1 mA, since this current flows through the voltage divider resistors when the voltage regulator operates without load. All data were obtained with a constant collector- emitter voltage of VCE = 3.3 V. Opposite to the results presented in Table 1, based on the measured mean values, the data presented in Fig. 3 were obtained using the instantaneous values of voltages and currents, at the operation point with constant output voltage (Vout = 5 V) and an appropriate input voltage of Vn = 8.3 V. As can be seen from Table 1 and Fig. 3, the three isothermal annealing sequences led to similar characteristics of marginally irradiated and mostly recovered L4940V5 voltage regulators. The computer simulation models for these, principally different, periods, were basically the same. Yet, this could not be used as evidence that the distribution of the trapped charge was the same at the beginning and at the end of this decade-long experiment. Using only SPICE models, the influence of the interface traps and the oxide-trapped charge could not be separated. As already stated, the initial assumption of this research was that, as in the case of MOSFET-based logical circuits [29], most of the oxide-trapped charge would recover after 100°C annealing, while at the end of the 150°C annealing only the interface traps would remain. In discrete bipolar transistors, the interface states would recover first, after the annealing at 100°C-200°C, while the oxide-trapped charge would start to recover at higher temperatures, following the isothermal annealing at 150°C-300°C [14]. Taking into account the arguments presented in the previous chapters and paragraphs of this research, it seems that, indeed, the oxide-trapped charge in the tested circuits, at most, recovered after long-term room-temperature and short-term 100°C annealing. Nevertheless, there were no principal differences in the results obtained at the beginning of irradiation and at the end of the three annealing sequences, either in the model of the serial PNP power transistor or in the response of the entire L4940V5 voltage regulator. So, the results obtained may be used only for characterization of the total power transistor's and voltage regulator's radiation and post-irradiation response, rather than making it possible to qualitatively separate the effects of the interface traps and the oxide-trapped charge. 6 Conclusion Data on the more than decade long examinations of the radiation tolerance of L4940V5 voltage regulators were unified and extended with the newly procured isothermal annealing results. These COTS, automotive circuits, demonstrated unexpectedly high radiation hardness during the previous experiments, potentially qualifying them as a cheap replacement for specially designed rad-hard power integrated circuits. The same samples, exposed to the Y-radiation more than ten years ago, were further analysed after long-term, room-temperature annealing, followed by two sequences of short-term, high-temperature annealing. The circuit response gave a unique opportunity to analyse exclusively the radiation hardness of the vertical serial PNP power transistor, since the small-signal, control circuit was marginally affected by ionising radiation. A broad ensemble of the experimental data enabled the creation of a credible SPICE model, successfully describing the circuit response in the Y-radiation field. The initial phase of irradiation, up to 200 Gy, was efficiently recreated using the variations of the maximum forward emitter current gain and the knee current of the serial PNP power transistor. The data and computer simulation showed significant agreement for load cur- 191 V. Dj. Vukic; Informacije Midem, Vol. 48, No. 3(2018), 181 - 193 rents of 100 mA, 400 mA and nearly 800 mA, for various 2. input voltages. The subsequent exposure to Y-radiation could not be successfully modelled, due to the expressed saturation of the serial transistor's excess base 3. current. The current limit protection of the driver NPN transistor further affected the circuit response. 4. Ten-year room-temperature annealing of integrated circuits, irradiated up to 500 Gy, caused the great recovery of the voltage regulator's quiescent current, yet followed by the further degradation of the maximum output current. The primary reason for the described response was the mutual recovery of the oxide-trapped 5. charge and the build-up of interface traps above the emitter area of the serial PNP power transistor. On the other hand, two successive, one-week, high-temperature annealing periods caused the tremendous recov- 6. ery of all the irradiated voltage regulators, reducing the circuit degradation down to the level specified after absorption of the total dose of 50 Gy. The initial phase of irradiation caused the voltage regu- 7. lator to degrade primarily through the influence of the oxide-trapped charge. The second phase of irradiation is a consequence of the activation of the overcurrent protection of the NPN driver transistor, followed by the saturation of the trapped charge density. Despite 8. the relatively high doping concentration of the P-type emitter area in the vertical PNP power transistor, increased surface recombination in the area of the inter- 9. digitated emitter was the primary cause of the sharp increase in the serial transistor's excess base current. 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Arrived: 14. 04. 2018 Accepted: 30. 07. 2018 193 Boards of MIDEM Society | Organi društva MIDEM MIDEM Executive Board | Izvršilni odbor MIDEM President of the MIDEM Society | Predsednik društva MIDEM Prof. Dr. Marko Topič, University of Ljubljana, Faculty of Electrical Engineering, Slovenia Vice-presidents | Podpredsednika Prof. Dr. Barbara Malič, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Iztok Šorli, MIKROIKS, d. o. o., Ljubljana, Slovenija Secretary | Tajnik Olga Zakrajšek, UL, Faculty of Electrical Engineering, Ljubljana, Slovenija MIDEM Executive Board Members | Člani izvršilnega odbora MIDEM Darko Belavič, HIPOT-RR d.o.o., Otočec, Slovenia Dr. Slavko Bernik, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Miha Čekada, Jožef Stefan Institute, Ljubljana, Slovenia Prof. DDr. Denis Donlagič, UM, Faculty of Electrical Engineering and Computer Science, Maribor, Slovenia Prof. Dr. Leszek J. Golonka, Technical University Wroclaw, Poland Dr. Vera Gradišnik, Tehnički fakultet Sveučilišta u Rijeci, Rijeka, Croatia Leopold Knez, Iskra TELA d.d., Ljubljana, Slovenia mag. Mitja Koprivšek, ETI Elektroelementi, Izlake, Slovenia Prof. Dr. Miran Mozetič, Jožef Stefan Institute, Ljubljana, Slovenia Prof. Dr. Janez Trontelj, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Dr. Danilo Vrtačnik, UL, Faculty of Electrical Engineering, Slovenia Supervisory Board | Nadzorni odbor Prof. Dr. Franc Smole, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia prof. dr. Drago Strle, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Igor Pompe, Ljubljana, Slovenia Court of honour | Častno razsodišče Emer. Prof. Dr. Jože Furlan, Slovenia Dr. Marko Hrovat, Slovenia Dr. Miloš Komac, Slovenia Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials ISSN 0352-9045 Publisher / Založnik: MIDEM Society / Društvo MIDEM Society for Microelectronics, Electronic Components and Materials, Ljubljana, Slovenia Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale, Ljubljana, Slovenija www.midem-drustvo.si