Original scientific paper 69 70 71 72 73 ISSN 0352-9045 Journal of Microelectronics, Electronic Components and Materials Vol. 50, No. 2(2020), June 2020 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 50, številka 2(2020), Junij 2020 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 2-2020 Journal of Microelectronics, Electronic Components and Materials VOLUME 50, NO. 2(174), LJUBLJANA, JUNE 2020 | LETNIK 50, NO. 2(174), LJUBLJANA, JUNIJ 2020 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2020. All rights reserved. | Revija izhaja trimesečno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale – Društvo MIDEM. Copyright © 2020. Vse pravice pridržane. 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Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madić Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana Journal of Microelectronics, Electronic Components and Materials vol. 50, No. 2(2020) Content | Vsebina 71 87 105 115 125 137 147 Izvirni znanstveni članki E. Sekar, S. Palaniswami: Strojna implementacija množilnikov ostankov na osnovi predznačenega RNS procesorja za sisteme kriptiranja A. Abolhasani, M. Mousazadeh, A. Khoei: Neinvazivno merjenje krvnega tlaka v realnem času brez uporabe manšete M. A. S. Bhuiyan, Z. Fan, Y. J. Leem, L. Y. Lee, M. B. I. Reaz, T. I. Badal, K. N. B. Minhad: Enopolno menjalno oddajno/sprejemno CMOS uporovno stikalo in nizkošumen ojačevalnik za internet stvari identifikacijske elemente na radijski frekvenci A. Rahnamaei: Visoko učinkovit CMOS 5-2 in 6-2 kodirnik za vzporedne množilnike velikih hitrosti W. Tangsrirat, T. Pukkalanun, O. Channumsin: Enojen multifunkcijski bi-kvadratičen filter na osnovi VDGA in sinusni kvadrantni oscilator M. E. Başak, E. Özer, F. Kaçar, D. Özenli: Štiri-kvadranten širokopasovni množilnik na osnovi DTMOS In memoriam Zaslužnemu profesorju dr. Jožetu Furlanu Naslovnica: Magnetni slikovni sensor ASIC (RLS d.o.o.) Original scientific papers E. Sekar, S. Palaniswami: Hardware Implementation of Residue Multipliers based Signed RNS Processor for Cryptosystems A. Abolhasani, M. Mousazadeh, A. Khoei: Real-time, Cuff-less and Non-invasive Blood Pressure Monitoring M. A. S. Bhuiyan, Z. Fan, Y. J. Leem, L. Y. Lee, M. B. I. Reaz, T. I. Badal, K. N. B. Minhad: CMOS series-shunt single-pole double-throw transmit/receive switch and low noise amplifier design for internet of things based radio frequency identification devices A. Rahnamaei: CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers W. Tangsrirat, T. Pukkalanun, O. Channumsin: Single VDGA-Based Dual-Mode Multifunction Biquadratic Filter and Quadrature Sinusoidal Oscillator M. E. Başak, E. Özer, F. Kaçar, D. Özenli: DTMOS Based High Bandwidth Four-Quadrant Analog Multiplier In memoriam Emeritus Prof. Dr. Jože Furlan Front page: Magnetic image sensor ASIC (RLS d.o.o.) Journal of Microelectronics, Electronic Components and Materials Vol. 50, No. 2(2020), 71 – 86 https://doi.org/10.33180/InfMIDEM2020.201 Hardware Implementation of Residue Multipliers based Signed RNS Processor for Cryptosystems Elango Sekar, Sampath Palaniswami Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Erode, Tamil Nadu, India Abstract: The Residue Number System (RNS) characterize large integer numbers into smaller residues using moduli sets to enhance the performance of digital cryptosystems. A parallel Signed Residue Multiplication (SRM) algorithm, VLSI parallel array architecture for balanced (2n-1, 2n, 2n+1) and unbalanced (2k-1, 2k, 2k+1) word-length moduli are proposed which in turn are capable of handling signed input numbers. Balanced 2n-1 SRM is used as a reference to design an unbalanced 2k-1 and 2k+1. The synthesized results show that the proposed 2n-1 SRM architecture achieves 17% of the area, 26% of speed, and 24% of Power Delay Product (PDP) improvement compared to the Modified Booth Encoded (MBE) architectures discussed in the review of the literature. The proposed 2n+1 SRM architecture achieves 23% of the area, 20% of speed, and 22% of PDP improvement compared to recent counterparts. There is a significant improvement in the results due to the fully parallel coarsely grained approach adopted for the design, which is hardly attempted for signed numbers using array architectures. Finally, the proposed SRM modules are used to design {2n-1, 2n, 2n+1} special moduli set based RNS processor, and the real-time verification is performed on Zynq (XC7Z020CLG484-1) Field Programmable Gate Array (FPGA). Keywords: signed modulo multiplication; Very Large Scale Integration (VLSI); FPGA; computer arithmetic; RNS Strojna implementacija množilnikov ostankov na osnovi predznačenega RNS procesorja za sisteme kriptiranja Izvleček: Številski sistem ostankov velike celoštevilske cifre v manjše ostanke na osnovi setov modulov za povečanje učinkovitosti sistemov kriptiranja. Predlagan je algoritem vzporednega množenja predznačenih ostankov (SRM) v VLSI paralelni arhitekturi za uravnotežen (2n-1, 2n, 2n+1) in neuravnotežen (2k-1, 2k, 2k+1) modul dolžine besede. Uravnotežen SRM je uporabljen kot referenca za načrtovanje neuravnoteženega algoritma. Rezultati kažejo, da predlagana arhitektura zajema 17% prostora, 26% hitrosti in 22% izboljšanost PDP glede na trenutne arhitekture. Izboljšava je dosežena na osnovi paralelnega načrtovanja. Verifikacija v realnem času je izvedena na Zynq FPGA. Ključne besede: predznačeno množenjem odulov; VLSI; FPGA; računalniška arithmetika; RNS * Corresponding Author’s e-mail: elangos@bitsathy.ac.in 1 Introduction In cloud computing and the Internet of Things (IoT), data security is one of the major concerns for service providers. Therefore a dedicated hardware cryptogra­phy support is needed for modern electronic devices [1],[2],[3][4][5]. In recent years, Elliptic Curve Cryptog­raphy (ECC) [6] has received scientific interest as it ensures more security through hard underlying math­ematical problems. It leads to an increase in the length of the key, and as a result, performing faster arithmetic operations on larger integers have become the bottle­neck problem. RNS based arithmetic operation [7,8] is a solution through which residue multiplication has be­come the heart of computation architecture. The natu­ral defense offered by RNS against attacks is another reason for the selection of residue arithmetic as the prime candidate in cryptosystems [9,10]. Similarly to the above operation, modular exponentia­tion [11] is a time-critical operation that is widely used in cryptographic algorithms like RSA. The modular exponentiation operation is performed in the form of residue multiplication. Therefore, the employment of efficient high-speed residue multiplication is vital in public-key encryption and decryption. Typical hardware implementation of the RNS based ap­plication is dependent on the chosen moduli set. The selection of RNS Moduli [12] and the width of the resi­due decide the efficiency and performance of the cryp­tosystems. A {2n-1,2n,2n+1} special moduli set represen­tation is a pairwise relatively co-prime standard RNS. These moduli set has a unique advantage in which two or more numbers do not have the same representation. Special moduli set shows better representational effi­ciency [12] compared to that of other moduli set and also maintains a good balance between the different moduli in a given moduli-set. Based on the number of bits used to represent the input, moduli and residue output are classified into balanced and unbalanced word-length moduli multiplication [13] [14]. Modified Booth Encoded (MBE) modulo multiplica­tion scheme is relatively faster and can handle both signed, and unsigned numbers, the researcher’s atten­tion turned towards it, and many modifications of the same are reported in recent years [15,16,17,18,19,20]. The residue multipliers based on diminished-1 input representation in array and bit pair recoding booth al­gorithm are seen in [16,17,21]. Based on the conducted survey, it is evident that there is no work based on a signed array modulo multiplication scheme reported in the literature. The reasons for the above could be based on the complexity in handling the Partial Product (PP) and poor speed performance. This is one of the reasons that have highly motivated us to attempt a proposal on an array-based high-speed area-efficient parallel SRM module for RNS. In this work, the high-speed perfor­mance is achieved by a new multiplication methodol­ogy incorporating parallelism in PP generation and ad­dition process. Six significant contributions for this work include (i) an SRM algorithm for 2n-1, 2n+1 and 2n balanced word-length moduli (ii) an SRM for 2k-1, 2k+1 and 2k unbalanced word – length moduli (iii) Mathematical modeling of SRM algorithm for each moduli (iv) VLSI characterization of proposed SRM algorithm in terms of high-speed area-efficient Carry Save Adder (CSA) architecture and very high-speed Han Carlson parallel prefix-based SRM array architecture (v) Functional veri­fication of the proposed modules in FPGA and synthe­sis in ASIC (vi) Design of RNS Processor to demonstrate the effectiveness of the proposed algorithm. The paper is structured as follows: In Section 2, the re­lated works connected to residue multipliers with vari­ous moduli sets performance are analyzed. In Section 3, characteristic equation, algorithm, and VLSI archi­tecture are presented for both balanced (2n-1, 2n, 2n+1) and unbalanced (2k-1, 2k, 2k+1) word-length moduli. The design of the RNS processor is given in section 4. In section 5, Synthesis results, performance analysis, and RNS processor implementation are presented. The conclusion for the proposed work is drawn in section 6. 2 Review of Existing Work An MBE based 2n-1 multiplication module to reduce the number of PPs is presented in [22]. The results show a significant improvement in area and delay. However, they fail to address power consumption. A radix-8 booth encoded RNS 2n-1 multiplier [14] using unbalanced word length of moduli supporting size­able dynamic range with adaptable delay to achieve less area and power consumption is presented. The same authors have designed a radix-8 2n-1 & 2n+1 mul­tiplier with a balanced word length of moduli in [18] using various modulo properties. The author claims that less area and power are achieved by using CSA in [14] and parallel prefix adders in [18] for efficient addi­tion operations with a slight increase in delay for lower bit width. Improved booth selector and encoder archi­tecture consist of MUX, and the EXOR gate for the 2n-1 MBE multiplication algorithm is presented in [23]. The architecture improves the speed performance and ef­ficiency, but the introduction of MUX in selector archi­tecture leads to a slight increase in area requirement, and also power consumption is not discussed. A compact ordinary array structure [15] based 2n+1 multiplication scheme by grouping the PPs and modify the correction bit are presented. The PP is reduced by the CSA tree, and the final carry propagation addition is carried out by prefix structure in order to achieve better area and delay performance in which the power consumption is not discussed. By introducing a new PP formation scheme, a binary-weighted representation based modulo 2n+1 multiplier is presented in [19] and is extended to implement a multiply-add unit. The au­thors have achieved less area and power consumption with similar delay performance compared to [15]. A ra­dix-4 MBE architecture with a diminished-1 input rep­resentation and dadda tree reduction scheme, which can handle zero operands with better speed and area, is discussed in [16]. A compressor structure is intro­duced in [24] for PP reduction. This work achieves less power, delay, and consumes less area compared to [15]. A hybrid input representation approach with a radix-4 booth encoding scheme utilizing one binary-weighted operand and diminished-1 input representation for the other operand is explained in [17]. The architec­ture supports both odd and even value of n. The au­thors have achieved a compact area with an enhanced speed compared to the existing multipliers. The radix-8 booth encoded 2n+1 multiplier for balanced word length moduli is designed in [18] using hard multiple generators, bias, and adders. The authors claim that the area and power reduction is accomplished compared to radix-4 and array type multiplier. However, there is an increase in operation time. In [20], the authors have improved the hard multiple generator method with a minimum number of bias terms compared to [18]. Two novel methods to increase the performance and to im­prove the efficiency of the radix-8 modulo 2n+1 multi­plier are explained in [20]. The first method significantly reduces the amount of bias, and the second one is new hard multiple generators based on a parallel-prefix structure computes carry only for odd positions. These schemes result in a lightweight parallel-prefix adder for the computation of triple the number with significant area-saving and improved fan-out. It achieves less area and power compared to the radix-8 booth multiplier [18]. There is an increase in HMG delay compared to [18] and almost maintains the same delay performance for multiplier operation compared to [18]. The problem in MBE based architecture is that it re­quires an efficient booth selector and encoder com­pared to the array-based architectures. The former scheme reduces the number of PPs and improves speed performance. However, it invites additional hard­ware costs during implementation. Our proposed work is an entirely different approach compared to [18], [20] designed to address the above issues. In the proposed approach, split array type architecture is considered for implementing the 2n+1 operation, which occupies less area compared to the MBE scheme. Array architecture is a non-encoded architecture compared to the booth, so it does not require hard multiples for processing the PPs. The problem of an increased number of PPs in an array is addressed in the proposed scheme by splitting array structure into four segments, and full parallelism is maintained in PP additions also. The parallelism in the architecture ensures improved speed by maintain­ing the area advantage of the general array structure. The handling of signed numbers in array architecture is another reason for which the array scheme is less ex­plored for data processing applications. The represen­tation of signed numbers is addressed in the proposed architecture using appropriate constants. 3 Proposed Work 3.1 Proposed balanced word-length SRM In balanced word-length modulo multiplication, the number of bits required representing the input, modu­li, and output bits are summarized in Table 1. The type mentioned above of multiplication called balanced res­idue multiplication as it maintains a balanced bit-width between input, output, and moduli representation, as given in Table 1. In literature, the design problem of 2n-1 and 2n+1 residue multiplication is achieved through MBE schemes, whereas the possibilities of addressing this problem using array architecture are hardly con­sidered, especially for signed numbers. The hierarchical approach for signed array multiplication presented in [25]. The motivation behind this work is the regularity in VLSI implementation and the reduced area budget offered by the array architectures compared to MBE ar­chitecture. The delay problem usually found in array ar­chitecture compared to the MBE scheme is addressed here using hierarchy based processing of the input bits and parallel addition structure. For comparative analy­sis, the adder structure is realized using CSA and Han Carlson parallel prefix [26] based schemes. The math­ematical background, algorithm, and architecture of proposed residue 2n-1, 2n+1, and 2n multiplications are presented in the following subsections. Table 1: Balanced word-length moduli representation Moduli 2n-1 2n 2n+1 Number of input bits A & B n Moduli representation bits n n n+1 Number of output bits - P n n n+1 Figure 1: Intermediate PPs arrangement (nxn) [25] 3.1.1 Proposed 2n-1 SRM The 2n-1 modulo multiplication module is one of the essential operations in the RNS independent arithme­tic channel. The mathematical background, algorithm, and the proposed architectures for the signed 2n-1 resi­due multiplier are given below. Mathematical modeling Consider the 2’s complement signed number represen­tation of two binary numbers A and B as given in Eq. (1) & (2) (1) (2) The 2n-1 residue product representation is given in Eq. (3) (3) Step 1. Partitioning of Input bits and Generation of in­termediate PPs W, X, Y, Z using hierarchical partition­ing multiplier [25] Step 2. PP arrangement: The generated PPs are arranged [25], and a constant is added, as shown in Fig. 1 where m=n/2. Step 3. Rearrangement of Intermediate PPs: Fig. 2 shows the rearrangement of PPs, and the addition process flow carried out for the 2n-1 residue multiplica­tion, and the corresponding mathematical operations are given in Eq. (4) – (6). The notations and operators used in this mathematical modeling are summarized in Table 2 and Table 3 respectively. Figure 2: PP Rearrangement and addition process 2n-1 (nxn) Table 2: Notations used in mathematical modeling Notations Description AH, AL, BH, and BL Higher and Lower bits of A & B inputs. Cb Compensation Bits Mi+1 || Mi Overflow bits of Mi-1 addition process CyI1 One bit Carry of I1 addition process that has to be IEAC (Inverted End around Carry) CyI2 One bit Carry of I2 addition process that has to be IEAC CyI3 One bit Carry of I3 addition process that has to be IEAC R1c Carry Bit of R1 (or) Overflow bit of R1 R2c Carry Bit of R2 (or) Overflow bit of R2 R3c Carry Bit of R3 (or) Overflow bit of R3 CyMi n/2 Overflow carry bits of Mi addition process. If No overflow occurred n/2 bit zeros is considered CyQi One bit Carry of Qi addition process that has to be IEAC Table 3: Operators used in mathematical modeling Decimal Format: a=12; b=8; n=4 Binary Format: a=1100; b=1000; n=0100 Operator Description/ Functionality Example Result AND (1000)2 | OR (1100)2 NOT (0011)2 NAND (0111)2 EXOR (0111)2 EXNOR (1000)2 + Addition (20)10 Modulus (6)10 Summation (12)10 Double Summation (96)10 - Subtraction (4)10 a b Multiplication a b (96)10 X Multiplication (96)10 / Division (3)10 Multiplicative Inverse (14)10 || Concatenation (11001000)2 (4) The final product is (5) The compensation bits are expressed as (6) Where Algorithm The proposed 2n-1 SRM algorithm is given below Architecture The architecture of proposed 2n-1 residue multiplica­tion is shown in Fig. 3. The architecture consists of three stages, namely the partitioning stage, intermediate PPs generation stage, and adder stage. The four parallel modules in the intermediate PP generation stage M-I, M-II, M-III, M-IV indicates the hardware required for computing W, X, Y, Z given in [25]. The four independ­ent parallel addition process observed in the architec­ture is the main reason for achieving high performance in the proposed array architecture. The compensation bits are gets added in the final stage to obtain mod­ulo results. CSA and Han-Carlson parallel prefix adder structure is incorporated in Fig. 3 in order to analyze the performance. The results of the proposed work are further discussed in Section 5. Figure 3: Architecture of 2n-1 SRM 3.1.2. Proposed 2n+1 SRM The 2n+1 residue multiplication problem is considered as a demanding operation in RNS Processor due to the increase in moduli output range compared to 2n and 2n-1 multiplications, as represented in Table 1. In the proposed scheme, the increased moduli output range is regulated using the diminished-1 approach for both multiplier and multiplicand. The primary advantage of using the proposed scheme is that this architecture can handle exceptional cases like ‘all-zeros’ input and ‘all-ones’ input, which consecutively produce the cor­rect results. This architecture handles the bit positions higher than n-1 by complementing and mapping them to the LSBs. The mathematical background, algorithm, and the proposed architectures for signed 2n+1 residue multipliers are given in the below subsections. Mathematical modeling The diminished-1 representation of binary inputs A and B are modified as A’ & B’, which is given in Eq. (7) – (8) (7) (8) The residue product P is given by the following Eq.(9) (9) The methodology and arrangements of PP are the same as step 1 and step 2 of signed 2n-1, but the in­puts are A’ and B’. The final product is obtained by rear­ranging the PPs of Fig. 1 in such a way to obtain the result of 2n+1 residue multiplication. Fig. 4 shows the rearrangement of PPs, the position of PPs, and the ad­dition process flow carried out for the 2n+1 multiplica­tion, and the same is represented in Eq. (10) – (20). The mathematical operations performed between Row 1 to Row 4 are given below Row 1: (10) (11) Row 2: (12) (13) Row 3: (14) (15) Row 4: (16) Figure 4: PP Rearrangement and addition process 2n+1 (nxn) Finally, all four rows get added as per the following equations. (17) (18) Where Cb is given in Eq. (19) (19) The 2n+1 multiplication is given in Eq. (20) (20) Algorithm The proposed 2n+1 SRM algorithm is given below Architecture The overall architecture arrangement of 2n+1 is similar to that of 2n-1 except for the fact that it has some ad­ditional modules to perform 2’s complement operation and Inverted End Around Carry (IEAC), as shown in Fig. 5. However, the compensation generation scheme is complicated compared to 2n-1 architecture. 3.1.3 Signed 2n residue multiplier Mathematical modeling The operation required to obtain Module I (W) follows the same pattern as in 2n-1. The X & Y are given in Eq. (21) and (22). Z is not required for computing 2n be­cause it has a higher weight position compared to 2n value. (21) (22) The final 2n product is given in Eq. (23) (23) 3.2 Proposed unbalanced word-length SRM The unbalanced word-length moduli multiplier typi­cally used in applications different bit-width propor­tion between input, moduli, and output is required. In unbalanced word-length residue multiplication, the number of bits required to represent the input, moduli, and output bit-width, which are summarized in Table 4. The strategy followed to design 2k-1module is derived from the 2n-1 balanced module. However, the 2k+1 is not derived from the 2n+1 balanced module because it may lead to comparatively complex architecture with more delay penalty. Instead, 2n-1 balanced design is converted to an unbalanced 2k+1 by modifying the fi­nal result of 2n-1 multiplication. Table 4: Unbalanced word-length moduli representa­tion Moduli 2k-1 2k 2k+1 Number of input bits A & B n Moduli representation bits k k k+1 Number of output bits -P k k k+1 3.2.1. Proposed 2k-1 and 2k+1 SRM Mathematical modeling Let us consider the n bit output of balanced 2n-1 mul­tiplication given in Eq. (5). It is split into two halves PL and PH, as shown in Fig. 6 to obtain the result k=n/2 & k=n/4 bits, and the corresponding equations are given in (24) – (25). For k=n/2 (24) Figure 6: Unbalanced PP Rearrangements and addi­tion process For k=n/4 k=n/4 design is derived from k=n/2. The output of k=n/2 acts as an input for the k=n/4 design. (25) Algorithm The proposed SRM algorithm for the unbalanced 2k-1 and 2k+1 is given below Architecture The unbalanced SRM architecture for 2k-1 and 2k+1 is depicted in Fig. 7. The architecture is derived from pro­posed 2n-1 SRM. Figure 7: Architecture of 2k-1 & 2k+1 SRM 3.2.2. 2k SRM The residue multiplication is derived from a 2n balanced residue multiplier equation. The character­istic equations of 2k unbalanced residue multiplication are given in Eq. (26) (26) 4 RNS processor 4.1 Architecture In general, the cryptographic algorithm requires many rounds of arithmetic operations in order to create the ciphertext. Instead of doing such lengthy arithmetic operations in binary representation, residue values can be used to save the area and time budget. The pro­posed balanced and unbalanced word-length residue multipliers are used for implementing special moduli set based RNS computing platforms, as given in Fig. 8. The RNS processing system consists of three blocks, namely Forward Converter (FC), Independent Modulo Arithmetic Processing Unit (IMAPU), and Reverse Con­verter (RC) [13], [27]. The proposed SRM architectures are used to design arithmetic channels and RC. The FC and RC blocks convert the binary number to residue number and vice versa. The IMAPU block consists of application-based arithmetic operations or any other desired operations in modulo representation. The RC operation can be performed using the Chinese Re­mainder Theorem (CRT) [28] or Mixed Radix Conversion (MRC) [29]. In this paper, the MRC technique [13,27] is considered for the conversion in the RC block. The characteristic equations of MRC given in Eq. (27) – (29) shows that the operation can be done by modulo sub­tractions, multiplicative inverses, and residue multi­plication. Here the multiplicative inverse is computed using the Extended Euclidean algorithm (EECD) [30]. From [13,27] the decoded number is expressed in the following form for MRC technique (27) where The mixed-radix digits are derived as, (28) The finalized equation is derived for the value of N bit as, (29) Where m1,m2,m3 are moduli sets, and x1, x2, x3 are resi­due output of IMAPU. Figure 8: Hardware realization of signed RNS processor The effectiveness of the proposed multiplier is tested by designing decoupled modulo arithmetic channels and memoryless MRC reverse converter, as shown in Fig. 8. An example calculation depicting the dataflow in the architecture is given in Table 5. 4.2 Range analysis The permissible number ranges for balanced and un­balanced word-length residue multipliers are shown in Table 6. The bit-width required to represent triple moduli set {2n-1, 2n, 2n+1} balanced system is 3n+1bits whereas the maximum number of bits required for un­balanced moduli {2k+1,2k, 2k-1} system is 3k+1. 5 Results and Discussions 5.1 FPGA synthesis The architecture level functional verification of the pro­posed design is coded using Verilog HDL and simulated in the Xilinx ISIM tool. The results corresponding to hardware architectures are synthesized in Xilinx Synthesis Technol­ogy (XST) for balanced and unbalanced type residue mul­tipliers. The results of the proposed architecture with CSA (Proposed-I) and prefix-based adders (Proposed-II) are presented in Table 7 and Table 8, respectively. Table 7: FPGA synthesis results of balanced word-length SRM Multiplier n Xilinx Zynq FPGA Board (XC7Z020CLG484-1) Proposed - I Proposed - II LUT (No’s) Delay (ns) LUT (No’s) Delay (ns) 2n 8 37 11.5 37 11.4 16 186 26.2 203 21.7 32 928 70.3 1026 45.1 2n-1 8 112 18.6 144 17.7 16 530 51.3 697 28.7 32 2134 155.7 2848 53.0 2n+1 8 235 29.4 270 27.4 16 688 85.8 861 44.1 32 2215 196.7 3705 79.8 5.2 ASIC synthesis 5.2.1 Performance analysis From Table 9, the area comparison of 2n-1 SRM shows that the proposed architecture I & II requires less area compared to other multipliers [14][22][23]. The synthe­sis results show that the proposed design I occupy 17% - 22%, and design II occupies a 10% lesser area than existing modulo MBE. Delay analysis indicates that the proposed-I has a 17% - 24% speed improvement, and Proposed-II excels in speed by 26% - 30%. Power analy­sis shows that the total power required for the design is almost the same compared to recent works. In 2n+1 SRM architectures, the proposed designs out­performs the other multipliers in area efficiency and speed improvement [15,16,17,18,19,20,21]. Proposed architecture I save area in the range of 23% - 44%, whereas the proposed architecture II reduces the area in the range of 10% - 32% compared to existing MBE architectures. The speed improvement of proposed-I and II lies between the ranges of 10% - 35% and 20% – 39%, respectively. The power profiles of the proposed multipliers are almost the same as that of recent works. Since the proposed unbalanced residue multipliers are derived from proposed balanced residue multipliers, they follow the same trend in the area, delay, and pow­er metrics, which are presented in Table 10. The core problem addressed in this work is the im­provement of speed performance of residue signed array multiplier, which generally consumes less area than its booth type counterparts. To achieve this objec­tive, an enormous parallel operation from start to end is envisioned, designed, and implemented. It is inferred from the analysis that proposed designs have signifi­cant improvement in speed and area performance. 5.2.2 Hardware Implementation of RNS Processor RNS processing examples discussed in Section 4 and the architecture is shown in Fig. 8 is simulated, and ISIM simulated results are shown in Fig. 9. The synthesis of the RNS Processor is done for both FPGA and ASIC platforms. The results for the same are presented in Table 11. The synthesized netlist of the RNS processor is implemented by targeting to the Xilinx Zynq board (XC7Z020CLG484-1). 6 Conclusion A new array signed residue multiplication scheme for balanced (2n-1, 2n+1, 2n) and unbalanced (2k-1, 2k+1, 2k) word-length moduli are proposed in this paper. The proposed architecture with enormous parallelism is realized by incorporating CSA and Han-Carlson pre­fix adder structures into it. The existing and proposed multipliers are synthesized in both ASIC and FPGA technologies. From the synthesis results, the proposed-I 2n-1 residue multiplication scheme saves 17% area. However, the scheme with prefix structure achieves 26% speed and 24% PDP improvement compared to state of the art MBE 2n-1 residue multipliers. Similarly, a balanced 2n+1 proposed-I saves 23% area requirement. Speed and PDP improvement of proposed-II is 20% and 22 %, respectively, compared to the state of the art 2n+1 residue multipliers. The unbalanced multipliers derived from the balanced multiplier follows the same trend. Finally, the proposed residue arithmetic modules are used in arithmetic channel creation, reverse converter design of {2n-1, 2n, 2n+1} triple moduli set RNS Processor and the same is implemented as hardware using Zynq (XC7Z020CLG484-1) device for real-time verification. The results indicate that the proposed designs can be efficiently utilized to improve the speed and area per­formances of RNS based cryptographic applications like RSA and ECC. The results also show that the pro­posed-I SRM architecture implemented using CSA may be used for area constrained RNS applications, and the Proposed-II SRM architecture using prefix can be used for high-speed applications. 7 Conflict of Interest We have no conflict of interest to declare. 8 References 1. Sousa, L., Antao, S., Martins, P., “ Combining Resi­due Arithmetic to Design Efficient Cryptographic Circuits and Systems,” IEEE Circuits Syst. Mag., vol.16, no.4, pp.6-32, 2016. https://doi.org/10.1109/MCAS.2016.2614714 2. Celesti, A., Fazio, M., Villari, M., Puliafito, A., “Adding long-term availability, obfuscation, and encryption to multi-cloud storage systems,” J. Netw. Comput. Appl., vol.59, pp. 208–218, 2016. https://doi.org/10.1016/j.jnca.2014.09.021 3. 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Noorimehr, M.R., Hosseinzadeh, M. & Farshidi, R. ‘High Speed Residue to Binary Converter for the New Four-Moduli Set {22n , 2n +1, 2n/2 + 1, 2n/2-1} Arabian Journal for Science and Engineering, vol.39, 2887,2014. https://doi.org/10.1007/s13369-014-0963-4 29. Sousa, L., Antao, S.: MRC-based RNS reverse con­verters for the four-moduli sets {2n-1,2n, 2n+1, 22n+1-1},”IEEE Trans. Circuits Syst. II Express Briefs,vol.59,no.4,pp.244–248,2012. https://doi.org/10.1109/TCSII.2012.2188456 30. Sedjelmaci, S.M., “A parallel extended GCD al­gorithm,” J. Discret. Algorithms, vol.6, pp.526 – 538,2008. https://doi.org/10.1016/j.jda.2006.12.009 Arrived: 27. 10. 2019 Accepted: 31. 03. 2020 E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 1. Input: A & B (A, B › n-bit signed numbers), where n = 4,8,16,32,etc.. 2. Output , where P ‹ n bit 3. Intermediate PPs Generation ›W,X,Y,Z 4. Rearrange the Intermediate PPs into 4 rows as in Fig. 1. 5. Split the arrangement in Fig. 1 into two equal halves LSP (Least Significant Plane) ‹ Bit_Pos(0 to (n-1)) MSP (Most Significant Plane) ‹ Bit_Pos(n to (2n-1)) 6. Fold the MSP towards LSP side as given in Fig. 2. 7. M ‹ Sum (LSP, Folded MSP, EAC) 8. P ‹ Sum (M,Cb) E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 1. Input: A & B (A, B› n-bit signed numbers), where n=4,8,16,32,etc.. 2. Output , where P ‹ n+1 bit 3. A’ ‹ Diminished-1 (A); B’ ‹ Diminished-1 (B); 3. Intermediate PPs Generation ›W,X,Y,Z 4. Rearrange the Intermediate PPs into 4 rows as shown in Fig. 1. 5. Split the arrangement in Fig. 1 into LSP ‹ Bit_Pos(0 to (n-1)) MSP ‹ Bit_Pos (n to (2n-1)) 6. Fold the MSP towards LSP as given in Fig. 4. 7. R1‹Sum (LSP, 2’s Comp. (MSP), IEAC); 8. R2‹Sum (LSP, 2’s Comp. (MSP), IEAC); 9. R3‹Sum (LSP, 2’s Comp. (MSP), IEAC); 10. R4‹Sum (LSP, 2’s Comp. (MSP), IEAC); 11. M ‹ Sum ((Rx,) A’, B’), where x =1,2,3,4 12. P ‹ Sum (M, 2’s Complement (CyMi),Cb, IEAC) Figure 5: Architecture of 2n+1 SRM E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 1. Input: A & B (A, B › n bit signed numbers), where n=4,8,16,32,etc.. 2. Output , where P ‹ k bit for- 2k-1 and k+1 bit for 2k+1 3. Consider Eq.(5) - , 4. Split the Eq. (5) into two equal halves PH ‹ Bit_Pos(0 to (n/2)-1) PL ‹ Bit_Pos((n/2) to n-1) 5. Fold the PH towards PL side as mentioned in Fig. 6. If (2k-1) Operation 6. P2 = Sum(PL, PH, EAC ) › k=n/2 7. P4 = Sum(P2L, P2H, EAC ) › k=n/4 8. P8 = Sum(P4L, P4H, EAC ) › k=n/8 If (2k+1) Operation 6. P2 = Sum(PL, 2’s (PH), EAC ) › k=n/2 7. P4 = Sum(P2L, 2’s (P2H), EAC ) › k=n/4 8. P8 = Sum(P4L, 2’s ( P4H), EAC ) › k=n/8 E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 Table 5: RNS processor computation A=600 B=600 m1=255 m2=256 m3=257 Forward Conversion a1=|600|255=90 a2=|600|256=88 a3=|600|257=86 b1=|600|255=90 b2=|600|256=88 b3=|600|257=86 IMAPU x1=|90x90|255= 195 x2=|88x88|256=64 x3=|86x86|257= 200 MRC based Reverse Conversion Z1 = 195 Z2 = ||255|-1256x(64-195)|256 = |255x-131|256 = 131 Z3 = |(||255|-1x|256|-1|257)x(200- (131x255)+195)|257 = |32768x(200-33600)|257 = 5 X=(5x255x256)+ ((131x255)+195) =326400+33405+195 X=360000 X=3,60,000 E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 Table 6: Range analysis of triple moduli set RNS processor Balanced Word-Length Moduli Unbalanced Word-Length Moduli Moduli 2n-1 2n 2n+1 2k-1 2k 2k+1 Number of Input Bits – A & B n Number of Output Bits -P n n n+1 k k k+1 Permissible Number Range Input Range (Signed Integers) Input Range (Unsigned Integers) [0 - 2n-1] Output Range -P [0 - 2n-2] [0 - 2n-1] [0 - 2n] [0 - 2k-2] [0 - 2k-1] 0 - 2k] Dynamic Range of the Moduli R= {23n-2n } R= {23k-2k } Permissible Range (Signed Integers) Permissible Range (Unsigned Integers) Table 8: FPGA synthesis results of unbalanced word-length SRM Mul. n Zynq FPGA Board (XC7Z020CLG484-1) k=n/2 k=n/4 k=n/8 LUT (No’s) Delay (ns) LUTs (No’s) Delay (ns) LUT (No’s) Delay (ns) Proposed -I 2k 8 6 8 - - - - 16 41 15 5 7.9 - - 32 250 43 41 13.2 5 7.9 2k-1 8 120 20 - - - - 16 645 67 654 68.8 - - 32 2577 162 2597 166.5 2605 168 2k+1 8 121 19 - - - - 16 649 70 654 78.1 - - 32 2587 173 1580 176.0 2599 179 Proposed -II 2k 8 5 8 - - - - 16 44 13 5 7.8 - - 32 255 25 44 15.0 5 7.8 2k-1 8 156 18 - - - - 16 735 52 753 55.0 - - 32 2967 157 3018 61.9 3049 164 2k+1 8 163 21 - - - - 16 960 54 980 36.0 - - 32 2996 160 3056 162.5 3081 165 *LUT – Look Up Table & LE- Logic Element E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 Table 9: ASIC synthesis results of balanced word-length SRM Mul. n Technology 180 nm 90 nm 45 nm Area (µm2) Power (µW) Delay (ns) PDP (pJ) Area (µm2) Power (µW) Delay (ns) PDP (pJ) Area (µm2) Power (µW) Delay (ns) PDP (pJ) 2n Proposed - I 8 2164 217 1.3 0.3 682 30 0.8 0.02 369 20 0.5 0.0 16 10438 1677 7.4 12 2967 308 4.2 1.3 1604 200 3.6 0.7 32 39171 6095 26.8 163 12273 1218 15.2 18.5 6557 739 13 9.4 Proposed - II 8 2044 228 1.2 0.3 652 51 0.8 0.0 357 32 0.8 0.0 16 11302 1809 6.7 12 3167 407 4.7 1.9 1712 232 4.1 1.0 32 45784 6316 23.5 148 15787 1264 16.7 21 8435 769 14 10.7 2n-1 [22] 8 8668 849 6.8 6 2733 169 4.2 1 1477 108 4.0 0.43 16 34382 4328 29.1 126 9770 797 16.4 13 5281 513 14.3 7 32 125346 19176 86.5 1658 39270 3835 48.9 188 20981 2323 41.2 96 [14] 8 8148 781 6.2 5 2569 156 3.8 1 1389 101 3.7 0.37 16 32663 3983 26.5 105 9282 732 15.0 11 5017 473 13.0 6 32 119079 17259 78.7 1357 37306 3452 44.5 154 19932 2089 37.5 78 [23] 8 8235 798 6.4 5 2597 158 3.9 1 1404 103 3.8 0.38 16 32663 4069 27.0 110 9282 748 15.3 11 5017 483 13.3 6 32 117825 18025 80.4 1449 36913 3607 45.5 164 19722 2185 38.3 84 Proposed - I 8 6518 789 5.1 4 2055 163 3.2 1 1111 124 3.1 0.38 16 26447 4058 22.2 90 7516 824 12.5 10 4063 537 10.9 6 32 97926 18282 67.0 1225 30679 3689 37.9 140 16392 2211 31.9 71 Proposed - II 8 6708 809 4.7 4 2081 169 2.8 0 1141 127 2.8 0.35 16 28937 4147 20.1 83 8120 845 11.3 10 4389 548 9.7 5 32 114459 18447 58.8 1084 35859 3722 33.7 125 19159 2234 27.5 61 2n+1 [21] 8 17659 1058 13.8 15 5588 209 8.6 2 3020 135 8 1 16 63121 5999 56.5 339 18179 1104 31.6 35 9827 713 27.8 20 32 254585 30713 170 5221 79827 6145 96 590 41349 3719 81 301 [15] 8 15365 1049 13.6 14 4874 207 8.3 2 2634 135 8 1 16 59211 5894 54.9 324 16899 1085 31 34 9135 699 27 19 32 237894 28951 168 4864 73352 5792 95 550 39659 3508 80 281 [16] 8 13961 944 11.1 10 4402 188 6.8 1 2380 122 6.6 1 16 53425 5216 51.6 269 15182 961 29.1 28 8207 618 25.4 16 32 210141 25176 159.6 4018 65835 5036 90.3 455 35175 3049 76 232 [17] 8 13251 870 12.2 11 4142 173 7.5 1 2239 112 7.2 1 16 52376 4658 46.7 218 14871 859 26.4 23 8039 554 23 13 32 224280 22582 141.1 3186 68951 4518 79.8 361 37280 2736 67.2 184 [18] 8 12565 954 13.3 13 3962 190 8.2 2 2142 122 7.9 1 16 48617 5306 57 302 13816 977 34 33 7468 629 29 18 32 187025 26057 155 4039 58593 5211 81 422 31305 3155 78 246 [19] 8 15058 975 14 14 4776 194 9 2 2582 125 8.5 1 16 52698 5130 55.1 283 15040 945 32 30 8130 610 28 17 32 166526 23163 154 3567 51347 4633 80 371 27762 2805 74 208 [20] 8 8796 916 12.4 11 2773 182 8.3 2 1499 118 7.4 1 16 38893 4882 44.6 218 11053 899 26.6 24 5974 581 22.5 13 32 158971 21889 134.7 2948 49804 4379 64.7 283 26610 2650 60.5 160 Proposed - I 8 8356 908 11.7 11 2635 186 7.9 1 1424 143 7.1 1 16 33059 4787 41.4 198 9395 972 24.5 24 5078 637 20.2 13 32 122408 21797 120.2 2620 38349 4439 57.6 256 20489 2670 55.6 148 Proposed - II 8 8831 929 11 10 2825 192 7.2 1 1495 148 6.5 1 16 36171 4841 37 179 10279 1004 22 22 5556 653 18.1 12 32 143074 22127 102 2257 44857 4472 50.7 227 23982 2683 49.8 134 E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 Figure 9: Simulation result of RNS processor Table 10: ASIC results (90 nm) of unbalanced word-length SRM Mul. n k=n/2 k=n/4 k=n/8 Area (µm2) Power (µW) Delay (ns) PDP (pJ) Area (µm2) Power (µW) Delay (ns) PDP (pJ) Area (µm2) Power (µW) Delay (ns) PDP (pJ) 2k Proposed - I 8 173 11.4 0.7 0.01 - - - - - - - - 16 640 32 2.5 0.08 124.2 5.4 1.6 0.01 - - - - 32 3224 241 8.0 1.93 739.2 26.4 5.8 0.15 142 13 1.5 0.02 Proposed - II 8 110 3.8 0.7 0.00 - - - - - - - - 16 637 45 2.7 0.12 110.7 10.7 1.5 0.02 - - - - 32 3564 254 8.5 2.16 732.6 36 4.5 0.16 129 20 2.6 0.05 2k-1 Proposed - I 8 2172 181 3.6 1 - - - - - - - - 16 7757 905 14.1 13 8146 934 15.2 14.2 - - - - 32 31413 3953 42.15 167 32984 4085 45.2 184.7 33314 4142 47 195 Proposed - II 8 2196 186 3.3 1 - - - - - - - - 16 8405 950 12.8 12 8659 986 13.9 13.7 - - - - 32 36643 3993 36.8 147 37742 4145 39.5 164 38122 4188 41 173 2k+1 Proposed - I 8 2212 203 3.7 0.7 - - - - - - - - 16 7846 964 14.3 14 8084 996 15.3 15 - - - - 32 31634 4043 42.6 172 32584 4184 45.5 190 32911 4241 48 204 Proposed - II 8 2240 209 3.6 0.7 - - - - - - - - 16 8575 1021 13.4 14 8821 1053 14.4 15 - - - - 32 36924 4142 38.2 158 38402 4264 40.1 171 39937 4323 45 192 E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 Table 11: FPGA and ASIC synthesis Results of RNS Processor Parameter FPGA Synthesis Parameter ASIC Synthesis 180 nm 90 nm 45 nm Proposed - I Proposed - II Proposed - I Proposed - II Proposed - I Proposed - II Proposed - I Proposed - II Number of LUTs 23490 26508 Area (µm2) 230237 241028 73676 77129 41259 43192 Power (mW) 36 41 15 18 10 12 Delay (ns) 936 875 Delay (ns) 870 700 440 325 170 145 E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 E. Sekar et al.; Informacije Midem, Vol. 50, No. 2(2020), 71 – 86 Copyright © 2020 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Journal of Microelectronics, Electronic Components and Materials Vol. 50, No. 2(2020), 87 – 103 https://doi.org/10.33180/InfMIDEM2020.202 Real-time, Cuff-less and Non-invasive Blood Pressure Monitoring Alireza Abolhasani, Morteza Mousazadeh, Abdollah Khoei Urmia University, Microelectronic Research Laboratory, Urmia, Iran Abstract: In in this study ultrasonic method was applied for the measurement of blood pressure (BP). First, a novel method is proposed to measure mean arterial pressure (MAP), diastolic blood pressure (DBP) and systolic blood pressure (SBP) using ultrasonic sensors. The proposed algorithm is implemented by measuring the diameter of the artery and the speed of blood flow based on Doppler physical phenomena so that the BP can be calculated. The results of the proposed algorithm for MAP, SBP, and DBP hypertension analyses were evaluated with the results of Association for the Advancement of Medical Instrumentation (AAMI standard) for all three cases and their mean error rate for the worst case was -0.233mmHg and the standard deviation for 422 samples taken from individuals in the worst case was 4.53 mmHg that meets the standard requirements. Also, according to the British Hypertension Society (BHS) standard, the proposed algorithm for the estimation of BP for all three cases of MAP, DBP, and SBP has Grade A, indicating its higher accuracy in measuring and using the most effective variables in the diagnosis of hypertension in the human body. The proposed algorithm in BP estimation is non-invasive, cuff-less which needs no calibration, and is only based on using the ultrasonic sensor. Keywords: cuff-less; continues monitoring;blood pressure Neinvazivno merjenje krvnega tlaka v realnem času brez uporabe manšete Izvleček: V članku je predstavljena metoda meritve krvnega tlaka z ultrazvočnimi senzorji. Najprej je predstavljena nova metoda merjenja povprečnega (MAP), diastoličnega (DBP) in sistoličnega tlaka(SBP) z uporabo ultrazvočnih senzorjev. Predlagan algoritem temelji na meritvi preseka žile in hitrosti pretoka krvi na osnovi dopplerjevega pojava. Razultati meritev so preverjeni z rezultati meritev po AAMI standardu. Povprečna napaka vseh treh veličin na najslabšem primeru je bila -0.233 mmHg s standardno napako 5.53 mmHg. Glede na britansko združenje BHS se metoda uvršča v razred A meritev krvnega tlaka. Metoda je ne invazivna brez uporabe manšete Ključne besede: brez manšete; nepretrgane meritve ;krvni tlak * Corresponding Author’s e-mail: m.mousazadeh@urmia.ac.ir 1 Introduction Cardiovascular disease (CVD) is one of the main caus­es of death in the world. According to the European Heart Institute reports, 4.1 million people die from the disease each year [1]. Long-term hypertension is one of the most important risk factors for coronary artery disease, stroke, heart failure, atrial fibrillation, periph­eral vascular disease, vision loss, chronic kidney disease and dementia [15-17]. The prevalence of hypertension in 2014 was 1.3 billion worldwide, and it is projected to reach 1.56 billion by 2030 [2, 3]. Blood pressure (BP) is one of the most important pa­rameters of the human body where by its measure­ment, very useful information can be provided for the physician. Repeated measurements of BP can lead to early diagnosis of the disease, which can be controlled and treated owing to the early diagnosis [4]. By defini­tion, BP is the pressure exerted by blood on the walls of a blood vessel. Its value depends on the functional fac­tors of the cardiovascular system, such as the strength of the cardiac extrusion, the flexibility, and the thick­ness of the vessel wall [5]. This pressure applied to the vessel wall differs in the two modes of cardiac func­tion and resting phase, which are termed the systolic pressure-maximum pressure (SBP) and the diastolic pressure-minimum pressure (DBP) respectively [6]. According to the National Heart, Lung and Blood Insti­tute (NHLBI), standard systolic and diastolic BP values are 120 and 80 mmHg, respectively. So, BP can be con­sidered in a range which varies proportional to each heartbeat [7]. Another important factor in BP measure­ment is obtaining the mean blood pressure (MAP) that can be calculated using equation (1). MAP = (2DBP + SBP)/3 (1) In health centers, BP is generally measured with a cuff, which is the most common method for its estimation [8]. Although the measurement of BP using cuff-based methods is meticulously acceptable and reliable, this method is completely dependent on the ability of the one who performs the measurement. Furthermore, cuff-based methods cannot be directly and continu­ously used because they require several minutes of interruption between each measurement [18]. Hence, the challenges of measurement using the cuff are: BP measurement during movement, the harmfulness of this type of pressure measurement for the patient’s cardiovascular system, the inability of the device in continuous measurement, The cuff weight itself, pa­tients’ dissatisfaction with the use of cuffs under spe­cific conditions, such as exercise testing and Ambula­tory Blood Pressure Monitoring (ABPM) (ABPM) [5, 9, 10]. In the last two decades, there have been extensive studies over non-invasive BP measurement without applying cuff that has led to good results. Amongst these technologies are wearable sensors used by typi­cal people daily, such as smart watches, which provide useful information about vital signs of the body. Many sensors that are used to gather vital body information such as body temperature, heart rate, the amount of oxygen for blood saturation and blood sugar, etc. can be made of flexible and portable materials so that they are easy to use [24 to 29]. This article aims at present­ing a novel method for measuring BP in a non-invasive way without using cuff. In order to measure BP without using cuff ,some other methods have been proposed ,in which most of the mathematical relationships and estimation of BP are obtained from one of the meas­ured elements of the body by either using sensors or by imaging the desired vessel as well as extracting their features using image processing techniques [72]. One of the most commonly used non-invasive BP measurements is Pulse Transit Time (PTT) [11]. The pulse transit time is when the heartbeat reaches the desired sensor mounted on the body. In many cases, researchers use electrocardiographic (ECG) signals and sensors (PPGs) to measure BP using this method. PTT measurements can be implemented by one ECG sen­sor and one PPG sensor or two PPG sensors [12]. The proper reception of the ECG signal requires at least three electrodes at three different points of the body. Patient movement, poor electrode contact with the skin surface and electrode wires for prolonged recep­tion can cause signal noise, which is a limiting factor for measuring BP based on this method [9, 13]. The high cost of using these different devices and sensors, the difficulties associated with installing sensors in differ­ent parts of the body and their interconnection with the central control system is a great concern in using this method to measure BP. As has been frequently re­ported, using PTT due to the dynamic nature of human muscles and hydrostatic changes cannot be a reliable method for measuring BP [20]. A simple and efficient way to directly measure BP using PPG sensors has been reported. In which they used a kind of regression mod­eling between the amplitude of the signals obtained from PPG sensors to estimate BP [21]. The results of this method were promising for estimating systolic BP, but in the estimation of diastolic pressure did not have a good performance and had significant errors. Fur­thermore, since regression has no memory, it cannot model the delay between the received PPG signal and the instantaneous BP which in turn, it can create some errors in the measurement [22]. Although this method is perfectly suited for modeling the portable systems, it has complex computations. In addition, the BP and the results of PPG sensors are not constant due to dynamic human muscle changes and hydrostatic vascular chang­es, so the application of this method may be limited to certain conditions. Particularly, if somebody would like to estimate BP using PPG, considering the fact that this method is based on measuring the amount of oxygen in the blood and when there are disorders such as hypoxia (hypoxia), this method cannot be practically used [23]. In [31] a new method has been reported for extracting BP characteristics from the amplitude and frequency of the signal received from the body based on PTT and Fourier Series Transform (FFT). In all the studies based on the extraction of amplitude and frequency informa­tion, after the formation of the characteristic vector and system training steps, using different machine learning algorithms such as regression algorithms, neural net­work [33] and fuzzy logic [10] The BP estimation is pos­sible. These methods, in which the features are extracted in the form of a signal, are called the parameter-based approach. This method has a lot of complexities and er­rors, so it is desirable to use more accurate methods to obtain BP. All the above-mentioned methods estimate BP somehow by measuring one of the characteristics of the body’s blood transfusion system and generalizing it to different conditions. It must be mentioned that the Bernoulli method can also be of interest for BP measurement. However, if we want to employ such a method, we need to measure the primary pressure. Therefore, it is not applicable for our purpose. According to the points mentioned above, in all these methods the amount of BP is measured indirectly by measuring one of the effects of increasing or decreasing BP in different parts of the body. On the contrary to what has been said earlier, the method presented in this paper, for the first time, directly examines the effect of blood changes on the blood vessels to measure BP very accu­rately. In the proposed method, the ultrasonic sensor is used to measure the transmitted and received waves, and after receiving the information from the ultrasonic sen­sor, using the Doppler physical phenomenon the vessel diameter and blood velocity are obtained, and then using the presented equations the amount of BP is calculated. Due to the flexibility and elasticity of the blood vessels, as the blood passes through them, the diameter of the ves­sels and then the volume of blood passing through the artery varies fully depending on the BP [14]. If the blood volume changes are accurately measured, they will have a waveform similar to Figure 1 and their frequency will be the same as the heart’s operating frequency [30]. The above signal can be divided into two parts. The upper part of the signal is related to the heart or systole, while the lower part is attributed to the diastole. Figure 1: The volume of blood vessels in one cardiac cycle 2 Hypothesis and objectives The main idea behind the paper was to introduce a continuous-time, cuff-less method for the measure­ment of the BP. According to the provided expressions in this study, the main parameters such as error, blood density and the diameter of the artery are supposed to have constant values. 3 Materials and methods How to describe and measure the elastic behavior of the arteries is of a great importance, since from the as­pect of basic physiology in the clinical domain, the risk of cardiovascular disease has been more prevailing. In 1960, Patterson is. [34] (2) In Patterson equation (Ep), P and D represent the pres­sure and the diameter respectively. The reverse of equation 2 was introduced in 1975 as the “arterial com­pliance” [2]. (3) Since then, however, various authors have used the term “distensibility” for such cases which led to a great­er association between mechanics and medical sci­ence. Accordingly, the authors recommend that this difference in terms all referring to the inverse of the elastic modulus be disregarded Instead, they had bet­ter use some terms which are well-defined and appro­priately used in various disciplines and replace “elastic modulus” and “compressibility” with “compliance” and “distensibility”[36-38]. In classical physics, the “elasticity” is measured by in­creasing the force, the amount of deformation of the isotropic sample, and finally, using these values the stress-strain curve is obtained. The amount of deforma­tion of a specimen will depend on the elastic modulus and its geometry (length and cross-section). In engi­neering designs, the information about the behavioral properties of materials is required, regardless of their geometry. Thus, to eliminate the effect of geometry, the existing data is converted to other parameters. For this purpose, the amount of tensile or applied compres­sive force and the deformation values are converted to stress and strain respectively. The relationship between stress and strain is linear until the material reaches the Yield strength. Ep represents the slope of this part of the curve which is identified by Young’s modulus or the modulus of elasticity that can be used to calculate Ep of material by Hook’s law as shown in Figure 2. .Vvolume the change in volume Vvolume from the isotrop­ic material that is created in response to the pressure change .P, the value of Vvolume ×.P/.Vvolume is known as the “volume elasticity coefficient” and is usually denot­ed by the letter K. In [39-40], in expression was driven for the forward go­ing velocity of the pressure pulse, .P, in an infinitely long, thin-walled elastic tube filled with an essentially incompressible fluid and with the elasticity of the tube wall was considered to be isotropic. This has been known as the characteristic pulse wave velocity as shown in the equation below if we consider blood as the expected fluid and the artery equivalent to a very long tube with thin walls; (4) In this equation, . is the density of blood and K is the elastic modulus of luminal volume change, per unit length of the artery (artery containing refined blood), which is calculated from equation 5.[78] (5) It may be noted that since where R is the luminal radius and, and if we consider .Vvolume to be small enough then equation 2 can be written as following. (6) Using Young-Laplace Equation Theory of Young-Laplace Equation and for thin-walled tubes, it can be concluded that the stress of the T-ring on the arterial wall with thickness t and radius R depends on the lu­minal pressure P and is obtained using the following equation [40]. (7) If we rewrite this equation based on the pressure, then the Barlow’s Formula will be obtained. (8) If the pressure P changes with a little value change as .P, then the stress will change with the little change value of .T using the following equation. (9) Therefore, Einc can be defined for static incremental Young’s modulus for arterial wall type: (10) (11) Since then the relation of pulse wave velocity can be written as follows: (12) Relation 12 refers to the Moens-Korteweg equation [41-42]. This equation assumes that the arterial wall is isotropic and experiences isometrics changes with the pulse pressure. A detailed study of the structure of the arterial wall re­veals that the three main components of arterial wall elasticity are: collagen, elastin, and smooth muscle, which cause different K values.[43-46] Thus, the value of K for each artery will vary with the pressure and the amount of stress applied [47-49]. As a result, a constant K value cannot be used in the analyses and accordingly in the estimation of BP because the K value is directly related to the individual, the material of vessels and many other factors that are unique to each individual. Therefore, it is proposed to describe the tensile behav­ior of the arterial walls, namely the elastic modulus for the volume change per unit length of the lumen and its inverse, that is, the amount of compression. 4 The proposed method According to the explanations given in the previous sections, and knowing the pulse velocity equation, we can rewrite equation 12 as equation 13.[79-80] (13) In this equation , Vvelocity is the velocity of blood passing through the vessel and t is the thickness of the artery, E is the Young’s module, d is the diameter of the vessel, . is the density of blood, and in this regard ,the value of E can be substituted by 14, where E0 is the value of the Young’s module at the pressure of zero and it is always about 33.7 to 63.7mmhg and also the coefficient . of the arteries that is always in the range 0.016 to 0.018 mmhg-1.[74-75] (14) Substituting the relation 15 [76-77] into relation 14, will have: (15) Then, after several steps of simplification and obtaining the parameter p from the relation 15, we will have: (16) The relation 16 is presented as the final relation for measuring the BP in which . is the density of blood with a value of 1080 kg/m^3 and t is the approximate thickness of the vessels which is 0.46mm. If we obtain the values of VVelosity for the velocity of blood flow through the artery and also the value of d for the diameter of the arterial vessels, we will be able to find the BP. The description given is shown as below: Figure 3: Artery and its related parameters Therefore, in order to obtain BP, we need to find the diam­eter of the artery and the velocity of blood flow, but since the method presented in this article is a non-invasive method; both of these quantities should be measured non-invasively. The best way to measure the blood velocity is using ul­trasound and Doppler methods because ultrasonic waves are one of the least dangerous methods for measuring all kinds of vital quantities and the simplest imaging meth­ods in the medical world. The procedure is carried out by sending a wave having a particular frequency to the tissue or the target part of the body and depends on the quantity being measured either by discrete Doppler method or by continuous Doppler method, the measurements are im­plemented. According to clinical trials, the best frequency to measure blood flow through the artery is 4.63MHz, and the frequency of ultrasonic waves transmitted to measure vessel diameter is 5MHz because of having the highest rate of reflection by blood and arteries walls [73]. In rela­tion 16, the parameters . and t are different for different individuals as the blood density and thickness of the ves­sel will change as the age goes up. Thus, to prove the va­lidity of the presented relationship and also to show that the presented relationship has the least error, these two factors are identified as the causes of error in the meas­urement results and then the error caused by the effect of these two parameters on the measured pressure value was obtained. If we determine the amount of changes in blood density with .. and the changes in artery thickness with .t, then we will have: (17) The second term in the above equation is equal to the error arisen from the density and the thickness so we will have: (18) Concerning the Taylor expansion of the logarithmic function, we can write: (19) If ../. and .t/t have the same signs, then the numera­tors of the fractions are reduced and the error value is reduced. If ../. and .t/t have opposite signs, then we will have the highest amount of error: There are two states for having opposite signs, in the first case when ../. is positive and .t/t is negative, there will be: (20) The numerator of the fraction will be positive and the denominator of the fraction will be less than one, and as the subsequent statements are subtracted, the error will be reduced. In the second case, if ../. is negative and .t/t is posi­tive, we will have: (21) The numerator will be negative and the denominator of the fraction will greater than one, so we will have the highest rate of error. If ../. and .t/t is considered to be equal, then we will have: (22) 5 The measurement of the blood flow velocity in the artery using Doppler theorem The Doppler phenomenon was originally proposed for frequency variations of the sound source in clas­sical physics. According to this effect, whenever the receiver of the audio source is moving relative to an audio transmitter, the receiver receives a frequency other than that sent one by the audio source. Taking into account the relativity theorem, there is no differ­ence in the movement of the sound transmitter rela­tive to the sound receiver or the sound receiver toward the sound transmitter. In this case, the received wave­length will be different from the transmitted one. In the Doppler theorem in the above relations, is C the veloc­ity of sound moving in the desired environment, . is the wavelength, and F is the ultrasonic wave frequency. Now if the generator source moves at the speed of V: (23) In equation 23, F is the frequency of the sent signal to­wards the moving fluid, V is the velocity of the move­ment of the waves in the desired environment, VS is the velocity of passing fluid and is the received frequency belonging to the reflected signal from the moving fluid, which can be readily obtained by knowing the veloc­ity of movement in the body and the frequency of the signals being transmitted and received. This is related to the condition that the transmitter and receiver are beside each other without having any angles relative to each other But in construction of two sensor side by side, one has the role of transmitter and the other one the role of the receiver, there will always be an angle with the blood flowing through the artery, and having this angle would give a better and more accurate meas­urement. Using the following equation, we also include this angle in our analyses to give a more accurate meas­urement so the relation about the Doppler theorem for measuring blood flow velocity can be rewritten as fol­lows: [69-71] (24) In equation 24, V is the velocity of the passing blood, F1 the frequency of the transmitted signal and F2 is the frequency of the received signal, and the difference be­tween these two frequencies is known as Doppler shift. Also, in the equation above, . is the angle between the ultrasonic signal transmitted and the blood flow­ing through the artery which will be adjusted once the device is constructed and it will be fixed, and C is the rate of movement of ultrasonic waves in body tissues. The operation of the above system is shown in Figure 3, where the signal is transmitted from the transmitter sensor to the target vessel and it is reflected in the ar­tery after moving through the blood. Then, the receiver sensor receives the reflected signal, and the Doppler shift can be obtained by detecting the frequency of the received signal. The accuracy of the system is very high because the only vessel near the elbow through which blood passes is the arterial vessel. It should be noted that there are other vessels at the location of measure­ment, but due to their small diameter or sub-arteries, they will have a smaller Doppler shift compared to the main vessel, and accordingly, to solve this problem, the receiver takes into account the highest difference of the received frequency. So, this problem is resolved automatically and what we have in the output is the velocity of the blood passing through the target artery. Figure 4: How to apply Doppler theorem to measure the blood velocity in an artery How to select the desired vessel from the vessels at the site of measurement is based on the selection of the highest frequency difference. Since there are no other vessels near the target vessel, even if the sensor is not positioned in the proper location, it will still be possible to detect the passage of blood correctly because the vessel has the highest rate of passing through it, and the adjacent arteries are much slower than the main artery and have a very little impact on the transmitted frequency. Then, by performing a maximization step, it practically filters out the effect of the other veins and the resulting change in the received frequency is due to the main artery and our target vessel, as shown in Fig­ure 4. The method of measuring blood velocity will be as in the block diagram of Figure 5, in which the block diagram sends a number of ultrasonic sensors acting as a transmitter and transmits a sound having the fre­quency of 4.63MHz to the target artery. This frequency is generated by the generator signal block. Another ultrasonic sensor that plays the role of the receiver re­ceives the frequency-shifted signal from the blood flow and sends it to the divider block after passing through an amplifier step. At the output of this block, we also have the frequency resulting from the division of the transmitted and the received signals. The output of the subtractor output is sent to the processor where along with the other required components, the desired pro­cess is performed and the blood flow rate is extracted. Figure 5: Block diagram of detection of the blood ve­locity 6 The measurement of vessel diameter using Doppler theorem As mentioned before, applying the ultrasonic system and the Doppler theorem can be done in two ways of continuous Doppler discrete Doppler. The Dop­pler transmits the ultrasonic waves continuously and the other sensor receives the reflected signal, and by synthesizing the received signal and extracting its fre­quency, the desired measurement can be made. This method based upon Doppler theorem is very useful for velocity measurement, and in the medical world, and especially in sonographic devices, this technique is used to find the rate of blood flowing through different parts of the body, as well as to detect vascular conges­tion and even blood flow in the fetus. An ultrasonic signal is sent to the desired location to measure the diameter of the artery, and with respect to the reflections made from different interior and exterior walls and so on the depth as well as the distance from the desired part to the sensor and body surface as well as the thickness can be measured and even it is feasible to obtain a three-dimensional shape of the desired body by considering the differences between the reflections made from different parts. We used this technique in this article to measure the vessel diameter. The procedure is done in this way that using the signal with specific frequency af­ter being transmitted by the transmitter sensor and the reflections made from the vessel walls; the diameter of the vessel can be detected. According to clinical trials, the vessel wall with the frequency of 5 MHz has the highest response and the highest reflection as well. In this case, the time difference between the signals with the high­est amplitude (the arteries with thicker wall diameters have more reflection at the desired frequency and reflect the transmitted signal more) will be equal to the sweep time of the signal from the vessel walls and then through which the diameter of the vessel can be calculated. The schematic function of the measurement of the vessel di­ameter system is shown in Figure 6 and the block diagram of the vessel diameter detection system is shown in Fig­ure 7. Since, however, the material the arterial wall is made of differs from that of the vein, and the frequency chosen to be transmitted toward the artery to measure artery diameter is proportional to the structure and material of the arteries, and most of the reflection is made from the arterial wall, not the vein, so, the selection of the arterial vessels will be done with a high accuracy. According to Figure 7, the system functions in this way that the signal is transmitted by the transmitter sensor at a frequency of 5 MHz and after colliding with the outer wall of the vessel, some portion of the signal is reflected and the rest continues its way and colliding with the other wall of the vessel, it will be reflected. By having the time difference between the first reflected signal and the second reflected signal and the wave velocity in the body tissues using equation 25, we can obtain the de­sired artery diameter. Here, d is the diameter of the de­sired artery, C is the velocity of ultrasonic movement in the body and .t is the time difference between the two signals reflected from the two vessel walls. The signals reflected through the vessel wall pass through an ampli­fier block and go into the Level Detector block. In this block, by detecting amplified signal edges, a counter is applied and starts counting at a specified frequency that can be obtained by measuring the amounts counted to obtain the diameter of the vessel. Figure 7: The block Diagram of the Measurement of artery Diameter (25) 7 The implementation of the total system of blood pressure measurement The block diagram of the total system for measuring the BP will be in figure 8. In this figure, the solid lines are related to the control path and the continuous lines are belonging to the data path. According to the descrip­tions above, using the ultrasonic sensors of the receiver the desired signal after being received is amplified and loaded into the Frequency detector and Time Detector block and then, from these blocks the velocity and the diameter of the blood artery are extracted. Finally, in the Processor block, the necessary processes are performed according to equation 17 and the BP is obtained. To demonstrate the correct performance of the pro­posed equations, we used MATLAB software; we con­sidered the blood velocities in the range of 30-50 cm/s and the vessel diameter 1.6-3.4mm to be variables, as­suming that the other parameters in the equation 18 were constant. Also, we considered the value of . as a constant coefficient of the vessel to be 0.017mmHg-1, E0 Young’s modulus at zero pressure to have the con­stant value of 4.5kPa, . representing the blood density of1080 kg/m^3 and the approximate thickness of the vessels to be 0.46mm. [73] After simulating the above relationship, the ranges of high and low BP changes were obtained as 135mmHg and 73mmHg, respec­tively. The effect of instantaneous changes in the artery diameter and blood flow velocity that are inversely cor­related is clearly shown in Figure 9. In order to verify the correct operation of the proposed method and its equations, clinical testing was per­formed at Urmia Shams Cardiology Center (Iran). The test was performed simultaneously on one person in two ways; one using a Finapres BP monitor NOVA (Fi­napres Medical Systems, Enschede, Netherlands) and the other one using an ultrasonic sensor. The NOVA device is able to measure the BP at the mo­ment, so it records the person’s BP momentarily and simultaneously we can simultaneously obtain the ves­sel diameter using the ultrasonic sensor and blood velocity and later, applying the proposed method we obtained the person’s BP. We compared the results of the systolic and diastolic BP measurements and MAP for 60 seconds with the NOVA device and the proposed method, and the curves presented in Figure 10 show the results of these measurements. The test was performed on the person in two different ways, one when the person was holding his or her breath and the other one when the person was breathing nor­mally. In the curves in Figure 10, the dashed lines (blue) are the results obtained from the NOVA and the solid lines (red) are the results of the instantaneous measure­ment of BP by the proposed method. By examining the results of the two methods, one can clearly show the ac­curacy of the measurement using the presented system. 8 Database The number of patients selected for measuring the BP was measured was 211, from whom 122 were males and 89 were females. For each individual, Sampling was taken twice. Hence the number of samples was 422. This test was performed at various medical and clinical centers, and for all individuals, both systolic and diastolic BPs were measured using the Riester Dip­lomat Mercury Sphygmomanometer (RDMS) desktop monitor and the proposed method. The results of this review are presented in Table 1. The histogram diagram of this test with the desktop device is also shown in Figure 11. To demonstrate the correct performance of the proposed method, these results are compared with two of the most important and accepted standards in this field. The validity of the proposed method was evaluated in the Association for the Advancement of Medical Instru­mentation (AAMI) standard, based on ME (Mean Error) and SD (Standard Deviation). According to this stand­ard, if the proposed method is experimented on at least 255 separate samples, the results will be reliable. This standard also allows a maximum of 3 samples per per­son, so at least 85 people must take the test. According to this standard, the validity of a method is confirmed when the measured ME is less than 5 mmHg and the SD is less than 8 mmHg. By comparing the values ob­tained from the measurements using the proposed method and the standard requirements of AAMI, it is revealed that all cases are acceptable and the values of SD and ME are lower than the expected values and the number of people tested is higher than the num­ber of people required by the standard. In addition, the accuracy of the proposed method was also evaluated by the British Hypertension Society (BHS) standard. In this standard three different grades are reported based on the cumulative error percentage. From the samples at least 85 should be examined, which is similar to the AAMI standard. The acceptable error values according to the BHS standard [59] along with a comparison of the results obtained from the method presented un­der this standard are presented in Table 3. By compar­ing the results of BHS standard and proposed method in all grades the results have much better conditions than the standard requirements and they are true for all three SBP, DBP, and MAP cases. Therefore, the pro­posed method meets the requirements of both BHS and AAMI standards. Figure 12 presents the rates of the errors created between the measurements using the RDMS model mercury Sphygmomanometer desktop and the proposed barometer. The graph shows that the error rates in the various measurements of SBP, DBP, and MAP have the highest correlation with the actual pressure value. It should be noted that the database used in this work contains SBP and DBP pressure data measured by RDMS and Aixplorersonographic probe manufactured by Supersonic Imagine to measure blood velocity and diameter of patients in different wards of Shams hos­pitals in Urmia city. But the research data in [65] and [67] were collected from healthy people. The results of the proposed method will undoubtedly be improved if healthy people’s data are added to the database. Better convergence results can be obtained provided that the number of samples in a database increases. According to the AAMI standard, one person’s data can be used up to three times in the database, but in this study we used the data belonging to 211 persons and each per­son was sampled twice and with increasing it to three times the accuracy of the result can be amended unlike other studies, as in [12] and [66], that used fewer peo­ple with more sampling. In many studies, calibration has been used to improve results, but our proposed method does not require any calibration. Table 4 shows a comparison between the proposed method and the other methods. Figure 13 illustrates the measure­ment of vessel diameter and blood velocity using an ultrasound probe and these results were analyzed us­ing MATLAB software. At the same time, we measured BP using a Sphygmomanometer desktop device. Both methods had similar results for systolic and diastolic BP. 9 Acknowledgments Special thanks to the respected physicians of Shams Heart Hospital and Seyyed-al Shohada University Heart Hos­pital and Imam Khomeini Hospital in Urmia, including Dr. Rasoul Abbas Gholizadeh, Dr. EhsanMozafari, Dr. Mehdi MehdiZadeh, Dr. Kamal KhademVatan and Dr. Muham­madi as cardiologists, and Dr. Siahi, Dr. Khashti and Dr. Sanei, as radiologists who have assisted in this research. 10 Conclusions In this paper, a new method based on the use of ultra­sonic signals for BP measurement is presented, which is a non-invasive and continuous method and does not require calibration. In this study, the problems of previous methods such as different PTT-based meas­urements with PPG and ECG sensors or BP estimation methods that only estimate BP by measuring one quan­tity of vessels have been resolved. The proposed meth­od was measured by calculating the diameter of the artery and the velocity of the blood passing through using ultrasonic waves, and then we obtained the BP using the presented equations. Finally, the compara­tive results show that the proposed algorithm is better than previous methods for accurate measurement of BP considering the results obtained for all three param­eters of DBP, SBP, and MAP. This method fully meets the requirements for AAMI and BHS standards, which are valid in this field. 11 Conflict of Interest The authors declare that there is no conflict of interest for this paper. Also, there are no funding supports for this manuscript. 12 References 1. M. Nichols, N. Townsend, P. Scarborough, M. Rayner, Cardiovascular disease inEurope: epide­miological update, Eur. Heart J. 34 (2013) 3028–3034. https://doi.org/10.1093/eurheartj/ehu299 2. W. H. Organization, et al., World Health Statistic 2015, World HealthOrganization, 2015. 3. V. Perkovic, R. Huxley, Y. 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Principles of Measurement and transduction of biomedical variables. Academic Press, 2015. Arrived: 31. 12. 2019 Accepted: 14. 05. 2020 A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 Figure 2: Stress-strain diagram A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 Figure 6: The mechanism of the measurement of ar­tery diameter Figure 8: The block Diagram of the total BP measure­ment system A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 Figure 9: The simulation of BP due to changes in the velocity and diameter of the artery Table 1: The comparison of mean and standard deviation values measured by Sphygmomanometer desktop device using the proposed method MEAN(mmHg) SD(mmHg) Min (mmHg) Max(mmHg) Measure with RDMS device DBP 65.16 10.31 51.3 112 SBP 110.47 10.50 90.6 146 MAP 80.3 10.18 65.1 122.2 Measure by proposed method DBP 65.04 10.91 47.82 114.40 SBP 110.24 11.28 90.63 148.49 MAP 80.11 10.47 63.31 124.50 Table 2: The comparison of the results of the proposed method with the AAMI standard. MEAN(mmHg) SD (mmHg) Subject Proposed Method Results DBP 0.118 4.218 211 MAP 0.015 3.235 211 SBP -0.233 4.538 211 AAMI[58] BP . 5 . 8 85 . A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 Figure 10: The results of a person’s BP test in two different ways A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 Table 3: The comparison of the results of this paper with the BHS standard. Cumulative Error Percentage . 5 mmHg . 10 mmHg . 15 mmHg BHS Standard [59] Grade A 60% 85% 95% Grade B 50% 75% 90% Grade C 40% 65% 85% Proposed Method Results SBP 164(78.09%) 197(93.8%) 207(98.6%) DBP 162(77.2%) 202(96.2%) 209(99.5%) MAP 191(90.6%) 209(99.5%) 210(100. %) A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 Figure 11: The Histogram diagram for the database presented in this article Table 4: The comparison between the proposed method and the other methods. MAP SBP DBP Record Subject Work RMSE* SD ME RMSE* SD ME RMSE* SD ME - 5.87 3.85 - 7.68 4.77 - 5.69 3.67 7678 32 [63] - - - - 6.85 0.16 - 4.72 0.03 3000 - [61] - - - - 7.08 0.06 - 4.66 0.01 69 69 [62] - 10.44 9.3E-7 - 13.81 -1.9E-16 - 9.45 7E-15 113 113 [64] - - - 10.9 - - 5.8 - - 910 - [14] - - - - 4.2 3.8 - - - - 10 [65] - - - - - - - - - 7000 19 [12] - - - - 2.91 2.32 - 2.47 1.92 250 - [33] - - - - - - - - - 15000 - [60] - - - - - - - - - 7000 32 [66] - - - - 4.3 5.1 - 4.3 4.6 78 65 [67] - 10.35 -3.38 - 19.35 -2.98 - 8.69 -3.65 53708 572 [68] 3.22 3.235 0.015 4.53 4.538 -0.233 4.20 4.218 0.118 422 211 This * Root Mean Square Error. A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 Figure 12: The histogram of the measured error based on the proposed method compared to the RDMS desktop device Figure 13: Measurement of vessel diameter and blood velocity instantaneously using Aixplorer ultrasound, the proposed method, and RDMS A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 103 A. Abolhasani et al.; Informacije Midem, Vol. 50, No. 2(2020), 87 – 101 Copyright © 2020 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Journal of Microelectronics, Electronic Components and Materials Vol. 50, No. 2(2020), 105 – 113 https://doi.org/10.33180/InfMIDEM2020.203 CMOS series-shunt single-pole double-throw transmit/receive switch and low noise amplifier design for internet of things based radio frequency identification devices Mohammad Arif Sobhan Bhuiyan1, Zhang Fan1, Yi Jie Leem1, Lou Yee Lee1, Mamun Bin Ibne Reaz2, Md. Torikul Islam Badal3, Khairun Nisa Binti Minhad1 1Xiamen University Malaysia, Electrical and Electronics Engineering, Bandar Sunsuria, Sepang, Selangor, Malaysia 2Universiti Kebangsaan Malaysia, Centre of Advanced Electronic and Communication Engineering, Bangi, Selangor, Malaysia 3RMIT University, Electronic and Telecommunication Engineering, Melbourne, Australia Abstract: The incompatibility between current radio frequency identification (RFID) standards has led to the need for universal and wireless fidelity (Wi-Fi) compatible RFID for internet of things (IoT) applications. Such a universal RFID requires a single pole double throw (SPDT) switch and a low noise amplifier (LNA) to direct and amplify the received raw signal by the antenna. The SPDT suffers from low isolation, high insertion loss and low power handling capacity whereas the LNA suffers from smaller gain, bulky die area, lesser quality (Q) factor, limited tuning flexibility etc. because of passive inductor usage in current generation of devices. In this research, complementary metal oxide semiconductor (CMOS) based inductorless SPDT and LNA designs are proposed. The SPDT adopts a series-shunt topology along with parallel resonant circuits and resistive body floating in order to achieve improved insertion loss and isolation performance whereas the LNA design is implemented with the gyrator concept in which the frequency selective tank circuit is formed with an active inductor accompanied by the buffer circuits. The post-layout simulation results, utilizing 90 nm CMOS process of cadence virtuoso, exhibit that our SPDT design accomplishes 0.83 dB insertion loss, a 45.3 dB isolation, and a 11.3 dBm power-handling capacity whereas the LNA achieves a peak gain of 33 dB, bandwidth of 30 MHz and NF of 6.6 dB at 2.45 GHz center frequency. Both the SPDT and LNA have very compact layout which are 0.003 mm2 and 127.7 µm2, respectively. Such SPDT and LNA design will boost the widespread adaptation of Wi-Fi-compatible IoT RFID technology. Keywords: active inductor; Complementary Metal Oxide Semiconductor (CMOS); internet of things (IoT); low noise amplifier (LNA); Radio frequency identification (RFID); single pole double throw (SPDT) switch Enopolno menjalno oddajno/sprejemno CMOS uporovno stikalo in nizkošumen ojačevalnik za internet stvari identifikacijske elemente na radijski frekvenci Izvleček: Nekompatibilnost trenutnih RFID standardov je pripeljala do uporabe Wi-Fi kompatibilnega RFID za internet stvari. Takšen univerzalen RFID zahteva uporabo enopolnega menjalnega stikala (SPDT) in nizkošumnega ojačevalnika (LNA) za usmerjanje in ojačenje sprejetega surovega signala. STPD ima nizko izolativnost, visoke vrinjene izgube in nizko zmogljivost prenosa moči, LNA pa majhno ojačenje, velikost , nižji faktor kvalitete in omejeno zmogljivost nastavljanja. V tem delu sta predlagana SPDT in LNA na osnovi CMOS brez uporabe tuljave. Topologija SPDT uporablja seriske upore v povezavi z vzporednim resonančnim vezje, in plavajočim uporovnim jedrom. LNA uporablja žiratorski koncept, pri katerem je frekvenčno nastavljivo vezje izvedeno z aktivno tuljavo in spremljajočim vezjem. Rezultati kažejo, da SPDT izkazuje 0.83 dB vrinjenih izgub, 45.3 dB izolativnost, in 11.3 dBm energijsko kapaciteto, LNA pa izkazuje ojačenje 33 dB, pasovno širino 30 MHz in NF 6.6 dB pri 2.45 GHz. Oba sta izvedena v kompaktnem dizajnu in omogočata povečano uporabo Wi-Fi kompatibilne RFID tehnologije v internetu stvari. Ključne besede: aktivna tuljava; CMOS; internet stvari; RFID; enopolno menjalno stikalo * Corresponding Author’s e-mail: arifsobhan.bhuiyan@xmu.edu.my; khairunnisa.minhad@xmu.edu.my; mamun@ukm.edu.my M. A. S. Bhuiyan et al.; Informacije Midem, Vol. 50, No. 2(2020),, 105 – 113 1 Introduction The widespread usage of smartphones and smart sen­sors today has transformed the network into a con­nected web of smart devices and intelligent services which introduces the concept of IoT. RFID is currently a very reliable wireless communication standard that stores and remotely retrieves the information. RFID has a great potential to be used as IoT devices for many useful applications. The technology comprises of main­ly transponders and readers. The transponders store information about its identification along with some additional information which is, generally, transferred to the reader on request. In RFID communication, a reader receives data from transponders wirelessly in High Frequency to microwave frequency band which is decided by the nature of the application. Among all concurrent identification technologies, RFID exhibits many advantages. As a consequence, RFID technology is being deployed for many commercial and home ap­plications since few decades and is anticipated to be available for more advanced applications in near fu­ture. The continuous downscaling of CMOS technology made it easy for the radio frequency integrated circuits (RFIC) designers to fabricate fully integrated, low-pow­er and compact RFID [1-2]. Figure 1: The IoT RFID front end blocks. In the current generation of RFID communication, the reader is the most exclusive module. Regardless of the versatile opportunities, RFID is yet to overcome the ob­struction of reader specific solutions and higher cost for widespread IoT application. In order to abolish the vendor specific unwanted operational cost, a state-of-the-art RFID communication system, by adopting IEEE 802.11b protocol, has been advised in which the wireless network interface cards can be a replacement of the typ­ical RFID reader using future IPV6 concept [2-3]. There­fore, it is expected that a universal RFID communication will be available at very cheap price for widespread IoT application. Fig. 1 illustrates the standard constituents of a transceiver front-end for IoT RFID consisting of a trans­mitter frontend, a receiver frontend and a common SPDT antenna switch along with a local oscillator for proper information exchange. A power amplifier (PA), band pass and low pass filters, and an up-conversion mixer constitute the transmitter front-end. On the other hand, an LNA, a down conversion mixer, a variable gain ampli­fier (VGA) and a low pass filter (LPF) build up the receiver frontend. All the modules must be properly matched for the best possible data transmission and reception. It is obvious that SPDT antenna switch and LNA are the significant modules of every RFID transceiver as it deals with varying low power raw analog signal. An SPDT switch makes it possible for a transceiver to share a com­mon antenna for both transmission and reception pro­cess. This design of this switch is quite complicated as it need to handle both high and low power signal. The researchers have tried different combinations of circuit design strategies in order to optimize the CMOS SPDT structure and performance such as: optimized transistor, MOS biasing, stacking transistors, impedance transfor­mation, adjusting substrate impedance [4-10]. However, the trade-off among different performance indicators including isolation, insertion loss, linearity, power han­dling capacity are application specific and have scope to improve the trade-off for IoT based RFID. For typical LNA architecture, the frequency selective tank (LC) circuit forms the heart of the LNA. Inductors are always essential components of analogue front-end of typical RF devices for widespread exciting appli­cations [11-16]. Usually, amplifiers and filters, operated in RF regime, utilize on-chip inductors. But inductors in silicon substrates suffer from the parasitic losses which in turn bring down the RF device performance. Additionally, the concerns like die size, lower Q factor, limited tuning flexibility etc. make RFIC designers think alternative to the onchip inductor [17]. In order to conquer the shortcomings, MOS based ac­tive inductors are introduced. These active inductors have the privilege of proper tuning in order to com­pensate the process-voltage-temperature (PVT) vari­ation effects. Moreover, they can offer higher induct­ance value and better quality factor at only 10% of the die compared to its on-chip equivalent [17]. Conse­quently, even rapid advancements in integrated circuit technologies cannot keep the passive inductors in the preferred list of RFIC designers. The concept of the active inductor is a consequence of the gyrator-capacitor model [18-19] as shown in Fig. 2. The gyrator is a two-port circuitry which is composed of a pair of transconductors interconnected in negative feedback in order to reproduce the inductor transfer function. The transconductors designed with NMOSs results in the simple active inductor circuit [19]. Nev­ertheless, such a composition usually brings some un­wanted issues including small inductance, low Q factor, and limited tuning flexibility. In order to compensate these issues, several design ideas have been incorpo­rated as illustrated in the literature [20-27]. Thus, in this proposal, a fully integrated inductorless SPDT and low noise amplifier have been designed and validated by post-layout simulation in 90 nm CMOS technology for 2.4 GHz ISM band IoT based RFID. 2 Design Strategy 2.1 SPDT Design There are four basic SPDT design topologies which are Series, Series-Shunt, Differential and Asymmetric. Among these, the series-shunt topology is consid­ered the best based on good trade-off between per­formance and size [5]. Therefore, the proposed series-shunt SPDT, as shown in Fig. 3, consists of transistors (M1, M2) responsible for switching and transistors (M3 and M4) responsible for directing the unwanted leak­age signal to the ground. The conduction of these tran­sistors are controlled by the control signals (Vc, Vc´). While the transmitter is active, M1 conducts the sig­nal from the (TX) port to the antenna (ANT) port and M4 drains any leakage approaching the receiver (RX) port to ground in spite of impedance imposed by the combination of non-conducting transistor M2 and ac­tive inductor. This improves the isolation of the SPDT with negligibly degraded insertion loss. In addition, the problem of low power handling capacity of the SPDT has been taken care of by utilizing the resistive body floated CMOS structure. At lower frequency bands, Isolation offered by a typi­cal SPDT is acceptable because of the high impedance of the non-conducting transistors which begins to low down as the signal frequency increases as a result of the leakage through the stray capacitances of the non-conducting transistor. But a selective inductance across this stray capacitance can impose a very high impend­ence by forming resonant circuit for certain frequency band. This design makes the SPDT offer frequency selective high isolation performance. With the aim of forming such a frequency selective circuit for SPDT, an on-chip inductor was proposed by Feng et al. (2010) [28]. As the lower Q value and larger chip size are the major concerns of on-chip inductors, an optimized ac­tive inductor, shown in Fig. 4 [27], has been employed in this SPDT design so that the optimal performance trade-off can be achieved. 2.2 LNA Design The proposed schematic of the LNA comprises of three major parts which are: input and output buffer and an active inductor based frequency selective tank circuit. Here, the active inductor utilizes the feature of very low admittance at the resonant-frequency to be used as a frequency selective circuit. Fig. 5 illustrates the schematic of the active inductor circuit used for the proposed LNA. In this active inductor, M1 and M2 act as a non-inverting transconductor (gM1) with the input voltage at V1 and output current at V3. M3 is an invert­ing transconductor (–gM2) with the input voltage at V3 and output current at V1. Hence, -gM2 and gM1 form the gyrator which in turn form an inductor at node 1 along with the parasitic capacitor C1 at node 3. This active in­ductor circuit can be represented as an equivalent RLC circuit as well. The values of the equivalent inductance, resistance and capacitance are evaluated by: (1) (2) (3) (4) Figure 5: The active inductor and its equivalent circuit proposed for LNA. The value of the resonant frequency is, therefore: (5) In the case of passive inductor, the prime noise contri­bution comes from the internal damping resistance. But in the case of CMOS based emulated active induc­tor, the main impact is because of the thermal noise modelling in CMOS channel. For the noise analysis of the active inductor, let us consider that it is terminated with a resistance, Rp, the value of which is greater than (1/gm1) and also neglecting the flicker noise of the transistors used, the spot noise figure for Gm cell can be approximately expressed as: (6) Where RS is the source impedance and . is some constant that depends on the thermal noise behaviour of a given fabrication process. The second term of the NF represents the noise added by M2 and a high ensuring matching conditions can make this term negligible. The third part characterizes the noise hosted by M1 and its transcon­ductance need to be kept small to contribute a lower total noise. The fourth term characterizes the noise added by the load. For a high gm2 value, this term becomes nearly identical to RS/RP. Hence, increasing the load RP has the ef­fect of reduced noise contributed by the load. The architecture of the inductorless nano-CMOS LNA including its biasing and tuning arrangements is shown in Fig. 6. The signal, extracted from the anten­na, is fed to the input buffer and is extracted from the output buffer. The active inductor provides all the am­plifications and noise minimization at 2.4 GHz band. In this LNA, the voltage biasing VIF, Vis/2, Vis, Vq, Vcm contrib­ute to the tuning of centre frequency, noise figure and frequency response. From the small signal equivalent circuit of the LNA, it is obvious that the maximization of the transconductances of M2, M3 and M4 improves the noise performance. But this corresponds to the in­crease in the parasitic capacitances which lower down the bandwidth and gain. Moreover, the transconduct­ances of M5 and M6 have very small effect on perfor­mance as those serve as current followers. So, in order to set the best possible tradeoff, these transconduct­ances have been tuned by trial and error basis. 3 Results and Discussions The inductorless SPDT and LNA are designed and simu­lated by 90 nm CMOS process in Analog Design Envi­ronment (ADE) of cadence virtuoso. In this study, the performance of the SPDT and LNA is assessed by the post-layout simulation results at standard temperature of 300° K. 3.1 SPDT Performance Analysis Fig. 7 shows the insertion loss and the isolation of the SPDT as a function of the input signal frequency. At higher frequencies, the insertion loss is increased be­cause of the effect of parasitic junction capacitances of the MOSs. The isolation of the switch is a maximum at the 2.4GHz set by the parallel resonant circuit, As the operating frequency shifts in both ways, the leakage causes the degradation of the isolation. The insertion loss and isolation of the SPDT at resonance are 0.83dB and 45.3dB respectively, Figure 8: The P1dB and the IP3 of the SPDT. Fig. 8 shows the power handling capacity and linear­ity of the SPDT. The P1dB point of this spdt is 11.3 dBm whereas the ip3 point is 19.60 dBm. Above this input power, the MOS body diodes experience break down which allow leakage of the signal to the ground. In the Monte-Carlo analysis for 50 samples, as illustrated in Fig. 9, the insertion loss was found between 0.88 dB and 0.82 dB, while the isolation was between 44.0 dB and 45.5 dB. The performance parameters of the SPDT were less dispersive and steady. The performance parameters of this SPDT has been listed in Table 1 for comparing to the other recently reported switches. The diode connected transistor pair and suppressing the channel forming signal helped Chen and Lin (2014) to elevate IIP3 and input P1dB of the SPDT to 22.4dBm P1dB and 33 dBm IIP3, respec­tively [6]. But the isolation and die area were still not satisfactory. Proper impedance matching implemen­tation by Tan et al. (2012) to design a high-power dif­ferential switch resulted in lower isolation compared to other designs [7]. Liu et al (2012) with his asymmetrical transistor based design succeeded to achieve lower IL and high P1dB but the core layout area was quite big [8]. Body floated transistors with proper impedance matching resulted in 40 dB isolation switch design by Nga et al. (2016) but at the cost of bulky chip and high­er IL [9]. The asymmetric SPDT utilizing ac-floating and dc-bias, designed by Chen and Gan (2017), achieved moderate P1dB but other parameters including chip area were quite undesired [10]. However, compared to these design, our SPDT realized the highest isola­tion and lowest die area due to the implementation of frequency dependent impedance imposed by parallel resonant circuit at 2.4 GHz band. All other parameters are reasonable and meets the 2.4 GHz prerequisites implying that our design demonstrates a good perfor­mance tradeoff for 2.4 GHz IoT applications. Table 1: Summary of the SPDT performance comparison Reference CMOS Technology IL (dB) ISO (dB) P1dB (dBm) Chip Size (mm2) [8] (2012) 0.18 µm 0.62 33 29.2 0.125 [7] (2012) 32 nm 1.3 32 34 - [6] (2014) 0.18 µm 0.72 24.5 22.4 0.037 [9] (2016) 65 nm 0.96 40 - 0.143 [10] (2017) 0.18 µm 1.16 20.8 20.5 0.26 This work 90 nm 0.83 45.3 11.3 0.03 3.2 LNA Performance Analysis From the AC analysis, as shown in Fig. 10, it is observed that the proposed LNA circuit has a high gain of 33 dB with 30 MHz pass-band at the center resonant frequen­cy of 2.45 GHz. Besides, the noise analysis of the LNA ex­hibits a noise figure of only 6.6 dB at its center frequen­cy. The peak reverse isolation of the LNA is -33.1 dB at 2.4 GHz as shown in Fig. 11. The total power dissipation for this amplification operation, including the biasing and buffer circuits, equals the only 1.08 mW from a 1.5 V power supply which is very competitive compared to other contemporary researches. Moreover, the power handling capacity and third order linearity have been evaluated as given in Fig. 12 which are also very com­petitive. For statistical analysis, Monte-Carlo analysis has been conducted and it shows a stable performance of this LNA where the gain varied between 32.8 dB to 33.3 dB and NF varied between 6.4 dB to 6.8 dB for 50 samples as evident from Fig. 13. Figure 10: The AC and NF analysis of the LNA. Figure 11: The reverse isolation analysis of the pro­posed LNA circuit. Table 2 illustrates the performance comparison of the low noise amplifier with other recent researches. It is clear from the comparison that the inductorless LNA has the smallest die area which is only 127.704 µm2. This is mainly due to the adaptation of small size transistors as well as avoidance of bulky passive constituents like capacitors, resistors etc. Moreover, the highest gain of 33 dB will facili­tate the receiver frontend to amplify the weak intercept­ed signal by the antenna because of proper selection of transconductances. However, this work suffers from rela­tively higher noise figure of 6.6 dB at 2.4 Ghz frequency due to the simple common gate topology used for the amplification and also for using smaller sized transistors. Other parameters, including power dissipation and band­width, are also very competitive and support the require­ments of 2.4 GHz RFID receiver specifications. Such a fully integrated inductorless LNA will be a handy block for low power compact readerless RFID for IoT applications oper­ated at 2.4 GHz ISM band. 4 Conclusions The widespread utilization of IoT, nowadays, urges the researchers to fabricate low power and portable de­vices. The overall performance of the IoT devices de­pends on its frontend performance; specially on SPDT and LNA. In this research, the proposed inductorless nano-CMOS SPDT and LNA for 2.4 GHz RFID for IoT application were designed and assessed through the post-layout simulation by using Cadence. The results confirm that the design presented experiences a bet­ter performance tradeoff along with smaller power consumption and very compact die area compared to other concurrent researches after meeting all the re­quirements for 2.4 GHz RF communication. Such high-performance SPDT and LNA will certainly improve the performance of Wi-Fi compatible low power compact RFID as IoT devices. 5 Acknowledgments This research was funded by the Xiamen University Ma­laysia, under grant no. XMUMRF/2018-C2/IECE/0002 and by the Universiti Kebangsaan Malaysia under grant no. DIP-2020-004. 6 Conflict of Interest The authors declare no conflict of interest. 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Rezaei, “A new active inductor and its application to wide tuning range LC oscillator,” International Journal of Soft Computing and Engineering, 2011, Vol. 1, No. 5, pp. 111-114. URL: http://www.ijsce.org/wp-content/uploads/papers/v1i5/E0162081511.pdf 28. Y. X. Feng, L. Kang, Y. Hao and X. Y. Bin, “A high isola­tion and low insertion loss T/R switch design,” 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010, pp. 749-751. https://doi.org/10.1109/ICSICT.2010.5667403 Arrived: 29. 01. 2020 Accepted: 26. 05. 2020 Figure 2: The concept of a typical gyrator. M. A. S. Bhuiyan et al.; Informacije Midem, Vol. 50, No. 2(2020),, 105 – 113 Figure 4: Active inductor for parallel resonant cir­cuit: M1-M6 (0.35/0.13), M7, M8 (20/0.13), M9-M12 (0.35/0.13). Figure 3: The design concept of SPDT: M1, M2 (100/0.13), M3, M4 (40/0.0.13), Rb, Rg = 10 K.. The di­mension of the SPDT die is only 0.003 mm2. M. A. S. Bhuiyan et al.; Informacije Midem, Vol. 50, No. 2(2020),, 105 – 113 Figure 6: LNA schematic and layout design: M1, M3, M4 (10/0.13), M2 (30/0.13), M5, M6 (3/0.13), M7 - M10 (0.12/0.36), M11 (1/0.36), VIF, Vis/2, Vis = 0.85 V, Vq = 0.7 V, Vcm = 0.7 V, VDD = 1.5 V. The die area of the LNA layout is only 127.704 µm2. M. A. S. Bhuiyan et al.; Informacije Midem, Vol. 50, No. 2(2020),, 105 – 113 Figure 7: The insertion loss and the isolation of the SPDT. M. A. S. Bhuiyan et al.; Informacije Midem, Vol. 50, No. 2(2020),, 105 – 113 Figure 9: The Monte-Carlo analysis of insertion loss and isolation of the SPDT. M. A. S. Bhuiyan et al.; Informacije Midem, Vol. 50, No. 2(2020),, 105 – 113 Figure 12: The linearity analysis of the proposed LNA circuit. Figure 13: The Monte-Carlo analysis of gain and noise figure of the LNA circuit. Table 2: Summary of the LNA performance comparison Specifications [22] (2016) [20] (2017) [24] (2017) [21] (2018) [25] (2019) This work Technology 130 nm CMOS 180 nm CMOS 180 nm CMOS 130 nm CMOS 65 nm CMOS 90 nm CMOS fc (GHz) 2.45 2.5 3-5 2.4 0.5–7 2.45 Gain (dB) 12.3 16.9 12.7 20.7 16.8 33 Power dissipation (mW) 0.4 9.5 8.4 24.9 11.3 1.08 Supply voltage(V) 1.0 1.8 1.8 1.2 1.2 1.5 BW (MHz) 0.1-2.2 GHz 0.1-1.45 GHz 3.43 GHz 550 6.5 GHz 30 NF (dB) 4.9-6 2.5 3.2 2.1 2.87-3.77 6.6 Active Die area (mm2) 0.0052 0.075 - 0.84 0.044 0.000127 M. A. S. Bhuiyan et al.; Informacije Midem, Vol. 50, No. 2(2020),, 105 – 113 M. A. S. Bhuiyan et al.; Informacije Midem, Vol. 50, No. 2(2020),, 105 – 113 Copyright © 2020 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Journal of Microelectronics, Electronic Components and Materials Vol. 50, No. 2(2020), 115 – 123 https://doi.org/10.33180/InfMIDEM2020.204 CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers Ali Rahnamaei Islamic Azad University, Ardabil Branch, Department of Electrical Engineering, Ardabil, Iran Abstract: In this article, the design procedure for high-speed 5-2 and 6-2 compressors, along with their analysis, has been discussed. With the help of the combinational logic consisting of the 4-2 compressor and 3-2 counter blocks, a high-performance structure for 6-2 compressor has been achieved, which shows significant speed improvement over previous architectures. The optimization has been carried out by reducing the carry rippling issue between the adjacent compressor structures. Also, the help of some modifications, the proposed 6-2 compressor will turn into a 5-2 compressor where the latency of the critical path has considerably been reduced, illustrating the superiority of designed circuits. The corresponding latencies of the proposed 5-2 and 6-2 structures are equal to 3.5 and 4 XOR logic gates, respectively, demonstrating speed boosting of 15% and 20% compared to the best-reported architectures. In addition, the power consumption and the transistor count of proposed circuits are have remained at a moderate level. Therefore, by considering the Power-Delay Product (PDP), our work will be a good choice for high-speed parallel multiplier design. Post-layout simulation results based on TSMC 90nm standard CMOS process and 0.9V power supply have been presented to confirm the correct functionality of the implemented compressors. These results have also been used as a fair comparison infrastructure between the proposed works and redesignated architectures of the previously reported schemes. Keywords: 6-2 compressor; 5-2 compressor; multiplier; CMOS; high-speed Visoko učinkovit CMOS 5-2 in 6-2 kodirnik za vzporedne množilnike velikih hitrosti Izvleček: V članku je predstavljen postopek načrtovanja in analiza hitrega 5-2 in 6-2 kodirnika. S pomočjo kombinatorne logike 4-2 kodirnika in 3-2 števca je bil izveden visoko učinkovit 6-2 kodirnik. Z dodatnimi poenostavitvami je bil načrtan 5-2 kodirnik pri katerem so bile močno zmanjšane latence kritičnih poti. Latence predlaganih 5-2 in 6-2 kodirnikov so enake 3.5 oziroma 4 XOR logičnim vratom, pri čemer je bila hitrost izboljšana za 15% oziroma 20%. Pri upoštevanju porabe se je izkazalo, da je predlagan kodirnik dober za hitre paralelne množilnike. Simulacije v standardnem CMOS okolju so potrdile rezultate raziskav. Rezultati pa so uporabljeni tudi za verno primerjavo nove arhitekture s prejšnjimi. Ključne besede: 6-2 kodirniki; 5-2 kodirnik; množilnik; CMOS; visoka hitrost * Corresponding Author’s e-mail: a_rahnamaei@iauardabil.ac.ir 1 Introduction In 1981 a new architecture was introduced by Wein­berger, which was based on the cascaded carry-save adders [1]. Getting popular as 4-2 compressor, the structure was composed of two Full Adders (FAs). One of the outputs of such structure (denoted as Cout) is hor­izontally sent to the next sitting compressor block with a higher binary bit position value [2]. Figure 1 illustrates the explained structure in which X1 – X4 constitute the main input bits while the fifth input comes from the previous compressor with a lower binary bit value [3]. Along with the development of VLSI circuits, which provided the possibility for hardware-level realization of the parallel multipliers [4], the applications of such systems were greatly increased in Digital Signal Proces­sors (DSPs) and microprocessors. A thorough literature review depicts that the parallel multiplier lies in the critical path for delay measurement of its former sys­tem [5]. Also, the most significant part of the propa­gation latency in a parallel multiplier belongs to the Partial Product Reduction Tree (PPRT) consisting of the compressors [6]. As a consequence, delay reduction for PPRT in state-of-the-art schemes is one of the main concerns for the circuit designers. One of the effective solutions for this purpose that im­pressively applies to the large input bit multiplications is the utilization of high compression rate compressors such as 5-2, 6-2, and 7-2 blocks [7]. Figure 1: General architecture of the 4-2 compressor consisting of two cascaded FAs. Following the general concept of the 4-2 compressor, the cascading of three FAs will result in the convention­al architecture of 5-2 compressor [7]. At least a latency of 5 XOR logic gates (in gate-level) is expected for this realization where with the help of some optimizations reported in [8], the delay has been reduced to 4 XOR gates. Although there are many structures reported in the literature [8, 9, 10, 11, 12, 13, 14], none of them have been able to reach latencies less than 4 XOR gates. This partially comes down to the lack of deep consideration and investigation of the original truth table for the 5-2 compressor block. The structure of a 6-2 compressor consists of three horizontal paths which transfer their corresponding bits to the adjacent block. Although several works have been introduced over recent years for hardware imple­mentation of this structure [10, 15, 16, 17, 18, 19], none of them could achieve latencies less than 5 XOR logic gates. A comprehensive study over n-2 compressor design depicts that there are some neutral states in the con­ventional truth table. These states can be helpful in the simplification of the Karnaugh Map (KM) for the corre­sponding compressor. The main objective is to obtain better speed performance while the power consump­tion would not be degraded. This concept is the basis of the idea in this article to design a high-performance 6-2 compressor. Furthermore, after successfully apply­ing the mentioned idea to the 6-2 structure and by us­ing some simplifications, a novel 5-2 compressor will be presented later in this paper. This scheme also out­performs previous works when the Power-Delay Prod­uct (PDP) is concerned. One important issue that needs to be considered in the design of the proposed structures is the reduction of carry rippling problem between the adjacent compres­sor blocks. For instance, in the horizontally cascaded architectures of Figure 2, the conventional design prin­ciples will lead to the rippling of input signals to three compressor blocks. The same concept also holds for 6-2 compressor. However, in this paper, careful design con­siderations have utilized to reduce the carry rippling problem by one level. The effect of such decrement is the key factor for speed enhancement. The organization of the paper is as follows. Section 2 explains the analysis and design of the proposed high-performance 6-2 compressor. In section 3, the novel 5-2 compressor architecture has been discussed. Post-Layout simulation results, along with the comparison tables, have been presented in section 4. Finally, sec­tion 5 contains the conclusions. 2 The 6-2 compressor The conventional structure of a 6-2 compressor com­prises two FAs along with one 4-2 compressor, as shown in Figure 3. Based on the defined architecture, a 6-2 compressor is composed of nine inputs and five outputs. The following expression describes the rela­tionship between the input and output bits [10]: (1) As Eq. (1) shows, all of the input bits along with output have the same weighting while the other four outputs will assume the next higher binary bit value. By con­sidering the proposed architectures for 4-2 compressor reported in [2] and [3], which exhibit 2 XOR logic gate-level delay from inputs to the outputs, the latency of less than 5 XOR logic gates is expected for implementa­tion of the 6-2 compressor in Figure 3. The design introduced in [10], directly uses the con­ventional structure for hardware realization of a 6-2 compressor. Because the 4-2 compressor of [7] was em­ployed, the latency of the circuit was equal to 5 XOR gates. If the compressor of [3] is going to be used in that structure, again, a slight amount of gate-level re­duction can be achieved for the critical path delay. In [15] and [19], gate-level simplification has been utilized for the design of 6-2 compressor. However, the critical path delay which belongs to output is still 5 XOR gates. The architectures used in [17] and [18] have modified the conventional structure by using two 4-2 compressors and one adder. But they were not able to reduce the latency, and due to the higher transistor count, neither active area nor power consumption has been improved. By considering the aforementioned implementations and their drawbacks, in this paper, a new architecture has been proposed for the 6-2 compressor. In this re­alization, the gate-level delay has been reduced con­siderably. Figure 3: Conventional structure of 6-2 compressor. The proposed circuit is shown in Figure 4, in which the pins labeled I1, I2, I3, I4, I5, and I6, along with Cin1, Cin2, and Cin3, constitute the input bits. Also, Cout1, Cout2, and Cout3, along with Carry6 - 2 and Sum6 - 2 form the output bits. The operating principle of the proposed structure can be seen as a 4-2 compressor that is fed by I1, I2, I3, I4, and I5 inputs. These inputs are then utilized to generate Cout1 and Cout2 outputs of the 6-2 compressor. If at least two of five inputs have high-level logic value, then one of Cout1 and Cout2 outputs will rise to high-level voltage. If at least four input bits have the logic value of one, then both of the outputs will get the high logic value as well. By considering the conventional architecture of the 4-2 compressor described in [7], the Boolean expressions pertaining to the functions of Cout1 and Cout2 will be as follows: (2) (3) The odd number of ones at the input pins will result in the corresponding sum output signal (denoted as Sum4 - 2) to get the high logic value. For the comparison of three horizontal inputs (repre­sented as Cin1, Cin2, and I6), an FA has been utilized where the corresponding carry output of this stage will estab­lish the Cout3 output of the proposed 6-2 compressor. In order to increase the speed performance, the three gates model of FA from [12] has been employed to im­plement such block. This output abides by the follow­ing relation: (4) The combination of two sum outputs coming from 4-2 compressor and the FA block will construct the Sum output of the 6-2 compressor, which is noted as Sum6 - 2. Finally, for Carry output will have: (5) The calculated Boolean expressions clearly demon­strate that the carry rippling issue has been reduced by one, which is a notable advantage of the proposed 6-2 compressor. To calculate the gate-level latency, we refer to the cal­culations provided in [7]. As shown in Figure 5(a) and discussed in [7], the latency of two output XOR/XNOR gate is considered .. As a consequence, the propaga­tion delay of the single output XOR gate in Figure 5(b) will be equal to 0.75 ., considering the fact that the Transmission Gate (TG) transistors are channel-ready transistors. For a channel-ready transistor, the corre­sponding latency is half of a transistor where the bias signal of the gate didn’t put the transistor in ON state. Figure 5: The XOR gates used in the compressor cir­cuits (a) Two output XOR-XNOR gate proposed in [7] (b) Single output XOR gate introduced in [2]. The same hypothesis also holds for the Multiplexer (MUX) gate of Figure 6, which is composed of two paralleled TGs. In the normal mode, the normalized la­tency of this gate will be equal to 0.5 ., while for the channel-ready case, the corresponding delay will be reduced to 0.25 .. Furthermore, the three input OR gate can be treated almost the same as two output XOR-XNOR gate con­cerning the propagation latency. Also, a single pass transistor-like device will have a delay value of 0.25 . of the unit gate [2]. The NAND/NOR gates will also be treated the same as the MUX circuit, which is operating in the normal mode. Therefore, according to the circuit structure in Figure 4, the critical path of the proposed 6-2 compressor will belong to Carry output. The start point for this path is at Cout2 output coming from the adjacent compressor, which then enters the FA block inside the proposed present 6-2 compressor. Such a gate-level delay (Td) will abide by: (6) in which tCout2 defines the corresponding delay for the generation of Cout2 from the previous level compressor block. Moreover, tFA illustrates the time interval for the generation of output in Figure 4. The terms tAND and t3OR represent the latencies for AND, and three input OR gates, respectively. By considering the optimizations pertaining to the conversion of AND to NOR and OR to NAND, tAND and t3OR can be replaced by tNOR and t3NAND to reduce the gate-level latency. Because the 4-2 compressor block reported in [3] has been utilized to achieve higher speed performance, tCount2 will be equal to .. On the other hand, in an FA block, two single output XOR gates are needed to pro­duce Sum. Therefore, tFA will be equal to 1.5 .. Substitu­tion of the obtained values in Eq. (6), will result in: (7) As Eq. (7) expresses, the gate-level delay of the pro­posed compressor is almost equal to 4 XOR logic gates, which is a substantial improvement for the delay per­formance of the proposed 6-2 compressor compared with the previously reported works. 3 The 5-2 compressor By applying some modifications, the designed 6-2 com­pressor can be used as a high-speed 5-2 compressor. In order to achieve this configuration, Sum. Therefore, tFA will be equal to 1.5 .. output should be connected to the ground. The proposed architecture has been illus­trated in Figure 7. Because one of the inputs to the FA cell has been eliminated, therefore, this block can be replaced with a Half Adder (HA), which is denoted in Figure 7 as H-Adder. Equations (8), (9), (10), and (11) present the cor­responding expressions for the four output signals of this system: (8) (9) (10) (11) With the help of the same definitions for propagation latency, it can easily be concluded that the delay of the critical path for the proposed 5-2 compressor will be­long to the Carry signal. By starting from the Cout1 node of the adjacent compressor, the path will end in the HA block. This can be expressed in terms of gate-level de­lay (T’d), by means of the following expression: (12) In this equation, tCount1 represents the delay associated with the generation of Cout1 from the previous compres­sor block, which is equal to the summation of two dif­ferent terms. Again, by considering the 4-2 compressor architecture of [3], the first term will belong to a two output XOR-XNOR gate. The second term will pertain to the latency of two cascaded MUX gates with channel-ready transis­tors. As a consequence, tCout1 will be equal to 1.5.. For a HA block, the propagation latency denoted by tHA will be equal to that of a single output XOR gate (0.75.). But for the AND gate, the combination of a NAND and inverter gate is needed, which makes the correspond­ing delay of this gate (tAND) be equal to .. Finally, t’MUX represents the propagation latency of a channel-ready MUX, which is equal to 0.25.. The sum of these laten­cies will result in the following value: (13) As Eq. (13) expresses, the gate-level delay of the de­signed compressor is almost 3.5 XOR logic gates, which is a notable improvement for the speed performance of this block. 4 Simulation results In order to perform a thorough analysis and compari­son for the simulation results of the works, which are discussed in this paper, at the first step, the layouts of the designed circuits have been drawn, and their para­sitics have been extracted. After that, some of the re­cently reported structures in the literature for 6-2 and 5-2 compressors with remarkable results and improve­ments have been selected and redesigned here using the similar gates employed for this work. Figure 8 illustrates the layout schemes for the proposed architectures. In Figure 8(a), the layout of the 6-2 com­pressor has been shown, which occupies an active area of 55×35mm2. For the implemented 5-2 compres­sor, as demonstrated in Figure 8(b), an active area of 35×30mm2 is needed. In order to resemble the practical situation in the sim­ulation setup, each of the inputs is driven by a buffer circuit. Every output has been passed through a buffer block as well to be able to drive the next stage without loading effect on the compressor circuit. In addition, the compressor blocks are used in a parallel fashion to cover the critical path, as shown in Figure 9. It must be mentioned that the configuration of Figure 9 is used for the case in which the propagation delay between two adjacent compressor structures finishes in the second compressor block. If the propagation de­lay is rippled for three horizontally cascaded compres­sors, then three compressors must be considered in the simulation environment. This fact has been presumed for the architectures reported in [9], [10], [12], [13], [14], [18] and [19] (similar as Figure 2). (a) (b) Figure 8: Layouts of the proposed architectures (a) 6-2 compressor (b) 5-2 compressor. Meanwhile, in the simulation environment, the propa­gation delay has been measured from the point that the earliest input transition reaches 50% of Vdd, to the point where the latest output signal rises to 50% of the Vdd voltage. [7]. The worst-case, which demonstrates the longest latency from inputs to the outputs (con­sidering the signal propagation between the adjacent blocks), shows the delay of the critical path. 4.1 The 6-2 compressor Post-layout simulations using HSPICE for TSMC stand­ard 90nm CMOS technology along with 0.9V power supply have been carried out to measure the delay, and power consumption of the proposed 6-2 compressor and the works reported in [10], [18] and [19] which are redesigned and optimized here to make a fair compari­son. Figure 10 illustrates the results for the correct func­tionality of the proposed architecture along with delay measurements. The results demonstrate the delay of 314ps for the critical path of the proposed circuit. Figure 10: Simulation results for correct functionality and delay measurement of the proposed 6-2 compres­sor. The result of the comparison for the power-delay meas­urement of the designed structure and the selected works is shown in Figure 11. The results indicate that the lowest PDP value belongs to the proposed archi­tecture. The design reported in [19], which has a delay value of about 481ps will need 53% more time to pro­duce the output compared to the designed scheme. Figure 11: Power-Delay comparison of the proposed work and redesigned 6-2 compressors based on the TSMC 90nm CMOS process. Also, the measurement results for the power dissipa­tion at the operating frequency of 100MHz demon­strate that the proposed compressor circuit has the lowest value of power consumption, while the design reported in [10] which shows the lowest power con­sumption among the competitors, consumes 6% more power compared to the proposed circuit. Table 1 illustrates the comparison between the rede­signed 6-2 configurations based on their circuitry and simulation results obtained by the author. Table 1: Comparison of Proposed 6-2 Compressor and Other Structures. Work Proposed [10] [18] [19] Technology (nm) 90 90 90 90 Transistor Count 125 140 152 142 Gate Level Delay (XOR) 4 gates 5 gates 6 gates 5 gates Power (µW) @100MHz 269 285 345 289 Delay(ps) 314 487 505 481 PDP (pJ) 0.084 0.139 0.174 0.139 4.2 The 5-2 compressor As described for 6-2 compressor, post-layout simulations using HSPICE for TSMC standard 90nm CMOS technol­ogy along with 0.9V power supply have been carried out to measure the delay and power consumption of the proposed 5-2 compressor and redesigned architectures reported in [8], [9], [10], [12], [13], and [14]. Figure 12 illustrates the results for the correct function­ality of the proposed structure along with the delay measurement, which depicts the value of 183ps for the delay of the critical path. Figure 12: Simulation results for correct functionality and delay measurement of the proposed 5-2 compres­sor. The result of the comparison for the power-delay measurement of the proposed design and the rede­signed works is shown in Figure 13. The results indicate that the lowest delay value belongs to the designed scheme. Also, the measurement result and compari­son for power dissipation at the operating frequency of 100MHz demonstrates that the power consumption of the proposed design is about 97µW, which is not the lowest among the presented works. The designs reported in [13] and [14] have the lowest power con­sumption. However, the lowest PDP belongs to the pro­posed scheme. Figure 13: Power-Delay comparison of the proposed work and redesigned 5-2 compressors based on the TSMC 90nm CMOS process. Finally, Table 2 summarizes the comparison between the redesigned 5-2 structures based on their circuitry and simulation results obtained by the author. 5 Conclusions In this article, a novel 6-2 compressor was introduced, which outperforms the previous designs from the view­point of the propagation delay for the critical path. The proposed architecture is based on the combinational circuit consisting of a 4-2 compressor and FA, which has resulted in a 20% speed improvement in comparison with the other works reported in this criterion. The de­sign approach for the proposed compressor was able to reduce the number of transistors used in the circuit. This is another advantage of the presented circuit, which will occupy a small area on the chip while the carry rippling problem has been reduced by one level. With some extra modifications, the proposed 6-2 com­pressor can be used as a 5-2 compressor. In this case, the latency of the critical path has also been reduced significantly. The gate-level delay of the proposed 5-2 and 6-2 compressors is equal to 3.5 and 4 XOR logic gates, respectively, which demonstrate a 15% speed enhancement for the proposed 5-2 architecture com­pared with the best-reported works. The aforemen­tioned advantages illustrate the capability of the im­plemented circuits for utilization in high compression multiplication systems. Simulation results of the proposed circuits using HSPICE for TSMC 90nm standard CMOS technology and 0.9V power supply represent the delay value of 314ps and 183ps for the proposed 6-2 and 5-2 compressors, respectively. The power dissipation is also 269µW and 97µW for these structures at the operating frequency of 100MHz. 6 Conflict of Interest The author declares no conflict of interest. The author declares that there is no funding support for this work. 7 References 1. A. Weinberger, “4:2 Carry-Save Adder Module,” IBM Technical Disclosure Bull., vol. 23, 1981. 2. A. Fathi, S. Azizian, Kh. Hadidi, A. Khoei, and A. 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Costa, “Using adder compressors for power-efficient 2-D approximate Discrete Tch­ebichef Transform,” 14th IEEE International New Circuits and Systems Conference, 2016, https://doi.org/10.1109/NEWCAS.2016.7604835. 19. W. Shi, and C.-S. Choy, “A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryption,” 29th IEEE International System-on-Chip Conference (SOCC), 2016, https://doi.org/10.1109/SOCC.2016.7905451. Arrived: 10. 11. 2019 Accepted: 05 .06. 2020 A. Rahnamaei; Informacije Midem, Vol. 50, No. 2(2020),, 115 – 123 A. Rahnamaei; Informacije Midem, Vol. 50, No. 2(2020),, 115 – 123 Figure 2: The carry rippling problem between three cascaded 5-2 compressor blocks. Figure 4: Proposed 6-2 compressor. A. Rahnamaei; Informacije Midem, Vol. 50, No. 2(2020),, 115 – 123 Figure 6: Utilized MUX gate and its circuitry. A. Rahnamaei; Informacije Midem, Vol. 50, No. 2(2020),, 115 – 123 Figure 7: Proposed 5-2 compressor. A. Rahnamaei; Informacije Midem, Vol. 50, No. 2(2020),, 115 – 123 Figure 9: Simulation setup for (a) 6-2 compressor (b) 5-2 compressor considering the propagation delay for two stages. A. Rahnamaei; Informacije Midem, Vol. 50, No. 2(2020),, 115 – 123 A. Rahnamaei; Informacije Midem, Vol. 50, No. 2(2020),, 115 – 123 Table 2: Comparison of Proposed 5-2 Compressor and Other Structures. Work Proposed [8] [9] [10] [12] [13] [14] Technology (nm) 90 90 90 90 90 90 90 Transistor Count 97 112 112 135 90 82 58 Gate Level Delay (XOR) 3.5 gates 4 gates 5 gates 5.5 gates 6 gates 6 gates 6 gates Power (µW) @100MHz 97 107 101 236 94 81 61 Delay(ps) 183 247 284 321 359 368 375 PDP (pJ) 0.0177 0.0286 0.0287 0.0757 0.0337 0.0298 0.0229 A. Rahnamaei; Informacije Midem, Vol. 50, No. 2(2020),, 115 – 123 Copyright © 2020 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Journal of Microelectronics, Electronic Components and Materials Vol. 50, No. 2(2020), 125 – 136 https://doi.org/10.33180/InfMIDEM2020.205 Single VDGA-Based Dual-Mode Multifunction Biquadratic Filter and Quadrature Sinusoidal Oscillator Worapong Tangsrirat1, Tattaya Pukkalanun1, Orapin Channumsin2* 1Faculty of Engineering, King Mongkut’s Institute of Technology Ladkrabang (KMITL), Bangkok 10520, Thailand 2Faculty of Engineering, Rajamangala University of Technology Isan, Khonkaen Campus, Khonkaen 4000, Thailand Abstract: This article relates to the realization of voltage-mode and/or current-mode multifunction biquadratic filter and quadrature oscillator circuits each using one voltage differencing gain amplifier (VDGA), two resistors and two grounded capacitors. The proposed dual-mode filter having one output and three inputs can provide the three standard biquadratic transfer functions with both voltage and current output filter responses simultaneously. It also has the independent tuning of the angular resonance frequency and the quality factor. With a slight modification of the proposed filter, a new dual-mode quadrature sinusoidal oscillator can be obtained. The proposed quadrature oscillator provides orthogonal resistive/electronic control of both oscillation condition and oscillation frequency. Non-ideal and parasitic conditions are also examined and their effects on the circuit performance are discussed. To confirm the theory, several computer simulation results with PSPICE program are given. Keywords: Voltage Differencing Gain Amplifier (VDGA); biquadratic filter; quadrature oscillator; dual-mode operation; voltage-mode circuit; current-mode circuit Enojen multifunkcijski bi-kvadratičen filter na osnovi VDGA in sinusni kvadrantni oscilator Izvleček: Članek opisuje multifunkcijski bi-kvadratičen filter v napetostnem in/ali tokovnem načinu ter kvadrantni oscilator. Oba sta zasnovana na osnovi VDGA ojačevalnik, dveh uporov in dveh ozemljenih kondenzatorjev. Predlagan filter ima en izhod in tri vhode, kar omogoča uporabo treh standardnih bikvadratičnih funkcij sočasno na napetostnem in tokovnem izhodu. Omogoča tudi neodvisno nastavljanje kotne resonančne frekvence in faktorja kvalitete. Z majhnimi spremembami lahko dobimo sinusni oscilator. Raziskani so tudi neidealni in parazitni pogoji in njihov vpliv na učinkovitost vezja. Teorija je bila preverjena v PSPICE simulacijskem okolju. Ključne besede: (VDGA); bikvadratičen filter; kvadrantni oscillator; napetostni način; tokovni način * Corresponding Author’s e-mail: o.channumsin.rmuti@gmail.com 1 Introduction Multifunction filters, which can simultaneously realize low-pass (LP), band-pass (BP) and high-pass (HP) filter responses with the same configuration, are fundamen­tal circuit elements widely used in the design of several electronic systems, such as phase-locked loop frequen­cy modulators, crossover networks, stereo demodula­tors, etc.[1]-[2]. For decades, multifunction biquadratic filters have been designed by using numerous modern electronic active elements, such as second-generation current conveyor (CCII) [1], [5]-[9], differential voltage current conveyor (DVCC) [2]-[3], [10]-[11], differential dif­ference current conveyor (DDCC) [4], differential voltage current conveyor transconductance amplifier (DVCCTA) [12], universal voltage conveyor (UVC) [13], unity gain cells [14]-[15], current-controlled current conveyor (CC­CII) [16], voltage differencing gain amplifier (VDGA) [19], voltage differencing transconductance amplifier (VDTA) [20-23]. Considering the number of input and output terminals, the previously designed configurations in literature can be classified as single-input multi-output (SIMO) [1], [3-7], [11-15], [18], [19], [22-23], multi-input single-output (MISO) [8], [10], [21] and multi-input multi-output (MIMO) [9], [16-17] filter topologies. If the type of signal processing is considered, these filters can further be classified as voltage-mode [3-7], [10-13], [16], [20], current-mode [1-2], [8-9], [14], [17-18], [21], and dual-mode [15], [19], [22-23] filter topologies. However, this finding focuses on the design of the dual-mode SIMO multifunction biquad filter with both voltage and cur­rent output responses using only a single active ele­ment. The topology in the literature [15] needs to em­ploy four voltage followers, four dual-output current followers, seven resistors, and two grounded capacitors. In [19], the single -input three-output dual-mode multi­function filter was developed by using two VDGAs and three capacitors. However, this configuration does not have the feature of independent control of its natural angular frequency (.o) and quality factor (Q). Separate studies in [22-23] introduced SIMO dual-mode biquad filters combining a single VDTA, one grounded resistor, and three capacitors. Both the circuits still require a float­ing capacitor and also perform only a biquadratic filter. In the design of electronic communication and control systems, sinusoidal quadrature oscillators (QOs) which can provide two periodic waveforms with a phase dif­ference of 90° are necessarily needed. Application tasks of QO are, for example, in quadrature mixers for mixing the analog signal outputs, in phase sensitive detection systems for generating reference signals, and in measurement systems for testing electronic de­vice and circuit characteristics. Up to now, several vari­able frequency quadrature oscillator circuits have been built employing various types of active elements, such as operational amplifier [24], CCII [25-26], DDCC [27], four terminal floating nullor (FTFN) [28-30], current feedback operational amplifier (CFOA) [31-33], current differencing buffered amplifier (CDBA) [34-35], current differencing transconductance amplifier (CDTA) [36-38], VDTA [39], and voltage differencing buffered am­plifier (VDBA) [40]. Note that the above mentioned QO circuits are useful in either voltage [24-27], [31-32], [34-35], [39-40] or current-mode [28-30], [33], [36-38] ap­plications. Some QO configurations were developed in [41-49], where the voltage and current quadrature out­puts are generated simultaneously. Several dual-mode QOs make use of one or more active elements [42-44], [47], [49]. Although another set of compact QO realiza­tions using a single active element were proposed in [46], [48], they do not permit non-interactive control of the condition of oscillation (CO) and the frequency of oscillation (.osc). Besides, the possible realization of the dual-mode multifunction biquad filter is not available with any of the previously mentioned QO realizations. This contribution led us to the design of the dual-mode multifunction biquad filter and sinusoidal quadrature oscillator which can provide both voltage and current output signals simultaneously. Each of the proposed configurations includes only a single voltage differ­encing gain amplifier (VDGA) [50], two resistors, and two grounded capacitors. The proposed dual-mode multifunction biquad configuration can orthogonally control of .o and Q. With a slight modification of the proposed biquad, a compact dual-mode QO circuit with non-interactive adjustment of CO and .osc is also obtained. Non-ideal characteristics parasitic element effects on the behavior of the proposed circuits are considered. The working of the circuits is evaluated by simulation results. 2 VDGA Description The VDGA device is a versatile six-terminal active build­ing block, which is recently introduced in [50]. As a consequence, a variety of VDGA-based analog circuit applications have been developed in technical litera­ture, such as active filters [50]-[51], quadrature sinu­soidal oscillators [52]-[53], and capacitance multiplier circuit [54]. Its schematic symbol is shown in Fig.1, where p and n are high-impedance voltage input ports, z+, z- and x are high-impedance current output ports, and w is low-impedance voltage output port. The ideal property of the VDGA device can be characterized as in the following matrix equation: , (1) where gmA and gmB are the transconductance gains, and ß is the transfer voltage gain of the VDGA. Fig.2 shows a CMOS implementation of the VDGA used in this work, and it is derived from the one in [50]. Ac­cording to [55], it can be realized from Fig.2 that each transconductance gmk (k = A, B, C) of the VDGA can be determined by: , (2) where , (3) for i = 1, 2, 3, 4 and the parameter K is the transconduct­ance of the transistor Mik. From equations (2) and (3), the value of gmk can be scaled electronically, since each transconductance gik is proportional to the square root of the bias current IBk. Furthermore, a pair of transcon­ductors M1B-M9B and M1C-M9C performs a current-con­trolled voltage amplifier with the voltage transfer gain b = vw/vz+ = gmB/gmC. 3 Proposed dual-mode multifunction biquadratic filter The proposed dual-mode multifunction biquadratic fil­ter topology is shown in Fig.3. It essentially comprises a single VDGA, two grounded capacitors and two re­sistors (one of them is grounded). A straightforward analysis with iin = 0 provides the three voltage transfer functions as follows: , (4) , (5) and , (6) where . (7) Therefore, the proposed circuit of Fig.3 provides a non-inverting BP, a non-inverting LP and an inverting HP filter voltage response at the output voltages vo1, vo2, and vo3, respectively. Equations (4)-(7) suggest that the characteristics .o and Q of the filter are obtained as : , (8) and . (9) It is important to note that the parameter .o is now tunable electronically by adjusting gmA and/or gmB, while the value of the Q-factor is adjustable through the value of R1 without affecting .o. In other words, the parameters .o and Q-factor of the filter are orthogo­nally controllable. Figure 3: Proposed dual-mode multifunction biquad­ratic filter. Considering again the proposed dual-mode frequency filter given in Fig.3, its routine algebraic analysis with vin = 0 also reveals the three following current transfer functions: , (10) , (11) and , ( 12) where the denominator D(s) is the same as in equa­tion (7). It is clear from equations (10)-(12) that, by the same structure, current-mode HP, BP, and inverting LP responses are simultaneously obtained at io1, io2, and io3, respectively. For this version, the .o and the Q-factor are the same as those given in equations (8) and (9). 4 Proposed dual-mode quadrature sinusoidal oscillator From Fig.3, it is further noted that the dual-mode quad­rature sinusoidal oscillator is obtainable by setting iin = 0, and connecting the p-terminal to the w-terminal of the VDGA. The resulting QO circuit is depicted in Fig.4, and its characteristic equation is found as: . (13) From the above equation, the CO and .osc of the real­ized QO are respectively given by: , (14) and . (15) It is clear from equations (14) and (15) that the CO of the oscillator can be varied independently of .osc by R1. This QO provides two voltage outputs and two current outputs, which relate as follows: , (16) and . (17) Equations (16) and (17) show that the two voltage and current outputs are each other shifted in phase by 90°, thereby exhibiting quadrature property to the pro­posed QO circuit. Moreover, the proposed oscillator also offers versatility by simultaneously providing both quadrature voltage as well as current outputs. 5 Effect of VDGA Non-idealities 5.1 Effect of transfer errors Taking into consideration the VDGA non-idealities, the characteristic of the practical VDGA can be written as: . (18) In above expression, .k (.k = 1 - ..) is the transconduct­ance inaccuracy parameter and . (. = 1 - ..) is the non-ideal voltage transfer gain of the VDGA. These unwant­ed parameters alter from unity by the transfer errors .. (|.. | << 1) and .. (|.. | << 1), respectively. The proposed dual-mode multifunction biquadratic filter of Fig.3 is re-analyzed using the non-ideal performance relation (18) of VDGA, and the non-ideal .o and Q become as follows: , (19) and . (20) Equations (19) and (20) indicate that the transfer er­rors directly affect the parameters .o and Q of the filter. However, since .A and .B are typically close to unity, these small deviations can be compensated by slightly re-adjusting the values of gmA and gmB via the bias cur­rents IBA and IBB, respectively. Similarly, in the non-ideal case, the characteristic equa­tion of the proposed dual-mode QO circuit in Fig.4 can be found as: , (21) where the parameters CO and .osc of the oscillator for this case are modified as: , (22) and . (23) The CO and .osc of the oscillator are deviated from the ideal case by the non-ideal transfer gains. In the same manner, because the voltage transfer gain ß is propor­tional to gmB/gmC, the transconductance gmC is adjust­able to minimize the influence of .A and . on the CO. Also, note from (23) that the slight .osc deviation can be overcome by re-tuning gmA and gmB. 5.2 Effect of parasitic elements In practice, a parasitic problem should be taken into count to determine the effects of the VDGA parasitic impedances on the proposed circuits. Fig.5 displays a sophisticated equivalent model behavior that rep­resents the practical VDGA. In Fig.5, the dashed line encircles the practical VDGA, while the continuous line denotes the ideal VDGA with various parasitic elements at its terminals. As can be seen, there are parasitic par­allel resistances and capacitances from terminals p, n, z+ and z- to ground [(Rp//Cp), (Rn //Cn), (Rz+//Cz+) and Rz-//Cz-)], and a parasitic serial resistance (Rw) at the terminal w. Therefore, by applying the practical model of the VDGA to the proposed dual-mode multifunction filter in Fig.3 and assuming the condition R2 >> Rw, the modi­fied .o and Q can be expressed as: , (24) and . (25) where R'1 = R1//Rz+, R'x = Rx//Rn, C'1 = C1 + Cz+ and C'2 = C2 + Cx + Cn. In a similar way, accounting for the VDGA parasitic ele­ments given in Fig.5, the CO and .osc of the proposed dual-mode sinusoidal QO in Fig.4 can be derived as: , (26) and . (27) From inspection of equations (24)-(27), it is possible to reduce the VDGA parasitic influences on the proposed circuits by taking the following conditions in the de­sign: R1 << Rz+, Rx << Rn, C1 >> Cz+ and C2 >> (Cx + Cn). Figure 5: Practical VDGA model 6 Simulation results and discussions The correct operation of the proposed dual-mode multifunction filter and QO topologies in Fig. 3 and 4 is assessed through PSPICE simulation results. For this purpose, the transistor models of the TSMC 0.25-µm CMOS process parameters have been used. The CMOS VDGA in Fig.2 is simulated under DC supply voltages of ±1V. The values of transistor aspect ratios (W/L) are provided in Table 1. Table 1: Values of transistor aspect ratios (W/L) of the VDGA circuit in Fig.2. Transistor W (µm) L (µm) M1k - M2k 15 0.25 M3k - M4k 23 0.25 M5k - M7k 4.5 0.25 M8k - M9k 6 0.25 6.1 Simulation results of the proposed dual-mode multifunction biquadratic filter For the proposed dual-mode multifunction biquadratic filter in Fig.3, the active and passive components are taken as: gmk . 1 mA/V (IBk = 100 µA), R1 = R2 = 1 k. and C1 = C2 = 100 pF which result in fo . 1.59 MHz and Q . 1. The simulated and ideal frequency responses for the voltage and current gains are represented in Fig.6. In Fig.7, the input and output waveforms for the pro­posed BP filters at 1.59-MHz sinusoidal input signals are also shown. Total harmonic distortions (THDs) are less than 4% and 1.6% for the voltage-mode and current-mode BP filters, respectively. In addition to the simula­tion result, this filter has the total power consumption of about 1.49 mW. Next, the large-signal behavior of the proposed filter is also evaluated by applying a si­nusoidal input signal of 1.59 MHz. The BP output re­sponses are found to demonstrate the THD variations of input signal amplitude as shown in Fig.8. (a) (b) Figure 6: Simulated and ideal frequency responses of the proposed dual-mode multifunction filter in Fig.3 (solid line: simulated response, dashed line: ideal re­sponse). (a) voltage-mode (b) current-mode. To test the adjustability of Q-factor without changing the fo-value, the following circuit components are se­lected as: gmk = 1 mA/V, C1 = C2 = 100 pF, with four dif­ferent values of R1 namely 0.5 k., 1 k., 2 k., and 10 k.. The four BP voltage responses are illustrated in Fig.9, which accordingly shows the orthogonal variability of Q-factor. Furthermore, by keeping the product of gm1R1 constant, and tuning the value of gm1/R1 only, an inde­pendent tunability of fo can be obtained as shown in Fig.10. The component values for simulating the real­ized BP filter with different fo and their resulting charac­teristics are given in Table 2. Figure 9: Gain-frequency characteristics with Q = 0.5, 1, 2, and 10 of the proposed voltage-mode BP filter in Fig.3. To evaluate the mismatch and process variation effects, Monte Carlo (MC) analysis has been performed for 100 iterations. MC simulation results showing deviations in filter responses for 5% changes in all passive elements (R1, R2, C1, and C2) and transconductances (gmk) are il­lustrated in Fig.11(a) and 11(b), respectively. Tempera­ture variation impacts on the filter responses are also studied for observed range 0°C to 100°C. The simula­tion results of the gain-frequency characteristics with a variation in operating temperature are drawn in Fig.12. From the graph, the value of fo varies from 1.69 MHz at 0°C to 1.35 MHz at 100°C with a maximum deviation of 17%. It may also be observed that the fo-value shifts to the lower frequencies with an increase in temperature. This is due to the fact that the transconductance de­creases with increases in temperature due to decrease in mobility. This shifting in fo can easily be compensat­ed through bias current variation, or the PTAT (Propor­tional to Absolute Temperature) current reference can be used as bias current sources to compensate for the temperature behavior of the proposed circuits. (a) (b) Figure 11: Monte Carlo analyses with 100 iterations, showing variations in LP, BP and HP filter responses, due to 5% changes in (a) all resistors and capacitors (b) all transconductances. Figure 12: Gain-frequency characteristics with a varia­tion in temperature from 0°C to 100°C. 6.2 Simulation results of the proposed dual-mode quadrature sinusoidal oscillator With the same above designed values, the proposed dual-mode QO circuit of Fig.4 has been simulated for a frequency of oscillation of fosc = 1.59 MHz. Simulation results of the voltage and current quadrature output responses are shown in Fig.13 and 14, respectively. Fig.13(a) indicates the two quadrature voltage outputs difference in phase by 88°, while Fig.14(a) shows 91° phase-shifted quadrature current outputs. The ob­served THD for both voltage and current outputs are around 3.76% and 3.73%, respectively. The Lissajous patterns for the two voltage and two current outputs are further depicted through Fig.15(a) and 15(b), re­spectively. It is observed that the resultants produce circles around the origin with no tilt in axis illustrating the quadrature property of the proposed oscillator cir­cuit. 7 Conclusions The paper proposes compact circuit configurations for realizing dual-mode (i.e. both voltage-mode and current- mode) multifunction biquadratic filter and quadrature sinusoidal oscillator. Each of the proposed circuit configurations requires a single VDGA, two grounded capacitors, and two resistors (one of them is grounded). The proposed filter can realize simultane­ously the three standard biquadratic filtering functions, i.e. LP, BP, and HP ones, with both voltage and current output responses. It has also capable of independent control of .o and Q-factor. Another notable advantage of the proposed circuit is that it can also be used as a sinusoidal quadrature oscillator to provide two quadra­ture voltage outputs and two quadrature current out­puts simultaneously. The oscillation condition and the oscillation frequency of the proposed dual-mode QO are orthogonally controllable by separate bias currents. The effect of non-idealities influences of the VDGA on the circuit functionality has been studied, and simu­lation results using PSPICE with TSMC 0.25-µm CMOS technology have also been included to validate the functionality of the proposed circuits in both frequen­cy filter and oscillator mode. (a) (b) Figure 13: Simulated voltage output responses. (a) time-domain responses (b) frequency spectrum. (a) (b) Figure 14: Simulated current output responses. (a) time-domain responses (b) frequency spectrum. Figure 15: Lissajous patterns illustrating the quadra­ture property. (a) voltage-mode (b) current-mode. 8 Acknowledgments This research project was supported by Rajamangala University of Technology Isan, Contract No. ENG28/63. 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Figure 2: Internal circuit configuration of the CMOS VDGA. W. Tangsrirat et al.; Informacije Midem, Vol. 50, No. 2(2020), 125 – 136 Figure 4: Proposed dual-mode quadrature sinusoidal oscillator. W. Tangsrirat et al.; Informacije Midem, Vol. 50, No. 2(2020), 125 – 136 W. Tangsrirat et al.; Informacije Midem, Vol. 50, No. 2(2020), 125 – 136 W. Tangsrirat et al.; Informacije Midem, Vol. 50, No. 2(2020), 125 – 136 (a) (b) Figure 7: Input (dashed line) and output (solid line) waveforms of the BP filter for 1.59-MHz sinusoidal in­put signal. (a) voltage-mode (solid line: vo1, dashed line: vin), (b) current-mode (solid line: io2, dashed line: iin) Figure 8: THD variations of the BP response versus in­put signal amplitude at 1.59 MHz. (a) voltage-mode (b) current-mode. Table 2: Component values for implementing the proposed BP filter in Fig.3 with independent adjustability of fo. gmk (mA/V) IBk (µA) R1 (kW) gmkR1 gmk/R1 fo (MHz) Q Simulated Theory 0.63 40 1.6 1 0.40E-06 1.01 0.98 1 1.00 100 1.0 1 1.00E-06 1.59 1.54 1 1.35 180 0.74 1 1.82E-06 2.15 2.05 1 W. Tangsrirat et al.; Informacije Midem, Vol. 50, No. 2(2020), 125 – 136 Figure 10: Gain-frequency characteristics with inde­pendent adjustability of fo of the proposed voltage-mode BP filter in Fig.3. W. Tangsrirat et al.; Informacije Midem, Vol. 50, No. 2(2020), 125 – 136 (a) (b) W. Tangsrirat et al.; Informacije Midem, Vol. 50, No. 2(2020), 125 – 136 W. Tangsrirat et al.; Informacije Midem, Vol. 50, No. 2(2020), 125 – 136 W. Tangsrirat et al.; Informacije Midem, Vol. 50, No. 2(2020), 125 – 136 Copyright © 2020 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Journal of Microelectronics, Electronic Components and Materials Vol. 50, No. 2(2020), 137 – 146 https://doi.org/10.33180/InfMIDEM2020.206 DTMOS Based High Bandwidth Four-Quadrant Analog Multiplier Muhammed Emin Başak1, Emre Özer2, Firat Kaçar3, Deniz Özenli4,5 1Yildiz Technical University, Faculty of Naval Archit. and Maritime, Istanbul, Turkey 2Istanbul University-Cerrahpasa, Vocational School of Technical Sciences, Department of Electrical & Energy, Istanbul, Turkey 3Istanbul University-Cerrahpasa, Faculty of Engineering, Department of Electrical & Electronics Engineering, Istanbul, Turkey 4National Defence University, Department of Electronics Engineering, Air Force Academy, Istanbul, Turkey 5Istanbul Technical University, Department of Electronics and Communication Eng., Istanbul, Turkey Abstract: Analog multiplication circuits are very important blocks widely used in analog signal processing applications. In analog multiplication circuits, low power consumption is expected with wide bandwidth, low nonlinearity and high input range according to the supply voltage. In this work, folded Gilbert cell structure was resized using dynamic threshold MOS (DTMOS) transistors. The proposed circuit is laid out with 491.4 µm2 chip area. Post layout simulations show that the proposed circuit has high bandwidth (1.2 GHz), low supply voltage (0.2 V), and low power consumption (44.6 µW). In addition, the proposed circuit is examined for temperature variation, total harmonic distortion, intermodulation products and Monte Carlo analysis of the dimensioning of the circuit. The post layout results show that the proposed circuit has promising performance against its counterparts in the literature. Keywords: Four-quadrant; analog multiplier; DTMOS. Štiri-kvadranten širokopasovni množilnik na osnovi DTMOS Izvleček: Analogna množilna vezja imajo zelo pomemben del pri analognem procesiranju signalov. Od njih se pričakuje nizka poraba, velika pasovna širina, nizka nelinearnost, in visoko vhodno območje glede na napajalno napetost. V tem delu je bila uporabljena povečana Gilbertova struktura z uporabo tranzistorjev z dinamičnim pragom (DTMOS). Vezje je narejeno na površini 491.4 µm2. Simulacije so pokazale, da je pasovna širina vezja 1.2 GHz, napajalna napetost 0.2 V in poraba 44.6 µW. Dodatno je bil raziskan vpliv temperature, skupna harmonična distorzija, intermodulacija in Monte Carlo analiza. Ključne besede: štiri kvadranten; analogni množilnik; DTMOS. * Corresponding Author’s e-mail: mebasak@yildiz.edu.tr 1 Introduction Analog multipliers that are commonly used in analog signal processing applications such as analog and fre­quency modulation, phase locked-loop, phase shifting and detection, frequency converter, automatic control, artificial neural networks, Neuro-fuzzy systems. The an­alog multipliers are electronic circuits with two input ports and one output port. Output signal of the mul­tiplier is defined by the transfer function z = K x x x y, where x and y are two continuous input signals and K is a constant value appropriately dimensioned. Analog multipliers are classified according to the polarization of their inputs. The classifications are as follows: i) One quadrant [1] whose inputs are non-polarized, ii) Two quadrant [2], [3] whose one of the inputs are polarized, iii) Polarized both inputs are called four quadrant [4–7]. In addition, the multipliers are divided into two types: current mode [8], [9] and voltage mode [4–7]. The first bipolar analog multiplier known as the Gilbert cell was published in 1968 by Barrie Gilbert [10]. Since analog multipliers based on CMOS technology have been classified (i) according to the form of the input signal; current or voltage mode (ii) with regard to the operating region of the transistors; weak inversion [8], [11], [12] strong inversion [13], [14], saturation region [15] and linear region [16], [17]. Although the input sig­nal range and bandwidth of analog multipliers operat­ing in the weak inversion region are quite narrow, they are frequently used in low power consumption appli­cations. Analog multipliers operating in the saturation region have wide bandwidth, dynamic input range and high speed. In multipliers operating in the strong inver­sion region, the error caused by the body effect causes mismatch in the threshold voltage. In recent years, the increasing popularity of portable devices such as smartphones and tablet computers has brought restrictions on battery capacity, weight and size. It has created serious restrictions on power consumption and led to the emergence of low-power and high-performance circuitry techniques. Thus, sev­eral methods have been suggested to concentrate the power consumption of the analog multipliers. Some of these techniques are as follows: weak-inversion [8], [11], [12], [18], subthreshold MOSFETs [19–23], bulk driven [11], [12], DTMOS [24][25], and floating gate MOSs [5], [26], [27]. It is seen that transistor multipliers working in weak inversion region have poor dynamic range, limited voltage swing and low bandwidth. In the study of Soltany and Razai [12], although the power consumption was reduced by bulk-input, it was seen that the speed and output voltage range were also very low. Even though, analog multipliers designed with transistors operating in the subthreshold region [19–23] show low power consumption, but the dynam­ic range and operating speed of the multiplier are low. In the study, using DTMOS transistor [24], low power consumption and full-scale input voltage were provid­ed, but -3dB bandwidth was obtained as 1.11 MHz. In articles [26] and [27] a low power consumption analog multiplication circuit was implemented using FGMOS, but their bandwidth was specified as 10 MHz and 200 MHz, respectively. In the study of Keles and Kuntman [5], FGMOS technique has been achieved with high bandwidth such as 1.5 GHz, but there is no information about power consumption here. In this article, a low power, wide bandwidth four-quad­rant analog multiplier by using DTMOS based folded Gilbert cell is proposed. The simulation results are giv­en using Cadence Environment using 0.18 µm TSMC CMOS technology under a supply voltage of 0.2 V. Gilbert cell is one of the first studies of analog multi­plication circuits proposed by Barrie Gilbert in 1968 [10]. Gilbert cell is popular in bipolar integrated circuits (IC) due to its wide dynamic range and bandwidth. In this study, the analog multiplier was realized with the folded Gilbert cell by using DTMOS technology and the bandwidth is obtained pretty much wider. Due to undesirable behavior in nonlinearity, the range of the input signal is limited to half or generally much less of the supply voltage. In this study, full-scale sup­ply voltage can be used for an input signal range [26]. In order to demonstrate its technological strength, Monte Carlo analyses were performed in AC form with 10% mismatch of process parameters (tox and VTH) and transistor widths. The rest of the paper is arranged as follows: Informa­tion on the DTMOS structure and the proposed multi­plication circuit structure as well as equations are given in Section 2. AC/DC characteristics, intermodulation products, temperature sensitivity, total harmonic dis­tortion and Monte Carlo analysis are given in Section 3. Finally, Section 4 concludes the paper. 2 DTMOS based four-quadrant analog multiplier Today, the increase in the use of portable devices has brought limits on battery capacity, weight and size. These restrictions have contributed to an increase in studies on low power and high performance circuit techniques. The need to reduce power consumption has led to a re­duction in the supply voltage of the circuits. Excessive lowering of the supply voltage causes standby power and speed problems of the memory elements. MOS­FET with dynamic threshold voltage was proposed by Assaderaghi et al. in 1994 to meet low voltage perfor­mance requirements [28]. The topology and symbol of the DTMOS obtained by connecting the body and gate of a MOSFET are given in Figure 1. The threshold voltage of DTMOS is as follows: (1) Vth is threshold voltage, Vt0 is the zero body bias thresh­old voltage. . is the body effect coefficient and it de­pends on the gate oxide capacitance, silicon permit­tivity and substrate doping .F. is the Fermi potential. VSB is the source to body voltage. The threshold voltage equation is written for a long channel NMOS transistor where drain-induced barrier lowering (DIBL) effect is neglected. The proposed DTMOS has a high threshold voltage at zero bias and low threshold voltage when the gate-source voltage is equal to supply voltage( Vgs = Vdd)[29]. By reduction of threshold voltage, inversion charge (QN) is increased; so, larger inversion charge leads to a higher current drive in DTMOS in comparison to the regular MOSFETs MOS transistor’s drain current is given by below Eq. (2). (2) According to the equation the transistor will saturate in weak inversion when VDS . 3kT/q [17]. Under some limitations, bulk-DTMOS technique can be applied to cheap standard CMOS fabrication process without ad­ditional processing steps. The transconductance gm is described by (3) DTMOS reduces the junction width and consequently the depletion region charge density, which contrib­utes to a decrease in the threshold voltage. In case of reverse bias, the depletion region width increases, and the increase in the body charges causes the thresh­old voltage to increase. DTMOS-based circuits in case of forward biasing, the threshold voltage will be low. When the transistor is turned off, the VTH becomes high, resulting the leakage current will also be low. Thus, the threshold voltage is changed dynamically with respect to the gate input, whereas operating state of the circuit is also changed. The DTMOS based four-quadrant analog multiplier circuit by using the folded Gilbert cell is presented in Figure 2. M3-M4 forms one differential pair, while M5-M6 transistors form another differential pair. The drain of M3-M5 and M4-M6 transistors are cross connected. The input signal VX is applied to the cross connected differential pairs, while the input signal VY is applied to another differential pair consisting of M1 and M2. The bias currents (ISS1, ISS2, ISS3) are the tail currents and ISS1 = ISS2 = ISS3. The output current expression of the circuit is: (4) Where kn and kp are the transconductance of the n-channel and p-channel transistors, respectively. kn = (µnCOX/2)(W/L), µn, is the electron mobility, COX is the gate oxide capacitance of the NMOS transistor. W and L are the width and length of the NMOS transistors, re­spectively. Figure 2: DTMOS based four-quadrant analog multi­plier by using folded Gilbert cell 3 Simulation Results Simulation results are presented in this section to eval­uate the performance of DTMOS based folded Gilbert cell four-quadrant analog multiplier. The design veri­fied by the Cadence Environment using 0.18 µm TSMC CMOS technology model parameters under 0.2 V sup­ply voltage and ISS1 = ISS2 = ISS3 = 100 µA. Dimensions of the transistors are given in Table 1. Layout of the proposed DTMOS based Analog Multiplier is given in Figure 3. Table 1: Aspect ratio of the analog multiplier Transistor W(µm) L(µm) M1, M2, M8, M9 20 0.26 M7, M10 10 0.26 M3-M6, M11, M12 1.3 0.26 The DC transfer characteristic of DTMOS based analog multiplier is given in Figures 4 and 5. For the proposed multiplier topology, the transfer curve IOUT versus VX and IOUT versus VY are shown in Figure 4 and Figure 5 respectively. In Figure 4, VY is swept from -200 mV to 200 mV while VX is varied from -200 mV to 200 mV in step size of 100 mV. In Figure 5, VX is swept from -200 mV to 200 mV while VY is varied from -200 mV to 200 mV in step size of 100 mV. Figures 4 and Figure 5 show that the proposed multiplier can be easily used as four quadrant multiplier. Figure 3: The layout of the proposed analog multiplier (Chip area of the proposed structure is 491.4 µm2.) In order to evaluate the AC transfer characteristics of DTMOS based analog multiplier, the input voltage VX 100 mV DC is kept constant while the other input voltage VY 100 mVp-p AC is applied. The frequency response characteristics of the analog multiplier are shown in Figure 6. -3 dB bandwidth of the proposed structure is 1.4 GHz and 1.2 GHz for the schematic and post layout simulations respectively. To evaluate the performance of the DTMOS-based analog multiplier as an amplitude modulator, two sinu­soidal signals with 200 mV amplitude at 10 kHz and 300 kHz frequencies were applied to the inputs, respective­ly. The multiplier can be used as a modulator is shown in Figures 7 and 8. Intermodulation distortion for analog multipliers is a performance criterion just like total harmonic distor­tion. Ideally, the total harmonic distortion at the output of a multiplier is zero and no intermodulation products are presented. Intermodulation products arise as a re­sult of the non-linearity of analog multipliers. Table 2 shows the 2nd, 3rd, 4th and 5th degree intermodulation products of the signal at the output of the proposed multiplier. Two sinusoidal signals were applied to the inputs of the analog multiplier at frequencies f1 = 10 kHz and f2 = 300 kHz. Furthermore, the frequency spec­trum of the output of the proposed multiplier is given in Figure 9. To evaluate the total harmonic distortion (THD) of the output signal of the proposed multipliers, a constant DC voltage of 200 mV was applied to the VY input, while a sinusoidal signal with a frequency of 1 kHz, 10 MHz and 100 MHz were applied to the VX input. The THD of the output voltage of the proposed multiplier is given in Figure 10 as a function of the input signal. THD [%] is composed of 9 harmonics and it is considered that the maximum THD is below 3% for the total scope of the input signal. In order to evaluate the performance of the proposed multiplier as a frequency doubler, a sinusoidal signal of 100 mV amplitude and 10 kHz frequency was applied to both inputs of the multiplier. The accuracy of the fre­quency doubler function for the proposed multiplier is indicated in Figure 11. The variation of AC and DC characteristics of the pro­posed multiplier with temperature is investigated. The temperature changes from 0 to 100 ° C, while the change in AC characteristic is shown in Figure 12. The DC characteristic change in the same temperature change is presented in Figure 13. VY is swept from -200 mV to 200 mV while VX is varied from -200 mV to 200 mV in step size of 100 mV. Figure 10: Relation between THD and VX (peak) voltage with respect to 1 kHz, 10 MHz and 100 MHz frequen­cies. The statistical distribution of the width (W) of the pro­posed multiplier circuit for 10% mismatch is given in Figure 13 for 200 runs. The histogram showing the sta­tistical distribution in Figure 14 according to the 10% mismatch change in transistor width is given in Monte Carlo analyses. According to the histogram, maximum bandwidth reaches up to 1.309 GHz whereas minimum bandwidth is 1.105 GHz. Also, average value is given as 1.230 GHz according to the post layout simulations. In addition to the 10% mismatch in width (W), the analy­sis made by adding 10% mismatch change in tox and VTH process parameters is presented in Figure 15. In the histogram showing the statistical distribution here, the maximum bandwidth is 1.360 GHz and the mini­mum bandwidth is 1.114 GHz respectively. The average bandwidth is 1.23 GHz. All simulations have been done with post layout simulations. Figure of Merit (FoM) is defined in order to compare the analog multiplier circuits in the literature with the pro­posed multiplier. Definition of FOM is: (5) where bandwidth is in (MHz), THD in (%), supply volt­age in (V), and power consumption is evaluated in (µW). The FoM value of the proposed multiplier out­performs the other multipliers in the literature. Table 3 shows the comparison of the multiplier according to FoM value and various performance criteria with the existing multipliers in the literature. The circuits with higher FOM values are superior to the others. Accord­ing to this, the FoM value of the circuit we recommend is 162.08, while the FoM value of the nearest circuit [30] is nearly four times less. 4 Conclusion In this study, a four-quadrant analog multiplier in with voltage input and current output is presented. The circuit is designed using dynamic threshold MOS and folded Gilbert cell structure. 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Surakampontorn, “CMOS volt­age-mode analog multiplier,” in 2006 IEEE Interna­tional Symposium on Circuits and Systems, 2006, vol. 1, no. 5, p. 4. https://doi.org/10.1109/ISCAS.2006.1693003 33. W. Liu and S. I. Liu, “Design of a CMOS low-power and low-voltage four-quadrant analog multiplier,” Analog Integr. Circuits Signal Process., vol. 63, no. 2, pp. 307–312, 2010. https://doi.org/10.1007/s10470-009-9382-y 34. A. Amiri and A. N. Saatlo, “Voltage mode imple­mentation of highly accurate analog multiplier circuit,” ICEE 2015 - Proc. 23rd Iran. Conf. Electr. Eng., vol. 10, pp. 1059–1062, 2015. https://doi.org/10.1109/IranianCEE.2015.7146368 35. V. Niranjan and M. Gupta, “Low voltage four-quad­rant analog multiplier using dynamic threshold MOS transistors,” Microelectron. Int., vol. 26, no. 1, pp. 47–52, Jan. 2009. https://doi.org/10.1108/13565360910923179 Arrived: 28. 03. 2020 Accepted: 24. 08. 2020 M. E. Başak et al.; Informacije Midem, Vol. 50, No. 2(2020), 137 – 146 M. E. Başak et al.; Informacije Midem, Vol. 50, No. 2(2020), 137 – 146 Figure 1: Topology and symbol of DTMOS. M. E. Başak et al.; Informacije Midem, Vol. 50, No. 2(2020), 137 – 146 Figure 4: DC characteristics of the proposed multiplier versus VX with VY as a parameter. Figure 5: DC characteristics of the proposed multiplier versus VY with VX as a parameter. M. E. Başak et al.; Informacije Midem, Vol. 50, No. 2(2020), 137 – 146 Figure 6: AC characteristics of the proposed multiplier for post layout and schematic simulations Figure 8: Output of the proposed multiplier as an am­plitude modulator Figure 9: Frequency spectrum of the proposed multi­plier as an amplitude modulator Figure 7: VX (10 kHz) and VY (300 kHz) input signals ap­plied to the proposed multiplier. M. E. Başak et al.; Informacije Midem, Vol. 50, No. 2(2020), 137 – 146 Table 2: Intermodulation products of the proposed multiplier. Order Harmonics [kHz] Fourier Components Normalized Fourier Components (dB) Intermodulation Products [kHz] Fourier Components Normalized Fourier Components (dB) 2 20 2.90×10-8 -24.55 290 8.26×10-6 0 600 2.02×10-8 -26.12 310 8.26×10-6 0 3 30 9.50×10-11 -49.39 320 3.10×10-9 -34.25 900 1.80×10-9 -36.62 590 7.70×10-11 -50.30 610 1.12×10-10 -48.69 4 40 1.68×10-9 -36.92 330 2.48×10-7 -15.22 580 9.48×10-9 -29.40 620 9.45×10-9 -29.42 1200 6.04×10-9 -31.36 890 1.11×10-6 -8.70 910 1.11×10-6 -8.70 5 50 8.59×10-11 -49.83 340 1.06×10-9 -38.92 630 1.10×10-10 -48.74 880 7.19×10-10 -40.60 1500 6.70×10-11 -50.91 920 7.94×10-10 -40.17 1190 1.51×10-11 -57.38 1210 5.62×10-11 -51.67 Figure 11: Output of the proposed multiplier as a fre­quency doubler. M. E. Başak et al.; Informacije Midem, Vol. 50, No. 2(2020), 137 – 146 Figure 12: Post layout AC characteristic of the proposed multiplier when the temperature varies from 0 to 100 ° C. Figure 13: Post layout DC characteristic of the proposed multiplier when the temperature varies from 0 to 100 ° C. Table 3: Comparison table of the proposed multiplication circuit with previous studies Ref Year Tech. Power Supply Bandwidth THD (Frequency, Voltage) Power Consumption Input Range FoM [4] 2014 0.25 µm ±1.25 V NA 1.62% (1 MHz, 125 mV) 4.02 µW 125 mV - [5] 2011 0.35 µm 2 V 1.5 GHz 2.67% (1 MHz, 1 V) NA ±1 V - [6] 2018 0.25 µm ±0.75 V NA 3% (1 MHz, 200 mV) 777 µW ±200 mV 0.002* [7] 2005 0.5 µm ±1.5 V 25.34 MHz 4.667% (1 MHz, 1 V) 1.6 mW ±1 V 0.0011 [31] 2000 0.35 µm ±1.5 V 1.3 GHz 0.9% (1 MHz, 1V) 2.6 mW ±1 V 0.1851 [32] 2006 0.35 µm ±2.5 V 30 MHz 0.62% (NA) 1.2 mW ±400 mV 0.0080 [11] 2013 0.18 µm 0.5 V 221 kHz 5.8 % (1 kHz, 50 mV) 714 nW ±80 mV 0.1067 [33] 2010 0.35 µm 1.5 V 268 kHz 4.2 % (10 kHz, NA) 6.7 µW ±120 mV 0.0063 [34] 2015 0.18 µm 1.8 V 1.45 GHz 0.37 % (1 MHz, 0.5 V) 84 µW 500 mV 25.9187 [26] 2012 0.13 µm 0.5 V 10 MHz 1.4 % (NA, 0.5 V) 1.56 µW ±600 mV 9.157 [30] 2010 0.18 µm 1.2 V 2 GHz 1.5 % (NA) 25 µW ±200 mV 44.4444 [24] 2019 0.18 µm ±0.2 V 1.11 MHz 3.7 % (1 kHz, 100 mV) 18.4 nW ±200 mV 40.760 [35] 2009 0.25 µm ±0.5 V 250 MHz NA NA NA - [23] 2019 0.5 µm 3.3 V 50 MHz lower 1 % (1 kHz, 0.2 V) 660 µW ±200 mV 0.022 Proposed# 2020 0.18 µm 0.2 V 1.2 GHz 0.83 % (10 MHz, 100 mV) 44.6 µW 200 mV 162.08 *Bandwidth is defaulted to 10 MHz. # Data are post layout simulation results M. E. Başak et al.; Informacije Midem, Vol. 50, No. 2(2020), 137 – 146 Figure 14: The bandwidth distribution of analog multi­plier depending on MOSFET widths (W) Figure 15: The bandwidth distribution of analog mul­tiplier depending on process parameters (tox and VTH) and MOSFET widths (W) M. E. Başak et al.; Informacije Midem, Vol. 50, No. 2(2020), 137 – 146 M. E. Başak et al.; Informacije Midem, Vol. 50, No. 2(2020), 137 – 146 Copyright © 2020 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. In memoriam Prof. dr. Jože Furlan Journal of Microelectronics, Electronic Components and Materials Vol. 50, No. 2(2020), 147 – 149 In memoriam zaslužnemu profesorju dr. Jožetu Furlanu (Žalna seja, UL FE, 1.7.2020) Prof. dr. Jože Furlan Zaslužni professor Univerze v Ljubljani (1934-2020) Spoštovana družina profesorja Jožeta Furlana, spoštovani prijatelji in sodelavci profesorja Jožeta Furlana, spoštovani bivši študenti, diplomanti in dok­toranti profesorja Jožeta Furlana, spoštovane dame in gospodje! V imenu Katedre za elektroniko želiva predstaviti zaslužnega profesorja Univerze v Ljubljani, rednega profesorja dr. Jožeta Furlana, univ. dipl. inž. el. In nje­govo življenjsko pot. Prof. Jože Furlan je preko šest desetletij oblikoval, zazna­moval in bogatil slovensko elektroniko kot univerzitetni učitelj Fakultete za elektrotehniko Univerze v Ljubljani. Prof. Furlan se je trajno zapisal v zgodovino slovenske elektronike kot pionir na področju polprevodniških el­ementov, tranzistorskih in integriranih vezij ter fotovol­taike. Jože Furlan je bil rojen leta 1934 v Limbušu pri Maribo­ru. Že v otroških letih se je navdušil nad elektrotehniko. Kot gimnazijski dijak je pridno obiskoval radioamater­ske tečaje in sestavljal radijske sprejemnike ter na ta na­čin prišel v prvi stik z elektroniko, ki se ji je nato zapisal za vse življenje. Med leti 1952 in 1957 je študiral elektrotehniko na Od­delku za elektrotehniko Tehniške visoke šole v Ljubl­jani. Med študijem je sodeloval kot demonstrator pri predmetu Elektronika in elektronske cevi ter vodil vaje za študente elektrotehnike in fizike. Hkrati je bil v viš­jih letnikih honorarno zaposlen na Fizikalnem inštitutu Medicinske visoke šole v Ljubljani, kjer je načrtoval in sodeloval pri gradnji elektronskih naprav. Zelo zgodaj se je zavedal pomena mednarodne vpetosti in znan­ja tujih jezikov. Tako se je kot študent usposabljal na 4-mesečni praksi v Nemčiji pri podjetju Electronic GmbH v Münchnu, po končani diplomi leta 1958 pa v Veliki Britaniji in sicer 2 meseca pri podjetju Edward’s High Vacuum v Crawleyu. Še istega leta se je zaposlil kot asistent pri prof. dr. Du­šanu Lasiču na Oddelku za šibki tok Fakultete za elek­trotehniko in strojništvo Univerze v Ljubljani. Prvo ra­ziskovalno in pedagoško področje prof. Furlana so bile tedaj, v predtranzistorskem obdobju, še vedno zelo ak­tualne vakuumske elektronke. Pri tem delu je preučeval električna polja in gibanje elektronov v večelektrodnih elektronkah ter raziskoval šum v osnovnih elektronskih elementih. Še posebej je znan njegov merilnik šumov fotopomnoževalk. Leta 1960 je bil z ameriško tehnično pomočjo na pollet­nem akademskem in raziskovalnem izpopolnjevanju v laboratoriju tedaj enega od vodilnih strokovnjakov na področju prihajajočih tranzistorjev, pri prof. Johnu Lin­villu na Univerzi Stanford, kjer je pridobival vrhunska znanja s področja polprevodniških elementov. Tako se je že na začetku šestdesetih let kot eden prvih sloven­skih elektronikov preusmeril od elektronk k tranzistor­jem in od tod naprej na področje mikroelektronike. Od jeseni 1960 je bil honorarni predavatelj za predmet Elektronika na Oddelku za fiziko in od jeseni 1963 tudi za predmet Osnove elektronike na Oddelku za meta­lurgijo Fakultete za naravoslovje in tehnologijo. Na III. stopnjo študija Elektronska optika na Fakulteti za elek­trotehniko se je vpisal leta 1961 in ga uspešno zaključil z magistrskim delom v letu 1966 in z doktoratom iz elektrotehniških znanosti 1968. Sredi šestdesetih let je napisal znano knjigo Elektronika, v kateri je obravnaval nova tranzistorska vezja in jih primerjal z vezji na osno­vi elektronk. Od leta 1966 je bil zaposlen kot redni do­cent za predmete Elektronika in Napajalne naprave, dve leti kasneje je prevzel še podiplomska predmeta Fizika šumov in Mikroelektronika. V letih 1969-1970 je bil na izpopolnjevanju v enem od vodilnih razvojno-raziskovalnih laboratorijev na področju mikroelektronike, pri podjetju Hewlett-Pack­ard v Silicijevi dolini, kjer je raziskoval tranzistorska inte­grirana vezja. Tu je pridobival najnovejša načrtovalska in tehnološka znanja na področju integriranih vezij. V tem obdobju je za Hewlett-Packard razvil tudi dve zahtevni integrirani vezji za števni merilnik frekvence HP 5345A. Kot je zapisala strokovna komisija ob nje­govi izvolitvi v izrednega profesorja leta 1972: “…, kjer je izvedel nekatere nove tipe integriranih tranzistorskih vezij pa tudi dva osnovna tipa in nekaj izvedenk eks­tremno hitrih integriranih vezij za impulzne signale na 500 MHz. Pripomniti velja, da najhitrejša komercialno dosegljiva vezja dosegajo komaj mejo 300 MHz.”. Po povratku v Ljubljano je prof. Furlan napisal prvi knjigi pri nas s področja mikroelektronskih tehnologij in elektronike integriranih vezij. Nato je do sredine sedemdesetih let intenzivno deloval pri raziskovalnem in pedagoškem delu v Laboratoriju za mikroelektron­iko na Fakulteti za elektrotehniko UL, pri čemer so bile za uspešno delo izredno koristne njegove bogate izkušnje, pridobljene v Ameriki. Profesor Furlan pa ni bil samo izredno prodoren na raziskovalnem in strokovnem področju. Vseskozi je bil tudi skrben pedagog in odličen predavatelj ter vses­transko aktiven, angažiran in predan. Leta 1977, ob izvolitvi v rednega profesorja, je stroko­vna komisija zapisala: “Kandidat je svojo družbeno aktivnost izpričal z delom v mnogih delovnih telesi: predstojnik oddelka, predstojnik katedre, predsednik sindikalnega odbora, 5 let poslanec Kulturno pros­vetnega zbora Skupščine SRS, član sveta VDO FE, član drugih odborov in komisij. S posebno zavzetostjo je vodil delo Sistematizacijske komisije kot njen predsed­nik.” Profesor Furlan je aktivno sodeloval tudi izven uni­verze, predvsem v stroki. Bil je med pobudniki in od samega začetka sodeloval pri snovanju jugoslovanske sekcije Mednarodne elektrotehniške organizacije IEEE. Od njene ustanovitve leta 1972 je deloval najprej kot tajnik, nato pa kot predsednik jugoslovanske sekcije IEEE. Mnogo let je bila Jugoslovanska sekcija IEEE edi­na iz skupine vzhodnoevropskih držav, kar je – v tistih precej hermetičnih časih – med drugim omogočilo nemoten dostop do vrhunskih IEEE publikacij ter do raznih drugih članskih ugodnosti. V drugi polovici 70-tih let se je raziskovalno delo prof. Furlana usmerilo v študij osnovnih pojavov, lastnosti in aplikacij polprevodniških elementov ter tedaj še razm­eroma novih sončnih celic iz monokristalnega in amor­fnega silicija. Ustanovil in mnogo let je uspešno vodil Laboratorij za nelienarne elemente, ki se je kasneje preimenoval v Laboratorij za elektronske elemente. Iz slednjega sta zaradi povečanega obsega raziskovalne­ga dela kasneje izšla dva uspešna laboratorija na UL FE, laboratorij LMSE (Laboratorij za mikrosenzorske struk­ture in elektroniko) in LPVO (Laboratorij za fotovoltaiko in optoelektroniko). Svoje bogate izkušnje je prof. Furlan prispeval v mno­gih uspešnih raziskovalnih projektih, tako v povezavi z domačimi in mednarodnimi raziskovalnimi institucija­mi kot v sodelovanju z industrijo. S podjetji je bilo naj­tesnejše in najplodnejše sodelovanje z Iskro Tovarno polprevodnikov v Trbovljah. Vsa leta aktivnega delovanja na Fakulteti za elektroteh­niko je prof. Furlan tudi zelo zavzeto predaval mnoge predmete in napisal večje število izvrstnih knjižnih del in učbenikov s področja elektronike, polprevodniških in drugih elektronskih elementov ter integriranih vezij. Tako univerzitetnih kot srednješolskih učbenikov. Na Fakulteti za elektrotehniko je predaval vrsto dodiplom­skih in podiplomskih predmetov, od osnov elektroni­ke do mikroelektronike, polprevodniških elementov in pasivnih elementov, optoelektronike, sončnih celic, te­orije polprevodnikov ter teorije šumov. Predaval je tudi predmete dodiplomskega in podiplomskega študija na Fakulteti za naravoslovje in tehnologijo, UL in tudi izva­jal predavanja za izredne študente v centrih Ljubljana, Kranj in Novo mesto. Prof. Furlan je vsa leta zelo prizadevno, kot izjemno po­zoren mentor, vodil tudi raziskovalno delo študentov in mladih raziskovalcev podiplomskega in doktorske­ga študija. Njegovi študentje in diplomanti so postali vodilni razvojniki, direktorji, znanstveni svetniki in celo redni profesorji. Rezultati opravljenih raziskav prof. Fur­lana, v sodelovanju z mlajšimi sodelavci in podiplom­skimi študenti, so bili objavljeni v mnogih skupnih pub­likacijah, ki so izšle v številnih znanstvenih revijah in na specializiranih konferencah doma in v tujini, o čemer priča tudi njegova izredno bogata bibliografija. Prof. Furlan je imel tudi vrsto vabljenih predavanj na ugled­nih univerzah v Evropi in v ZDA. Na Fakulteti za elektrotehniko je med drugim vrsto let vodil Oddelek za elektroniko in bil dolga leta predstoj­nik Katedre za elektroniko. Bil je tudi prodekan za pe­dagoško delo in predsednik komisije za podiplomski študij. Prof. Furlan je bil tudi izumitelj. Prijavil je več izumov in patentov. S področja polprevodniških struktur in in­tegriranih vezij je npr. prijavil novo vezje polnega sešte­valnika, integrirano MOS izvedbo elektronskega časov­nega izbiralnika in novo strukturo modificirane CHIL celice. S področja fotovoltaike je najbolj znan ameriški patent o paralelni tandemski sončni celici iz amorfnega silicija. Za svoje bogato pionirsko, znanstveno-raziskovalno in pedagoško delovanje na področju polprevodnikov, mikroelektronike in fotovoltaike je prof. Furlan prejel številna priznanja in nagrade. Med prvimi učitelji na FE UL je prejel Vidmarjevo nagrado za odlično pedagoško delo. Za raziskave optoelektronskih lastnosti monokristalne­ga in amorfnega silicija je s sodelavci leta 1989 prejel nagrado Sklada Borisa Kidriča. Za pomembne dosežke v IEEE organizaciji je prejel IEEE Third Millenium Medal. Leta 1990 je za posebne zasluge in uspehe pri delu pre­jel Red dela z zlatim vencem. Leta 2000 mu je Univerza v Ljubljani podelila naziv za­služnega profesorja Univerze v Ljubljani. Slika: Podelitev nagrade Sklada Borisa Kidriča 1989 Prof. Furlan je kljub formalni upokojitvi konec leta 1999 ostal zelo aktiven in nadaljeval z iskanjem odgovorov na nova, nerešena vprašanja na področju polprevodniških elementov in fotovoltaike. V sodelo­vanju z mlajšimi raziskovalci je z navdušujočo energijo, zavzetostjo in pronicljivostjo razčlenjeval in pojasnje­val nove pojave na omenjenih področjih, kar je vodilo do novih spoznanj ter do znanstvenih objav v medn­arodnih publikacijah tudi 15 let po upokojitvi. Celotna fakulteta, še posebej pa Katedra za elektroniko je z globoko pretresenostjo prejela žalostno vest, da je srce pionirja slovenske elektronike in vsem nam pre­dragega zaslužnega profesorja Jožeta Furlana zastalo. V imenu Katedre za elektroniko izrekava globoko sožalje gospe Dragici Furlan in otrokom Ariani, Alenki, Tamari, Andreju, doktorici Tjaši Furlan in vnukom ter vsem žalujočim. Prof. dr. Jože Furlan je pustil neizbrisljive sledi in z ve­likim spoštovanjem ga bomo ohranili v trajno lepem spominu. Slava mu! Prof. dr. Slavko Amon Prof. dr. Marko Topič In memoriam Prof. dr. Jože Furlan 147 – 149 In memoriam Prof. dr. Jože Furlan 147 – 149 Boards of MIDEM Society | Organi društva MIDEM MIDEM Executive Board | Izvršilni odbor MIDEM President of the MIDEM Society | Predsednik društva MIDEM Prof. Dr. Marko Topič, University of Ljubljana, Faculty of Electrical Engineering, Slovenia Vice-presidents | Podpredsednika Prof. Dr. Barbara Malič, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Iztok Šorli, MIKROIKS, d. o. o., Ljubljana, Slovenija Secretary | Tajnik Olga Zakrajšek, UL, Faculty of Electrical Engineering, Ljubljana, Slovenija MIDEM Executive Board Members | Člani izvršilnega odbora MIDEM Darko Belavič, HIPOT-RR d.o.o., Otočec, Slovenia Dr. Slavko Bernik, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Miha Čekada, Jožef Stefan Institute, Ljubljana, Slovenia Prof. DDr. Denis Đonlagič, UM, Faculty of Electrical Engineering and Computer Science, Maribor, Slovenia Prof. Dr. Leszek J. Golonka, Technical University Wroclaw, Poland Dr. Vera Gradišnik, Tehnički fakultet Sveučilišta u Rijeci, Rijeka, Croatia Leopold Knez, Iskra TELA d.d., Ljubljana, Slovenia mag. Mitja Koprivšek, ETI Elektroelementi, Izlake, Slovenia Prof. Dr. Miran Mozetič, Jožef Stefan Institute, Ljubljana, Slovenia Prof. Dr. Janez Trontelj, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Dr. Danilo Vrtačnik, UL, Faculty of Electrical Engineering, Slovenia Supervisory Board | Nadzorni odbor Prof. Dr. Franc Smole, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Prof. Dr. Drago Strle, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Igor Pompe, Ljubljana, Slovenia Court of honour | Častno razsodišče Darko Belavič, Slovenia Dr. Marko Hrovat, Slovenia Dr. Miloš Komac, Slovenia Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials ISSN 0352-9045 Publisher / Založnik: MIDEM Society / Društvo MIDEM Society for Microelectronics, Electronic Components and Materials, Ljubljana, Slovenia Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale, Ljubljana, Slovenija www.midem-drustvo.si