SWITCHING NOISE IN DISTRIBUTED CLOCK SYSTEMS
Dušan Raič
Faculty of Electrical Engineering, University of Ljubljana, Slovenia
Key words: electronics, integrated systems, A-D integrated systems, analogue-digital integrated systems, mixed design, substrate noise, switching circuits, switctiing noise, distributed clock signal, noise optimization, design results
Abstract: Substrate noise is a serious limiting factor in the design of analogue-digital systems. Distributed clock systems can be used as an efficient method to solve the crosstalk and simultaneous switching noise associated with the data processing and clock distribution. In this paper we concentrate on the switching noise model for clock pipelines in orderte find some interesting parameters for the circuit design. Expressions for clock transition time, switching current ripple and optimal clock symmetry are given. The comparison of an optimized clock pipeline, consisting of N stages with the central clock buffer shows that substrate noise due to the power bus voltage drops can be reduced approximately by 1.2-/V. Similarly, the reduction factor for substrate noise due to carrier injection from clock nodes can be as high as » 0.75-A/.
Preklopni šum v sistemih s porazdeljenim signalom ure
Ključne besede: elektronika, sistemi integrirani, A-D sistemi analogno digitalni integrirani, snovanje mešano, šum substrata, vezja preklopna, šum preklopni, signal ure porazdeljeni, optimizacija šuma, rezultati snovanja
Izvleček: Šum substrata je eden od pomembnih faktorjev ki omejujejo integracijo analogno-digitalnih sistemov. S porazdelitvijo signala ure lahko pomembno zmanjšamo presiuhe in preklopni šum, ki je povezan z signalom ure in z obdelavo podatkov. V delu raziskujemo model preklopnega šuma v razvodu ure in poiščemo nekatere najbolj pomembne parametre za načrtovanje. Izvedeni so izrazi za čas prehoda signala ure, za stresanje toka napajanja in za optimalno simetriranje signala ure. Primerjava optimalno porazdeljenega signala s klasičnim pokaže, da v sistemu z N stopnjami lahko dosežemo zmanjšanje šuma v substratu za faktor »1.2'N zaradi zmanjšanih konic v napajalnem toku in za faktor » 0.75-N zaradi manjšega vpliva signala ure na substrat.
1.	Introduction
In distributed clock systems the central clock is replaced by a large number of time-distributed signals, generated by a clock pipeline. In the simplest form the pipeline can be built as the chain of invertors integrated with the flip flops and logic gates /1/. If the system layout is done in such a way that pipeline stages are put close together with their loads, noise performance of the circuit as a whole can be improved significantly.
2.	Switching properties of the
distributed clock driver
The CMOS load is a combination of parasitic capacitances to Vdd, represented as Cp and parasitic capacitances to Vss, represented by Cn- To analyze the circuit speed, all capacitances can be treated as one single load Ci = Cp + Cn connected to Vss. However, for the switching noise analyze the mode how the capacitances are connected with regard to power supply and the driving stage becomes important and the two capacitances must be treated separately. As presented on Fig.1, the power bus currents are different from the currents in the driving stage; they are smaller and different at the rising or falling edge of the signal.
Dynamic characteristic of the CMOS inverter becomes very complex if the slope of the input signal is comparable to the output signal slope. However, the influence of input signal waveform on the output is limited because of nonlin-
earities in the vicinity of the threshold voltage. If we apply a ramp function to the input of the chain of equally loaded inverters, such as presented on Fig.2, the responses converge rapidly to a 'characteristic' waveform /2/ that is independent from the initial signal slope. The most important measure for clock driver noise analyze are the slew rates of the rising and falling edges in the characteristic waveform, measured at their maximum value. These values are very close to slew rates measured at Vdd/2'.
rii]!iiig cdgo cunvnis kir- lop f Icii lb - icp
__^ - li^itlg CfigO CUITOHIS
k!r Icp : Icn lb - Icn
Figure 1: Load currents in the CiVIOS buffer with local loads; power bus currents are different from the driving transistor currents
s, - max
s J- - max
fdv(t)^	^ dv{t)		
dt V /	dt	v(i)=vd(l/2	(1) V(
f-dv(t)^	^ dv{t)
dt	dt
v{i)=vdd /2
(2)
In general, Sr and si are not equal so that it is appropriate to define the slew rate symmetry ss
s..
ss = ■
(3)

Clocl< drivers are usually based on equal slope design (ss ~1) to achieve best noise immunity and waveform symmetry. For this type of characteristic, the threshold voltages and gain factors (Kp, Kn) for PMOS and NMOS transistors must be equal /3/.
Table 1:Peak currents in the power bus and in the driving transistors
l(peal<)	Power bus	Driving transistor
Rising edge	sr -Cn	sr ■ (C„+C,)
Falling edge	sf -Cp	sf -(C^+C,)
Table 1 shows the difference between peak currents in the power bus and driving transistors in a single CMOS clock buffer. To achieve the symmetric characteristic, the P-transistor must be larger than the N transistor so that Cp ~ 3Cn. Under these conditions the difference between rising and falling edge bus current spikes becomes considerable. For purposes of noise analyze we will use

(4)
The simplified presentation of switching currents in stage / and the neighboring stages is shown on Figure 3. The interaction of delay times and signal slopes determines how individual switching currents are summed in time to form the power supply current.
li-i
Vosc
tp VI
On :::
Cp
VV1
Cp Vi
Cn
Figure 3: Bus currents in the chain of inverting buffers with local loads
Due to the serial signal passing across the buffer chain only a few stages are active at a given time. The sum of power supply currents in the chain depends on the interaction of delay times and the shape of the switching waveforms, but is independent of the chain length (Fig. 4).
If stage / is considered as reference stage in the clock pipeline, neighbor activity an can be defined as the ratio of slew rates in neighboring stages and the reference stage, measured when the reference output reaches Vdd/2:
(X.. =

25,,
(5)
In the case when slew rate of the reference signal is larger than slew rates of it's neighbors, the switching point in stages with lower slew rates comes closer to Uc/o/2 so that an increments. Neighbor activity in pipelines with non-symmetric switching characteristics is therefore different if measured at the rising edge or at the falling edge of the reference signal. However, as long as we are not too far from the symmetric case, values for both edges are close to each other so that an average value can be substituted.
Inia.x
li-H
Cp
ViH
Cn
Cp Vn
Cn
Vdd
Td " (Tlh +Thl)/2
T d
Td
Figure 2: The distributed clock driver as the chain of inverting buffers
* ichain.cir
1.5
> 500m 11
10u ' 8u -
S" 8u -
I
§ 4u -Ü
2u -0 .,
10u 8u
S 6U "
I
g 4u Ü
2u
0
X-
eon
80n
120n
140n 160n Time (lin) (TIME)
ichain.cir
200n
220n
240n
300n
140n 160n Time (lin) (TIME)
* ichain.cir
140n 160n Time (iin) (TIME)
Figure 4: Accumulation of local currents into the supply current for the case when siCp>SrCn. Upper pane represents output signal in stage j; current contribution of stage j is shown by dashed line In the middle pane against the total supply current (solid line). Dashed lines in the lower pane represent current contribution of stages 1, k against total supply current (solid line). On the rising edge, the supply current is dictated by currents in stages 1, / that exhibit falling edges; on the falling edge, it is dictated by the current spike in stage i. The difference between solid line and the dashed lines (~ 20%) is due to the activity of the neighboring stages. The circuit, based on Figures 1 and 2 with N = 8, was simulated at Vdd = 2Vt, C; = lOCgand SfCp = 2.5srCn ■
The average value in the range Kp/Kn ~ 0.5...2 is practically independent from Kp/Kn and load capacitances (Fig.5). With a series of simulations for circuits with equal absolute threshold voltages for P and N-type transistors we have found a satisfactory approximation for an as
a = 0.555
-V-r V,
(6)
If we take into consideration supply currents in the driving stage and in the closest two neighbors, the total supply current for rising edge signal is equal to
I = V r
^dd.rise ^r^i

where Sj stands for slew rate in the neighboring stages when Sr is maximal:

so that

(7)
Current peak for the falling edge signal can be expressed in a similar way. Once both current peaks are known, we can define the relative supply current ripple as
r.. =
(Id, rise
- ss -
^M.fall
C„+2a„C„
(8)
For each signal transition on the input, active driver stages draw supply current Idd(t). As the signal travels along the pipeline, Idd(t) alternates between leading edge [Idd.rise) and trailing edge {Iddjaii) peaks. Signal transition time for the whole chain is given by
a
0.4 --
0.3
0.2 --
0.1 --
rising edge
falling edge
/
1.0
2.0
3,0
K /K P '
Figure 5: Activity of the first neighbors (stages i-1, i+1), measured when V, in the reference stage reaches Vdd/2.
Activity of stages next to the dosest neighbors is practicaily equal to 0. The dashed line shows rising/ falling edge average.
T +T T = N "'
2
(9)
Maximum supply current takes place in stages with rising edges if Tf > 7, or in stages with falling edges if the relation is opposite. Regardless of the case, maximum current occurs in every second stage so that the ripple period is equal to
T -T +T
pair ' Ih ' ' hi
(10)
In general, the entire switching event must be covered. Rising and falling edge currents are equal as long as we treat the optimized pipeline as a whole, but they can be different inside individual stages. Forthat reason the single stage current must be expressed by the average of rising/ falling edge values, so that ap of a noise-optimized pipeline can be given by

I

dd.risi'.slage ^dd,fall,slage
3. Noise optimisation
The supply current ripple can be minimized if the rising and the falling edge peaks are made equal. By setting rr = 1, equation 8 gives optimal clock symmetry
ss ~
"opt
p + 2a,
(11)
l + 2a„p
If we now apply equation 6, we get optimal Kp/Kn ratio as
K..
= 2ss -1 =
Jopl
3 + {l-a„Xp~2) 2{i + 2a„p)
(12)
For purposes of noise analyze it is convenient to define the pipeline activity ap as the ratio of switching currents of the entire driver chain and one single stage:
_ ^dd .rpipc'line
dd, St age
I
dd, fall, pipeline
^ dd jise,stage ^ dd .fall,stage
From the second expression we get

ss + p
Application of optimal symmetry from equation 11 gives
(14)

a,jr + p+ a„
(15)
In spite of quadratic form the pipeline activity ap shows almost linear dependence from an and p in the range of common design conditions. Influence of p is very low because the pipeline is optimized. In most cases ttp evaluates to values around 1.4 ~ 1.5.
4. Results
The power bus relaxation of a distributed clock system compared to the central clock system can be estimated by the ratio of peak supply currents. If Cl is the total load of a central clock buffer then the load of an equivalent N-staged clock pipeline would be given by
c,=yv(c„+cj
We can assume that the central clock buffer has got symmetric switching characteristic, defined by s = (Sr +Sf)/2. In favor of fair comparisons we will consider only the last stage of the central clock driver. According to table 1, the switching current in that stage would reach
Lki central = S - Cj . The Switching current of the distributed driver can be expressed by the average single stage current and rxp, so that we can define the power bus relaxation factor R as
R =
I
(Id x'cn I ml
cicLpipeline
(s, +,i,)/v(c.+cj
a
Application of equations 14 and 11 gives
{p + l)\2a„+l) 2/;+ 4a„ (/; + !)'
R = N
(17)
For a typical design case with p = 2 and an = 0.15 we get ft = 1.24 N. Bus relaxation factor larger than N can be explained by optimal weighting of rising/falling edge currents and local load discharging in the pipeline, leading to a situation where discharge currents disappear from the power supply lines.
Substrate noise reduction has somehow different background. Since only one pipeline node is active at a given time, we can assume that the coupling capacitance of clock nodes is virtually reduced by N. If the pipeline activity is considered as well then a rough estimation for substrate noise reduction can be given by
5 =
N
a..
(18)
We see that substrate noise reduction is smaller than f?, particularly because equation 18 is probably too optimistic. Typical values for S can be expected somewhere from 0.5 A/to 0.75 W.
It has to be pointed out that above noise reduction assessments are valid for clock pipeline alone. Although being known as an important source of switching noise, the clock driver is not the only noise generator Regular structure of the pipelined driver allows relative high values for R and S that cannot be achieved in other parts of the system.
5. Conclusion
One way to distribute activities of a synchronous digital system in time is to replace the central clock by a large number of equally delayed signals generated by a clock pipeline. The sum of switching currents in this case produces pulses with low amplitude and long duration, leading to substantial reduction of supply current spikes in comparison to systems with central clock. The resulting power bus relaxation and substrate noise reduction are beneficial for both pure digital and mixed projects.
Pipeline clocking has the potential to reduce three important noise sources: power bus bouncing, signal cross-talk and substrate noise, in order to find optimal design measures for noise reduction, switching properties of clock pipelines have been studied. Neighbor activity has been defined as the basis for calculation of a number of important parameters, among which supply current ripple, ripple frequency and length, optimal symmetry and the Kp/K n ratio have been found. Assessment of power bus relaxation and substrate noise reduction have been given as well.
References
/1/ D.Raič, "Method for switching noise reduction". Electronics
Letters, vol, 35, pp. 1794-1795, October 1999. /2/ J. R. Burns, "Switching Response of Compiernentary-Symme-try MOS Transistor Logic Circuits", RCA Review, vol. 25, pp. 627-661, December 1964. /3/ N. M. Rabaey, "Digital Integrated Circuits: a design perspective", Englewood Cliffs, NJ: Prentice-Hall, 1996
Dušan Raič Faculty of Electrical Engineering Tržaška 25 SI 1000, Ljubljana Slovenia
E-mail: dusan. raic@fe. uni-lj. si
Prispelo (Arrived): 26.10.01
Sprejeto (Accepted): 10.12.01