Možnosti izvedbe adaptivnega FIR sita s programirnimi (FPGA) vezji - Osebik, Davorin (Informacije MIDEM, 2002)
The FPGA circuits have become a good alternative for digital signal processing appplications. In this article the mathematical description and computer simulation of the hardware implementation of the adaptive FIR digital filter structure in FPGA circuits is presented. The hardware implementation of digital filter structure is based on the use of distributed arithmetic filter arhitecture which uses no multipliers in its realisation of the filtering functions. Adaptive digital filters are successfully used in different fields, such as communication, radar, sonar, seismic, and biomedical engineering. Almost all of these adaptive filters have one common characteristic that a reference input signal vector u(k) and primary signal d(k) are applied to compute an estimation error signal e(k), which is used to control the values of adjustable digital filter coefficients h(k). The presented adaptive digital FIR filter which is carried out with programmable gate array could be used for noise cancelling from the corrupted input signal. The basic application of adaptive structure is shown in block diagram in figure 2. The first unit is the FIR filter structure, which determines the output values y(k) with distributed arithmetic principle by equations 6. The partial sums of filter coefficients signed as vi and defined with equations 6, are calculated from vector of filter coefficients h(k) and the vector of inputs u(k), by using of equation 12. Because of current calculations of their adapted values, they can not be stored in the ROM memory as in the ROM-accumulator structure of classical distributed arithmetic realisation /5/.The 16 taps FIR digital filter structure, made within FPGA circuit XC4013 is shown in figure 3. The hardware complexity is accomplished with 16 bits input and output word length and with 16 to 24 bits word length of arithmetic-logic unit. The second unit in the figure 2 is the structure for adaptive filter coefficients calculation, where the least-mean-square (LMS) adaptation algorithm is used. The coefficients of nonrecursive filter vector h(k) was initially obtained from equations (2) and (3) and from (16), (17) and (19) respectively. In these equations ?$/mu$? is the step of adaptation, e(k) is the estimation error signal, and u(k) is the reference signal as the input signal in the FIR filter. The product of the e(k)u(k) from (15) is also implemented with distributed arithmetic technique, where the seriallogic of arithmetic operation is used. The hardware complexity of the structure for adaptive filter coefficients calculation rises linear with number of taps. In figure 4 the block diagram of unit for adaptive filter coefficients calculation is shown. For complexity of 16 taps and 19 bits of arithmetic and logic unit the structure is made within one FPGA circuit XC4020E and a adapted set of the taps is obtained every 10 ?$/mu$?s. The whole hardware structure was simulated with OrCAD Express and Xilinx XACT 5.2. With 20MHz clock frequency the input signals u(k) and d(k) sampling frequency of 100 kHz was obtained. The results of presented adaptive digital filter application are shown as noise cancelling from corrupted input signal. In this application the street noise signal is taken into account. The results depends on the signal to noise (S/N) ratio of the input signal. At S/N ratio of the input signal of about -20dB the noise component is successfully eliminated, and improvement of S/N ratio of 22dB is obtained. The results are shown as comparision of input reference, primary signal and output signal in the time and frequency domain in the figures 6,7 and 8 and as power S/N ratios of the input signal (Pvh), output signal (Pizh) and improved output signal (Praz) in the figure 11 respectively.
Keywords: digitalna obdelava signalov; digitalna sita