Elektrotehniški vestnik 85(5): 248-254, 2018 Original scientific paper
On Realization of a New High-Precision and Low-Power CMOS Analog Multiplier Circuit
Tohid Aghaei1, Ali Naderi Saatlo*2
1Young researchers and elite club, Urmia Branch, Islamic Azad University, Urmia, Iran 2Department of Electrical-Electronics EngineeringUrmia Branch, Islamic Azad University, Urmia, Iran. *corresponding author, E-mail: a.naderi@iaurmia.ac.ir
Abstract. This paper proposes a new current-mode four-quadrant analog multiplier in the CMOS technology based on dual translinear loops. Compared with the previous works, this circuit has a simpler structure resulting in a higher frequency response, low-power consumption and low body-effect error. The circuit is thoroughly analyzed in terms of the of body-effect error and its results are presented. In order to verify its performance, the circuit is used in two useful applications: as an amplitude modulator and frequency doubler. The circuit is designed and simulated using HSPICE and 49 parameters (BSIM3v3) inthe 0.18 ^m technology. The simulation results demonstrate the linearity error of 0.76%, THD of 0.92 in 1MHz, -3dB bandwidth of 104MHz and maximum power consumption of 0.18mW. the Monte Carlo analysis is carried out to ensure robustness of the circuit performance against process variations.
Keywords: Analog multiplier; current mode; translinear loop; four-quadrant; low power.
Zasnova analognega množilnika z visoko natančnostjo in majhno porabo moči v tehnologiji CMOS
V članku predstavljamo nov tokovni štirikvadrantni analogni množilnik v tehnologiji CMOS na osnovi dvojnih povratnih vezav. V primerjavi z obstoječimi množilniki ima predlagani množilnik preprostejšo zgradbo, kar ima za posledico višji frekvenčni odziv, majhno porabo moči in manjšo strukturno napako. Delovanje vezja in njegovo zmogljivost smo preverili pri zasnovi amplitudnega modulatorja in frekvenčnega podvajevalnika. Vezje smo zasnovali in simulirali s programskim paketom HSPICE in parametri level 49 (BSIM3v3) v tehnologiji 0.18 ^m. Rezultati simulacij potrjujejo napako linearnosti 0.76 %, 0.92 THD pri 1MHz, pasovno širino 104 MHz in največjo porabo moči 0.18 mW. Z analizo Monte Carlo smo preverili zmogljivost vezja glede na odstopanja v tehnološkem procesu.
1 Introduction
The intensive use of analog multipliers as an essential building block of the analog signal system in a multitude of applications, such as modulators, frequency doublers, artificial networks, fuzzy integrated systems, automatic gain controlling [1-4], is the key driving factor for their considerable study and conception. The multiplier provides a product of two continuous signals, such as x and y, yielding an output of z = Kxy, where K is a constant value with a suitable dimension. The linearity, speed, bandwidth and power dissipation are the main goals of the design. At present, the power consumption is a key parameter in designing a high-
performance mixed-signal integrated circuit. Some of the multipliers [5-9] are not optimal for the low-voltage and low-power applications. Several techniques for reducing the power consumption in circuits of this type have recently been proposed, they include the floating gate technique [10-12], bulk-driven method [13, 14], subthreshold mode [15, 16], or class-AB mode [17, 18]. However, these analog multiplier circuits have been proposed either in the voltage or current modes.
One of the important classes of multipliers which uses current-mode technique is based on the translinear loop (TL) principle [19-21]. TL is a special device arrangement that allows a useful large signal relationship among its currents [19]. Usually, the devices employed in the TL loops can be BJT, MOS transistors or diodes. If diodes are used, usually an extra active circuit is required [21]. The advantage of this circuit is independence of the output current expression on technological parameters and the circuit operation is not affected by temperature variations, ideally.
Considering the operation region of the TL transistors, they can be classified in two classes: weak inversion [22-24] and strong inversion [25-29]. For the weak inversion, although it leads to circuits offering a low power dissipation, the bandwidth and dynamic range are limited. For the TL circuits in the strong inversion, the error resulting from the body effect is a serious problem for causing a mismatch in the threshold voltages which in turn, affects the linearity and precision of the circuits. However, in some studies this
Received 24 June 2018 Accepted 24 August 2018
ON REALIZATION OF A NEW HIGH-PRECISION AND LOW-POWER CMOS ANALOG MULTIPLIER CIRCUIT
249
effect is properly discussed and a few techniques are proposed [30,31]. Also, some CMOS multiplying circuits are designed using MOS transistors operating in the linear region [31-33]. Several CMOS multiplying circuits are designed using a short-channel MOSFET, but they has not compensate for the error due to the carrier mobility reduction [34-38]. Therefore, the accuracy of these circuits is degraded.
In this paper, a new topology of the analog-multiplier circuit based on a translinear loop is presented. Its main advantages are a high-precision performance as well as low power dissipation. In order to verify the efficiency of the performance circuit, the error caused by the body effect is analyzed and then minimized in the simulation results. Moreover, to prove the process and threshold voltage-variation effect on the circuit performance, the Monte-Carlo simulation is adopted. The paper is organized in five sections: The proposed method for implementation of the multiplier circuit as well as the transistor level design are presented in section 2. In section 3, the HSPICE simulation results of the proposed circuit are presented to prove the efficiency of the design. The performance analysis of the circuit is described in section 4. Finally, conclusions are outlined in section 5.
2 CircuitDescription
The principle of operation of the proposed multiplier is based on the square-difference algebraic characteristic:
transistor.Applying KVL in the first dual translinear loops yields:
V +V = V +V
r GS i GS 2 r GS 3 GS 4
(4)
Assuming that all CMOS transistors operate in the saturation region, using Equation (2) and Equation (3) and considering IDS3 = IDS4= IB , we have:
"J1 DS1 ^ V1DS 2 ^DS 3 ^ V1DS 4
"J1 DS1 +*<JIDS 2 ~
Writing KCL at nodes A and Bas:
1DS 2 ~ 1DS1 +1 in1 Io1=IDS 1+ Ia
(5)
(6)
(7)
(8)
Since IDS2 = Ia and substituting Equation (7) in Equation (8), we have:
Ids 1 = (loi -Iini)'2
IDS2 = (Ioi +1ini) / 2
(9) (10)
Substituting Equation (9) and Equation (10) in Equation (6) and squaring both sides:
(X +Y )2 — (X —Y )2 = 4XY
(1) 4Ib = Ioi — (Iini / 2) + ( I in i / 2) + 2jl012— Ini2 (1 1)
Thus, subtraction, summing and squaring are the operations needed to be done for the multiplier circuit. To generate Equation (1) in an analog multiplier circuit, two squarer blocks are required toproducea two-squarer function and its outputs need to be subtracted. Fig. 1 shows the proposed four-quadrant CMOS analog multiplier circuit. It is based on two dual translinear loops. The first loop, consisting of (M1 - M4), realizes the (X -Y)2 function and the second loop, consistingof(M3 - M6),therealizes the (X + Y) 2 function. The drain current of the MOS transistor operated in the saturation region is given by:
Ids =k (Vgs —vt )
(2)
Eliminating Iin1/2 and squaring both sides again yields:
16I b 2" 8IBIO1=~I,„12	(12)
Then, the output current of I01 can be written as:
(13)
I 2 I	+ 2I
0i 8I ß B
In asimilar way, for Io2 we have:
' DS 3 ^ yJIDS 4 ^/_' DS 5 ^ yJI DS 6
(14)
VGsS = Vt +
K
(3)
Where K = 0.5^0COX(W/L) is the transistor transconductance parameter, n0 is the electron mobility, Cox is the gate oxide capacitance per unit area, W/Lis the transistor aspect ratio, Vcsis the gate-to-source voltage and Vt is threshold voltage of the MOS
and:
IDS 5 IDS 6 ^I in 2	I I DS 6 (I o 2 I in 2)/2
I o 2 I DS 6 + Ib
resulting:
Ids 5 = (i o 2 + inn 2)/2
(15)
DS
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AGHAEI, SAATLO
T8 T
\lol
^hhS ^pP Si—
¡in!
GND
Figure! .Proposed current-mode analog multiplier circuit.
(16)
I 2
o2 8Ib
The total output current of Iout is given by:
I out _ Io 2 - Io!	(17)
Considering Iin1 = IX—IY and Iin2 = Ix+Iy, and substituting Equation(13) and Equation (16) into Equation (17) results in:
I _ IXIY
out 2I „
(18)
As clearly seem from Equation (18), the output of the proposed circuit yields a multiplication of Ix and IY divided by the constant current of 2IB hereIB is a constant current of lO^normalized to one.
3 Simulation Results
The analog multiplier circuit of Fig. 1 is simulated using HSPICE with the0.18 pm CMOS technology, the supply voltage is 1.8 V and the bias current of IB is set to 10^A. As mentioned, Equations (13) and (16) are the current squarer of the input signals, and thesimulation result of thefirst squarer circuit is shown in Fig. 2 where the upper waveform is the input current, the middle waveform is the output current and the bottom waveform shows the error measurement. The average error in this simulationremains as low as 0.29 %.
3. 3
3.
Time (//s)
Figure 2. Simulation results of thecurrent squarer of the input signal (lln1) in the loop (M1 — M4) and error measurement (frequency = 1 MHz).
Fig.3 shows the DC transfer characteristic of the proposed analog multiplierwhere/^ is set to a pulse with a variable amplitude from -20^.4 to 20/^A to varying IY from -10^.4 to 10^4 As a result, the output current varies from -10^4 to 10^^.Within this range, the measured nonlinearity error is 0.76 %.
1 2
£ -2 -4 -6 -8 -10
		i. -1 L ______;.._..]______
X.		
, i i " i-		^----
		— | | N.
i/		
		
-20 -16 -12 -8
Ix(M)
Figure 3. Simulation results of thecurrent squarer of the input signal (lln1) in the loop (M1 — M4) and error measurement (frequency = 1 MHz).
ON REALIZATION OF A NEW HIGH-PRECISION AND LOW-POWER CMOS ANALOG MULTIPLIER CIRCUIT
251
Fig. 4 shows results of other simulations with error measurements in which Ix and IYare sinusoidal at 200 KHz with amplitudes of 10^.4 and 5pA, respectively, which yields a sinusoidal output with a high precision that marked with ared line. Within this range, the measured nonlinearity error is 0.76 %.
0
-5
-10 60 40 20 0 -20 -40 -60
the proposed multiplier, while the bias currentis constant. Fig. 8 shows how the multiplier circuit can be employed as a frequency doubler. If both frequencies of the input currents are 1 MHz, the figure shows the corresponding output waveform with adouble frequency as well as the error quantity.
0	2	4	6	8	10
Time (/v s )
Figure 4. Other simulations of theanalog multiplier circuit in 0.2 MHz and error measurement.
Fig. 5 demonstrates the total harmonic distortion (THD) versus theinput signal at 100 kHz and 1 MHz simultaneously. The simulations are performed for both Ix and IY, in which one of them is constant andthe other one is sinusoidal. In the worst case, the input signal of 20^AP-P at a frequency of 1 MHz results in THD of less than 0.92 %.
--1 MHz (Iy=const.)
—A— 100 kHz (Iy=const.) --o— 1 MHz (Ix=const.) -□-100 kHz (Ix=const.)
0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30
Frequency (Hz)-1,04e-KX)8 Current (dB)=-3.00e*-000 Derivative^ .22e-008
10
10
10°
10
10°
10'
10*
10*
Frequency (log) (Hz)
Figure 6. Frequency response of the proposed circuit.
3 2
i O
-100 -zoo
Figure 7. Proposed multiplier as an amplitude modulator. A1 MHz carrier sinusoid and 100 kHz modulating signal (upper waveform); AC modulated output (middle waveform); Error measurement (lower waveform).
Figure 5. Relation between THD ,lx and ly.
The frequency response of the circuit in Fig. 6 shows thatthe -3dB bandwidth is 104 MHz when the input signal is applied to lxand IY = 10 ^A. It should be pointed out that the input signals are applied in where the circuit output is 0 dB for aprecise measuring ofthe-3 dB bandwidth of the circuit. Thetotal power consumption is 0.18 mW.
Fig. 7 demonstrates the multiplier being used forthe balance modulator. Ix and/y are 1 MHz and 100 kHz, with avariable amplitude froma -20ßA to 20ßA carrier and modulation signals, respectively, fed to theinputs of
-50 -100 -150 -200
Time C
Figure 8. Proposed multiplier as a frequency doubler: a) input waveform (upper); b) output waveform (middle); c) error measurement (lower).
0,8
0,6
0
0
5
10
15
20
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AGHAEI, SAATLO
4 Performance Analysis
Assuming IB = KhV2and squaring both sides of Equation (24), current I'out can be expressed as:
In this section, the characteristics of the analog multiplier in the terms of the body-effect error and threshold-voltage mismatch in a translinear loop are discussed. TheMonte Carlo analysis and temperature-variation simulations are carried out to verify the circuit performance of process variation conditions
4.1 Body Effect Error
In the MOS transistor, thebody effect refers to achange in the transistor threshold voltage resulting from a voltage difference between the transistor source and substrate, characterized by:
I 2
J t _ __in_
out 8K A V (A V + 28)
+
2K AV (AV + 28) (25)
In this equation we can see that themismatch error Between the threshold voltages is dispensable, because AV » 28.
Subtracting Equation (18) from Equation (25), we obtain theoutput-current error quantity:
1 = / . -IL =
out	out
8K AV
2K AV
Vt =Vt 0 + X
V(2 + Vsb I) -
(19)
Where Vt0 is the zero-bias threshold voltage, y is the body-effect coefficient and is the bulk potential. To avoid this effect, the cascaded MOS transistors are placed in separate wells and VSB will be zero. Thus, these transistors will have azero-bias threshold voltage.
Let us consider the first translinear loop, consisting of (M1 - M4). In athin loop, theM2 and M4 transistors bulk are connected to the ground, hence VSB = 0 and vt = vto, but intheM1 and M3 transistors VSB ± 0. Considering this mismatch betweentheM1 and M3 transistors, we can write
Vgsc =Vt i +AV1
V	_V +AV
V	GS 3 V 13 + AV 3
(20)
(21)
8K AV (AV + 28)
+ 2KAV (AV + 28)

8
4KAV 2 (AV + 28)
I,„2 - 4K 8AV
(26)
Ignoring theterms containing AVn(n = 3,4,5), S2
(27)
TermA73 in Equation (27) shows avery small error. The advantage of using the function(X + Y)2 -(X - Y)2 in the multiplier circuit is the possibilityto cancel the offset and body-effect errors by eliminating the second term in Equation (25). Consequently, the output current is given by:

Ixh
2Ib + 4 8K AV
(28)
Substituting Equation (20) and Equation (21) in Equation (4) yields:
V	+AV +V _V +AV +V
V	11 + AV 1 +V GS 2 V 13 + AV 3 +V GS 4
(22)
Where7t1 = Vt + S, Vt3 = Vt-S and 5 is the mismatch term between Vt1, Vt3. Rewriting Equation 6,
IdS1 = ¡DS2 = Ib, IdS3 = Q'out — hv)/2 , IDS4 = ^f
Iin and assuming^ = VtA(\VSBl = 0), we obtain

8 +

J3
K
(23)
Substituting I3 = (I'out — hn)/2 in Equation (23), squaring both sides and ignoring the terms containing S2 are get
4.2 Mismatch and Temperature Effects
The Monte Carlo analysis of the proposed circuit with 100 iterations is carried out by applying amismatch in thetransistors aspect ratio and threshold voltage withthe Gaussian distribution. This is done to ensure the robustness of the circuit performance against the fabrication process (see Fig. 9). The output of the multiplier without any mismatch shown in Fig. 5 is considered as an ideal output without any error (0%).The Monte Carlo analysis is theycarried outdemonstratingthat 91% of thetotal samples occurs with an error of less than ±1% forthan threshold voltage and transistors aspect-ratio variations.
88 /— + +
IK K
I '
. out
K
+
■\JlOut2
K
(24)
2
2
ON REALIZATION OF A NEW HIGH-PRECISION AND LOW-POWER CMOS ANALOG MULTIPLIER CIRCUIT
253
Ü 15
Q.
E
.- 10 o n E
Table 1 .Comparative parameters of the proposed multiplier with other recent works.
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Relative Error (%)
Figure 9. Monte Carlo analysis of the multiplier circuit for the mismatch in the transistors aspect ratio and threshold voltage.
Fig. 10 shows the circuiterror atvarious temperatures, while the maximum error occurring at 80 oC is 0.93 %. In this simulation, the obtained output at the temperature of 25 oC is considered as the reference value (relative error=0). The outputs in other temperatures are thancompared with that value and the relative error is computed. It should be pointed out that the input signals are the same as the signals applied in the Monte Carlo analysis. The equations should be written in italics and numbered:
	OJ T- 00 CD T * * J						
			g				
			© r r e				
			£ •-B «				
			&				
	0,2 -0						
		I—					
35
55
75
Reference
[5] [8] [19] [37] [38]
This work
Power						
consumption	0.7	0.47	0.52	0.34	0.15	0.18
(mW)						
Bias	100			10		10
current (^A)						
Power supply (V)	5	±1.5	2.8	3.3	±0.75	1.8
THD(%) (1MHz,20^A)	-	0.87	1.45	0.97	0.8	0.92
Nonlinearity (%)	-	1.3	1.12	1.1	1.1	0.76
-3db						
bandwidth	12.3	24.3	137	41.8	300	104
(MHz)						
Technology (pm)	2.4	0.35	0.18	0.35	0.18	0.18
References
[i]
-45 -25 -WFq
Figure 10. Relative error of the circuit versus different temperatures.
5 Conclusion
A four-quadrant CMOS multiplier based on dual translinear loops in a current mode is proposed. The performance of the multiplier is simulated using the HSPICE software. The simulation results indicate that the multiplier has remarkable benefits in terms of a high bandwidth (104 MHz), low-power consumption (0.18 mW), and low body-effect error. In order to verify the circuit performance, the designed circuit is used in two useful applications: the amplitude modulator and frequency doubler. Moreover to prove the process and threshold-voltage variation effect on thecircuit performance, theMonte-Carlo simulation was adopted. The characteristics of the circuit are summarized in Table 1 and compared with the former works to prove the efficiency circuit.
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Tohid Aghaei received his B.Sc. and M.Sc. degrees in Electronics Engineering from the department of Electrical and Electronics Engineering, Urmia Azad University, Urmia, Iran, in 2015 and 2018, respectively. His areas of interest include current-mode circuits design, low-power, VLSI circuits and CMOS analog integrated-circuit design.
Ali Naderi Saatlo received his B.Sc. degree in Communication Engineering from Urmia Azad University, in 2005, the M.Sc. degree in Electrical Engineering from Urmia University, Urmia, Iran in 2008, and the Ph. D in Electronics Engineering from Istanbul Technical University, Istanbul, Turkey in 2014. Since 2011, he has been a faculty member of electrical engineering department of Urmia Azad University. His research interests are analog and digital integrated circuit design for fuzzy applications, fuzzy sets and systems, high performance analog circuits, and digital signal processing. He is the author or co-author of about 20 papers published in scientific journals or conference proceedings.