Original scientific paper Original scientific paper 15 14 2 © MIDEM Society 3 © MIDEM Society 1 2 4 5 ISSN 0352-9045 Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 1(2017), March 2017 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 47, številka 1(2017), Marec 2017 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 1-2017 Journal of Microelectronics, Electronic Components and Materials VOLUME 47, NO. 1(161), LJUBLJANA, MARCH 2017 | LETNIK 47, NO. 1(161), LJUBLJANA, MAREC 2017 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2016. All rights reserved. | Revija izhaja trimesečno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale – Društvo MIDEM. Copyright © 2016. Vse pravice pridržane. Editor in Chief | Glavni in odgovorni urednik Marko Topič, University of Ljubljana (UL), Faculty of Electrical Engineering, Slovenia Editor of Electronic Edition | Urednik elektronske izdaje Kristijan Brecl, UL, Faculty of Electrical Engineering, Slovenia Associate Editors | Odgovorni področni uredniki Vanja Ambrožič, UL, Faculty of Electrical Engineering, Slovenia Arpad Bürmen, UL, Faculty of Electrical Engineering, Slovenia Danjela Kuščer Hrovatin, Jožef Stefan Institute, Slovenia Matija Pirc, UL, Faculty of Electrical Engineering, Slovenia Matjaž Vidmar, UL, Faculty of Electrical Engineering, Slovenia Editorial Board | Uredniški odbor Mohamed Akil, ESIEE PARIS, France Giuseppe Buja, University of Padova, Italy Gian-Franco Dalla Betta, University of Trento, Italy Martyn Fice, University College London, United Kingdom Ciprian Iliescu, Institute of Bioengineering and Nanotechnology, A*STAR, Singapore Malgorzata Jakubowska, Warsaw University of Technology, Poland Marc Lethiecq, University of Tours, France Teresa Orlowska-Kowalska, Wroclaw University of Technology, Poland Luca Palmieri, University of Padova, Italy International Advisory Board | Časopisni svet Janez Trontelj, UL, Faculty of Electrical Engineering, Slovenia - Chairman Cor Claeys, IMEC, Leuven, Belgium Denis Đonlagić, University of Maribor, Faculty of Elec. Eng. and Computer Science, Slovenia Zvonko Fazarinc, CIS, Stanford University, Stanford, USA Leszek J. Golonka, Technical University Wroclaw, Wroclaw, Poland Jean-Marie Haussonne, EIC-LUSAC, Octeville, France Barbara Malič, Jožef Stefan Institute, Slovenia Miran Mozetič, Jožef Stefan Institute, Slovenia Stane Pejovnik, UL, Faculty of Chemistry and Chemical Technology, Slovenia Giorgio Pignatel, University of Perugia, Italy Giovanni Soncini, University of Trento, Trento, Italy Iztok Šorli, MIKROIKS d.o.o., Ljubljana, Slovenia Hong Wang, Xi´an Jiaotong University, China Headquarters | Naslov uredništva Uredništvo Informacije MIDEM MIDEM pri MIKROIKS Stegne 11, 1521 Ljubljana, Slovenia T. +386 (0)1 513 37 68 F. + 386 (0)1 513 37 71 E. info@midem-drustvo.si www.midem-drustvo.si Annual subscription rate is 160 EUR, separate issue is 40 EUR. MIDEM members and Society sponsors receive current issues for free. Scientific Council for Technical Sciences of Slovenian Research Agency has recognized Informacije MIDEM as scientific Journal for microelectronics, electronic components and materials. Publishing of the Journal is cofi­nanced by Slovenian Research Agency and by Society sponsors. Scientific and professional papers published in the journal are indexed and abstracted in COBISS and INSPEC databases. The Journal is indexed by ISI® for Sci Search®, Research Alert® and Material Science Citation Index™. | Letna naročnina je 160 EUR, cena posamezne številke pa 40 EUR. Člani in sponzorji MIDEM prejemajo posamezne številke brezplačno. Znanstveni svet za tehnične vede je podal pozitivno mnenje o reviji kot znanstveno-strokovni reviji za mikroelektroniko, elektronske sestavne dele in materiale. Izdajo revije sofinancirajo ARRS in sponzorji društva. Znanstveno-strokovne prispevke objavljene v Informacijah MIDEM zajemamo v podatkovne baze COBISS in INSPEC. Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madić Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana Journal of Microelectronics, Electronic Components and Materials vol. 47, No. 1(2017) Content | Vsebina 3 14 24 32 40 49 55 Izvirni znanstveni članki K. Górecki, K. Górski, J. Zarębski: Vplivi izbranih parametrov na termične parametre impulznih transformatorjev H. Sood, V. M. Srivastava, G. Singh: Modeliranje majhnih signalov na pomanjšanem MOSFET z dvemi vrati za GHz aplikacije J. H. See, M. K. Md Arshad, M. F. M. Fathil, C. H Voon, U. Hashim, S. C. B. Gopinath: Načrtovanje eksperimenta vplivov debeline in upornosti epitaksijske plasti P-i-N diode pri reverznih napetostih nad 300 V A. Jiménez P., A. Carrillo C., S. Tilvaldyev, M. A. Quevedo L., J. A. Munoz G.: 2D simulacija TFT tipa p s kemijsko nanešenim aktivnim poli-PbS kanalom D. Vasiljević, D. Brajković, D. Krklješ, B. Obrenović, G. M. Stojanović: Preizkušanje in karakterizacija večslojnih uporovnih senzorjev sile izdelanih na fleksibilnih substratih A. Samir, B. Batagelj: Sedem-jedrno vlakno za fluorescenčno spektroskopijo Napoved in vabilo k udeležbi: 53. Mednarodna konferenca o mikroelektroniki, napravah in materialih z delavnico o materialih za pretvorbo energije in njihovih aplikacijah Naslovnica: SEM slika bakrove plasti (D. Vasiljević et al..) Original scientific paper K. Górecki, K. Górski, J. Zarębski: Investigations on the Influence of Selected Factors on Thermal Parameters of Impulse-Transformers H. Sood, V. M. Srivastava, G. Singh: Small Signal Modeling of Scaled Double-Gate MOSFET for GHz Applications J. H. See, M. K. Md Arshad, M. F. M. Fathil, C. H Voon, U. Hashim, S. C. B. Gopinath: DOE Study of Epitaxial Layer Thickness and Resistivity Effects on P-i-N Diode for beyond 300 V of Reverse Voltage Applications A. Jiménez P., A. Carrillo C., S. Tilvaldyev, M. A. Quevedo L., J. A. Munoz G.: 2D Simulation Study of p-type TFTs with Chemically Deposited Poly-PbS Active Channel D. Vasiljević, D. Brajković, D. Krklješ, B. Obrenović, G. M. Stojanović: Testing and Characterization of Multilayer Force Sensing Resistors Fabricated on Flexible Substrate A. Samir, B. Batagelj: A Seven-core Fibre for Fluorescence Spectroscopy Announcement and Call for Papers: 53nd International Conference on Microelectronics, Devices and Materials With the Workshop on Materials for Energy Conversion and Their Applications Front page: SEM micrographs of carbon layer (D. Vasiljević et al.) Editorial | Uvodnik Dear Reader, This issue brings 6 original scientific papers and the Call for paper at the 53rd MIDEM conference that the MIDEM So­ciety organizes in late September/early October every year. The conference will be organized at the largest research institute in Slovenia, the Jozef Stefan Institute in Ljubljana. Among highlights of the conference will be the Workshop on Materials for Energy Conversion and their Applications: Electrocalorics and Thermoelectrics. The organizers invite you to join us at the inspiring invited talks and full three-day programme. Readers of the journal will get a chance to read selected papers from the conference in coming Issue 4 in December. The landscape of academic journals started to change since 2002, when the Budapest Open Access Initiative has been released. Fifteen years later we can state that it did not change dramatically, but brought new players – publishers, policy makers, charitable foundations, scholarly collaboration networks and additional authors and reviewers. Euro­pean Commission urges that dissemination of knowledge generated with EU funding needs to follow open access. All peer-reviewed scientific publications relating to the projects funded within Horizon 2020 programme must be pub­lished as green or gold open access. Member states follow and Slovenia is no exception. Science Europe committed to playing a role in accomplishing the transition to Open Access in an efficient and sustainable way. It recommends that scientific institutions disclose payments of Open Access publication fees by participating in the ‘Open APC Initiative’. This will help create a more transparent cost structure in the Open Access publication market and stimulate competi­tion. Our journal is not declared as an open access journal, but it requests page charges for papers published in the journal to cover publishing costs and to secure continuation of quality growth. We continue to provide a free electronic ac­cess to all papers published in Informacije MIDEM –Journal of Microelectronics, Electronics Components and Materials (since 1986) and authors are welcome to disseminate and upload them at ResearchGate, Google Scholar or other platforms. Prof. Marko Topič Editor-in-Chief P.S. All papers published in Informacije MIDEM –Journal of Microelectronics, Electronics Components and Materials (since 1986) can be access electronically for free at http://midem-drustvo.si/journal/home.aspx. A search engine is provided to use it as a valuable resource for referencing previous published work and to give credit to the results achieved from other groups. Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 1(2017), 3 – 13 Investigations on the Influence of Selected Factors on Thermal Parameters of Impulse-Transformers Krzysztof Górecki, Krzysztof Górski, Janusz Zarębski Gdynia Maritime University, Department of Marine Electronics, Gdynia, Poland Abstract: In the paper the results of experimental investigations illustrating the influence of the selected factors on parameters of the thermal model of the transformer are presented. The form of this model and the applied method of measurements of the transformer structural components’ self and mutual transient thermal impedances are described. The influence of the selection of material of the core, its geometrical dimensions, spatial orientation, shape of the core, frequency of the primary winding current in the transformer and power lost in this element on the considered thermal parameters of the transformer are discussed. An analytical formula describing the dependence of the considered transient thermal impedances on the internal temperature of the windings is proposed and verified experimentally. Keywords: thermal parameters;selfheating; impulse-transformers Vplivi izbranih parametrov na termične parametre impulznih transformatorjev Izvleček: Članek prikazuje rezultate eksperimentalnih raziskav vplivov izbranih faktorjev na parameter termičnega modela transformatorja. Opisan je model, uporabljene merilne metode in vzajemne tranzientne termične impedance. V smislu termičnih parametrov so obravnavni: izbira materiala jedra, geometrija, orientiranost, frekvenca toka primarnega navitja in izgube. Predlagana in eksperimentalno preverjena je analitična enačba odvisnosti tranzientne termične impedance od temperature navitja. Ključne besede: termični parametri; lastno segrevanje; impulzni transformator * Corresponding Author’s e-mail: k.gorecki@we.am.gdynia.pl 1 Introduction Impulse-transformers are commonly used in switched-mode power electronic converters [1, 2, 3, 4]. The con­sidered elements have a simple construction - they consist of the ferromagnetic core and windings. The properties of both these components influence tem­perature, the change of which causes changes of the value of technical parameters of the core and windings [4, 5]. Particularly, when the core temperature is higher than the Curie temperature, magnetic permeability of the ferromagnetic core decreases to the value near permeability of free air, and the transformer practically does not transfer energy from the input to the output. In turn, the excess of the admissible temperature of windings can cause destruction of isolation of winding wires [4, 5], leading to the short-circuit of turns. The temperatures of the core and windings of the transformer during its operation are higher than the ambient temperature as a result of self-heating in the core and in the winding [5-14], as well as mutual ther­mal coupling between them. Calculating values of tem­perature of structural components of the transformer demands using the thermal model. Such a model can have the form of the detailed model, making it possi­ble to calculate time-space distribution of temperature in the considered element [9-12, 15], or the compact model - making possible calculations of waveforms of temperature of this element [6, 13, 14] or the selected structural components of the transformer [5, 7]. In the paper [13] many results of calculations of temperature distribution in a planar transformer obtained with the use of the finite element method (FEM) are presented. In these calculations uniform distributions of the pow­er dissipated in the core and in the windings were as­sumed. The results of measurements shown in this pa­per prove that this assumption is fulfilled. In the case of the use of the compact thermal model it is indispensable to measure the transformer’s self and mutual transient thermal impedances. Thermal models presented in papers [5, 6, 7, 8, 13] are linear models, i.e. transient thermal impedances in these models neither depend on constructional factors nor on the power lost in the transformer. Yet, in papers [16, 17, 18] (for in­stance) it was shown that thermal parameters of semi­conductor devices strongly depended, among other things, on the power dissipated in them, the type of the case, or the manner of mounting the considered de­vice. It can be expected that a similar influence will be observed in the case of magnetic elements, to which the transformer belongs. In the paper the method to measure thermal param­eters existing in the thermal model of the transformer and the results of measurements of these parameters illustrating the influence of the selected factors on ef­ficiency of transformers cooling are presented. Trans­formers with ring cores considered in the present pa­per are characterized by uniform distribution of the magnetic force and magnetic flux density, similarly as transformers considered in paper [13]. Therefore, distri­bution of power density in the core is also uniform. In Section 2 the form of the thermal model of the trans­former is presented and the transformer’s self and mu­tual transient thermal impedances are defined. Section 3 contains a description of the measuring method to measure the transformer’s self and mutual transient thermal impedances. In Section 4 the results of meas­urements of thermal parameters of the selected con­structions of transformers are presented and the analyt­ical formula describing the influence of the dissipated power on the considered parameters is proposed and experimentally verified. 2 Thermal Model of Transformer The thermal model describes the dependence of the internal temperature of the electronic component on the power emitted in it. In the case of commonly used compact thermal models this dependence can be de­scribed by means of the convolution integral [19, 20, 21]. As it is shown, among other things, in papers [5, 7, 22], in order to describe correctly thermal properties of magnetic elements it is indispensable to take into ac­count both self-heating in the core and in windings, as well as mutual thermal coupling between them. Hence, the temperature of k-th winding can be described by the following formula (1) where Ta denotes the ambient temperature, k repre­sents the name of the winding, pk(t) denotes the pow­er dissipated in k-th winding of the transformer and Z’thwkj(t) represents the time derivative of the devices’ self (for k = j) or mutual (for k K j) transient thermal impedance between the windings of the transformer, n – the number of windings, Z’thck(t) – the time derivative of mutual transient thermal impedance between the core and the k-th winding, whereas pc(t) is the power dissipated in the core. In turn, the temperature of the core is given by the fol­lowing formula (2) where Z’thc(t) is the time derivative of the core’s self transient thermal impedance. The core’s self or mutual transient thermal impedance can be modelled using the classical formula [19, 23, 24] (3) where Rth is thermal resistance, tthk denotes k-th ther­mal time constant, ak is the ratio factor corresponding to this time constant, whereas N is the number of ther­mal time constants. The presented thermal model, given by equations (1 – 3) of the transformer can be described as the RC electri­cal analog, like the linear thermal model presented in [5]. In the real situation, where the parameters existing in Eq. (3) depend on the value of the dissipated power, the nonlinear thermal model is needed. The simple form of this model for the electronic device non-cou­pled thermally with any other device is proposed in [17]. In this model, the controlled voltage and current sources are used instead of RC elements. 3 Method to Measure Thermal Parameters of the Transformer The transformer’s self and mutual transient thermal im­pedances of the selected magnetic devices were meas­ured with the use of the method described in papers [25, 26]. This method is realised by means of the meas­urement set presented in Fig.1. Figure 1: Measurement set for measuring thermal pa­rameters of the transformer [26] The measurements are realised in two steps. The first step needs stimulations of the primary winding with a current step and the measurement of waveforms of the windings temperature and the core temperature by means of thermo-hunters (pyrometers with IR sen­sors) until the thermally steady-state is achieved. In the considered measurement set the thermo-hunters of the type PT-3S by Optex are used [27]. The range of the measured temperature is from 0 to 200 oC and the resolution is equal to 0.1oC. These thermo-hunters are situated in the distance of 25 mm from the measured transformer. The area, on which the temperature is measured, has the form of a circle with the diameter 2.5 mm. During measurements it was assumed that emis­sivity of all components of the considered transformers has the constant value equal to 0.95. This value is close to typical values of emissivity of materials used to con­struct transformers. As it results from the Authors’ investigations presented in [26], in the area of a transformer, in which the wind­ings are located, practically uniform distribution of the temperature is observed. Similarly, temperature distri­bution of the core is quasi-uniform. Therefore, averag­ing the temperature value in a circle of the diameter equal to 2.5 mm does not cause a visible measurement error. The waveforms of the core temperatures TC(t) and of the winding temperature TW(t) while heating the trans­former are registered by the computer PC coupled with two thermo-hunters. By means of the voltme­ter and the ammeter the values of the voltage on the primary winding V1 and the current of this winding I1 are measured at the steady-state. The results of these measurements are used to calculate transient thermal impedance of the winding ZthW(t) and mutual transient thermal impedance between the core and the wind­ings ZthWC(t) with the following formulas (4) (5) where Ta is the ambient temperature. In the second step, the primary winding of the trans­former is stimulated by a sinusoidal signal of frequency fs, whereas the temperature of the core is measured by the thermo-hunter. When the steady state is obtained, the hysteresis loop of the magnetising characteristic B(H) of the core is measured using the oscilloscope and next - transmitted to the computer (PC). The waveforms of the magnetic force H(t) and flux den­sity B(t) are calculated using the following formulas (6) (7) in which R and C denote resistance of the resistor and capacitance of the capacitor used in Fig.1, respectively, z1 and z2 are numbers of turns in primary and second­ary windings, respectively, SFe – the cross-section area of the core, lFe – magnetic path in the core, uC – voltage on the capacitor C, whereas i1 – the current of the pri­mary winding. The area SH of the obtained hysteresis loop B(H) is given by following formula (8) This integral is calculated using the Excel software and the method of numerical integration. The used values of frequency fs are in the range from 1 kHz to 100 kHz. Next, in the moment t = 0 the power supply of the pri­mary winding is switched off and waveforms of the core temperature TC(t) are measured until the steady state is obtained. The transient thermal impedance of the core ZthC(t) is calculated using the following formula (9) where VC represents volume of the core. In Eq. (9) only the power dissipated in the core is taken into account, whereas the power dissipated in the windings is omit­ted. This is justified, if the value of the power dissipated in primary and secondary windings is much smaller than the power dissipated in the core. Such conditions are fulfilled when (10) where I1 and I2 are RMS values of primary and second­ary windings currents, whereas R1 and R2 are resistanc­es of these windings. 4 Investigation Results Using the method presented in Section 3, measure­ments of thermal parameters of transformers contain­ing ferromagnetic cores made of the powdered iron (RTP), the ferrite (RTF) and the nanocrystalline cores (RTN) were performed. The first series of measurements was performed for ring cores of the dimensions RTP 26.9x14x11 made of material T106-26, RTN-26x16x12 made of material M-070, RTF-25x15x10 made of material F-867, called in the further part of this paper small ring cores. The sec­ond series of measurements was made for cores made of the same ferromagnetic materials, but of the big­ger dimensions: RTP 39.9x24.1x14.5 made of material T157-26, RTF 40x24x16 made of material F-867, called in the further part of this paper large ring cores and for the pot core B65701 -T1000-A48 of the diameter 30 mm and heights 19 mm made of material N48. In Ta­ble 1 the values of basic parameters of the considered ferromagnetic materials are collected. In this table Bsat denotes saturation flux density at the magnetic field strength Hsat, HC is the coercive field strength, TC – Curie temperature, whereas PV – relative core losses. In marking ring cores each number means the outside diameter, the inside diameter and the height of the core expressed in millimetres, respectively. The view of the ring core with its dimensions is shown in Fig. 2, whereas the view of the pot core is shown in Fig. 3. The temperature of windings of the transformer with the pot core can be measured using a hole in this core. Figure 2: View of the ring core with its dimensions On small ring cores two windings containing 22 turns were wound with copper wire in the enamel of the di­ameter 0.8 mm. In turn, on large ring cores two wind­ings containing 30 turns of copper wire in the enamel of the diameter 0.8 mm were wound. The transformer with the pot core contains two windings made with the same wire consisting of 22 turns. The views of trans­formers with the ring core and with the pot core are shown in Fig. 4 and Fig. 5, respectively. As it is visible, the distance between turns in each wind­ing is not constant. The temperature of these windings is measured for the area in which this distance is the smallest and much smaller the measuring spot of the used thermo-hunter. In the following figures the results of measurements of self and mutual transient thermal impedances Zth(t)of the selected constructions of impulse transformers (solid lines) and approximation of these curves (dashed lines) with Eq. (3) are presented. The values of param­eters of the model described with the equation (3) are estimated with the use of the method proposed in [5]. The value of Rth is estimated by averaging the wave­form of the considered transient thermal impedance in the steady state (typically for the last 100 seconds), whereas the values of the parameters ai and thermal time constants tthi are determined by the least square method. Starting from the longest thermal time con­stant through approximation based on the formula [5] (11) the linear function given by Figure 3: Cross-sections of the pot core B65701 -T1000-A48 with its dimensions Figure 4: View of the transformer with the ring core Figure 5: View of the transformer with the pot core (12) is used. Attention is focused on the parameters describing self-heating phenomenon in the core (ZthC(t)) and in the winding (ZthW(t)), as well as mutual thermal coupling between the core and the windings (ZthWC(t)). The mu­tual thermal couplings between the windings are not taken into account. The values of parameters Rth, ai, tthi approximating the selected waveforms of the investigated transformers’ self and mutual transient thermal impedances are col­lected in Tables 2 - 5. Table 2: Parameters values of transient thermal imped­ances in transformers with the small ring core RTP situ­ated horizontally parameter ZthW(t) ZthWC(t) ZthC(t) Rth [K/W] 22.15 18.12 25.39 a1 0.664 0.758 0.925 a2 0.206 0.242 0.068 a3 0.13 0.007 tth1 [s] 661.2 710.5 702.1 tth2 [s] 134.1 259 283 tth3 [s] 10 12.8 Table 3: Parameters values of transient thermal imped­ances in transformers with the big ring core RTP orientation horizontally vertically parameter ZthW(t) ZthWC(t) ZthW(t) ZthWC(t) Rth [K/W] 13.5 11.1 11.1 9.01 a1 0.6 0.774 0.742 1 a2 0.192 0.226 0.118 a3 0.148 0.09 a4 0.06 0.05 tth1 [s] 1062.5 1078.4 680.1 654.9 tth2 [s] 470.5 459.4 114.8 tth3 [s] 30.9 19.4 tth4 [s] 5.64 14.7 Table 4: Parameters values of transient thermal imped­ances in transformers with the small ring core RTF parameter ZthW(t) ZthWC(t) ZthC(t) Rth [K/W] 24.88 14.26 11.98 a1 0.651 1 0.92 a2 0.255 0.08 a3 0.094 tth1 [s] 474.1 449.5 483.4 tth2 [s] 126.8 53.1 tth3 [s] 9 Table 5: Parameters values of transient thermal imped­ances in transformers with the big ring core RTF orientation horizontally vertically parameter ZthW(t) ZthWC(t) ZthW(t) ZthWC(t) Rth [K/W] 14 7.59 13.42 6 a1 0.595 1 0.605 1 a2 0.225 0.275 a3 0.13 0.118 a4 0.05 0.002 tth1 [s] 918 1050.5 792.8 800 tth2 [s] 224.8 152.8 tth3 [s] 23.5 11.18 tth4 [s] 5.67 5.67 Comparing the data collected in the mentioned tables one can observe that the description of the considered transient thermal impedances demands the use of a different number of thermal time constants tthi. In the case of large ring cores RTP and RTF up to 4 thermal time constants appear in the description ZthW(t), while in the description ZthWC(t) for both ferrite cores RTF - just only one thermal time constant. In all the considered cases the prevailing meaning has the longest thermal time constant tth1. The corresponding to it weight- co­efficient a1 assumes the values in the range from 0.595 to 1. In turn, the values th1 are in the range from 471 s (for the small ring core RTF) to 1078 s for the large ring core RTP. The presented below results of investigations illustrate the influence of geometrical dimensions of the core (Fig.6), its spatial orientation (Fig. 7), shape of the core (Fig. 8), current of the primary winding (Fig. 9), mate­rial the core is made of (Fig. 10) and frequency of the current on the primary winding (Fig. 7) on waveforms of the transformers’ self and mutual transient thermal impedances. In Fig. 6 the measured and modelled with the Eq. (3) waveforms of transient thermal impedance of the winding ZthW(t) and mutual transient thermal imped­ance between the winding and the core ZthWC(t) for transformers containing ring cores RTP (Fig.6a) or ring cores RTF (Fig. 6b) of different dimensions are present­ed. The measurements were performed at the stimula­tion of the primary winding with the direct current of the value equal to 9 A. As one can notice in Fig. 6, the process of heating the core and the winding of the transformer with the con­sidered cores runs slowly. The time indispensable to obtain the steady state exceeds 3000 s for the small ring core, 4000 s - for the pot core and 5000s - for the large ring core. The value of transient thermal imped­ances ZthW(t) is about 40% greater for the transformer with the small ring core RTP than for the transformer with the large ring core RTP (Fig. 6a). In the case of the transformer with the core RTF (Fig. 6a) one obtained greater by about 10% values of the considered param­eter for transformers with ring cores made of the same material, while the transformer with the pot core shows average values of the time needed to settle the course between the values of this parameter corresponding to different measurements of ring cores. Waveforms of mutual transient thermal impedance between the winding and the core ZthWC(t) are late in relation to waveforms ZthW(t) by more than 20 s, and values ZthWC(t) at the steady-state are smaller than the value ZthW(t) at the steady-state. For transformers with cores RTP this difference is about 15%, and in the case of transform­ers with cores RTF these differences are bigger and are about 50% for ring cores and about 30% for the sot core. For all the considered waveforms the very good agreement between the results of measurements and the calculations performed with the use of the consid­ered model is obtained. In Fig. 7 waveforms ZthW(t) and ZthWC(t) for transform­ers with large ring cores RTP (Fig. 7a) and RTF (Fig.7b) placed both horizontally and vertically at the stimula­tion of the primary winding with the direct current of the value 9 A are presented. As one should expect the waveforms ZthW(t) and ZthWC(t) obtained in horizontal orientations lie above the wave­forms obtained for the transformers situated vertically. It is the result of more efficient convection of heat for ele­ments situated vertically, similarly to the situation with transistors mounted on any heat-sink situated vertically [9]. The vertical orientation of the considered elements quickens the perpendicular air flow along the sides of these elements, because the length of these sides is greater at this arrangement of the investigated element. The values of the considered transient thermal imped­ances in the steady-state in the horizontal and vertical orientation differ from each other by about 15% for the transformer with the core RTP and by about 10% for the transformer with the core RTF. It is visible that the consid­ered model approximates well the measured waveforms ZthW(t), whereas it is possible to observe divergences between the measured and approximated waveforms ZthWC(t), especially for small values of time t. In Fig.8 the influence of the selection of material of the ferromagnetic core on waveforms ZthW(t) and ZthWC(t) of transformers containing the small (Fig. 8a) or large (Fig. 8b) ring core is illustrated. The measurements were performed at the stimulation of the primary winding with the direct current of the value 9A. As it can be noticed in Fig.8a, heat removal from the transformer containing the ferrite core (RTF) is the least efficient, while transformers with the powder core (RTP) and nanocrystalline core (RTN) have almost iden­tical waveforms ZthW(t). It is worth noticing that dissipa­tion of power of the same value in the winding causes a considerably higher temperature increase of the core RTP than the remaining cores, considered in this paper. This results from the greater value of thermal conduct­ance of this material, which causes more efficient re­moval of heat generated in the winding through the core. Therefore, in the transformer with this core con­siderably smaller differences appear between tem­peratures of the winding and of the core than for the remaining considered transformers. The qualitatively similar results were obtained for transformers contain­ing the large ring core. In this case, increases of the winding and the core temperatures of the transformer with the core RTP differ only just by about 20%, and for the transformer with the core RTF – up to about 60%. In Fig. 9 the influence of the current flowing through the primary winding of the transformer on waveforms of transient thermal impedance of the winding and mutual thermal impedance between the winding and the core was illustrated. The measurements were per­formed for the transformer with the large ring core RTP situated horizontally for the current equal 7.35A and 9.1A, respectively. As one can notice, with the current of the primary winding of the value 9.1A the values ZthW(t) and ZthWC(t) are by about 8% smaller than with the current equal to 7.35A. The improvement of efficiency of cooling with an increase of the current of the winding results from an increase in the value of the power dissipated in this element, which causes a temperature rise of the wind­ing. In turn, the temperature rise of the winding causes an increase in efficiency of heat convection. Fig. 10 illustrates the influence of the shape of the waveforms ZthC(t) of the transformer with the core RTF at the stimulation of the primary winding with the si­nusoidal signal. In this case the power dissipated in the winding is negligible in relation to the power dissipat­ed in the core. Figure 10: Measured (solid lines) and modelled (dashed lines) waveforms of transient thermal imped­ance of the core of transformers with the core RTF at the stimulation with the sinusoidal current In Fig. 10 distinct differentiation of the obtained wave­forms ZthC(t) is visible. The large ring core assures the most efficient cooling and the small ring core - the least efficient. The average values ZthC(t) are obtained for the transformer with the pot core. The obtained values of the considered transient thermal impedance differ from each other even four times. In Fig. 11 the influence of frequency of the signal stimu­lating the primary winding of the transformer with the large ring core RTP on the waveforms ZthC(t) and ZthCW(t) is illustrated. Investigations were made for the transformer placed horizontally at two values of frequency equal to 25kHz and 75kHz, respectively. It is visible that an increase of frequency of the stimulating signal from 25 kHz to 75 kHz causes an increase in the value of transient thermal impedances ZthC(t) and ZthCW(t) by about 10%. Figure 11: Measured (solid lines) and modelled (dashed lines) waveforms of transient thermal imped­ance of the core and mutual transient thermal imped­ance between the core and the winding of the trans­former with the small ring core RTP at the stimulation with the sinusoidal current of frequency equal to 25kHz and 75kHz The observed differences between waveforms of the considered thermal parameters can be caused not only by changes of the value of frequency, but also with changes of the power dissipated in the core at these frequencies (1 W at f = 25 kHz and 0.8 W at f = 75 kHz). Similarly, as this was shown in Figs. 9, an increase in the value of the power dissipated in the considered ele­ment causes a decrease in the value of thermal param­eters of the transformer. As one can notice in Figs. 6 - 11 for all the considered constructions of transformers and for all the considered cooling conditions the good agreement between the results of measurements and calculations performed with the use of Eq. (3) was obtained. However, as it is re­sults among other things, from papers [16, 17] thermal resistance existing in this model is a decreasing func­tion of the power dissipated in the modelled element. The decreasing dependence of thermal resistance on the dissipated power is a result of improved cooling of the transformer component with an increase in their temperature. As it is commonly known efficiency of convection and radiation increases with an increase in temperature of the heat source. Therefore, the depend­ence of thermal resistance on internal temperature of the heating source (the core or the winding) can be ap­proximated with the function of the form: (13) where T denotes temperature of the considered com­ponent of the transformer, whereas Rth0, Rth1, T0 and ap are the model parameters. The correctness of the presented description was veri­fied experimentally. For example, in Fig.12 calculated (lines) and measured (points) dependences of thermal resistance of the winding RthW and mutual thermal re­sistance between the winding and the core RthWC on the dissipated power in the winding of the transformer with the big ring RTP core are shown. Solid lines cor­respond to the transformer placed horizontally, and dashed lines - to the transformer situated vertically. Figure 12: Measured (points) and modelled (lines) de­pendences of thermal resistance of the winding and mutual thermal resistance between the winding and the core on the dissipated power for the transformer with the big ring core RTP at the stimulation with the dc current As it is visible, both the considered dependences are monotonically decreasing functions. The good agree­ment between the results of calculations and measure­ments is obtained. This proves that the proposed de­scriptions of the dependences RthW(p) and RthWC(p) are useful. Figure 13: Measured (solid lines) and modelled (dashed lines) waveforms of self transient thermal im­pedance of the winding of the transformer with the big ring core RTP situated vertically at the stimulation with the direct current of different values The considered dependences were used to model wave­forms of transient thermal impedances of the impulse transformer. In this model only the value of thermal re­sistance is a function of the dissipated power given by Eq. (7), whereas the values of parameters ai and tthi exist­ing in Eq. (3) are constant for the considered transformer. For example, in Fig.13 the waveforms of measured (solid lines) and calculated (dashed lines) transient thermal im­pedance of the winding of the transformer with the big RTP core are presented at different values of the power dissipated in the primary winding. As it is visible, the good agreement between the results of calculations and measurements is obtained. The difference between the temperature inside the core and on its surface is caused only by a non-zero value of thermal conductance of material used to make the core. Of course, the temperature inside the core is the highest, when power losses in the core dominate. In turn, the temperature rise of the core as a result of thermal coupling between this core and the windings is higher on the surface of the core than in the middle of it. Therefore, it is difficult to formulate the universal dependence between the temperature inside the core and on its surface. It is possible only to estimate the dif­ference between temperatures of the surface and the middle of the core assuming that the only mechanism of heat transfer is conduction, generation of heat ap­pears in the infinitely thin ring situated in the middle of the core, and heat flux density has uniform distribu­tion. With these assumptions, for the ring core of the outside diameter equal to 5 cm, the inside diameter equal to 3 cm and the height equal to 1 cm, made of powdered iron at the power dissipated in the core of the value equal to 1 W the maximum temperature dif­ference between the middle of the core and its surface amounts to 14 K. 5 Conclusions In the paper the method to measure transient thermal impedances in the transformer and the results of meas­urements, illustrating the influence of the selected fac­tors on waveforms of these thermal parameters, are presented. The research done by the Authors proves that efficiency of cooling the structural components of the transformer can be characterised by means of parameters of the compact thermal model and that the waveforms of the considered thermal parameters change depending on many factors. For example, an increase in the value of the power dissipated in the winding by more than 30% causes a decrease of the waveforms ZthW(t) by several percent. In turn, enlargement of the diameter of the ring core by about 60% is effective with deterioration of thermal resistance by even about 50% and with extension of the indispensable time to obtain the steady state even by about 60%. For comparatively large sizes of the in­vestigated elements, the time indispensable to obtain the thermally steady state reaches even 2 hours. The change of spatial orientation of the transformer (hori­zontal or vertical orientation) causes a change of the considered parameters by even about 20%. The essential meaning has also the material, the core is made of, because its thermal conductance influences the measured waveforms ZthW(t) and ZthWC(t) in an essen­tial manner. The least differences between waveforms of the mentioned thermal parameters, not exceeding 20%, were observed for transformers with cores RTP (characterised by high thermal conductance), and the greatest (by even above 50%) - for cores RTF. The analytic description of dependences of self and mutual thermal resistances of the transformer on the power dissipated in it is proposed. It was shown experi­mentally that the use of this dependence in the clas­sical literature model of transient thermal impedance assured correct modelling of waveforms of transient thermal impedances of the transformer over a wide range changes of the current of the primary winding. It is worth noticing that the classical literature descrip­tion of transient thermal impedance with the proposed description of thermal resistance enables very good approximation of the measured waveforms of transient thermal impedance of the winding for all the consid­ered transformers. One observes, however, essential differences between the measured and approximated waveforms of mutual transient thermal impedances between the winding and the core and transient ther­mal impedances of the core for transformers contain­ing ferrite or nanocrystalline cores. In the mentioned above transformers a large delay of the process of heat­ing the core appears, which reaches even 100 s. The correct modelling of this delay demands correction in the thermal model of the transformer, which is at pre­sent an objective of the Authors investigations. The results of investigations presented in this paper can be useful for constructors of impulse-transformers and constructors of switched-mode power supplies contain­ing these transformers. These results will be of service also to the Authors as experimental material, indispensable to formulate the non-linear electro-thermal model of the im­pulse-transformer. In this model the influence of internal temperature of the core and the windings, of dimensions of the core and its spatial orientation on thermal param­eters of the transformer will take into account. 6 References 1. Kazimierczuk M.K.: Pulse-width Modulated DC-DC Power Converters. John Wiley&Sons, 2008. 2. Ericson R., Maksimovic D.: Fundamentals of Power Electronics, Norwell, Kluwer Academic Publisher, 2001. 3. Rashid M.H.: Power Electronic Handbook, Aca­demic Press, Elsevier, 2007. 4. Van den Bossche A., Valchev V.C.: Inductors and transformers for Power Electronics. CRC Press, Taylor & Francis Group Boca Raton, 2005. 5. Górecki K, Rogalska M.: The compact thermal model of the pulse transformer. Microelectronics Journal, Vol. 45, No. 12, 2014, pp. 1795-1799. 6. Wilson P.R., Ross J.N., Brown A.D.: Simulation of magnetic component models in electric circuits including dynamic thermal effects. IEEE Trans. on Power Electronics, Vol. 17, No. 1, 2002, pp. 55-65. 7. Górecki K., Zarębski J.: Electrothermal analysis of the self-excited push-pull dc-dc converter. Microelec­tronics Reliability, Vol. 49, No.4, 2009, pp. 424-430. 8. Górecki K., Rogalska M., Zarębski J.: Parameter es­timation of the electrothermal model of the fer­romagnetic core. Microelectronics Reliability, Vol. 54, No. 5, 2014, pp. 978-984. 9. Allahbakhshi M., Akbari A.: An improved compu­tational approach for thermal modeling of power transformers. International Transactions on Elec­trical Energy Systems, Vol. 25, No. 7, 2015, pp. 1319-1332. 10. Penabad-Duran P., Lopez-Fernandez X.M., Turows­ki J.: 3D non-linear magneto-thermal behavior on transformer covers. Electric Power Systems Re­search, Vol. 121, 2015, pp. 333-340. 11. Sitar R., Janic Z., Stih Z.: Improvement of thermal per­formance of generator step-up transformers. Applied Thermal Engineering, Vol. 78, 2015, pp. 516-524. 12. Tsli M.A., Amoiralis E.I., Kladas A.G., Souflaris A.T.: Power transformer thermal analysis by using an advanced coupled 3D heat transfer and fluid flow FEM model. International Journal of Thermal Sci­ences, Vol. 53, 2012, pp. 188-201. 13. Bernardoni M., Delmonte N., Cova P., Menozzi R.: Thermal modeling of planar transformer for switching power converters. Microelectronics Re­liability, Vol. 50, No. 9-11, 2010, pp. 1778-1782. 14. Tsli M.A., Amoiralis E.I., Kladas A.G., Souflaris A.I.: Hybrid numerical-analytical technique for power transformer thermal modeling. IEEE Transactions on Magnetics, Vol. 45, No. 3, 2009, pp. 1408-1411. 15. Villar I., Viscarret U., Etxeberia-Otadui I., Rufer A.: Transient thermal model of a medium frequency power transformer. 34th Annual Conference of the IEEE Industrial Electronics Society IECON 2008, Vol. 1-5, 2008, pp. 982-987. 16. Górecki K., Zarębski J.: Modeling the influence of selected factors on thermal resistance of semi­conductor devices. IEEE Transactions on Compo­nents, Packaging and Manufacturing Technology, Vol. 4, No. 3, 2014, pp. 421-428. 17. Górecki K., Zarębski J.: Nonlinear compact ther­mal model of power semiconductor devices. IEEE Transactions on Components and Packaging Technologies, Vol. 33, No. 3, 2010, pp. 643-647. 18. Oettinger F.F., Blackburn D.L.: Semiconductor Measurement Technology: Thermal Resistance Measurements, U. S. Department of Commerce, NIST/SP-400/86, 1990. 19. Szekely V.: A New Evaluation Method of Thermal Transient Measurement Results. Microelectronic Journal, Vol. 28, No. 3, 1997, pp. 277-292. 20. Janke W., Blakiewicz G., Semi analytical recursive algorithms for convolution calculations, IEE Proc.- Circuits Devices Systems, Vol. 142, No. 2, 1995, pp. 125-130 21. Zarębski J., Górecki K.: Properties of Some Convo­lution Algorithms for the Thermal Analysis of Semi­conductor Devices. Applied Mathematical Model­ling, Elsevier, Vol. 31, No. 8, 2007, pp.1489 – 1496. 22. Górecki K., Detka K.: Electrothermal model of choking-coils for the analysis of dc-dc converters. Materials Science & Engineering B, Vol. 177, No. 15, 2012, pp. 1248-1253. 23. Pietrenko W., Janke W., Kazimierczuk M.K.: Appli­cation of semianalytical recursive convolution al­gorithms for large-signal time-domain simulation of switch-mode power converters. IEEE Transac­tions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 48, No. 10, 2001; pp. 1246-52. 24. Bagnoli P.E., Casarosa C., Ciampi M., Dallago E.: Thermal Resistance Analysis by Induced Transient (TRAIT) Method for Power Electronic Devices Thermal Characterization – Part I: Fundamentals and Theory. IEEE Transactions on Power Electron­ics, Vol. 13, No. 6, 1998, pp. 1208-1219. 25. Górecki K., Zarębski J., Detka K., Rogalska M.: The method and circuit for measuring own and mu­tual thermal resistances of a magnetic device. Eu­ropean Patent Application EP 13460073, 2013. 26. Górecki K., Górski K.: The influence of core materi­al on transient thermal impedances in transform­ers. Journal of Physics: Conference Series, Vol. 709, 2016, MicroTherm’2015 and SENM’2015, 012010, pp. 1-7, doi:10.1088/1742-6596/709/1/012010 27. http://www.optex.co.jp/meas/english/potable/pt_3s/index.html Arrived: 31. 10. 2016 Accepted: 04. 01. 2017 K. Górecki et al; Informacije Midem, Vol. 47, No. 1(2017), 3 – 13 K. Górecki et al; Informacije Midem, Vol. 47, No. 1(2017), 3 – 13 K. Górecki et al; Informacije Midem, Vol. 47, No. 1(2017), 3 – 13 Table 1: Values of basic parameters of the considered ferromagnetic materials parameter T106-26 and T157-26 M-070 F-867 N48 manufacturer Micrometals Magnetec Feryster Epcos Bsat [T] 1.38 1.2 0.5 0.42 Hsat [A/m] 19.9x103 590 966 1200 HC [A/m] 440 9 75 26 TC [oC] 750 600 215 170 PV [kW/m3] 180 @f=100 kHz 800 @f=100 kHz 400 @f=100 kHz - K. Górecki et al; Informacije Midem, Vol. 47, No. 1(2017), 3 – 13 K. Górecki et al; Informacije Midem, Vol. 47, No. 1(2017), 3 – 13 a) b) Figure 6: Measured (solid lines) and modelled (dashed lines) waveforms of transient thermal impedances in transformers with ring cores RTP (and) and RTF (b) of different dimensions at the stimulation with the direct current of the primary winding and the horizontal ori­entation of the core K. Górecki et al; Informacije Midem, Vol. 47, No. 1(2017), 3 – 13 a) b) Figure 7: Measured (solid lines) and modelled (dashed lines) waveforms of transient thermal impedances in the transformer with the core RTP (and) and RTF (b) at the stimulation with the direct current in the vertical and horizontal orientation of transformers K. Górecki et al; Informacije Midem, Vol. 47, No. 1(2017), 3 – 13 a) Figure 9: Measured (solid lines) and modelled (dashed lines) waveforms of transient thermal impedances of transformers with the large ring core RTP at the stimu­lation with the direct current of different values b) Figure 8: Measured (solid lines) and modelled (dashed lines) waveforms of transient thermal impedances of transformers with the small (a) or large (b) ring core made of different materials K. Górecki et al; Informacije Midem, Vol. 47, No. 1(2017), 3 – 13 K. Górecki et al; Informacije Midem, Vol. 47, No. 1(2017), 3 – 13 K. Górecki et al; Informacije Midem, Vol. 47, No. 1(2017), 3 – 13 Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 1(2017), 14 – 23 Small Signal Modeling of Scaled Double-Gate MOSFET for GHz Applications Himangi Sood1, Viranjay M. Srivastava2, Ghanshyam Singh1 1Department of Electronics and Communication Engineering, Jaypee University of Information Technology, Waknaghat, Solan, India. 2Department of Electronic Engineering, Howard Collage, University of KwaZulu-Natal, Durban, South Africa. Abstract: The limits on scaling suggest the technology advancement for the solid-state devices. The double-gate (DG) MOSFET has emerged as an alternative device structure due to the certain significant advantages, i.e. increase in mobility, ideal sub-threshold slope, higher drain current, reduced power consumption and screening of source end of the channel by drain electric field (due to proximity to the channel of the second gate, which reduces the short channel effects). In this work, we have analyzed the double-gate MOSFET (undoped body because the doping rapidly varies the threshold voltage). The analytical expressions has been derived on the basis of surface potential model, which has been further used to yield the potential distribution, drain current, conductance and trans-capacitance. This illustrate the volume inversion effect is quite significant in this device upto the certain range of dimensions. In addition to this, we have analyzed the performance of symmetric DG MOSFET based on the circuit design prospective using S-parameters. Keywords: Short channel effect; Double-gate MOSFET; S-parameters, RF devices; Microelectronics; VLSI. Modeliranje majhnih signalov na pomanjšanem MOSFET z dvemi vrati za GHz aplikacije Izvleček: Meje pomanjševanja zahtevajo napredno tehnologijo polprevodniških elementov. MODFET z dvojnimi vrati se kaže kot alternativen element zaradi očitnih prednosti, kot so: večja mobilnost, idealen naklon pod pragom, višji ponorni tok, znižana poraba in spremljanje izvorne strani kanala z električnim poljem ponora (zaradi bližine drugega kanala, kar zmanjšuje vplive kratkih kanalov). V delu smo analizirali MOSFET z dvemi vrati (nedopiran, saj dopiranje vpliva na pragovno napetost). Analitičen izraz je bil pridobljen na osnovi modela površinskega potenciala in je bil nadalje uporabljen za določanje porazdelitve potenciala, ponornega toka ter prevodnosti in trans kapacitivnosti. Volumski inverzijski vplivi so pomembno do določenih dimenzij. Dodatno smo raziskali učinkovitost simetričnega MOSFET z dvemi vrati na osnovi načrtovanja veza z S parametri. Ključne besede: kratki kanal; MOSFET z dvemi vrati; S parameteri, RF elementi; mikroelektronika; VLSI. * Corresponding Author’s e-mail: himangisood@gmail.com 1 Introduction The MOSFETs are basic cells for the integrated circuits but the demand to increase the switching speed, pack­ing density and reduction in power consumptions are the reasons to extend the work in the direction of miniaturization as suggested by ITRS [1]. Initially, the scaling was the basic tool for miniaturization, however with the advancement in scaling, certain undesirable effects restrict the performance of the device such as short channel effects (SCE) [2, 3]. This motivated to move onto the new device structures. Therefore, Bal­estra et. al. [4] have proposed the first double-gate (DG) MOSFET with significant volume inversion effect. Cur­rently, the DG MOSFET is a subject of intense very large scale integration (VLSI) research and a replacement for conventional bulk MOSFET beyond the 45-nm technol­ogy [5]. It can be scaled to the shortest possible chan­nel length for a given oxide thickness and more elec­trostatically robust than the earlier reported MOSFETs due to the dual-gate shielding and the reduced SCE [6]. Fossum et. al. [7] have analyzed the higher processing speed of DG MOSFET as compared to that of the single-gate MOSFET which further encouraged Solomon et. al. [8] to confer the advantages of the two gates over one gate. Fig. 1 shows the schematic of a DG MOSFET and the Fig. 2 presents the two major DG MOSFET struc­tures: Symmetric type with both gates of identical work-func­tions where both the surface’s channels turn on at the same gate voltage [9] and Asymmetric type with either different work function of the gates or different gate oxide thicknesses where only one channel turns ON at the threshold voltage [10, 11]. Figure 1: The schematic of double-gate MOSFET. Figure 2: (a) Symmetric Double-gate MOSFET, (b) asymmetric Double-gate MOSFET [11]. Taur et. al. [12] have derived the analytical model based on the charge sheet approximation which is applica­ble to all operating regions such as cutoff, linear and saturation. Lu et. al. [13] also have developed a design based on the Poisson theory and the current continuity equation without charge sheet approximation and ac­counting the volume inversion concept. The drain cur­rent, terminal charges and the capacitances are further developed based on the numerical iterations. However, both the authors [12, 13] discussed the asymmetric DG MOSFET which is more sensitive as compared to the symmetric, to Silicon body thickness which further var­ies the threshold voltage. Yu et. al. [14] have proposed an algorithm and the PSP model for approximation of the surface potential of both the single-gate (SG) MOS­FET and DG MOSFET. The model can cover all the oper­ating regions without the use of fitting parameters or charge sheet approximation. However, this algorithm is really complex for implementation. In addition to this, Conde and Sanchez [15] have devel­oped a unified model for symmetric, asymmetric DG MOSFET and bulk MOSFET by using the mix-formula­tion of the charge and surface potential approaches. The mathematical expression derived for the drain current depends on the Silicon body thickness. How­ever, the assumption is made that for the symmetric DG MOSFET, the electric field vanishes at the mid-point of the front and back surfaces but for the asymmetric DG MOSFET, the electric field is present. In addition to this, for the conventional MOSFET the charge cou­pling factor is zero and charge sheet approximation has not been used in ref. [15]. The state of the art of compact models for undoped DG MOSFET using the 1-D Poisson equation with the introduction of the SCE has been discussed in detail in ref. [16]. The threshold voltage based model for undoped DG MOSFET was also explored in ref. [17] and discusses the feasibility and the advantages of DG MOSFET over the conven­tional MOSFET. In ref. [18], an analytical expression for electric potential of the symmetric and asymmetric DG MOSFET with undoped body has been derived by con­sidering the mobile charge in the Poisson equation and it has been illustrated that the ON-state currents differ slightly from each other when the Silicon thickness is significantly small. Cakici and Roy [19] have discussed a circuit perspective with the effect of connected gates or independent gates DG MOSFET, and illustrated that the significantly high noise immunity at low dynamic power dissipation can be achieved by the indepen­dently operating gates (as it increases the gate to gate coupling). In addition to this, it also affects the delay, leakage power and process variations. Moreover, with the use of independent-gates technology, the dynamic threshold voltage control is feasible. Singh and Jiang [20] showed that with the help of asymmetric DG MOS­FET high performance and low power circuits are feasi­ble in the nanometer regime. Therefore, this structure can be used in phase locked loop where the require­ment is high speed, low voltage and low power opera­tion [21]. Further, the other application of symmetric DG MOSFET is as a fast switching device [22]. Recently, Srivastava et. al. [22-24] have analyzed the DG MOSFET and cylindrical surrounding double-gate (CSDG) MOS­FET for the application as a double pole four throw switch. In this research work, we have analyzed the perfor­mance of the symmetric DG MOSFET based on the potential distribution, sheet charge, drain current, terminal charges and trans-capacitance. Further, the trans-capacitances are used for the circuit simulation. The work has been organized as follows. Section 2 has discussion about the symmetric DG MOSFET with its design philosophy and working operation. Section 3 deals with the analysis and the simulation model. Sec­tion 4 explores the simulation results of the symmetric DG MOSFETs. Finally, the Section 5 concludes the work and recommends the future aspects. 2 Symmetric Double-Gate MOSFET The planar DG MOSFET is an extension of the single-gate MOSFET which consist two gates designated as front-gate and back-gate, and a sandwiched ultra thin Silicon layer between these gates [25]. The additional gate significantly increases the electrostatic gate con­trol over the channel and these gates are effective in shielding the drain electric field lines from reaching the source to reduce the potential barrier as well as reduc­ing the short channel effects (SCE). Due to undoped / lightly doped body, the problem of random dopant fluctuation is also negligible. Moreover, both the gates contribute to inversion carriers, which have high drive capability and two channels for the current flow are formed (when these two gates simultaneously control the charge). Also, due to the very thin Silicon film, a bet­ter coupling between front-gate and back-gate exists, which affects the terminal characteristics of the MOS­FET. Double-gate silicon-on-insulator transistor with vol­ume inversion has been analyzed by Balestra et. al. [26]. The basics of the fabrication processes are helpful in the fabrication of DG MOSFETs [27]. Yesayan et. al. [28] have included the effect of interface traps in nanowire and double-gate junction-less devices through a charge-based model that has been developed previously. Roy et. al. [29] have accurately handled both Fermi–Dirac statistics and bias-dependent diffusivity regarding core compact model for undoped, high mobility, and low density of states materials in a double-gate device ar­chitecture. Taur et. al. [13, 30] have presented an ana­lytic potential model for long-channel symmetric and asymmetric double-gate MOSFETs. This design has been derived from the solution of Poisson’s and current continuity equation without the charge-sheet approxi­mation. This results in the analytic expressions of the drain-current, terminal charges, and capacitances for long channel DG MOSFETs continuous in all operation regions (linear, saturation, and sub-threshold), making it suitable for compact modelling. The extension of the DG MOSFET is as cylindrical surrounding-gate MOSFET has been analyzed by Sood et. al. [31]. (a) (b) Figure 3: The band model of the symmetric DG MOS­FET a) Vgs = 0 V b) Vgs = Vth [9 ]. For the symmetric double-gate device structure, at the zero gate voltage the Silicon bands are flat for the mid-gap gate work function as shown in Fig. 3(a). However, at Vg = Vth, the edge of conduction band (Silicon body) near the surface bents as in Fig. 3(b) and approaches the conduction band edge of the n+ source/drain. How­ever, the conduction bands in both surfaces, under both gates, are bent by the similar value as the work functions of two gates are identical. At ON-state, two conductive channels (under both the gates) are formed for the symmetric double-gate device, unless the Sili­con body is not very thin [12]. 3 Analysis of Parameters To analyze the various parameters, we have first ana­lyzed the 1-D Poisson’s equation in the Cartesian coor­dinate system with gradual channel approximation which is given as [32]: (1) where, q and .si are the electron charge and dielectric permittivity of Silicon respectively. The ni, k, and T are the intrinsic concentration of Silicon, the Boltzmann constant, and working room temperature, respective­ly. The V represents the quasi-Fermi potential V = 0 at source side and V = Vds at drain side. We have consid­ered the n+ DG MOSFET, therefore the holes density is negligible and the Silicon film is undoped or lightly doped that is: (2) where, nb is the doping concentration. However, inte­grating the Equation (1) twice, we can get the potential distribution equation as a function of ‘x’ which is po­sition in the Silicon body thickness. In the symmetric DG MOSFET, the electric field is zero at x = 0 that is the center of the Silicon body thickness. 3.1 Surface Potential The surface potential (.s) for DG MOSFET is: (3) The boundary condition for symmetric DG MOSFET: (4) where, .ox, Vgs and tox are the permittivity of oxide, gate voltage and oxide thickness respectively. After bound­ary conditions are satisfied, the center potential is giv­en by: (5) where, tsi is the Silicon body thickness. The surface po­tential is given by: (6) where, (7) 3.2 Drain Current By following the dual integral [33], the drain current can be written as: (8) where Q represents the inversion charge. Therefore, the drain current becomes: (9) where, .ss and .sL are the potential at source side (V = 0) and potential at drain side (V = Vds) which can be found through Equation (6). 3.3 Terminal Charges For the modeling of total inversion charge, Ward Dut­ton charge partition method [24] has been used where the total inversion charge given by is partitioned into source charge (Qs), drain charge (Qd), and gate charge (Qg) such as [34]: (10) We are modeling the charges based on the surface po­tential, therefore transforming y to .s in all the equa­tions and then performing the integration analytically which yields the expressions for the terminal charges. 3.4 Trans-Capacitance Based on the expressions of the terminal charges, the capacitances of the double-gate MOSFET such as gate to source (Cgs), gate to drain (Cgd), and source to drain (Csd) can be written as: (11) where the values of charges Qs, Qd, and Qg are given in Equation (10). These capacitances were used in circuit simulations. The DG MOSFET with same potential ap­plied to both gates is a combination of two single-gate MOSFETs connected in parallel. 3.5 Small Signal Model The small signal equivalent circuit as shown in Fig. 4 has been analyzed. This equivalent circuit has been de­rived from the formation of capacitance and resistance at the junctions and the body of the double-gate MOS­FET. Based on the intrinsic parameters of the device, the Y-parameters can be derived. However, scattering parameters can be obtained by applying the normal conversion based on the Y-parameters [35, 36]. 4 Results and Its Analysis We have presented the simulion results for symmetric DG MOSFET based on the electric potential, electron density, drain current, conductance, terminal charges and transcapacitance. In addition to this, the S-parme­ter and gain analysis has also been performed. 4.1 Volume Inversion Analysis The volume inversion effect is quite significant when the gate-source voltage is less than that of the thresh­old voltage. With the increase in gate voltage, the po­tential increases at the surface as the channel is formed on the surface and the minimum electric potential lies at center of the body x = 0, due to the screening of the center of the Silicon body by the charges on the surface as shown in Fig. 5. In addition to this, the significant ef­fect can be seen for the Vgs = 0.412 V and Vgs = 0.845 V. Figure 5: Electric potential variation with Silicon body thickness (nm). The volume inversion effect is significant up to thresh­old voltage, Vth = 0.4 V but as the gate voltage crosses the threshold voltage the surface and the center po­tentials are decoupled. The center potential saturates at a specific value of potential as the arcsine argument in the Equation (5) cannot grow beyond ./2 but the surface potential keeps on increasing. It is illustrated through the Fig. 6 that the surface potential variation above the threshold voltage is independent of the Sili­con body thickness. The input and output charecter­stics of the DG MOSFET as shown in Fig. 7(a) and Fig. 7(b) are similar to that of the conventional MOSFET. The response of drain to source voltage over the drain cur­rent with various values of Vgs shown in Fig. 7(b) reveals the two operating regions (i. e. linear and saturation re­gions). By extrapolating these curves and finding the intersection with the x-axis the corresponding values of threshold voltage can be obtained (Vth= 0.6 V and Vth = 0.7 V for Vds = 0.5 V and Vds = 1 V, repectively). Figure 6: Electric potential variation with gate to source volatage. 4.2 Drain current analysis The drain current is independent of the device width, however, its dependence over the oxide thickness is quite significant as shown in Fig. 8. It is well illustrated in Fig. 8(b) that the charge formation on the surface increases with the reduction in the oxide thickness, hence results in the increased device current. 4.3 Conductance and Transconductance Analysis Fig. 9 shows the effect of oxide thickness on the con­ductance and transconductance for W = 30 nm and L = 90 nm. As the drain to source voltage increases for chosen oxide thickness, the conductance of the device decreases and reduces to zero as the pinch-off point is achieved as shown in Fig. 9(a). In addition to this, with the decrease of oxide thickness, the conductance of the device increases. In Fig. 9(b) as the gate voltage reaches the threshold voltage the transconductance increases with increasing Vgs. However, transconduct­ance , depends on Cox as in Equation (9) through Ids. Therefore with the increase of oxide thick­ness (which reduces the Cox), the transconductance de­creases. This concludes the significant enhancement in the overall gain of the device. 4.4 Trans-Capacitance and Terminal Charge Analysis Fig. 10(a) and Fig. 10(b) illustrate the trans-capacitance and the variation of terminal charges with Vds for spe­cific value of the oxide thickness. As the oxide thickness increases, the charge storage capacity decreases which further results in the decrease in capacitance of the de­vice. However, the gate to drain capacitance (Cgd) and the source to drain capacitance (Csd) do not depend on drain voltage after the saturation is achieved. Fig. 10(c) and Fig. 10(d), where tox = 2 nm, W = 20 nm shows the variation with width of device (W). When comparing Fig. 10(a) and Fig.10(b) with these, it can be seen that as the width reduces the terminal charges the trans-capacitances are also reduces due to smaller device area. It is illustrated by Fig. 10(b) and Fig. 10(d) that the source charge always saturates to the value of 6/10 of the gate charge and drain charge saturates to 4/10 of the gate charge. 4.5 S-Parameters Analysis Fig. 11 shows the S-parameters computed analytically using equivalent circuit of DG MOSFET with tox = 2 nm, W = 40 nm, L = 1 µm, Vgs = 1 V and Vds = 0.9 V. The S11 represents the input reflection coefficient and it has been illustrated that the S11 reduces for high frequency, which is an advantage as the return loss is reduced for the device. The S21 represents the amount of power transferred from the input port to the output port and it also illustrates that as the frequency increases the S21 parameter remains constant which implies constant forward gain at higher frequencies. Figure 11: S-parameters over a range of high frequen­cies. 4.6 Power Gain Analysis Fig. 12 represents the power gain achieved by the DG MOSFET over the range of frequencies. The unilateral power gain is the gain achieved when the input and the output port are matched simultaneously and the feed­back is neutralized by adding a feedback network. As the frequency increases, this gain decreases exponen­tially and the decrease is smaller at high frequency due to the dual gate controllability. By extrapolating the curve for the gain of 1 dB, the maximum frequency of oscillation can be inferred from the Fig. 12 to be around 254 GHz. The gain achieved (when the two ports are si­multaneously matched) is known as maximum stable power gain. It is predicted by the Fig. 12 that as the fre­quency increases the input-output mismatch decreas­es. In addition to this, the gain always remains above 0 dB which suggests a major figure-of-merit for low noise amplifiers. The maximum unilateral transducer power gain is the ratio of power delivered to load to the power available at the source when the neutralization is pro­vided which further enhances the maximum power transfer. All these gains are stable with the frequency only due to the dual gate controllability as suggested by Fig. 12. Therefore, the DG MOSFET with the analyzed dimensions is useful for high frequency applications. 5 Conclusions and Future Recommendations In this work, the analytical modeling of symmetric DG MOSFET with undoped Silicon body has been pre­sented. The results reveals that for the symmetric DG MOSFET the electric potential varies in proportion with the gate voltage and the minimum potential lies at the center of the Silicon body due to the symmetric nature of device. In addition to this, the volume inversion ef­fect is also significant and the surface potential varia­tion beyond the threshold voltage is independent of the Silicon body thickness. The I-V and C-V model are also reproduced and it is seen that the drain current in strong inversion region is invariant to width of device. Moreover, the intrinsic model has been proposed from where the high fre­quency characteristics in terms the S-parameters and gain are obtained. The results show that the DG MOS­FET is useful for high frequency applications. However, with the optimization of the device structural param­eters, the performance can be improved, which will be reported in future communication. 6 References 1. International Technology Roadmap for Semicon­ductors-2013, www.public.itrs.net 2. Adel S. Sedra and Kenneth C. Smith, Microelec­tronic Circuits: Theory and applications, 7th Ed., Ox­ford University Press, USA, 2014. 3. Ben Streetman and Sanjay Banerjee, Solid State Electronic Devices, 6th Ed., Prentice Hall Publica­tions, USA, 2005. 4. Francis Balestra, Sorin Cristoloveanu, Mohcine Benachir, Jean Brini, and Tarek Elewa, “Double-gate Silicon-on-insulator transistor with volume inversion: A new device with greatly enhaced per­formance” IEEE Electron Device Letters, vol.8, no. 9, pp.410-412, Sept. 1987. 5. Ooi Chek Yee and Lim Soo King,“A comparison simulation study of double gate MOSFET at 45 nm and double gate nano-MOSFET at 10 nm,” Int. J. of Advanced Electrical and Electronics Engineer­ing, vol. 3 no. 3, pp. 17-19, Jan. 2014. 6. D. J. Frank, S. E. Laux, and M. V. Fischetti, “Monte carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?” Proc. of Int. Electron Devices Meeting Technical Digest., San Francisco, CA, USA, 13-16 Dec. 1992, pp. 553-556. 7. Jerry G. Fossum, Lixin Ge, and Meng Hsueh Chi­ang, “Speed superiority of scaled double-gate CMOS,” IEEE Trans. on Electron Devices, vol. 49, no. 5, pp. 808-811, May 2002. 8. P. M. Solomon, K. W. Guarini, Y. Zhang, K. K. Chan, E. C. Jones, G. M. Cohen, A. Krasnoperova, Maria Ro­nay, O. Dokumaci, H. J. Hovel, J. J. Bucchignano, C. Cabral Jr., C. Lavoie, V. Ku, D. C. Boyd, K. S. Petrarca, J. H. Yoon, I. V. Babich, J. Treichler, P. M. Kozlowski, J. S. Newbury, C. P. D’Emic, R. M. Sicina, J. Benedict, and Hon Sum Philip Wong, “Two gates are better than one,” IEEE Circuits and Devices Magazine, vol. 19, no.1, pp. 48-62, Jan. 2003. 9. Qiang Chen, Evans M. Harrell, and James D. Mein­dl, “A physical short-channel threshold voltage model for undoped symmetric double-gate MOS­FETs,” IEEE Trans. on Electron Devices, vol. 50, no. 7, pp. 1631-1637, July 2003. 10. S. Oda and D. Ferry, Silicon Nanoelectronics, CRC Press, Boca Raton, FL, 2006. 11. Jin Woo Han, Chung Jin Kim, and Yang Kyu Choi, “Universal potential model in tied and separated double-gate MOSFETs with consideration of sym­metric and asymmetric structure,” IEEE Trans. on Electron Devices, vol. 55, no. 6, pp. 1472-1479, June 2008. 12. Yuan Taur, Xiaoping Liang, Wei Wang, and Huaxin Lu, “Continuous analytical drain current model for double gate MOSFET,” IEEE Electron Device Letters, vol. 25, no. 2, pp. 107-109, Feb. 2004. 13. Huaxin Lu and Yuan Taur, “An analytical potential model for symmetric and asymmetric DG MOS­FETs,” IEEE Trans. on Electron Devices, vol. 53, no. 5, pp. 1161-1168, May 2006. 14. Bo Yu, Huaxin Lu, Minjian Liu, and Yuan Taur, “Ex­plicit continuous models for double-gate and sur­rounding-gate MOSFETs,” IEEE Trans. on Electron Devices, vol. 54, no. 10, pp. 2715-2722, Oct. 2007. 15. Adelmo Ortiz Conde and Francisco J. Garcia Sanchez, “Unification of asymmetric DG, symmet­ric DG and bulk undoped-body MOSFET drain current,” Solid State Electronics, vol. 50, no. 11-12, pp. 1796–1800, Nov. – Dec. 2006. 16. Adelmo Ortiz Conde, Francisco J. Garcia Sanchez, Juan Muci, Slavica Malobabic, and Juin J. Liou, “A review of core compact models for undoped double-gate SOI MOSFETs,” IEEE Trans. Electron De­vices, vol. 54, no. 1, pp. 131-140, Jan. 2007. 17. Giorgio Baccarani and Susanna Reggiani, “A com­pact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects,” IEEE Trans. on Electron Devices, vol. 46, no. 8, pp. 1656-, Aug. 1999. 18. Yuan Taur, “Analytic solutions of charge and ca­pacitance in symmetric and asymmetric double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2861-2869, Dec. 2001. 19. Riza Tamer Cakici and Kaushik Roy, “Analysis of options in double-gate MOS technology: A circuit perspective,” IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3361-3368, Dec. 2007. 20. Amrinder Singh and Jiang Hu, “Case studies on variation tolerant and low power design using planer asymmetric Double Gate transistor,” Proc. of IEEE 57th Int. Midwest Symposium on Circuits and Systems, College Station, Texas, USA, 3-6 Aug. 2014, pp. 1021–1024. 21. Jubayer Jalil, Mamun Bin Ibne Reaz, and Mohd Alauddin Mohd Ali,“CMOS differential ring oscilla­tors,” IEEE Microwave Magzine, vol. 15, pp. 97-109, July-August 2013. 22. Viranjay M. Srivastava and Ghanshyam Singh, MOSFET technologies for double-pole four-throw radio-frequency switch, Springer International Publishing Switzerland, 2014. 23. Viranjay M. Srivastava, Kalyan S. Yadav, and Ghan­shyam Singh, “Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch” Microelectronics Journal, vol. 42, no. 3, pp. 527-534, 2011. 24. Viranjay M. Srivastava, “Signal processing for wire­less communication MIMO system with nano-scaled CSDG MOSFET based DP4T RF Switch,” Re­cent Patents on Nanotechnology, vol. 9, no. 1, pp. 26-32, March 2015. 25. Hon Sum Philip Wong, Kevin K. Chan, and Yuan Taur, “Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel,” Proc. of Int. Electron Devices Meeting Technical Digest, 10 Dec. 1997, pp. 16.6.1-16.6.4. 26. Francis Balestra, Sorin Cristoloveanu, Mohcine Benachir, Jean Brini, and Tarek Elewa, “Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance,” IEEE Electron Device Letters, vol. 18, no. 9, pp. 410-412, Sept. 1987. 27. Sorab K Ghandhi, VLSI fabrication principles: Sili­con and Gallium Arsenide, 2nd Ed., Wiley India Pvt. Limited, India, 2008. 28. Ashkhen Yesayan, Farzan Jazaeri, and Jean Michel Sallese,”Charge-based modeling of double-gate and nanowire junctionless FETs including inter­face-trapped charges,” IEEE Trans. on Electron De­vices, vol. 63, no. 3, pp. 1368-1374, March 2016. 29. Ananda S. Roy, Sivakumar P. Mudanai, Dipanjan Basu, and Mark A. Stettler, “Compact model for ultrathin low electron effective mass Double Gate MOSFET,” IEEE Trans. on Electron Devices, vol. 61, no. 2, pp. 308-313, Feb. 2014. 30. Xiaoping Liang and Yuan Taur, “A 2-D Analytical Solution for SCEs in DG MOSFETs,” IEEE Trans. on Electron Devices, vol. 51, no. 8, pp. 1385-1391, Au­gust 2004. 31. Himangi Sood, Viranjay M. Srivastava, and Ghan­shyam Singh, “Performance analysis of undoped and Gaussian doped cylindrical surrounding-gate MOSFET with it’s small signal modeling,” Microe­lectronics Journal, vol. 57, pp. 66–75, Nov. 2016. 32. A. B. Bhattacharyya, Compact MOSFET models for VLSI design, John Wiley and Sons, Singapore, March 2009. 33. H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of metal–oxide (insulator)–semiconductor transistors” Solid State Electronics, vol. 9, no. 10, pp. 927-937, Oct. 1966. 34. Donald E. Ward and Robert W. Dutton, “A charge-oriented model for MOS transistor capacitances,” IEEE J. of Solid State Circuits, vol. 13, no. 5, pp. 703-708, Oct. 1978. 35. Simon Ramo, John R. Whinnery, and Theodore Van Duzer, Fields and waves in communication electronics, 3rd Ed., John Wiley and Sons Inc., New York, pp. 537-541, 1993. 36. Madhu S. Gupta, “Power gain in feedback ampli­fiers, a classic revisited,” IEEE Trans. on Microwave Theory and Techniques, vol. 40, no. 5, pp. 864-879, May 1992. Arrived: 03. 11. 2016 Accepted: 03. 01. 2017 H. Sood et al; Informacije Midem, Vol. 47, No. 1(2017), 14 – 23 H. Sood et al; Informacije Midem, Vol. 47, No. 1(2017), 14 – 23 H. Sood et al; Informacije Midem, Vol. 47, No. 1(2017), 14 – 23 H. Sood et al; Informacije Midem, Vol. 47, No. 1(2017), 14 – 23 (a) (b) Figure 4: Small signal modeling of DG MOSFET at (a) Switch-ON state, and (b) Switch-OFF state. H. Sood et al; Informacije Midem, Vol. 47, No. 1(2017), 14 – 23 (a) (b) Figure 8: Response of drain current for various gate to source voltage at Vds = 1 V and L = 90 nm for (a) fixed tox = 2 nm and (b) fixed width W = 30 nm. (a) (b) Figure 7: Drain current variation of DG MOSFET for tox = 2 nm, W = 30 nm and L = 90 nm at various (a) gate to source voltage and (b) drain to source voltage. H. Sood et al; Informacije Midem, Vol. 47, No. 1(2017), 14 – 23 (a) (a) (b) (b) Figure 9: Effect of oxide thickness on the (a) conduct­ance at Vgs = 1 V and (b) trans-conductance at Vds = 1 V. (c) (d) Figure 10: (a) Trans-capacitance, (b) terminal charges for W = 30 nm and L = 90 nm, (c) Trans-capacitance, and (d) terminal charges for W = 20 nm, tox = 2 nm and L = 90 nm, at Vgs = 1 V. H. Sood et al; Informacije Midem, Vol. 47, No. 1(2017), 14 – 23 Figure 12: Response of the power gain at various fre­quencies for the DG MOSFET. H. Sood et al; Informacije Midem, Vol. 47, No. 1(2017), 14 – 23 H. Sood et al; Informacije Midem, Vol. 47, No. 1(2017), 14 – 23 Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 1(2017), 24 – 31 DOE Study of Epitaxial Layer Thickness and Resistivity Effects on P-i-N Diode for beyond 300 V of Reverse Voltage Applications J. H. See1, M. K. Md Arshad1,2, M. F. M. Fathil1, C. H Voon1, U. Hashim1,2, Subash C. B. Gopinath1 1Institute of Nano Electronic Engineering, Universiti Malaysia Perlis, Kangar, Perlis, Malaysia 2School of Microelectronic Engineering, Universiti Malaysia Perlis, Kangar, Perlis, Malaysia Abstract: A discrete power switching device used in the applications of computer and telecommunications requires operating less than 300 V during reverse bias, but for the use of motor control, robotics, and power distribution, it requires operating at beyond 300 V. With the current design structure, the P-i-N diode device can only operate at 250 V. To widen the operating range of the P-i-N power switching avalanche diode that can be operated more than 300 V, we studied the effects of the epitaxial layer thickness (WD) and resistivity (.) during forward and reverse biasing by performing a process simulation as well as the confirmation on the two level factorials of design of experiment (DOE) of physical wafers. The result shows that, the changes of the WD of 42 µm and . of 32 ohm·cm on a P-i-N diode can increase the reverse breakdown voltage (VR) performance beyond 300 V during reverse bias. Keywords: Forward voltage; Breakdown voltage; Power device Načrtovanje eksperimenta vplivov debeline in upornosti epitaksijske plasti P-i-N diode pri reverznih napetostih nad 300 V Izvleček: Diskretni močnostni stikalni element za uporabo v računalnikih in telekomunikacijah zahteva delovanja pri zaporni napetosti pod 300 V. Pri krmiljenju motorjev, v robotiki ali pri močnostnih aplikacijah pa zahteva delovanje v zaporni smeri preko 300 V. Trenutna struktura P-i-N diode lahko deluje le do 250. Za višje napetosti je potrebna močnostna plazovita P-i-N dioda, na kateri smo preučevali vplive debeline epitaksijske plasti in upornosti pri prevodni in zaporni napetosti. Analiza sloni na simulaciji procesa dvonivojske faktorizacije načrtovanja eksperimenta silicijeve rezine. Rezultati izkazujejo, da sprememba debeline za 42 µm in upornosti za 32 ohm·cm zviša prebojno napetost preko 300 V. Ključne besede: Forward voltage; Breakdown voltage; Power device * Corresponding Author’s e-mail: mohd.khairuddin@unimap.edu.my 1 Introduction Diode is a simple semiconductor device with two ter­minals, allowing only unidirectional current to flow. It is created with the presence of p-type and n-type semi­conductor materials in intimate contact on an atomic scale, yielding the P-N junction in between [1]. The formation of P-N junction occurred by diffusion of ac­ceptor impurities (p-type dopant) into an n-type silicon crystal or vice versa. A depletion region formed instan­taneously across a P-N junction and it is easily to be de­scribed when the junction is in thermal equilibrium or in a steady state: in both of these cases, the properties of the system does not vary in time; thus, it is known as dynamic equilibrium [2, 3]. Figure 1 (a) shows the diode 2D structure and electrical field distribution of P-N diode. For high power applications, an ideal power diode should be able of conducting high forward bias current (IF) during forward bias voltage (VF) of ~0.7 V and supporting high reverse breakdown voltage (VR) in the range of 50 to 200 V [4, 5]. During reverse bias, P-N diode experiences the ava­lanche breakdown. To achieve the avalanching, besides the requirement of a large field, it also requires a suffi­cient distance to allow the electron to accelerate, hence gain enough kinetic energy, and lead to an avalanche of multiple hole-electron pair’s creation [6]. In other words, to ensure the high VR, a thick n-type substrate bulk is required for a vertical structure of simple P-N junction diode. For a vertical structure of P-N junction diode, a very thick wafer substrate bulk can be used to fulfill the requirement of a power diode. However, thicker substrate exhibits several drawbacks, which are 1) greater weight and 2) higher production cost. Alternatively, higher VR and IF can be achieved by using the P-i-N diode structure with a thinner substrate. The P-i-N diode was one of the very first semiconductor de­vices developed for power circuit application [4, 7]. This evolution came from a conventional P-N junction di­ode with the addition of an extra intrinsic layer depos­ited between p-type and n-type regions. Figure 1 (b) (i) illustrates the P-i-N diode structure in 2D structure and electrical field distribution of P-i-N diode. In P-i-N diode, the reverse breakdown voltage is dependence on the depletion region formed with a P-N junction structure. The voltage is primary determined within the N-type drift region. Thus low doping concentration for the N-type drift region is more beneficial in order to hold the carrier from flowing between P- and N-region. The sili­con P-i-N diode is designed to support large voltages, which rely upon the high level injection of minority carrier in the N-type drift region [8]. Therefore, to sup­port a large voltage in the reverse breakdown voltage mode, an appropriate choice of doping concentration and thickness of the N-drift region needs to be made. Nevertheless, a narrower drift region is preferable be­cause it can contain smaller amount of stored charges during the on-state operation, enabling faster turn-off. Material substitution is one way to achieve narrower drift region thickness [9]. For example, by using silicon carbide, narrower drift region can be attained when compared to silicon devices. This is due to much larger electric field can be supported in silicon carbide. As a result, it favors a faster switching speed with reduced reverse recovery current and very high breakdown voltage can be achieved [10]. However, the high cost is a major concern, and silicon P-i-N diode still can be modified and continue to play an important role in the application, especially in medium range of breakdown voltage. This can be explained based on expression as shown in Equation (2). The expression for VR in this P-i-N diode can be derived by using higher critical electric field (EC) [11, 12] Based on Figure 1 (b) (ii), EC is the critical elec­tric field and WD is depletion region thickness during reverse bias. Since P-i-N diode operates in a thickness-limited mode, which is controlled by the thickness of N- region epitaxial layer, the WD can be referred to as the thickness of the N- epitaxial layer in i-region. The VR can be calculated as the area of the trapezium (Figure 1 (b) (ii)) as in Equation (2). (2) By using the Equation (2) for the variation in the electric field with distance: (3) and substituting Equation (3) in Equation (2), the VR for the punch through diode is obtained as in Equation (4): (4) The VR can be affected by the variable thickness of the N- region (WD) and the doping concentration of the N- epitaxial layer (ND). The ND can be translated into the resistivity of the N- layer [11],. The increase of the ND results in lower resistivity. In this paper, P-i-N diode with high resistivity N region (N- region) is used to replace the intrinsic layer. For this purpose, a commercially available 250 V P-i-N power switching diode was used to evaluate effects of N- epi­taxial layer thickness (WD) and resistivity (.) as the in­trinsic layer effect to the P-i-N power switching diode on the performance of current-voltage (I-V) charac­teristic in terms of diode’s VR. The aim of this study is to have a diode that can withstand beyond 250 V for motor control, robotics and power distribution appli­cations. The N- region is deposited on top of the wafer substrate through epitaxial process. 2 Methodology In this work, the simulation of the P-i-N diode is per­formed using technology computer-aided design (TCAD) simulation software i.e. Sentaurus WorkBench, as well as the fabrication and characterization of the P-i-N diode. The P-i-N power switching diode diffuses a circular shaped boron (P+ anode junction) into an N- type epitaxial layer on a low bulk resistance N+ substrate. Another N+ diffused isolation region at the perimeter of the anode junction to reduces leakage current. The backside of the wafer is sputtered with platinum (Pt) and gold (Au). The process followed by a quick drive-in cycle for both elements, from the bulk all the way through the epitaxial layer and the P+ anode junction. Pt improves the life time cycle, reducing the reverse recovery time (trr) [13]. Au increases the epitax­ial layer’s trr resistance, which increases the resistance of drastic oscillation of the signal. Thus, it produces a wider P-N junction depletion region and reducing the capacitance. Figure 2 illustrates the cross-section de­sign of the P-i-N power switching diode. Figure 2: Cross-section structure of P-i-N power switch­ing diode. 2.1 Numerical Simulation The VR of P-i-N power switching diode operates in WD limited mode of the epitaxial layer. The first approach is to alter the WD by adjusting the depth of the P+ an­ode junction through diffusion with boron as demon­strated in Figure 2. By reducing the junction diffusion drive time, a shallower anode junction is formed. With this approach, the WD is increased [14]. However, this method has several weaknesses. The anode junction diffusion process is difficult to control, which leads to process variation. The inconsistent process tempera­ture of diffusion furnace results in lower VR at the edges compared to the centre of the wafers, as wafer edges tend to have a higher process temperature compared to the wafer centre [14]. Another drawback is the dif­fusion process is performed under a high temperature, thus caused the up diffusion from the heavily doped N+ bulk substrate. This resulted in a less favourable higher VF [14]. The second approach is to adjust the epitaxial layer pro­file (WD and .) of the substrate [14]. With the zero punch through structure of the P-i-N diode, as observed from the Equation (4), the WD and ND are dominant factors, which increase the VR. The second approach is more favourable due to better control of wafer fabrication process. A series of simulation and DOE is performed to show the effects of the WD and ND on the I-V characteristic using TCAD simulation software. The applications of TCAD simulation include technology and design rule development, as well as the extraction of compact models for manufacturability [15]. Initially, a half diode cross-section structure is designed by using SProcess. After the half diode is created, reflecting boundary con­ditions is applied to generate a full simulation diode model symmetrically. For the SProcess step, a layer of phosphorus dopant (N- epitaxial) thickness is grown on top of the N+ bulk silicon substrate, which is initially doped with arsenic. The silicon substrate orientation of <100> is used. The dopant parameter is defined as @epidose@ and WD pa­rameter is defined as @epiThick@. With the parameters are defined in general, several WD and doping concen­trations are utilized in the simulation (Table 1) to evalu­ate the output response of the I-V characteristic. Table 1: Simulation thickness and concentration dos­age of N- layer. Split Epitaxial Layer Thickness, @epiThick@ (µm) Epitaxial Layer Dopant Concentration, @epidose@ (cm-3) a 42 1.68×1014 b 42 1.58×1014 c 42 1.48×1014 d 42 1.36×1014 e 34 1.68×1014 f 34 1.58×1014 g 34 1.48×1014 h 34 1.36×1014 The selection of the 34 µm and 42 µm thickness of WD in simulation is due to lower and upper specification on the existing diode device epitaxial layer evaluation shown as group C in Figure 5, which will be explained in Section 2.2. The various dopant concentrations of N- epitaxial layer are selected to measure the electrical output response impact in simulation. By adjusting the phosphorus dopant concentration at the N- epitaxy layer via implantation, the . can be controlled, since the dopant concentration is inversely proportional with resistivity [16]. Subsequently, a 1 µm thickness of oxide layer is depos­ited, followed by opening of the anode area with the photolithography and etching process for electrode deposition. Next, boron is implanted with a dosage of 5×1015 cm-3, anode junction drive in temperature and time for 1200 °C and 240 mins, respectively. After the anode junction is formed, the oxide layer is stripped off and then re-deposited with the same thickness. This re-deposited oxide layer is to react as the pattern oxide, followed by a 2 µm thickness of front metal Al layer, which act as the ohmic contact and a 1 µm thickness of Si3N4 nitride layer, which act as the passivation layer. All of these three layers are formed with photolithog­raphy and etching process. The final device structure is shown in Figure 3. Figure 3: P-i-N diode structure with doping profile dis­tribution. 2.2 Design of experiment and process split Based on the simulated results, the devices are fabri­cated with a four corners matrix DOE to investigate the effects of WD and . in order to achieve VR above 300 V. In the fabrication process, the epitaxial layer is grown and diffused with dopant material on the wafer bulk as shown in Figure 4. Figure 4: Wafer starting material with deposited epi­taxial layer. The DOE of the four corners matrix that includes the WD and . is detailed in Table 2. As mentioned previous­ly, the epitaxial layer dopant concentration and . are inter-related. The relationship between resistivity and phosphorus doping concentration has been studied for doped silicon as in [16]. Four corners matrix are groups of epitaxial layer covering the lower and upper speci­fications. It is used in the evaluation of the P-i-N diode performance when operating at the corners (lower or upper end) of epitaxial specifications as compared to the centre. Illustrations of total 5 groups with two level factorial DOE are shown in Figure 5 consisting of group A, B, C, D and E. The two factors (epitaxial layer thick­ness and resistivity) in low, centre and high condition. Design of experiments (DOE) is a systematic approach in engineering problem-solving that applies principles and techniques from the data collection stage. The out­put response from the data collection includes forward voltage, reverse breakdown voltage and reverse leak­age current. The focus on the study is to increase the VR during reverse bias without changing much of the VF and IR. A total of 15 wafers lot are fabricated with the same P-i-N diode design at process corners with low/high WD and low/high .. Afterward, the wafers are fabricated and electrically characterized. Electrical results of VF, VR, and reverse leakage current (IR) are the main param­eters of interest and then analysed with statistical soft­ware (for profiler study). The predicted profiler study is done to determine the dominant factor that affects the electrical performance and the optimal epitaxial pro­file. To ensure the repeatability of the result, each of the splits is repeated 3 times for the wafer fabrication and characterization. 3 Results and discussions 3.1 Simulation results Figure 6 shows (a) reverse bias and (b) forward bias of the simulated I-V characteristics for different WD and concentration of the N- epitaxial layer as tabulated in Table 1. In Figure 6 (a), a clear significant difference of the VR with difference of WD (i.e. 34 and 42 µm) is ob­served. At 10 nA (shown as dotted line), the 34 µm of WD, results in lower VR ranging from -400 V to -415 V. In contrast the 42 µm of WD shows a higher VR ranging from 460 V to 490 V. The increase of the WD leads to an increment of the stored charges available and makes the diode to behave like a resistor [17]. According to Ohm’s law and with the same current, the resistance is increased as a result of the increase in voltage. On the other hand, the increase of the dopant concentra­tion ND, from 1.38×1014 cm-3 to 1.68×1014 cm-3, results in slight decrease of VR. This shows that the WD is more dominance factor affecting the VR performance. Never­theless, both impacts are in agreement with Equation (4) as previously explained. Figure 6 (b) shows the forward bias results of the simu­lated diode. One can see that, significant impact is only related to the different WD (i.e. 34 µm and 42 µm), while no variation can be observed for different dopant con­centration. In comparison between 34 µm and 42 µm of WD, 1) at low current of 200 mA (shown in the blue dotted line) regardless of the dopant concentration dif­ference, VF values of 870 mV and 880 mV, respectively. At low IF biasing, the difference of the WD results in a small change of VF with the range of 10 mV difference. 2) The difference in VF output response becomes widen between various WD with the increase of the IF. This can be explained, when a P-i-N diode is forward biased, where holes and electrons are injected from the P and N regions into the i-region, which is represented as WD. These charges do not recombine immediately. Instead, a finite quantity of charge always remains stored and results in a lowering of the .. So, the increase of IF leads the decrease of the forward series resistance (RS) [18]. The WD plays a greater role to change the VF with low resistivity. (a) (b) Figure 6: I-V characteristics under (a) reverse bias and (b) forward bias for different WD and dopant concentra­tions. From the simulation, by changing the WD and dopant concentration of the epitaxial layer, the VR shows more significant difference compared to VF. The reason being the P-i-N diode exhibiting reverse capacitance charac­teristics during reverse bias where dopant concentra­tion and the WD shows a more responsive curve. While forward biasing, P-i-N diode exhibits the forward se­ries resistance characteristics where the difference of the WD plays a greater role when the IF is increased to a certain level [18], [19]. The phenomenon of the less responsive output on the forward bias is preferable as the focus on the study is to increase the VR during re­verse bias without changing the VF. With the confirmation of the theory through the TCAD simulation software, a wafer fabrication DOE has been conducted to validate the results by taking into ac­count of the process variation and material variation. 3.2 DOE wafer results From the DOE experimental results, in addition to VR and VF, and IR are also considered. The statistical analy­sis, i.e. JMP profiler is used to analyse the effect of the WD and . as shown in Figure 7. The line curve can be analysed by separating the two groups, which are WD and . versus electrical responses. The x-axis of the chart represents the WD, the . and the desirability of the responses. The curvature of the line in desirability row indicates how impactful the two factors (WD and .) to the electrical output response of the device. The y-axis represents the electrical output response of VR, VF and IR. In Figure 7, WD plays a dominant factor compared to the . in VR and VF. This is due to the VR and VF show more responsive curve on WD compared to .. In other words, a greater gradient is observed in WD line curve when compared to the .. However, the IR change on both WD and . is not significant (in nano-ampere range). Figure 7: Statistical data on the impact of WD and . on the fabricated devices. As expected, by changing the WD (34 µm to 42 µm), a significant difference on electrical performance for both VF at 200 mA and VR at 100 µA can be observed. This is related to the increase of the WD results in the VR and VF is also increased. Interesting to note that, an increase of VF around 10 mV can be observed in Figure 7, is similar to the result obtained in simulation Figure 6 (b). With WD increased from 34 µm to 42 µm, at 100 µA, the VR shows almost similar response between simula­tions versus actual DOE. The voltage different between simulation and actual DOE is around 20 V is due to the uniformity of the boron pre deposition process. In Figure 7, based on the statistical analysis JMP soft­ware, the VR shows a significant improvement from 300 V to more than 500 V when replaced with WD of 42.43 µm and the . of 33.22 ohm.cm. From the DOE evaluation, both WD and . in group A shows the optimum condition to achieved the desired device performance. The target WD is 42 µm with win­dow of 40–44 µm and the target . is 32 ohm·cm with window of 30–34 ohm·cm. The tolerance of ±4 µm of WD and ±2 ohm·cm window are the narrowest toler­ance, limited by process fabrication for this device. The small tolerance is preferable to reduce the process variation. With the fixed epitaxial layer substrate profile window, a total of 3 qualification lots with 5 wafers each have been fabricated in different time frames to moni­tor the process variation. All VR and VF are monitored at wafer level electrical test. Based on the 3 qualification lots result shown in Figure 8, VR and VF electrical test re­sult distribution are well within the specifications. The VF distributions are less than 1.5 V and VR distribution are above 450 V. 4 Conclusion In summary, through the understanding of device be­haviour and process TCAD simulation performance, the WD plays a major role to increase the VR when com­pared to the .. Further, the simulated result is validated through fabricated devices. To achieve beyond 300 V of VR, the WD is 42 µm and the target . is 32 ohm·cm. A statistical analysis based on the electrical data was carried out to determine the best wafer substrate win­dow. Subsequently, a validation process using 3 qualifi­cation lots is done. The VR shows a significant improve­ment from 300 V to more than 500 V when replaced with the WD of 42 µm and the epitaxial resistivity of 32 ohm·cm. The implementations of the new epitaxial specification have been successfully used to expand the product portfolio of this 300V P-i-N power switch­ing diode that can be used in motor control, robotics and power distribution. 5 Acknowledgments The authors would like to acknowledge all the team members in Institute of Nano Electronic Engineer­ing (INEE), Universiti Malaysia Perlis (UniMAP) for their guidance and help. 6 References 1. M. Quirk and J. Serda, Semiconductor Manucfac­turing Technology. Prentice Hall, 2001. 2. J. E. Ayers, Digital Integrated Circuits: Analysis and Design. Taylor & Francis, 2003. 3. S.-M. Kang and Y. Leblebici, CMOS Digital Integrat­ed Circuits. Tata McGraw-hill, 2003. 4. B. J. Baliga, Power Semiconductor Devices. PWS Publishing Company, 1996. 5. D. A. Neamen, “Semiconductor Materials and Di­odes,” in Microelectronics: Circuit Analysis and De­sign, McGraw-Hill, 2010, pp. 9–66. 6. J. J. Sparkes, Semiconductor Devices, 2, Revised ed. CRC Press, 1994. 7. A. A. Sweet, Designing Bipolar Transistor Radio Frequency Integrated Circuits, Illustrate. Artech House, 2007. 8. J. F. White, Microwave Semiconductor Engineer­ing, Illustrate. Springer Science & Business Media, 2012. 9. Z. Xu et al., “Fully- and Quasi-Vertical GaN-on-Si p-i-n Diodes: High Performance and Comprehen­sive Comparison,” IEEE Trans. Electron Devices, pp. 1–7, 2017. 10. J. Xu, “Technology for Planar Power Semiconduc­tor Devices Package with Improved Voltage Rat­ing Technology for Planar Power Semiconductor Devices Package with Improved Voltage Rating,” Virginia Polytechnic Institute and State University, 2008. 11. B. Jayant Baliga, Fundamental of Power Semicon­ductor Devices. Springer, 2008. 12. P. Spirito, Power Semiconductor Devices. Dept of Electronics and Telecommunications, University Federico II. 13. C. M. Cheh et al., “The Impacts of Platinum Diffu­sion to the Reverse Recovery Lifetime of a High Power Diode Devices,” MATEC Web Conf., vol. 78, p. 1089, Oct. 2016. 14. C. C. Mee, M. K. Md Arshad, M. Fathil, and U. Hashim, “The effects of intrinsic silicon epitaxial layer in p-i-n diode for high power devices,” ARPN J. Eng. Appl. Sci., vol. 10, no. 18, 2015. 15. R. W. Dutton and A. J. Strojwas, “Perspectives on technology and technology-driven CAD,” IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 19, no. 12, pp. 1544–1560, 2000. 16. J. C. Irvin, “Resistivity of bulk silicon and of dif­fused layers in silicon,” Bell Syst. Tech. J., vol. 41, no. 2, pp. 387–410, 1962. 17. N. I. Shuhaimi et al., “Comparison on I-V perfor­mances of Silicon PIN diode towards width vari­ations,” in 2010 IEEE International Conference on Semiconductor Electronics (ICSE2010), 2010, pp. 12–14. 18. B. Doherty, “PIN Diode Fundamentals,” Microsemi. 19. W. E. Doherty and R. D. Joos, The PIN Diode Circuit Designers’ Handbook. Watertown: Microsemi Cor­poration, 1998. Arrived: 05. 11. 2016 Accepted: 22. 02. 2017 J.H. See1 et al; Informacije Midem, Vol. 47, No. 1(2017), 24 – 31 Figure 1: Comparison of ideal (a) P-N junction and (b) P-i-N diode in terms of (i) 2D structure and (ii)electrical field distribution. J.H. See1 et al; Informacije Midem, Vol. 47, No. 1(2017), 24 – 31 J.H. See1 et al; Informacije Midem, Vol. 47, No. 1(2017), 24 – 31 Figure 5: a) Two level factorials of DOE, Factor A and B refer to epitaxial layer thickness and epitaxial layer resistivity respectively. b) The location of four corners and centre of the evaluation samples consists of group A, B, C, D and E. J.H. See1 et al; Informacije Midem, Vol. 47, No. 1(2017), 24 – 31 Table 2: Substrate 4 corner split table Wafer# Group Description (Thickness/ Resistivity) Target Thickness (µm) Phosphorus dopant concentration (cm-3) Conversion of dopant concentration to Resistivity (ohm·cm) Target resistivity value (ohm·cm) Exact Thickness value (µm) Exact resistivity value (ohm·cm) 1 A High / High 42 1.36×1014 32.8 32 42.6 33.223 2 D Low / High 34 1.36×1014 32.8 32 34.34 30.093 3 C Center / Center 38 1.58×1014 28.2 29 37.95 28.742 4 A High / High 42 1.36×1014 32.8 32 42.6 33.223 5 D Low / High 34 1.36×1014 32.8 32 34.34 30.093 6 B High / Low 42 1.68×1014 26.6 26 42.15 26.524 7 E Low / Low 34 1.68×1014 26.6 26 33.85 25.723 8 C Center / Center 38 1.58×1014 28.2 29 37.89 28.742 9 B High / Low 42 1.68×1014 26.6 26 42.15 26.524 10 E Low / Low 34 1.68×1014 26.6 26 33.85 25.723 11 A High / High 42 1.36×1014 32.8 32 42.6 33.223 12 C Center / Center 38 1.58×1014 28.2 29 37.95 28.742 13 D Low / High 34 1.36×1014 32.8 32 34.34 30.093 14 E Low / Low 34 1.68×1014 26.6 26 33.85 25.723 15 B High / Low 42 1.68×1014 26.6 26 42.15 26.524 J.H. See1 et al; Informacije Midem, Vol. 47, No. 1(2017), 24 – 31 J.H. See1 et al; Informacije Midem, Vol. 47, No. 1(2017), 24 – 31 Figure 8: Qualification lot electrical distribution when (a) VF at 200mA and (b) VR at 100 µA. J.H. See1 et al; Informacije Midem, Vol. 47, No. 1(2017), 24 – 31 Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 1(2017), 32 – 39 2D Simulation Study of p-type TFTs with Chemically Deposited Poly-PbS Active Channel Abimael Jiménez P.1, Amanda Carrillo C.1, Shehret Tilvaldyev1, Manuel A. Quevedo L.2, J. Antonio Munoz G.3 1Electrical and Computer Engineering Department, Universidad Autónoma de Ciudad Juárez, Ciudad Juárez, Chihuahua, México 2Materials Science and Engineering Department, University of Texas at Dallas, Richardson, USA 3Engineering Department, Universidad de Guadalajara, Jalisco, México Abstract: In this work, the two-dimensional (2D) numerical simulation of p-type poly-PbS TFT electrical characteristics are performed using a physically based device simulator Atlas/Silvaco. The analytical expressions of defect density models for acceptor- and donor-like traps are defined for poly-PbS thin film material deposited with chemical bath deposition technique. The parameters of defect density model are optimized based on Levenberg-Marquardt algorithm to fit simulated and experimental results of TFTs. It is shown that the spatially uniform density of defect states method used for trapped charge evaluation in Atlas gives good agreement between simulated and experimental characteristics. An important presence of deep (Gaussian) acceptor- and donor-like density of states in poly-PbS band gap is confirmed. By controlling cation (donor-like) and anion (acceptor-like) vacancies of poly-PbS films could improved the performance of p-type TFTs. Keywords: thin film transistor, simulation, density of states, optimization, defects, chemical bath deposition 2D simulacija TFT tipa p s kemijsko nanešenim aktivnim poli-PbS kanalom Izvleček: Dvodimenzonalne simulacije električnih karakteristik TFT tipa p s poli-PbS so opravljene s simulatorjem Atlas/Silvaco. Analitični izrazi modelov stanj defektov za akceptorje in donorje so določeni za poli-PbS material, ki je nanešen s pomočjo tehnike kemijske kopeli. Parametri modela so optimizirani s pomočjo Levenberg-Marquardt algoritma tako, da se simulacije ujemajo z eksperimentalnimi meritvami. Izkazalo se je, da se rezultati prostorsko enotne metode v Atlas-u dobro ujemajo z eksperimentalnimi rezultati. Dokazana je bila pomembnost prisotnosti globoke Gausove porazdelitve defektov. Učinkovitost TFT-ja se lahko izboljša s kontroliranim vnosom vrzeli donorskega oziroma akceptorskega tipa. Ključne besede: tankoplastni tranzistor, simulacije, gostota stanj, optimizacija, defekti * Corresponding Author’s e-mail: abimael.jimenez@uacj.mx 1 Introduction Thin film transistors (TFTs) are a growing technology in the flexible and large area of electronic fields, and recently they have been investigated mainly because of their low cost of production. Also, this technology is interesting due to the recent increase in the area of displays and its use to develop high-speed devices switching pixels, electroluminescent displays, active matrix displays, image sensors, and identification sys­tems [1, 2]. There is a variety of thin film mature technologies in the market such as hydrogenated amorphous silicon TFTs (a-Si:H TFTs), polycrystalline TFTs (particularly low tem­perature), and organic TFTs (OTFTs). These technolo­gies have advantages and disadvantages. For example, although a-Si:H TFTs have good uniformity, they have the disadvantages of insuficient mobility for driving a large screen LCD at a high speed, a large threshold volt­age (VTH) instability due to the desorption of hydrogen, and the absence of p-type semiconductor material for Metal-Oxide-Semiconductor (MOS) technology. Fur­thermore, poly-TFTs have high mobility, but they have a drawback in that VTH largely varies due to a process for crystallizing an active layer by annealing. Also, OT­FTs have effcient p-type semiconductor materials, but they have the disadvantages that there is not a solution for n-type semiconductor material, they have VTH in sta­bility due to the oxidation of organic materials [3], and the organic molecules need to be aligned well at the interface or formed into large, low-defect grains, which is no trivial work. Because some disadvantages are present in TFTs tech­nology, researchers are looking for different options that can replace commercial materials and contribute to a better physical understanding of new materials for flexible electronics. The most important advantage of low temperature poly-TFTs technology is that it does not need expensive equipment of vacuum and high temperature processes, but printing or chemical bath deposition (CBD) techniques can still be used. In ad­dition, CBD chalcogenide films are attractive for poly-TFTs for large area electronics given their simple fabri­cation, low temperature, and compatibility with most substrates. Moreover, chalcogenides materials are suit- able candidates for their implementation in poly-TFTs because they have good electrical and morphological properties. In particular, lead sulfide (PbS) chalcogenide is an im­portant binary IV-VI semiconductor material with a di­rect narrow band gap [4]. It is also widely used in MOS transistors and optical devices [5], and it is one of the most widely studied semiconductos over the last dec­ades [6, 7]. Recently, a p-type poly-TFT fabricated with PbS as semiconductor deposited by CBD technique was reported [8]. Using this technique, PbS thin films with photosensitive polycrystalline p-type conductiv­ity can be obtained at room temperature. Nevertheless, the CBD technique introduces structural defects (traps) during the deposition process, and nu­merous important electrical parameters of the TFTs are strongly affected by the density of defect states [9]. Besides, a model to predict and optimize the electrical characteristics of PbS poly-TFTs based on CBD tech­nique is needed, so undoubtedly, device simulation tools are necessary to model and simulate a PbS poly-TFT. This work implements the 2D simulation of p-type poly-TFTs electrical characteristics using Atlas/Silvaco simulation models for Density of Defect (Trap) States (DDS). 2 Simulation of a p-type poly-PbS TFT The simulated poly-PbS TFT is shown in Fig. 1, which has the same configuration of the fabricated device. It was fabricated in a bottom gate contact configura­tion by following these steps. First, 100 nm of Chro­mium (Cr) were deposited on the substrate. Second, the Cr film was patterned to define the gate contact. Third, 90 nm of hafnium oxide (Hf O2 ) were deposited as gate dielectric. Then the PbS thin film was deposited by the CBD technique. After that, PbS and HfO2 films were patterned and etched. Finally, 100 nm of gold (Au) were deposited and patterned to form the source and drain contacts. This process yields devices with channel widths (W) of 40, 80, and 160 µm and channel lengths (L) of 20, 40 and 80 µm. The detailed fabrication infor­mation of the p-type poly-PbS TFTs can be found in the literature [8]. However, in this work only the results of a TFT with W = 40 µm and L = 20 µm are reported. Also, the geometrical and technological parameters of simu­lated poly-TFT are listed in Table 1. Figure 1: Cross section of PbS TFT simulated whit W=40 and L=20 µm. We used Cr as gate metal, Hf O2 as dielectric, and Au as source - drain contacts. 2.1. Simulation Method In this study the spatially uniform DDS method was adopted [10, 11]. It considers a polycrystalline PbS film as a homogenous material with an effective den­sity of trapping states, which are uniformly distributed throughout the semiconductor layer of PbS. The ad­vantage of this method is that it avoids complex mesh definitions of multigrain structures, which require the knowledge of the grain size. If the transistor has a long channel (>10µm), this method will be effective for sim­ulations of poly-TFTs due to the large number of grains and grain boundaries. For instance, the thin PbS films used in the device fabrication have an average grain size of (~ 22nm) [8]. It results in the closely spaced grain boundary regions with increased defect densities and domination of carrier dynamics in the intergrain re­gions over the intragrain monocrystalline effects in the carrier transport. For this reason, the thin film of poly-PbS can be considered as a homogenous material with approximately uniformly distributed defect states. Table 1: Device Parameters used in Simulation. Parameter Value Channel length L (µm) 20 Channel width W (µm) 40 Gate oxide thickness tox (nm) 90 PbS thickness (nm) 64 Energy gap at 300 K (eV) 0.37 Dielectric constant 175 Low field hole mobility (experimental) (cm2 /Vs) 0.09 Low field hole mobility (optimized) (cm2 /Vs) 0.064 Gate workfunction fms (eV) 4.4 Density of acceptor-like tail states NTA (cm-3/eV) 1.74x1021 Density of donor-like tail states NTD (cm-3/eV) 2.38x1017 Density of acceptor-like Gaussian states NGA (cm-3/eV) 4.35x1018 Density of donor-like Gaussian states NGD (cm-3/eV) 2.04x1018 Decay energy for acceptor-like tail states WTA (eV) 0.0041 Decay energy for donor-like tail states WTD (eV) 0.0104 Decay energy for acceptor-like Gaussian WGA (eV) 0.0054 Decay energy for donor-like Gaussian WGD (eV) 0.0040 Energy of Gaussian for acceptor-like states EGA (eV) 0.20 Energy of Gaussian for donor-like states EGD (eV) 0.20 2.2. Optimization Method In the context of nonlinear least squares data fit­ting, the objective is to estimate a set of parameters which minimizes the residual between the measured or experimental data y(x) and the pre­dicted data In particular the eval function correspond to the numerical solution of the partial differential equation (PDE) of the simulator Atlas/Silvaco. The above equa­tion can be generalized for multiple curve responses case; however, a simple notation was kept for simplic­ity. T he numerical determination of the set of parame­ters q which minimizes F(q) corresponds to the iterative Levenberg-Marquardt (LM) algorithm (1) where J is the Jacobian matrix of derivatives of the residuals with respect to the parameters q, the resid­ual vector is r, the matrix identity is I, and the adap­tive damping parameter is l. The above procedure is a standard numerical scheme used to perform nonlinear data fitting, where the convergence properties rela­tionship with the steepest descent and Gauss-Newton method are understood [12]. The Silvacos manuals do not explain how they code the LM algorithm; however, it is understandable that they employ finite dfferences schemes to approximate the partial derivatives on the Jacobian matrix. Besides, in modern computer simulators, each numerical solver are coded independently, this is the case on the Atlas/Silvaco tool, where the communication between the LM algorithm and the PDEs solver is achieved through files. Furthermore, at each time that the calculation of Jacobian or the residual evaluation is needed, it is re­quired to solve numerically the PDEs, where the param­eters are taken from a given data file. So, this procedure is general, and allows the interchange of numerical solvers without modify the rest of the programs. 3 Trap Density in poly-PbS Thin Film A poly-PbS film consists of a number of small crys-talline grains with boundaries. As mentioned before, this kind of materials contains a large number of de­fect states within the band gap of the material. Com­pared with the crystalline TFT, a much higher density of trap charge in poly-PbS dominates the Poisson’s equa­tion even when these devices work under the above threshold region [13]. In narrow gap materials, as PbS, the defects arise from variation in bond lengths, grain boundaries, dangling bonds (vacancies) and other microscopic point defects. The trap states exist within the crystal grains, but many are located at the front and back oxide interfaces and the grain boundaries [14]. Moreover, experimental methods reveal that the Gaussian (deep level) gap state exhibits distinctly a peak structure in some amorphous and polycrystalline oxide semiconductor [15]. Each kind of defect plays an important role in many electrical properties in semiconductors, serving as a scattering and/or a recombination center during transport. But also the vacancies, for example, acting as largely uncontrolled dopants and having the effect on electron and hole mobilities [16]. Therefore, in order that the performance of TFTs based on chalcogenides thin films by CBD technique could be improved, the study of the native defects in the deposited thin films is undisputed. 3.1. Density of States Model The total DDS distribution of trapping states g(Et) in the polycrystalline PbS films is taken to be composed of four bands: two tail bands (a donor-like valence band, gTD (Et ) and an acceptor-like conduction band, gTA (Et)), and two deep Gaussian level bands (one acceptor-like, gGA (Et) and the other donor-like, gGD (Et)) by (2) (3) (4) (5) (6) where Et is the energy of trap, Ec is the conduction band energy, Ev the valence band energy and, the subscripts (T, G, A, D) stand for tail, Gaussian (deep level), accep­tor- and donor-like trap states, respectively. The donor-like traps are positively charged (cation vacancy); therefore, they can only capture electrons. They are positive when unoccupied by an electron, but they are neutral when occupied. On the other hand, acceptor-like traps are negatively charged (anion va­cancy); therefore, they can only emit an electron. They are negative when occupied, but they are neutral when unoccupied. The capture and emission processes are predicted by Atlas simulator using the Shockley-Read-Hall (SRH) recombination model. In the steady-state, the probability of occupation of a trap level at energy Et for the tail and deep states is given by Fermi-Dirac (FD) occupation function [17]. The total trap charge QT = q(nT - pT) is evaluated in Atlas by following these steps. First, the density of ionized ac­ceptor- and donor-like states is simply the product of g(Et) and the FD occupation function. Then this product is integrated to obtain the density of carriers (nT and pT) over all possible energies within a band gap. Finally, the total trap charge QT obtained is subtracted from the right hand side of Poisson’s equation. QT is also used to modify the standard SHR model in order to account for electrons and holes being emitted and captured by the acceptor and donor-like traps. 4 Simulation Results The 2D numerical simulations of p-type PbS poly-TFT device were performed with Atlas/Silvaco simulator. The iterative Marquart algorithm (1) was used to deter­mine the parameters NTA , NTD , NGA , NGD , WTA , WTD, WGA and WGD of the DDS model (2)-(6) numerically. So, it was necessary to propose the initial, maximum and mini­mum values of each parameter. These values were pro­posed according to the data reported by some authors that analyze the electronic properties of nanocrystal­line PbS films where the DDS is extracted from experi­mental data [18, 19, 20]. As a result, the set of param­eters, which best fit the experimental drain current (IDS ) of p-type TFT as function of both drain-source voltage VDS and gate-source voltage VGS were obtained and are listed in Table 1. The example of simulated and measured IDS - VDS output characteristics after the optimization of DDS model are displayed on Fig. 2. Having in mind the large tolerances in physical and geometrical parameters of experimen­tal devices obtained from fabrication process, a good agreement between simulated and measured results is achieved in Fig. 2. The optimized simulation results indicate that the spatially uniform DDS method with simplified mesh generation is suitable choice for nu­merical simulations of long channel and thin film poly-PbS TFTs. The optimized tail and deep density distributions of acceptor- and donor- like trap states for the simulated poly-PbS TFT are depicted in Fig. 3. As can be seen the density profile of defects across the forbidden gap of poly-PbS has a shape of two tail band edges and two deep levels near the midgap. The exponential band tails stem from the structural disorder in the lattice while the deep defect bands arise from impurities. Deep defects are very important for narrow band gap semiconductors [21]. The impurities and native point defects (vacancies and interstitials) are largely associ­ated to deep traps. The deep levels can capture holes or electrons and hence acts as an electron/hole trap, which clearly affects the device performance. Fig. 3 shows that Gaussian (deep) defect bands of poly-PbS film have a peak structure, which agree with the study presented in [15]. Figure 3: Optimized tail and Gaussian density distribu­tions of acceptor- and donor-like trap states in poly-PbS TFT. The energy-band diagram for p-type PbS MOS struc­ture under thermal equilibrium VGS = 0 (a) and accu­mulation regime VGS < 0 (b) is shown in Fig. 4. If VGS = 0 the semiconductor Fermi level EF is near valence band and from Fig. 3 can be seen that the charge neutrality level (CNL) (the crossing point at which acceptor- and donor-like densities of states are equal) is located near midgap. For VGS < 0, the bands bend upwards, drawing CNL away from EF as shown in Fig. 4(b). As can be seen EF lies below CNL, and ionized empty deep donor-like states build up a large positive interface charge. That is, the FD function of deep donor-like trap, which means the probability that the trap is not occupied by an elec­tron, is increased as negative VGS increases. Moreover, theorical results of [22] predict that S vacancies (accep­tor-like traps) act as n-type PbS, whereas Pb vacancies (donor-like traps) act as p-type PbS. Figure 4: Energy band diagram drawn in scale for p-type PbS MOS structure (a) for VG = 0V and (b) for VG < 0 (accumulation regime). Here, only the semiconductor and the interface with the oxide insulator are shown. In Fig. 5 we display the simulated hole mobility (µp) as a function of transverse electric field (E^) and VDS (inset). We can notice that µp shows a strong dependence on E^ and it is considerably lower than the mobility of crys­talline TFTs. This behavior can be explained by consid­ering that for a small negative VGS most of the charges are trapped. When VGS becomes more negative, eventu­ally more trap states become ionized (see Fig. 4). In this situation the effect of traps vanishes and the mobility remains almost constant with negative VGS. The inset of Fig. 5 shows µp as a function of VDS at different VGS (-5V, -10V, -15V and -20V). It can be seen that µp has the cor­rect behavior and it is well predicted by Atlas simulator. Both experimental and optimized (simulation) low field hole mobilities (µp0 ) are shown in Table 1. In Fig. 4 is shown that tail donor-like states are located under EF. So, they are occupied by an electron, and they are neutral; similarly, tail acceptor-like states are locat­ed above the EF. So, they are unoccupied, and they are also neutral. So, in p-type PbS TFTs deep density states play an important role in charge transport [23]. For this reason, only the effect of different values of Gauss­ian density states on the transfer characteristics of the poly-PbS TFT simulated are shown in Figs. 6 and 7. As mentioned before, under low negative VGS , most of the induced charge is trapped in deep states, the dominant term in Poisson equation is the density of traps ndeep and pdeep. Therefore, the sub-threshold characteristic of poly-PbS TFT can be improved by reducing both den­sity of deep states and film thickness. As the deep acceptor-like traps were increased, the states of electron capture (minority carriers) are in­creased and they cause less leakage current (see Fig. 6). Nevertheless, no significant change was observed in transfer characteristics of TFT when the deep acceptor-like traps were reduced. Accordingly, the effect of ac­ceptor-like traps is less important in a p-type poly-PbS TFT in the accumulation regime. On the other hand, larger deep donor-like traps means larger positive ion­ized states. Notice that this situation states both less holes and less mobility in the channel (see Fig. 7). Fur­thermore, the total current of poly-PbS TFT is reduced. Whether the deep donor-like traps are reduced, the total current is increased, yet the VTH shifts to posi­tive values. Moreover, although the experimental and simulated value of VTH is positive, it should be nega­tive (accumulation regime). A similar conclusion about the effect of deep traps on VTH behavior is presented in [24] for TFTs with cadmium sulfide (CdS) films, as active channel, deposited by CBD technique. Because the deep traps affect the device performance by either doping the PbS film or acting as trap sites, both accep­tor- and donor-like traps should be controlled in order to improve the p-type poly-PbS TFT electrical charac­teristics. Figure 7: Transfer characteristics of the poly PbS TFT simulated as a function of VGS for different values of deep donor-like traps (increased and reduced). Fig. 3 shown that the point defects act as deep traps states situated at different energy depths within the forbidden gap, thereby influencing the principal pa­rameters of poly-PbS TFTs (VTH , mobility, Ion /Iof f ratio and mobile charge density). It is demonstrated that after thermal annealing the electrical properties of thin films deposited by CBD are improved [8, 24]. This is attributed to the change in larger grain size, lattice parameter and crystalline structure along with a reduc­tion of defects. Nevertheless, some defects are still pre­sent in the thin film and longer annealing times might be necessary to eliminate the vacancies or interstitials. In addition, a significant amount of S or Pb (anion or cation) vacancies could be created in the PbS films as function of the environment used during the synthesis, sulfur-poor or lead-poor. Also, the velocity of ions in a solution should be considered in order to control the S and Pb vacancies in the thin films deposited by CBD technique. 5 Conclusions To sum up, the p-type PbS poly-TFT’s electrical charac­teristics can be predicted with physically based two-di­mensional device simulator Atlas using the embedded density of defect models. The spatially uniform den­sity of defect states method used for trapped charge evaluation and the parameter optimization of density defect model give a good agreement between simu­lated and experimental characteristics. Also, it is clear that the deep density of states in poly-PbS band gap affects the electrical characteristics of p-type TFTs. The high density of deep donor-like states (cation vacan­cies) found to be degrading device performance while it is not a concern for deep acceptor-like states (anion vacancies). The cation vacancies act as a deep electron donor, which affect the p-type device performance. To optimize the design of p-type PbS poly-TFTs both an­ion and cation vacancies should be controlled. These findings are important for the better understanding of TFTs based on calchogenides materials deposited by chemical bath deposition technique. 6 References 1. Z. Meng, M. Wang, M. Wong, High performance low temperature metal-induced unilaterally crys­tallized polycrystalline silicon thin film transistors for system-on-panel applications, IEEE Transac­tions on Electron Devices 47 (2) (2000) 404–409. doi:10.1109/16.822287. 2. S. Zhang, C. Zhu, J. K. O. Sin, J. N. Li, P. K. T. Mok, Ultra-thin elevated channel poly-si tft technology for fully-integrated amlcd system on glass, IEEE Transactions on Electron Devices 47 (3) (2000) 569–575. doi:10. 1109/16.824731. 3. H. W. Zan, S. C. Kao, The effects of drain-bias on the threshold voltage instability in organic tfts, IEEE Electron Device Letters 29 (2) (2008) 155–157. doi:10.1109/LED.2007.914081. 4. A. Obaid, M. Mahdi, Y. Yusof, M. Bououdina, Z. Hassan, Structural and optical properties of na­nocrystalline lead sulfide thin films prepared by microwave-assisted chemical bath deposition, Materials Science in Semiconductor Process­ing 16 (3) (2013) 971 – 979. doi:http://dx.doi.org/10.1016/j.mssp.2013.02.005. URL http://www.sciencedirect.com/science/article/pii/S1369800113000413 5. V. Stancu, M. Buda, L. Pintilie, I. Pintilie, T. Botila, G. Iordache, Investigation of metal-oxide semi­conductor field-effect transistor-like si/sio2/(nano)crystalline pbs heterostructures, Thin Sol­id Films 516 (12) (2008) 4301 – 4306. doi:http://dx.doi.org/10.1016/j.tsf.2007.11.116. URL http://www.sciencedirect.com/science/article/pii/ S0040609007019682 6. G. P. Agrawal, N. K. Dutta, Semiconductor Lasers, 2nd Edition, Kluwer Academic, 1995. 7. T. K. Chaudhuri, A solar thermophotovoltaic con­verter using pbs photovoltaic cells, International Journal of Energy Research 16 (6) (1992) 481–487. doi:10.1002/er.4440160605. URL http://dx.doi.org/10.1002/er.4440160605 8. A. Carrillo-Castillo, A. Salas-Villasenor, I. Mejia, S. Aguirre-Tostado, B. Gnade, M. Quevedo-Lpez, P-type thin films transistors with solution-depos­ited lead sulfide films as semiconductor, Thin Solid Films 520 (7) (2012) 3107 – 3110. doi:http: //dx.doi.org/10.1016/j.tsf.2011.12.016. URL http://www.sciencedirect.com/science/article/pii/ S0040609011021183 9. G. Fortunato, P. Migliorato, Determination of gap state density in polycrystalline silicon by fieldeffect conductance, Applied Physics Let­ters 49 (16) (1986) 1025–1027. doi:http://dx.doi.org/10.1063/1.97460. URL http://scitation.aip.org/content/aip/journal/apl/49/16/10.1063/1.97460 10. M. D. Jacunski, M. S. Shur, M. Hack, Threshold volt­age, field effect mobility, and gate-to-channel capacitance in polysilicon tfts, IEEE Transactions on Electron Devices 43 (9) (1996) 1433–1440. doi:10.1109/16.535329. 11. Y. Z. Xu, F. J. Clough, E. M. S. Narayanan, Y. Chen, W. I. Milne, Turn-on characteristics of polycrystalline silicon tft’s-impact of hydrogenation and channel length, IEEE Electron Device Letters 20 (2) (1999) 80–82. doi:10.1109/55.740658. 12. J. Nocedal, S. Wright, Numerical Optimiza­tion, Springer Series in Opera- tions Research and Financial Engineering, Springer New York, 2006. URL https://books.google.com.mx/books?id=eNlPAAAAMAAJ 13. Y. Liu, R. h. Yao, B. Li, W. L. Deng, An analytical model based on surface potential for a-si:h thin-film transistors, Journal of Display Technology 4 (2) (2008) 180–187. doi:10.1109/JDT.2007.907122. 14. M. Kimura, Evaluation of trap states at front and back oxide interfaces and grain bounda­ries using electrical characteristic analysis and device simulation of polycrystalline silicon thin-film transistors, Electronics and Communica­tions in Japan (Part II: Electronics) 88 (2) (2005) 1–10. doi:10.1002/ecjb.20124. URL http://dx.doi.org/10.1002/ecjb.20124 15. H.-H. Hsieh, T. Kamiya, K. Nomura, H. Hosono, C.-C. Wu, Modeling of amorphous ingazno4 thin film transistors and their subgap den­sity of states, Applied Physics Letters 92 (13). doi:http://dx.doi.org/10.1063/1.2857463. URL http://scitation.aip.org/content/aip/journal/apl/92/13/10.1063/1.2857463 16. S. Ahmad, S. D. Mahanti, K. Hoang, M. G. Kanatz­idis, Ab initio studies of the electronic structure of defects in pbte, Phys. Rev. B 74 (2006) 5205. doi:10.1103/PhysRevB.74.155205. 17. S. Sze, K. Ng, Physics of Semiconductor Devic­es, Wiley, 2006. URL https://books.google.es/books?id=o4unkmHBHb8C 18. Z. Jin, A. Wang, Q. Zhou, Y. Wang, J. Wang, Detect­ing trap states in planar pbs colloidal quantum dot solar cells, Scientific Reports 6 (3) (2016)569–575. doi:http://dx.doi.org/10.1038/srep37106. 19. N. MI, H. R, W. S, M. H, S. M, H. W, T. J, L. MA, Broaden­ing of distribution of trap states in pbs quantum dot field-effect transistors with high-k dielectrics, ACS Appl Mater Interfaces 9 (5) (2017) 4719–4724. doi:http://dx.doi.org/10.1021/acsami.6b14934. 20. N. MI, H. R, W. S, M. H, S. M, H. W, T. J, L. MA, High mobility and low density of trap states in dual-sol­id-gated pbs nanocrystal field-effect transistors, Advanced Materials 27 (12) (2015) 2107–2112. doi:http:// dx.doi.org/10.1002/adma.201404495. 21. S. Mahanti, K. Hoang, S. Ahmad, Deep defect states in narrow band-gap semiconductors, Phys­ica B: Condensed Matter 401402 (2007) 291 – 295, proceedings of the 24th International Conference on Defects in Semiconductors. doi:http://dx.doi.org/10.1016/j.physb.2007.08.169. URL http://www.sciencedirect.com/science/article/pii/S0921452607007168 22. D. Zong-Ling, X. Huai-Zhong, X. Sheng-Lan, H. Yan, C. Xiao-Shuang, First-principles study of electron­ic properties in pbs(—100) with vacancy defect, Chinese Physics Letters 24 (11) (2007) 3218. URL http://stacks.iop.org/0256-307X/24/i=11/a=054 23. P. Nagpal, V. I. Klimov, Role of mid-gap states in charge transport and photoconductivity in semi­conductor nanocrystal films, Nature Communi­cations 2 (486). doi:http://dx.doi.org/10.1038/ncomms1492. 24. A. L. Salas-Villasenor, I. Mejia, M. Sotelo-Lerma, Z. B. Guo, H. N. Alshareef, M. A. Quevedo-Lopez, Improved electrical stability of cds thin film tran­sistors through hydrogen-based thermal treat­ments, Semiconduc- tor Science and Technol­ogy 29 (8) (2014) 085001. URL http://stacks.iop.org/0268-1242/29/i=8/a=085001 Arrived: 22. 12. 2016 Accepted: 03. 05. 2017 Abimael Jiménez P. et al; Informacije Midem, Vol. 47, No. 1(2017), 32 – 39 Abimael Jiménez P. et al; Informacije Midem, Vol. 47, No. 1(2017), 32 – 39 Abimael Jiménez P. et al; Informacije Midem, Vol. 47, No. 1(2017), 32 – 39 Figure 2: Simulated and experimental IDS -VDS charac­teristics of poly-PbS TFT device. Abimael Jiménez P. et al; Informacije Midem, Vol. 47, No. 1(2017), 32 – 39 Abimael Jiménez P. et al; Informacije Midem, Vol. 47, No. 1(2017), 32 – 39 Figure 5: Hole mobility as a function of transverse elec­tric field obtained from Atlas simulator. The inset com­pares the dependence of VDS on hole mobility at differ­ent values of VGS. Figure 6: Transfer characteristics of the poly PbS TFT simulated as a function of VGS for different values of deep acceptor-like traps (increased). Abimael Jiménez P. et al; Informacije Midem, Vol. 47, No. 1(2017), 32 – 39 Abimael Jiménez P. et al; Informacije Midem, Vol. 47, No. 1(2017), 32 – 39 Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 1(2017), 40 – 48 Testing and Characterization of Multilayer Force Sensing Resistors Fabricated on Flexible Substrate Dragana Vasiljević, Danka Brajković, Damir Krklješ, Boris Obrenović, Goran M. Stojanović University of Novi Sad, Faculty of Technical Sciences, Novi Sad, Serbia Abstract: This paper presents design, fabrication and characterization of force sensing resistors (FSRs) which can be used in many applicable devices in medicine, rehabilitation, robotics, dentistry, etc. They consist of printed interdigitated electrodes on flexible substrate, an adhesive spacer and a carbon based sensing layer. Four types of FSRs were fabricated with different designs of active area. Measurement setup for testing and characterization has been developed in laboratory conditions and represents a device for precise implementation of a controlled force on FSRs. The characteristics of FSRs - the resistance as a function of applied force and temperature as well as the voltage as a function of applied force are presented. The obtained resistances were in the range of tens of Ohms for a wide range of applied force (1 N – 65 N). Keywords: Electronic component; Materials; Force Sensing Resistor (FSR); Flexible substrate; Characterization Preizkušanje in karakterizacija večslojnih uporovnih senzorjev sile izdelanih na fleksibilnih substratih Izvleček: Članek predstavlja dizajn, izdelavo in karakterizacijo uporovnih senzorjev sile (FSR), ki se jih lahko uporabi v številnih aplikacijah v medicini, robotiki, zobozdravstvu… Sestaljeni so iz tiskanih prepletenih elektrod na fleksibilnem substratu, lepljivim distančnikom in senzorsko plastjo na osnovi ogljika. Izdelani so bili štirje tipi senzorjev glede na obliko aktivne plasti. Vzpostavljeno je bilo merilno in karakterizacijsko orodje v laboratorijskem okolju, ki omogoča natančno implementacijo kontrolirane sile na FSR. Prikazane so karakteristike FSR – upornost kot funkcija sile in temperature ter napetost kot funkcija sile. Upornosti so v razredu ohmov za široki razpon uporabljenih sil (1 N – 65 N). Ključne besede: elektronske komponente; materiali; uporovni senzor sile; fleksibilen substrat; karakterizacija * Corresponding Author’s e-mail: sgoran@uns.ac.rs 1 Introduction Force and position sensing are an integral part to a wide range of measurements. Force sensing resistors (FSRs) have been used in a number of force sensing applica­tions in many fields, such as medicine, rehabilitation, robotics, etc. [1-3]. FSRs are devices that allow measur­ing static and dynamic forces applied to a contact sur­face. Their range of responses is basically depending on the variation of its electric resistance. The FSR is usually a flat, flexible device that exhibits decreasing electrical resistance with increasing force applied normal to its surface. Some of the most popular commercial types of FSRs are: FSR Interlink Electronics [4], FlexiForce-Teks­can [5] and PS3-LuSense [6] sensors. A commercial FSR encompasses of two layers, namely a conductive sur­face and the printed electrodes. Both are facing each other which allow a contact between two surfaces. This results in the conductive layer of the printed electrodes short circuit to reduce the electric resistance upon force pressure. Usually, the resistance dropped from 1 M. to 10 K. for the applied force is in the range from 1 N to 10 N. FSRs are available in a few different shapes such as round, square and strip and their small thickness and mechanical flexibility allow them extensive applicabil­ity. Force sensors are widely used in the robotic field, particularly for robot interaction control application. A study has been conducted in [7] to utilize the Tekscan Flexiforce and the Interlink FSR sensors in robotic and biomechanical applications. Two different set of experi­ments (the hardness detector system and the force-position control system) were carried out in [8] to test the effectiveness of the Flexiforce and Interlink sensors. Characteristics of three types of force-sensing resistors (Interlink FSR - Standard 402, FlexiForce - A201, LuSe­nse PS3 - Standard 151) were identified in [9] for usage in a refreshable and portable E-Braille device that can assist the blind and visually impaired persons. An effec­tive technique that improves reliability and accuracy of measuring compression force using FSRs (Interlink Electronics) was presented in [10], for biomedical and industrial design applications where measurement of finger and hand force are needed. In the paper [11], authors reported FSRs that are adequate to be part of wearable components. Authors focused on the sensing technologies that are compliant with the integration inside garments or other kinds of clothing (i.e., shoes, backpacks). Two different force sensitive resistors: FSR 406 (produced by Interlink Electronics) and A401 (from Tekscan) were evaluated in [12], while demonstrat­ing gaits of healthy individuals through their loading behaviour. The flexible tactile force sensors presented in [13], were fabricated using a moulding process of a composite material, which is a mixture of two compo­nents: conductive ink and silicon elastomer, expressing good linearity and repeatability. A system with force sensors (Tekscan FlexiForce), which are placed on the hands rather than on objects, allowed improvements in versatility and spatial resolution to be made in meas­uring forces developed by human hand, was present­ed in [14]. The system has been successfully used to measure forces involved in a range of everyday tasks such as driving a vehicle, lifting a sauce pan, or hit­ting a golf ball. A wearable arm device that equipped with a monitoring system for post-stroke rehabilitation was designed and proposed in [15]. The device was equipped with an Interlink FSR sensor along with other sensors such as flex sensor and accelerometer. In the paper [16], FSRs were used to detect the transitions be­tween five main phases of gait for the control of electri­cal stimulation while walking with several children with cerebral palsy. The paper [17] described testing of a bite force sensor based on force sensing resistor. The sensor surfaces were manufactured in silicone material that had mechanical properties similar to those of tough foodstuffs. The instrument has such clinical merits, as to favor its use in experimental clinical studies on the biomechanics of prosthetic applications. An electrolar­ynx which can change intensity as well as frequency simultaneously during conversation was described in [18]. A specialized FSR sensor was used to make possi­ble controlling frequency and intensity simultaneously by applying pressure to the button. This system can be used as one of the rehabilitation methods for laryngec­tomees. From above-mentioned review of open litera­ture it can be concluded that there are a huge interest for application of FSRs and consequently their custom-made innovative design. This paper proposes various designs of FSRs on me­chanically flexible substrate which can be exposed to a wide range of applied force (up to 65 N). The four types of FSRs were fabricated on the foil (Kapton film), with very low value of resistance in a wide range of applied forces. In-house measurement setup tool has been de­veloped for determining characteristics of these FSRs. Comparison of their performances was performed with reference to resistance vs. applied force curve as well as changing these graphs with increasing the operating temperature which is very important from application point of view. The article is organized as follows. Section 2 describes design and fabrication procedure of the proposed FSRs as well as measurement setup tool used for characteri­zation of the manufactured force sensing resistors. Dis­cussion of obtained results is presented in Section 3. The concluding remarks are given in Section 4. 2 Experimental 2.1 FSRs design and fabrication In this paper, four different designs of force sensing re­sistor were proposed, as can be seen in Fig. 1. First two structures are round and they have different shapes of interdigitated electrodes, while the third structure has square shape active area (Fig. 1c). The fourth structure has 4-zones active area, and just first zone has been used for testing, shown in Fig. 1d. Dimensions of four types of fabricated sensors are shown in Table 1. All FSRs were manufactured by ink-jet printing using Dimatix deposition material printer - DMP3000 [19] and RK Control printing proofer - RK K [20]. The first layer of the sensor was fabricated by printing of commercially available SunChemical silver nanopar­ticle ink with 20 wt% - Jet Silver U5714 [21]. Thickness of polymide film for active area was 75 µm. The resolution of the inkjet process using DMP-3000 printer is mainly governed by the nozzle diameter (approximately the droplet diameter) and the statistical variation of the droplet flight and spreading on the substrate. In case of printing with silver nanoparticle ink the minimum drop­let diameter was around 36 µm, and drop spacing was 18 µm (from center to center) obtained by changing the printhead angle. Silver interdigitated electrodes for the first FSR’s layer were printed and sintered at 240 °C for 30 min. The second sensor’s layer was fabricated by printing of carbon ink using RK K printing proofer on 50 µm GTS polyimide film [22]. Carbon ink has been print­ed in several layers (three) on GTS film, shown in Fig. 2a. After fabrication both layers have been attached using two component epoxy glue, which has been mounted around the edges of the active area, shown in Fig. 2b. When the two substrates are pressed together, the mi­croscopic protrusions on the FSR ink surface shorten across the interdigitated fingers of the facing surface. At low forces, only the highest protrusions make con­tact, while at higher forces, there are more and more contact points between the two substrates. The result is that the resistance between the electro conductive segments is inversely proportional to the applied force. The contact wires were mounted using silver paste, for testing purpose, at the ends of silver conductive lines and after finishing these steps, the four types of fabri­cated FSRs can be seen in Fig. 2c. Figure 2: a) Printed carbon ink, b) mounted two com­ponent epoxy glue and c) four types of FSR sensors af­ter manufacturing, respectively 2.2 Characterization techniques The following instruments have been used for materi­als characterization: (1) for structural characterization - scanning electron microscope (SEM), JOEL JSM 6460 LV scanning microscope with EDS; (2) for mechani­cal characterization - nanoindentation, Nanoindenter G200, which uses the Berkovich diamond indenter with a face angle of 65.27°. 2.3 Measurement setup The force sensing resistors testing were performed us­ing an innovative in-house developed measurement setup shown in Fig. 3. It consists of a rigid frame, linear electric actuator with position feedback, spring, actua­tor sensor holder and reference force sensor. The com­plete system also includes digital electronic system control and operator control software (user friendly in-house developed software tool, entitled Forcer) shown in Fig. 4, which allows position change and changing of applied force [23]. Resistance and voltage of fabricated sensors were measured using multimeter (shown in Fig. 3b). For the purpose of measurements a voltage source was used (Fig. 3b). Force used for measurements was applied to the fixed part or all over the active part of the sensor. Figure 3: a) Positioning FSR and b) complete measure­ment setup Figure 4: In-house developed software tool for control­ling the measurement process. For resistance as a function of force, measurement set­up described at the beginning of this section was used, and for voltage as a function of force, as addition to the setup, a voltage divider circuit which was connected to fabricated FSR, shown in Fig. 5, was used. The measur­ing resistor, RM, is chosen to maximize the desired force sensitivity range and to limit current. For resistance as a function of temperature heat source was used to reach the desired temperature and an IR camera was used to monitor temperature variations. Figure 5: FSR voltage divider circuit 3 Results and discussion 3.1 SEM results With the aim to determine the exact thickness of sil­ver conductive layer as well as carbon layer, scanning electron microscopy (SEM) was conducted. SEM mi­crographs are presented in Fig. 6. It can be seen from this figure that thickness of silver layer was around 260 nm, whereas the thickness of carbon layer was around 6 µm. 3.2 Mechanical characterization results Bearing in mind that FSRs will be exposed to different mechanical stress during the practical application, their mechanical characterization was performed by means of nanoindentation. We used an Agilent Nano indenter G200 to investigate mechanical properties of sintered silver layers as well as carbon layers. Multiple indenta­tion (at least 10 indentations were made) tests provide measurement repeatability for the mechanical proper­ties of analyzed samples/layers. Nanoindentation tests were conducted with a Berkovich diamond indenter, which ensures a precise control over the indentation process. Fig. 7a shows load-displacement curves meas­ured on the silver layer, whereas Fig. 7b presents load-displacement curves measured on the carbon layer. It can be seen from Fig. 7a that maximum load on sil­ver layer was at 0.35 mN and corresponding maximum depth of penetration was around 240 nm, which con­firm that we did not reach the substrate (the thickness of this layer is around 250 nm). Fig. 7b presents load-displacement response for carbon layer for a maximum load of about 1.8 mN and the penetration depth was about 2.25 µm (which is around one third of the thick­ness of this layer). These force-displacement curves confirm repeatability of obtained results. 3.3 Resistance/Voltage vs. force results A typical FSR’s characteristic represents dependence of resistance vs. force, thus we analyzed firstly this be­haviour of the proposed sensors. The resistance as a function of force characteristic for four types of FSRs, at room temperature, is depicted in Fig. 8. Three areas of different sensor behaviour can be distinguished. The first area is leftmost area in which the resistance is high and the sensitivity is also very high. This area has non­linear properties of a dead lash at the beginning of the area characterized by a breaking force that introduces the sensor in the high sensitivity area. The component abruptly switches into the second – the regular area, which is commonly used for sensing. In this area the conductance fairly linearly depends on the applied force (force difference). Finally, when excessive force is applied, the component starts to saturate. The transi­tion to the saturation is not abrupt, but rather gradual [24]. Fig. 8 shows that resistance of sensor decreases with an increase in force, and it can be observed for all types of analyzed FSRs. The force range was from 1.19 N to 65.7 N and the same range was used for all four types of FSRs. This force was implemented on FSRs by means of in-house developed system, presented in Fig. 3. In Fig. 8 is visible that the third type of FSR, which has the largest active area, has lowest resistance, 8.81 . when applying maximal force, while the fourth type of FSR, with smallest ana­lyzed active area, has resistance of 24.81 . when ap­plying the same force. For practical application point of view and connecting with electronic circuits, it is im­portant to have voltage-force characteristics. FSRs are usually configured in voltage divider circuits for simple resistance-to-voltage conversion, as already shown in Fig. 5. Voltage change due to change in force for sev­eral values of RM resistor (depicted in Fig. 5), which al­lows voltage change in the whole range, is presented in Fig. 9 and 10. Moreover, Fig. 11 depicts voltage as a function of applied force for proposed types of FSRs, for constant values of RM equal to 18 .. The voltage increases with the increase of applied force, which can be seen using voltage divider equation: (1) where Vout is output voltage, V+ bias voltage, RFSR resist­ance of FSR, and RM measuring resistor. The resistance of FSR decreases with increasing force. Applying that in (1), Vout increases with RFSR decrease, which can be seen in Figs 9 - 11. This is valid for all four types of the proposed sensors. From Fig. 11, it can be seen that volt­age range is from 3 V to 3.5 V, which is very appropriate range for further connection to read-out electronics or displays. Using (1) it can be also calculated which value of RFSR will be obtained for already measured voltage shown in Figs 9 and 10. This will confirm validity of re­sistance values shown in Fig. 8. RFSR can be calculated from the following equation: (2) where V+ = 5 V. In Fig. 11 can be seen that applied force was from 5 N to 15 N, since at larger forces changes in voltage are neg­ligible due to small change of RFSR. Fig. 11 shows that the output of the sensor varies linearly with the force applied. The 2nd type of FSR demonstrated the best lin­earity, in a wide range of applied forces. This FSR has our novel design and can not be found commercially. FSRs may also find their application in systems with higher temperature than room temperature. Because of that, we analyzed the behaviour of the proposed FSRs at elevated temperature. Fig. 12 shows that resist­ance of FSRs increases with an increase in temperature. Temperature was changed in the range from 30 °C to 90 °C, while applied force was constant with value of around 12 N (which belongs to a linear range). This in­crease of resistance can be explained using following equation for R(T) at room temperature: (3) where .0 is temperature coefficient, R(T0) is resistance at room temperature, and .T=T-T0 is difference between actual and room temperature. As .0 for silver is 0.0061 oC-1 and for carbon -0.0005 oC-1, using (3) it can be seen that with an increase in temperature, value of R(T) also increases. This increase in resistance can be observed for all four types of FSRs (Fig. 12). It can be seen that the smallest variation of resistance with changing temper­ature demonstrated the first and second types of FSRs which have the lower total active area, comparing with the third and the fourth design of proposed FSRs. In addition to this, .0 for all four fabricated FSRs has been calculated and results are presented in Table 2. Table 2: Temperature coefficient .0 for characterized FSRs .0 (oC-1) 1st type of FSR 0.0019 2nd type of FRS 0.0032 3rd type of FSR 0.0035 4th type of FSR 0.0037 The obtained results are directly connected with sen­sors structure. When pressed or touched, the FSR ink carbon based structures act as a short between the conductive traces from the contact area, resulting in a resistance that depends on the applied force. When the two substrates are pressed together, the microscopic protrusions on the FSR ink surface shorten across the interdigital fingers of the facing surface. At low forces, only the tallest protrusions make contact, while at higher forces, here are more and more contact points between the two substrates. As a consequence, the resistance between the electro conductive lines is in­versely proportional to the applied force, as presented in Fig. 8. The voltage is directly proportional with ap­plied force, in accordance with equation (1), and as it is demonstrated in Figs 9-11. Our results revealed that presented cost-effective FSRs are reliable and have a good sensing property for measuring force. The proper design of FSRs, which this paper has proposed (even unconventionally), is very important when dealing with different shape of objects, in order to be able to detect adequately applied force. 4 Conclusion In this paper four types of flexible FSRs, fabricated in low-cost and easily accessible ink-jet and screen print­ing technologies, with different design of active area were tested. Each of four FSRs shows that measured resistance of FSR decreases with an increase in ap­plied force, that voltage increases with an increase in force and that resistance increases with an increase in temperature. Measured values of resistance were in the range of 8.81 - 24.81 . and voltage was in range from 0.79 V to 3.73 V, while applied force from around 1 N up to maximum of 65 N. Obtained results showed that sensor with largest active area has lowest resist­ance when applying maximal force, while sensor with smallest active area has largest value of resistance at the same applied force. The novelty of this paper can be summarized as follows: (1) innovative design of sec­ond type of FSRs which showed the best linearity and the smallest resistance variation at elevated tempera­ture comparing to other designs which can be usually found off-the-shelf; (2) together with flexibility and thin structure of the sensor this brings a very wide pos­sibilities of sensors applications in many delicate and important fields such as prosthetic medicine, dentistry, rehabilitation, robotics, etc.; (3) comparison of the com­plete set of performances of four different types of FSRs performed for the first time; (4) presented FSRs can be exposed to a wide range of applied forces up to 65 N; and (5) completely novel in-house developed system for experimental testing of FSRs has been presented. 5 Acknowledgement This paper is partly supported by the Ministry of Edu­cation, Science and Technological Development within the project no. TR32016, project no. 114-451-2723/2016 funded by the Provincial Secretariat for Science and Technological Development as well as EU funded pro­ject MEDLEM no. 690876. 6 References 1. T. D’ Alessio, ”Improving the use of force sensing resistors arrays for the measure of hand grasp”, Proceedings of the electrotechnical conference, MELECON ‘96, vol. 3, pp. 1383-1386, 1996. DOI: 10.1109/MELCON.1996.551205 2. A. A. Gopalai, ”Force sensing resistors for moni­toring proprioception response in rehabilitation routines”, Proceedings of the 12th international conference on intelligent systems design and ap­plications (ISDA), 27-29 November 2012, pp. 941-946. DOI: 10.1109/ISDA.2012.6416665 3. N. K. Rana, ”Application of Force Sensing Resistor (FSR) in design of pressure scanning system for plantar pressure measurement”, Proceedings of the second international conference on comput­er and electrical engineering, ICCEE ‘09, 28-30 De­cember, 2009, vol. 2, pp. 678-685. DOI: 10.1109/ICCEE.2009.234 4. Interlink Electronics, “FSR® Integration Guide”, FSR® Force Sensing Resistors®, pp. 11-12. 5. Tekscan, Inc., 307 West First Street, South Boston, “Comparison of interface pressure measurement options”, pp. 2. – See more at: http://www.tek­scan.com/pdf/Comparison-Pressure-Measure­ment-Options.pdf 6. IEE International Electronics & Engineering. Spec­ification Sheet for Standard LuSense Sensors of the PS3 Family. Revision 0, March 29, 2001. 7. C. Lebosse, B. Bayle, M. De Mathelin, and P. Re­naud, “Nonlinear modeling of low cost force sen­sors,” 2008 IEEE Int. Conf. Robot. Autom., pp. 3437–3442, 2008. DOI: 10.1109/ROBOT.2008.4543736 8. A. S. Sadun, J. Jalani, J.A. Sukor, “Force Sensing Resistor (FSR): A Brief Overview and the Low Cost Sensor for Active Compliance Control”, First Inter­national Workshop on Pattern Recognition, ed­ited by Xudong Jiang, Guojian Chen, Genci Capi, Chiharu Ishii, Proc. of SPIE Vol. 10011, 2016. DOI: 10.1117/12.2242950 9. M. Y. Saadeh, M B. Trabia, “Identification of a force-sensing resistor for tactile applications”, Journal of Intelligent Material Systems and Structures, vol. 0, pp. 1-15, 2012. DOI: 10.1177/1045389X12463462 10. R. S. Hall, G. T. Desmoulin, T. E. Milner, “A technique for conditioning and calibrating force-sensing re­sistors for repeatable and reliable measurement of compressive force”, Journal of Biomechanics, vol. 41, pp. 3492-3495, 2008. DOI: 10.1016/j.jbio­mech.2008.09.031 11. D. Giovanelli, E. Farella, “Force Sensing Resis­tor and Evaluation of Technology for Wear­able Body Pressure Sensing“, Journal of Sen­sors, Vol. 2016, Article ID 9391850, 13 pages. DOI:10.1155/2016/9391850 12. M. F. Shaikh, Z. Salcic, K. Wang, “Analysis and Se­lection of the Force Sensitive Resistors for Gait Characterisation”, Proceedings of the 6th Inter­national Conference on Automation, Robotics and Applications, Feb 17-19, pp. 370-375, 2015, Queenstown, New Zealand. DOI: 10.1109/IC­ARA.2015.7081176 13. C. Cho, Y. Ryuh, “Fabrication of flexible tactile force sensors using conductive ink and silicon elasto­mer”, Sensors and Actuators A: Physical, vol. 237, pp. 72-80, 2016. DOI: 10.1016/j.sna.2015.10.051 14. A. Nikonovas, A. J. L. Harrison, S. Hoult, D. Sam­mut, “The application of force-sensing resistor sensors for measuring forces developed by the human hand” , Proc. of the Institution of Me­chanical Engineers, Part H: Journal o Engineer­ing in Medicine, vol. 218, pp. 121-126, 2004. DOI: 10.1243/095441104322984013 15. R. Bin Ambar, B. M. P. Hazwaj, A. M. B. M. Ali, M. S. Bin Ahmad, and M. M. Bin Abdul Jamil, “Multi-sensor arm rehabilitation monitoring device,” 2012 Int. Conf. Biomed. Eng. ICoBE 2012, no. February, pp. 424–429, 2012. DOI: 10.1109/IC­oBE.2012.6179051 16. B. T. Smith, D.J. Coiro, R. Finson, R.R. Betz, J. Mc­Carthy, ”Evaluation of force-sensing resistors for gait event detection to trigger electrical stimula­tion to improve walking in the child with cerebral palsy”, IEEE Transactions on Neural Systems and Rehabilitation Engineering, Vol. 10, No. 1, pp. 22-29, 2002. DOI: 10.1109/TNSRE.2002.1021583 17. C. P. Fernandes, P.J. Glantz, S.A. Svensson, A. Berg­mark, “A novel sensor for bite force determina­tions”, Dental materials, Vol. 19, Issue 2, pp. 118-126, 2003. DOI: 10.1016/S0109-5641(02)00020-9 18. H. S. Choi, Y.J. Park, S.M. Lee, K.M. Kim, ”Functional Characteristics of a New Electrolarynx “Evada” Having a Force Sensing Resistor Sensor”, Journal of Voice, Vol. 15, No. 4, pp. 592-599, 2001. DOI: 10.1016/S0892-1997(01)00062-5 19. http://www.fujifilmusa.com 20. http://www.rkprint.co.uk 21. http://www.sunchemical.com 22. http://www.gts-flexible.com 23. L. Nagy, D. Krklješ, K. Babković, “Specific con­ductance characteristic of force sensing resistor with custom made single-gap conductive con­tacts“, Materials and applications for sensors and transducers II, Vol. 543, pp. 184-187, 2013. DOI: 10.4028/www.scientific.net/KEM.543.184 24. D. Krklješ, L. Nagy, K. Babković, “Evaluation of the possibility of using a different excitation of FSR force sensor”, Proceedings of the international symposium on power electronics – Ee2011, Novi Sad, Serbia, October 26-28, 2011, pp. 3. ISBN 978-86-7892-356-2 Arrived: 16. 02. 2017 Accepted: 26. 04. 2017 D. Vasiljević et al; Informacije Midem, Vol. 47, No. 1(2017), 40 – 48 Table 1: Dimensions of 4 different types of FSRs 1st type of FSR 2nd type of FSR 3rd type of FSR 4th type of FSR Active area diameter/surface (mm) 12.7 12.7 24 x 24 18 x 18 Length of structure with terminals (mm) 51.4 51.4 63.4 38.83 Width of interdigitated electrodes (mm) 0.4 0.2 0.4 0.36 Distance between interdigitated electrodes (mm) 0.4 0.5 0.3 0.27 D. Vasiljević et al; Informacije Midem, Vol. 47, No. 1(2017), 40 – 48 Figure 1: Four different structures after sintering: a) 1st type of FSR, b) 2nd type of FSR, c) 3rd type of FSR and d) 4th type of FSR, respectively D. Vasiljević et al; Informacije Midem, Vol. 47, No. 1(2017), 40 – 48 Figure 6: SEM micrographs of a) silver interdigitated electrodes, b) carbon layer D. Vasiljević et al; Informacije Midem, Vol. 47, No. 1(2017), 40 – 48 (a) (b) Figure 8: Resistance as a function of force for four types of FSRs Figure 7: Load-displacement curves for a) silver inter­digitated electrodes, b) carbon layer D. Vasiljević et al; Informacije Midem, Vol. 47, No. 1(2017), 40 – 48 (a) (b) (a) Figure 10: Voltage as a function of force characteristics for: (a) 3rd type of FSR, (b) 4th type of FSR (b) Figure 9: Voltage as a function of force characteristics for: (a) 1st type of FSR, (b) 2nd type of FSR Figure 11: Voltage as a function of force for four types of FSRs and for RM = 18 . in linear sensors’ regime D. Vasiljević et al; Informacije Midem, Vol. 47, No. 1(2017), 40 – 48 Figure 12: Voltage as a function of force for four types of FSRs and for RM = 18 . D. Vasiljević et al; Informacije Midem, Vol. 47, No. 1(2017), 40 – 48 D. Vasiljević et al; Informacije Midem, Vol. 47, No. 1(2017), 40 – 48 Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 1(2017), 49 – 54 A seven-core fibre for fluorescence spectroscopy Ahmed Samir1, 2, Boštjan Batagelj1,3 1University of Ljubljana, Faculty of Electrical Engineering, Ljubljana, Slovenia 2Ain Shams University, Faculty of Science, Physics Department, Cairo, Egypt 3Centre of Excellence for Biosensors, Instrumentation and Process Control, Ajdovscina, Slovenia Abstract: Fibre-optic fluorescent probes need special filtering; this allows them to reject the strong excitation light while transmitting the weak fluorescent light to the detector. In this paper, a seven-core fibre with optically coupled cores is proposed for fluorescent probes. Using core-to-core mode coupling for filtration instead of mounting conventional filters would decrease the number of necessary parts and the size of the probe, making it suitable for spectroscopic applications. The proposed probe was assembled with the central core being used to transmit and couple the excitation radiation to the outer six cores. Using all the cores for delivering the excitation light from the source to the sample reduces the risk of sample being photochemically damaged compared to excitation by a single-core fibre. Fluorescence emission feedback radiation at a higher wavelength can be collected in the outer six cores, and then the fluorescence signal can be coupled from these cores to the central core. The results from the numerical simulations of the 3D full-vectorial model show two cases corresponding to peak transmission at wavelengths of 410 nm and 480 nm. Therefore, the selectivity of the wavelength ensures that the light directed into the central core will pass through it and reach the end of the probe, except for certain wavelengths, where it will couple and appear at the end of the other cores. Keywords: multi-core fibre (MCF); fluorescent probe; wavelength filtering devices; spectral filtering Sedem-jedrno vlakno za fluorescenčno spektroskopijo Izvleček: Fluorescenčne sonde iz optičnega vlakna potrebujejo posebno filtriranje, ki omogoča zavračanje močne vzbujevalne svetlobe medtem ko na detektor prepušča šibko fluorescenčno svetlobo. V tem prispevku je za fluorescenčno sondo predlagano sedem-jedrno vlakno z optično sklopljenimi jedri. Uporaba rodovnega sklapljanja iz jedra na jedro za filtracijo namesto montaže običajnih filtrov zmanjša število potrebnih sestavnih delov in velikost sonde, ki je primerna za uporabo v spektroskopiji. Predlagana sonda je sestavljen iz osrednjega jedra, ki se uporablja za oddajanje in sklapljanje vzbujevalnega sevanja na zunanjih šest jeder. Uporaba vseh jeder v primerjavi z enim samim jedrom vlakna za dostavo vzbujevalne svetlobe od vira do vzorca zmanjša tveganje za fotokemično poškodovanje vzorca. Povratno sevanje fluorescenčne oddaje, na višjih valovnih dolžinah, se lahko zbira v zunanjih šestih jedrih od koder je nato sklopljeno v osrednje jedro. Rezultati numeričnih simulacij s tridimenzionalnim popolnoma vektorskim modelom prikazujejo dva primera, ki ustrezata največji propustnosti pri valovnih dolžinah 415 nm in 480 nm. Pri tem selektivnost valovne dolžine omogoča da bo svetloba usmerjena v osrednje jedro prehajala skozenj in dosegla konec sonde, medtem ko se nekatere valovne dolžine sklopijo in pojavljajo na koncu drugih jeder. Ključne besede: večjedrno vlakno, fluorescenčna sonda, naprave za filtriranje valovnih dolžin, spektralno filtriranje * Corresponding Author’s e-mail: ahmed.samir@fe.uni-lj.si 1 Introduction Optical fibres have been used in many sensing appli­cations [1-2]. Fluorescence-based optical-fibre sensors are of special interest because of their various appli­cations in non-invasive, in-vitro/in-vivo detection sys­tems, drug discovery, the analysis of biomolecules for disease diagnostics, environmental monitoring, three-dimensional, in-situ analyses of living organisms, and the investigation of tissues [3-6]. Fluorescence measurement techniques with free beam optics have many optical components, such as an off-axis parabolic reflector and dichroic beam splitters. This bulky optical arrangement requires a precise optical alignment. Fluorescence-based optical fibre measure­ment techniques are more convenient compared to fluorescence-based, free-beam optics techniques due to their flexibility, immunity to external electromagnet­ic interference, cost-effectiveness, compactness, small size, remote-monitoring capability, long-range opera­tion and their ability to operate in harsh environments. Several configurations of fibre probes for fluorescence spectroscopic systems have been employed. The first configuration consists of a single-fibre probe: the same fibre is used to deliver the excitation radiation to the sample and to collect the emitted radiation. In the second configuration one fibre is used to trans­mit the excitation radiation to the sample and a second fibre is used to collect and guide the emission radiation to the detection system. Using separate fibres eliminates the need for fibre splitters, but decreases the chances of capturing the emission photons, as only a small portion of the excited fluorescence can be collected. In the third configuration fluorescence measurements are made with fibre bundles, where half of the fibres carry the excitation radiation, while the other half re­turn the emission radiation [7, 8]. There are also other designs that include a central excitation fibre surround­ed by a number of collection fibres located in one or more rings known as collection rings [9]. In the fourth configuration, probes based on a multicore-coupled structure have been proposed [10]. Multi-core fibres (MCFs) have many advantages over fibre bundles, such as an increased stability, as each core will under­go the same environmental changes, like temperature increases, vibrations and pressure changes. The overall size is also reduced; this is because multiple cores can be designed in a fibre with the same width as a single-core fibre. The core separations throughout the fibre are con­stant, compared to fibre bundles made by inserting mul­tiple single-core fibres into a capillary, and adding extra functionality to MCFs is easier and more readily repeat­able than for a fibre bundle. It also offers new oppor­tunities. The first opportunity is the sinusoidal spectral response due to the coupling between the cores, which allows correlating the property being measured with ei­ther the intensity changes or the spectral shifts over the section of the sinusoidal. They have been widely used in a variety of different applications, such as fibre sensors [11], spatial division multiplexing [12], microwave pho­tonics [13], fibre lasers [14], and amplifiers [15]. Our objective is to introduce a new type of optical fi­bre, with novel capabilities for fluorescence detection, as shown in Fig. 1. One advantage of our proposed MCF probe is the use of core-to-core coupling for filtration in­stead of external conventional filters. Fluorescence-based, optical-fibre probes with conventional external filters re­quire proper fixations and careful positioning. Another limiting factor that applies to the filters is the outer diam­eter of such probes. For these reasons, the replacement of the conventional external filters with another, alternative filtering is still of interest [16, 17]. The integration of fibre Bragg gratings into the fibre cores has already been sug­gested [18, 19]. The challenge is, however, to optimize the filtering characteristics of the MCF filter in order to match the excitation/emission wavelength fingerprint of any selected fluorophore. Therefore, MCF filters with differ­ent structures resulting in appropriate optical properties have to be designed and the optical filtering characteris­tics must be determined to enable the fabrication of the optimal filter for the detection of a selected fluorophore. Figure 1: Seven-core fibre for sending the excitation light to the fluorophore and collecting the emitted fluorescence light. Here, we focus on the design of a seven-core fibre with coupled cores that we intend to use as a probe for fluorescence spectroscopy. The paper is structured as follows. In Section 2 the fundamentals of the seven-core fibre structure are presented on the basis of the Eigen mode expansion theory. Then, in Section 3, the numerical simulations of the complete modal analysis via a 3D full-vectorial model based on the EME method is used to illustrate the modal characteristics of the su­per modes inside the MCFs. In Section 4 the simulation results obtained by FIMMWAVE and FIMMPROP will be discussed. Finally, the conclusions will be drawn. 2 Fundamentals of seven-core fibres MCFs can be classified into three categories: multicore, single-mode fibres with coupled cores; multicore, sin­gle-mode fibres with uncoupled cores; and multicore few-mode fibres. For all the MCF structures we consider the homogenous, identical, 7-core MCFs consisting of one central core labelled (1) concentrically surrounded by hexagonally distributed six cores labelled (2–7) as shown in Fig. 2. For simplicity of design and fabrication, we assume that each core has an identical radius and refractive index rco and nco, respectively, while the clad­ding has a refractive index of ncl as in Table 1. The values of refractive indexes correspond to fluorine-doped fi­bre [20] at the wavelength 415 nm. It is also assumed that the MCF cross-section is uniform along the z-axis. Table 1: MCF parameters and their values. Parameter Value rco 2 [µm] L 7 [µm] nco 1.45125 ncl 1.449 3 The 3D full-vectorial Eigen Mode Expansion (EME) method In this section the EME method is used to model the field propagation in the MCFs. The EME method has been well known in photonics for some time through the film-mode matching (FMM) method [21], [22]. It is based on the idea that any solution of Maxwell’s equations in the region of the waveguide can be written in terms of a su­perposition of the forward (propagating along +z) and backward (propagating along -z) propagating modes [23]. The field in any section can be written as a linear combination of the 2D eigenmodes with the corre­sponding propagation constants ßk. Such modes can be calculated using Fimmwave’s mode solvers: (1) where ..i=[Ei , Hi] is the mode profile, ßk is the corre­sponding propagation constant, and are the for­ward and backward complex amplitude coefficients of the ith mode, respectively. For MCFs with coupled cores, the pitch distance be­tween the cores is reduced in order to increase the core-to-core coupling. As a result, evanescent core coupling occurs and light propagates through all the cores as a super-mode. Each super-mode is a linear superposition of the individual core modes. The total number of non-degenerate super-modes equals the number of cores. The super-mode patterns are calcu­lated using a finite-element mode solver (Fimmwave by Photon Design). The intensity patterns for the seven super-modes of the seven-core fibre design based on table 1 are shown in Fig. 3. In theory, if the excitation radiation is only launched into the central core, only the super-modes with none zero intensity in the centre core, performing the mode-overlap conditions, can be excited. These modes are SM1 and SM6 in Fig. 3. Currently, analytical expressions have been proposed for the propagation constants and the super-modes in­side the MCFs with circularly distributed cores [24-27]. In addition, a semi-analytical model [28] was calculated for the transmission of light in the MCF using the equa­tion (2) where P1 and P6 are the fraction of light carried by the super-modes SM1 and SM6, respectively, C is the core-coupling coefficient and L is the MCF segment length. 4 Simulation results and discussion The methodology was applied to simulate different de­signs of seven-core fibre by changing the lattice param­eters, core diameters and scanning the transmittance in the external cores and the central core of the MCF in a certain range of wavelengths until we reach the op­timum design, which matches the excitation/emission wavelength fingerprint of any selected fluorophore. In order to simulate the propagation dynamics of the seven-core fibre design based on table 1 as a function of the fibre length for a wavelength of 415 nm the light launched into the central core of the MCF, i.e., A1(0)=1. Then the transmitted power in every core is detected by an “offset” single-mode waveguide having a radius similar to that of the cores in the MCF. The result is pre­sented in Fig. 4. This figure shows how the power trans­fer to the outer cores after the coupling length and then swings back again along the length of the MCF. To further numerically simulate the transmission char­acteristics of the proposed seven-core fibre, we define the transmission function Tp ( . ) for the pth core as the ratio of the power output from this core to the power input into the central core at z = 0. Next, we set the MCF length to an integer multiple of the coupling length and run the simulation to scan the transmittance in all the cores as a function of the wave­length. The results are shown in Fig. 5. The important features in Fig. 5 are the two cases corresponding to the peak transmission at wavelengths of 365 and 410 nm. Therefore, the central core can be used to transmit and couple the excitation radiation of 365 nm to the outer six cores. Using all the cores for delivering the ex­citation from the light source to the sample in compari­son to excitation by a single-core fibre reduces the risk of the sample causing photochemical damage due to high light power density. Then the fluorescence emis­sion feedback radiation (415 nm) can be collected in the outer six cores, and the fluorescence signal can be coupled from these cores to the central core. 5 Conclusions A novel type of fibre probe has been proposed. It can be used for many applications such as efficient fluo­rescence signal collection and spectral filters. With an appropriate choice of parameters, the probe can be de­signed to offer a narrowband spectral filter. Changing the optical or geometrical parameters in.uences the effective refractive index of the coupled modes and therefore leads to variations in the coupling coef.cient and the overall response of the coupled sys­tem. One obvious challenge is to optimize the filtering char­acteristics of the MCF filter in order to match the exci­tation/emission wavelength fingerprint of any selected fluorophore. This can be done by changing the geo­metrical parameters of the MCF probe. Our future work will be to splice a conventional single-core, step-index, single-mode fibre to the central core of the fabricated MCF and to measure the transmis­sion characteristics of the proposed fibre probe with a broadband light source and an optical spectrum ana­lyser. 6 Acknowledgments The authors would like to thank the Optacore team for supplying seven-core fibre to acquire knowledge about fluorescence probes. 7 References 1. K. V. Grattan, T. Sun, “Fiber optic sensor tech­nology: an overview”, Sensor and Actuators A: Physical,vol. 82, pp. 40-61,2000. 2. S. Begus, G. Beges, J. Dronvsek, D. Hudoklin, “A novel NIR laser-based sensor for measuring the surface moisture in polymers”, Sensors and Actua­tors A: physical, vol. 221, pp. 53-59, 2015. 3. W. R. Seitz, “Chemical sensors based on fiber op­tics”, Anal. Chem., vol. 56, pp. 16A-34A, 1984. 4. M. L. Myrik, S. M. Angel and R. Desidero, “Compari­son of some fiber optic configurations for meas­urements of fluorescence and Raman scattering”, Appl. Optics, vol. 29, no. 9, pp. 1333-1343, 1990. 5. A. H. Uddin, P. A. E. Piunno, R. H. E Hudson, M. J. Damha and U. J. Krull, “A fiber optic biosensor for fluorimetric detection of triple-helical DNA”, Nucleic Acids Research, vol. 25, no. 20, pp. 4139–4146, 1997. 6. M. C. Yappert, S. Lai, and D. Borchmanj, “Age De­pendence and Distribution of Green and Blue Fluorophores in Human Lens Homogenates”, In­vest. Opthalmol. Vis. Sci, vol. 33, no. 13, pp. 3555-3560, 1992. 7. L. A. Saari, W. R. Seitz, “pH Sensor Based on Im­mobilized Fluoresceinamine”, Anal. Chem., vol. 54, pp. 821-823, 1982. 8. G.F. Kirkbright, R. Narrayanaswamy, N. Welti, “Fi­bre-optic pH probe based on the use of an immo­bilised colorimetric indicator”, Analyst, vol. 109, pp. 1025-1028, 1984. 9. G. K. Bhowmic, N. Gautam, L.M. Gantayet, “De­sign optimization of fiber optic probes for remote fluorescence spectroscopy”, Optics Communica­tions. 282:2676-2684, 2009. 10. A. Samir, B. Batagelj, “A multicore fibre probe for fluorescence spectroscopy”, Proceedings, 52nd International Conference on Microelectronics, Devices and Materials, September, Ankaran, Slo­venia, MIDEM - Society for Microelectronics, Elec­tronic Components and Materials 2016. 11. J.R. Guzmán-Sepúlveda, R. Guzmán-Cabrera, M. Torres-Cisneros, J.J. Sánchez-Mondragón, D.A. May-Arrioja, “A highly sensitive .ber optic sensor based on two-core .ber for refractive index meas­urement”, Sensors vol. 13, 14200–14213, 2013. 12. X. Liu, S. Chandrasekhar, X. Chen, P.J. Winzer, Y. Pan, T.F. Taunay, B. Zhu, M. Fishteyn, M.F. Yan, J.M. Fini, E.M. Monberg, and F.V.Dimarcello ,“1.12-Tb/s 32-QAM-OFDM superchannel with 8.6–b/s/Hz intrachannel spectral efficiency and space-divi­sion multiplexed transmission with 60-b/s/Hz aggregate spectral efficiency”, Opt. Express, vol. 19, pp. B958–B964, 2011. 13. I. Gasulla and J. Capmany, “Microwave photonics applications of multicore fibers”, IEEE Photonics J., vol. 4, pp. 877–888, 2012. 14. B.M. Shalaby, V. Kermene, D. Pagnoux, A. Des­farges-Berthelemot, and A. Barthélémy, “Phase-locked supermode emissions from a dual mul­ticore fibre laser”, Appl. Phys. B, vol. 105, pp. 213–217, 2011. 15. Y. Huo, P. K. Cheo, and G. King, “Fundamental mode operation of a 19-core phase-locked Yb-doped fiber amplifier”, Opt. Express, vol. 12, , pp. 6230–6239, 2004. 16. X. Li, B. Sun and Y. Yu, “Ultra-wide bandwidth wavelength selective couplers based on the all solid multi-core Ge-doped fibre”, Opto-Electron­ics Review, vol. 22, pp. 166–170, 2014. 17. M. Kovačič, J. Krč, B. Lipovšek and M. Topič, Model­ling of diffraction grating based optical filters for fluorescence detection of biomolecules, Biomedi­cal Optics Express, vol. 5, pp. 2285-2300, 2014. 18. P. R. Stoddart and D. J. White, “Optical fibre SERS sensors”, Anal. Bioanal. Chem., vol. 394, pp. 1761–1774, 2009. 19. S. Dochow, I. Latka, M. Becker, R. Spittel, J. Kob­elke, K. Schuster, A. Graf, S. Brückner, S. Unger, M. Rothhardt, B. Dietzek, C. Krafft, and J. Popp, “Mul­ticore fiber with integrated fiber Bragg grating for background-free Raman sensing”, Opt. Express, vol. 20, pp. 20156-20169, 2012. 20. M. Oto, “Resistivity for deep-UV laser irradiation in flu­orine doped silica glass fiber”, Proc. SPIE 6586, Dam­age to VUV, EUV, and X-ray Optics, vol. 6586, 2007. 21. A. S. Sudbo, ”Film mode matching: a versatile numerical method for vector mode field calcula­tions in dielectric waveguides. Pure”, Appl. Opt. vol. 2, pp. 211-233, 1993. 22. S. T. Peng, and A. A. Oliner, “Guidance and leak­age properties of a class of open dielectric wave­guides: Part I mathematical formulations”, IEEE-MTT vol. 29, pp. 843-855, 1981. 23. D. F. G. Gallagher, T.P. Felici, “Eigenmode Expan­sion Methods for Simulation of Optical Propaga­tion in Photonics - Pros and Cons”, Proceedings of SPIE, Vol 4987, pp. 69-82, 2003. 24. J. Hudgings, L. Molter, and M. Dutta, “Design and modeling of passive optical switches and power di­viders using non-planar coupled fiber arrays,” IEEE J. Quantum Electron. 36(12), 1438–1444 (2000). 25. Y. C. Meng, Q. Z. Guo, W. H. Tan, and Z. M. Huang, “Analytical solutions of coupled-mode equations for multiwaveguide systems, obtained by use of Chebyshev and generalized Chebyshev polyno­mials,” J. Opt. Soc. Am. A 21(8), 1518–1528 (2004). 26. N. Kishi and E. Yamashita, “A simple coupled-mode analysis method for multiple-core optical fiber and coupled dielectric waveguide struc­tures,” IEEE Trans. Microwave Theory Tech. 36(12), 1861–1868 (1988). 27. J. Zhou, “Analytical formulation of super-modes inside multi-core fibers with circularly distributed cores”, OPTICS EXPRESS, Vol 22, pp. 673-688, 2014. 28. C. Jollivet, A. Mafi, D. Flamm, M. Duparré, K. Schus­ter, S. Grimm, and A.Schülzgen, “Mode-resolved gain analysis and lasing in multi-supermode mul­ti-core fiber laser”, OPTICS EXPRESS, Vol 22, pp. 30377-30386, 2014. Arrived: 03. 03. 2017 Accepted: 10. 04. 2017 A. Samir et al; Informacije Midem, Vol. 47, No. 1(2017), 49 – 54 A. Samir et al; Informacije Midem, Vol. 47, No. 1(2017), 49 – 54 Figure 2: Seven-core coupled structure consisting of 6 cores symmetrically disposed around a central core. Figure 3: Electric field of the seven super-modes using a finite-element mode solver. A. Samir et al; Informacije Midem, Vol. 47, No. 1(2017), 49 – 54 Figure 4: Propagation dynamics of a homogeneous seven-core MCF for the case of light injected into the central core. Figure 5: Transmittance of the central core and the outer cores as a function of the wavelength. A. Samir et al; Informacije Midem, Vol. 47, No. 1(2017), 49 – 54 A. Samir et al; Informacije Midem, Vol. 47, No. 1(2017), 49 – 54 Call for papers Journal of Microelectronics, Electronic Components and Materials Vol. 47, No. 1(2017), 55 – 55 MIDEM 2017 53rd INTERNATIONAL CONFERENCE ON MICROELECTRONICS, DEVICES AND MATERIALS WITH THE WORKSHOP ON MATERIALS FOR ENERGY CONVERSION AND THEIR APPLICATIONS Announcement and Call for Papers October 4th – 6th, 2017 Jožef Stefan Institute, Ljubljana, Slovenia ORGANIZER: MIDEM Society - Society for Microelec­tronics, Electronic Components and Materials, Ljublja­na, Slovenia CONFERENCE SPONSORS: Slovenian Research Agen­cy, Republic of Slovenia; IMAPS, Slovenia Chapter; IEEE, Slovenia Section; GENERAL INFORMATION The 53rd International Conference on Microelectronics, Electronic Components and Devices with the Work­shop on Materials for Energy Conversion and Their Applications continues a successful tradition of the annual international conferences organised by the MIDEM Society, the Society for Microelectronics, Elec­tronic Components and Materials. The conference will be held at Jožef Stefan Institute, Ljubljana, Slovenia, leading Slovenian scientific research institute, from OCTOBER 4th – 6th, 2017. Topics of interest include but are not limited to: - Workshop focus: Materials for Energy Conversion and Their Applications: - Electrocalorics and Thermoelectrics - Novel monolithic and hybrid circuit processing techniques, - New device and circuit design, - Process and device modelling, - Semiconductor physics, - Sensors and actuators, - Electromechanical devices, Microsystems and na­nosystems, - Nanoelectronics - Optoelectronics, - Photonics, - Photovoltaic devices, - New electronic materials and applications, - Electronic materials science and technology, - Materials characterization techniques, - Reliability and failure analysis, - Education in microelectronics, devices and mate­rials. ABSTRACT AND PAPER SUBMISSION: Prospective authors are cordially invited to submit up to 1 page abstract before May 1st, 2017. Please, iden­tify the contact author with complete mailing address, phone and fax numbers and e-mail address. After notification of acceptance (June 15th, 2017), the authors are asked to prepare a full paper version of six pages maximum. Papers should be in black and white. Full paper deadline in PDF and DOC electronic format is: August 31st, 2017. IMPORTANT DATES: Abstract deadline: May 1st, 2017 (1 page abstract or full paper) Notification of acceptance: June 15th, 2017 Deadline for final version of manuscript: August 31st, 2017 Invited and accepted papers will be published in the conference proceedings. Deatailed and updated information about the MIDEM Conferences is available at http://www.midem-drustvo.si/ under Conferences. Boards of MIDEM Society | Organi društva MIDEM MIDEM Executive Board | Izvršilni odbor MIDEM President of the MIDEM Society | Predsednik društva MIDEM Prof. Dr. Marko Topič, University of Ljubljana, Faculty of Electrical Engineering, Slovenia Vice-presidents | Podpredsednika Prof. Dr. Barbara Malič, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Iztok Šorli, MIKROIKS, d. o. o., Ljubljana, Slovenija Secretary | Tajnik Olga Zakrajšek, UL, Faculty of Electrical Engineering, Ljubljana, Slovenija MIDEM Executive Board Members | Člani izvršilnega odbora MIDEM Darko Belavič, In.Medica, d.o.o., Šentjernej, Slovenia Dr. Slavko Bernik, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Miha Čekada, Jožef Stefan Institute, Ljubljana, Slovenia Prof. DDr. Denis Đonlagič, UM, Faculty of Electrical Engineering and Computer Science, Maribor, Slovenia Prof. Dr. Leszek J. Golonka, Technical University Wroclaw, Poland Dr. Vera Gradišnik, Tehnički fakultet Sveučilišta u Rijeci, Rijeka, Croatia Leopold Knez, Iskra TELA d.d., Ljubljana, Slovenia mag. Mitja Koprivšek, ETI Elektroelementi, Izlake, Slovenia Prof. Dr. Miran Mozetič, Jožef Stefan Institute, Ljubljana, Slovenia Prof. Dr. Janez Trontelj, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Dr. Danilo Vrtačnik, UL, Faculty of Electrical Engineering, Slovenia Supervisory Board | Nadzorni odbor Prof. Dr. Franc Smole, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia prof. dr. Drago Strle, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Igor Pompe, Ljubljana, Slovenia Court of honour | Častno razsodišče Emer. Prof. Dr. Jože Furlan, Slovenia Dr. Marko Hrovat, Slovenia Dr. Miloš Komac, Slovenia Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials ISSN 0352-9045 Publisher / Založnik: MIDEM Society / Društvo MIDEM Society for Microelectronics, Electronic Components and Materials, Ljubljana, Slovenia Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale, Ljubljana, Slovenija www.midem-drustvo.si