756 KB37 KB198520252003Babič, RudolfOsebik, DavorinSolar, Mitjaštevilka:3letnik:33str. 170-177ISSN:0352-9045COBISSID:8591126URN:URN:NBN:SI:doc-WZ825YEEslStrokovno društvo za mikroelektroniko, elektronske sestavne dele in materialeInformacije MIDEMasinhrono vezjedigitalna obdelava signalovFIR filtriporazdeljena aritmetikaAdaptivna struktura s polji programirnih vezij za izvedbo nerekurzivnih digitalnih sit|In this article the two mode of hardware implementation of digital FIR filter in adaptive structure implemented with field programmable gate arrays XC4000 is presented. Implementations of digital FIR filter with programmable logic celi array circuits can be realized using different structures. Adaptive application of digital FIR filters requires low complexity and quick enough entry of coefficients and calculation of output word y(k). These conditions are satisfied by implementation of digital FIR filter in the structure of concentrated arithmetic with distributed adders and implementation in the structure of distributed arithmetic in fully parallel form. The structure of distributed arithmetic in fully parallel form is shown in block diagram in figure 3 and digital FIR filter in the structure of concentrated arithmetic with distributed adders is shown in figure 1. Fully parallel form of digital FIR filter in the structure of distributed arithmetic The vector of directly calculated partial sums of coefficients v(k-1) is calculated in circuit's unit for up-to-date calculation of partial sum of coefficients. Equation (10) describes calculation of the vector of partial sums of coefficients v(k-1). Equations 5, 7 and 9 describe the relationship between input signal u(k), vector of history of input signal u(k) and vector bu(k-1), where the bu(k-1),i are the bits with values O or 1, bu(k-1), Bu is the sign bit and bu(k-1).O is the last significant bit (LSB). The vector bu(k-1) has dimension BuxN, where Bu is the number of bits of input signal u(k) and N is the number of coefficients of FIR filter. The output word is calculated by equation (13). Tables 1 and 2 show the increase of the number of configuration logic blocks. The increase of configuration logic block depends on number of taps digital FIR filter and number of bits BH. BH describes quantization of the taps of digital FIR filter. The hardware complexity of the structure of fully parallel form of digital FIR filter increases with (const. xNxBH)2. Digital FIR filter in the concentrated arithmetic In this chapter the two mode hardware implementation of digital FIR filter in concentrated arithmetic is presented. This implementation of FIR filter uses parallel multipliers or serial multipliers. We constructed serial multiplier based on parallel multiplier. Figure 4 shows a diagram of parallel multiplier. Implementation of the parallel multiplier with two 16 bits long words needs 528 configuration logic blocks. Preliminary estimation of device utilization for part XC4013 is shown on table 3. The parallel multipliers take up the disproportionally large amount of the configuration logic blocks. The serial multiplier is composed of one BU+2 -input adder, one Bu -bit multiplexer, and two Bu -bit register. Bu is the number of bits of input word u(k). One input hi of this multiplier is in parallel form while other u(k) is bit serial with the least significant bit bu(k-1 ),0 presented first. hi are the coefficients of digitalFIR filter. The output is bit serial, with the least significant bit first. Figure 5 shows the structure of serial multiplier. Bu -bit multiplexer can be replaced by Bubit register. Figure 6 shows the structure of serial multiplier without multiplexers. Preliminary estimation of device utilization for part XC4013 of one is shown on table 4 and Preliminary estimation of device utilization for part XC4013 of sixteenth is shown on table 5. All these hardware structures of digital FIR filter were constructed with OrCAD Express and Xilinx XACT 5.2. Fully parallel form of digital FIR filter with 16-tabs in the structure of distributed arithmetic obtained equally hardware complexity than digital FIR filter with 16-tabs in concentrated arithmeticV članku so opisane izvedbe digitalnih FIR sit s polji programirnih FPGA vezjih, ki so primerna za uporabo v adaptivnih aplikacijah digitalnih sistemov. Prikazana je analiza kompleksnosti aparaturne izvedbe adaptivnih struktur digitalnih FIR sit. Podali smo primerjavo vzporedne oblike digitalnega FIR sita v strukturi porazdeljene aritmetike z digitalnim FIR sitom v strukturi koncentrirane aritmetike izveden im z uporabo zaporedne logike za izvajanje aritmetično logičnih operacij. Za obe strukturi smo opravili analizo naraščanja aparaturne kompleksnosti v odvisnosti od stopnje sita. Z dobljenimi rezultati smo pokazali primernost izvedbe digitalnih FIR sit v strukturi koncentrirane aritmetike z uporabo zaporedne logike za izvajanje aritmetično logičnih operacijTEXTznanstveno časopisjejournalsSlovenian National E-content AggregatorNational and University Library of SloveniaStrokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale