3152 KB61 KB198520262025Kuppusamy, ParamasivamThirunavukkarasu, Jaspar Vinitha Sundarištevilka:4letnik:55str. 201-217ISSN:0352-9045DOI:10.33180/InfMIDEM2025.401COBISSID_HOST:281578755URN:URN:NBN:SI:doc-WWK2T6R5enStrokovno društvo za mikroelektroniko, elektronske sestavne dele in materialeInformacije MIDEMaverage power consumptionhibridni dinamični komparator z zapahomhitro polnjenjehybrid dynamic latched comparatorlatch regeneration delaypovprečna poraba energijerapid charge holding latched comparatorzakasnitev regeneracije zapahaDesign and analysis of low power rapid charge holding dynamic latched comparator| Oblikovanje in analiza dinamičnega komparatorja z zapahom z nizko porabo energije in hitrim polnjenjem|The need for portable devices with high precision has raised the demand for optimization of power and delay in various dynamic comparator topologies. In this paper, an efficient architecture that does timely yet rapid comparison with reduced power dissipation and optimal energy per comparison is proposed. Introducing an extra tail transistor in preamplifier of comparator, assists in holding the high gain, thereby reducing delay as well as power. The latch is meanwhile ready with a minimum threshold value at its output nodes with the help of a pass transistor in between latch output nodes. The conventional, hybrid, and proposed architecture, namely Low power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC) are simulated and verified for power, delay, and energy efficiency in Cadence Virtuoso Spectre. The proposed technique shows a significant improvement in delay and power consumption when compared to conventional comparators. Monte Carlo simulation shows that the proposed technique is robust to the process mismatch, sustaining optimal power, delay and energy efficiencyPotreba po prenosnih napravah z visoko natančnostjo je povečala povpraševanje po optimizaciji moči in zamika v različnih dinamičnih topologijah komparatorjev. V članku je predlagana učinkovita arhitektura, ki omogoča pravočasno in hkrati hitro primerjavo z zmanjšano porabo energije. Dodajanje dodatnega repnega tranzistorja v predojačevalnik komparatorja pomaga ohraniti visoko ojačenje, s čimer se zmanjša zakasnitev in poraba energije. Zapah je medtem pripravljen z minimalno mejno vrednostjo na izhodnih vozliščih. Konvencionalna, hibridna in predlagana arhitektura, imenovana Low power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC), je simulirana in preverjena glede moči, zakasnitve in energetske učinkovitosti v Cadence Virtuoso Spectre. Predlagana tehnika kaže znatno izboljšanje zakasnitve in porabe moči v primerjavi s konvencionalnimi komparatorji. Simulacija Monte Carlo kaže, da je predlagana tehnika odporna na neskladje procesov, pri čemer ohranja optimalno moč, zakasnitev in energetsko učinkovitostTEXTznanstveno časopisjejournalsSlovenian National E-content AggregatorNational and University Library of SloveniaStrokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale