<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:doc-WRYN9XBC</identifier><date>2002</date><creator>Kač, Uroš</creator><relation>documents/doc/W/URN_NBN_SI_doc-WRYN9XBC_001.pdf</relation><relation>documents/doc/W/URN_NBN_SI_doc-WRYN9XBC_001.txt</relation><format format_type="issue">2</format><format format_type="volume">32</format><format format_type="type">article</format><format format_type="extent">str. 123-129</format><identifier identifier_type="ISSN">0352-9045</identifier><identifier identifier_type="COBISSID">17112871</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-WRYN9XBC</identifier><language>eng</language><publisher>Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale</publisher><source>Informacije MIDEM</source><rights>InC</rights><subject language_type_id="slv">elektronska vezja</subject><subject language_type_id="slv">načrtovanje</subject><subject language_type_id="slv">standardi</subject><subject language_type_id="slv">tiskana vezja</subject><title>IEEE 1149.1 standard: a widely supported design for testability technology</title><title>IEEE 1149.1 standard: dobro podprta tehnika načrtovanja zmožnosti testiranja vezij</title></Record>