881 KB43 KB198520252001Čučej, ŽarkoKaiser, Mihaelštevilka:3letnik:31str. 197-204ISSN:0352-9045COBISSID:6758422URN:URN:NBN:SI:doc-RNNJP64VslStrokovno društvo za mikroelektroniko, elektronske sestavne dele in materialeInformacije MIDEMarhitektura (računalnik)hitra omrežjakomunikacijekomunikacijska omrežjaprenos podatkovstikalaKlasifikacija v hitrih omrežjih: komponente in sistemi| Classification in high speed networks: components and systems|The main topic in the paper is a problem of packet classification in high speed networks (2.5 and 10 Gbps). More processing power is needed in the nodes because of the ever increasing speed of physical links and the growing complexity of network devices. The process of classification is the essential factor impacting the throughput of whole system. It si the creator of traffic flows users packets and requires multiple lookups per packet in different information tables (Fig. 1). A traffic is than elementary subject of further processing. Classical approach in building the modem high speed switches with the simple high over dimensioning of devices is no longer a promising solution for the economical use. We show that with such an approach the upper limit of the components used is reached. In the introduction the topic is classified from the point of view of telecommunication's requirements and trends. In the continuation paper describes architectures of modem communication devices and analyses the building blocks. A modem switch is typicaly built of a processor, a fast memory and integrated circuits with implemented logic. The main reason for fast evolution of the switch architectures lies in the requirements for ever faster and more intelligent devices in the network nodes. Services differentiation requires more intelligent treatment hundreds of traffic flows through the network. A power of evolution path to the fifth generation of switch architectures is presented, with the analysis of different components which are appropriate for implementing the functionality of classification algorithms (Fig. 2). The evolution path is characterized mainly with the three bottlenecks. First, increasing speed of communication links requires intelligent interfaces. Secondly, after distribution of processing power among the main processor and intelligent interface cards a new bottleneck was evodent on the interconnection path, that is a shared bus. Thirdly, when interconection bottleneck is removed with the switch the fabric the lack of processing power on interfaces became a bottleneck again. A solution has emerget in the form of the application specific integrated circuits (ASICs) which implement the time critical processing functionality in the hardware. Technics for improving the performance of classification algorithms are also shown with the illustration of the nowadays systems limitations. Among limitations the long accessing time of fast memories and the non-optimized instruction set of general processing units are the prevalent ones. The paper is concluded with requirements and suggestions for the new generation of switches, where the need for higher flexibility in the mean of programmability is exposed. Ever changing standards and market demands in the field with short time-to-market solutions require the use of highly programable components for a fast adaptation to the new situation. A lot of expectation is put into the network processor, which combines the speed of applicaiton specific integrated circuits (ASICs) and the programmability of RISC processors. Therefore the functionality and the architecture of a network processor is described (Fig. 3), which is according to high investiments possibly the hottest area in the processor industry today. The importance of functional programming in these environments in the closing themeV članku opisujemo problematiko klasifikacije paketov v hitrih telekomunikacijskih omrežjih (2,5 in 10 Gb/s). Zaradi vedno hitrejših fizičnih povezav in kompleksnosti komunikacijskih naprav je v vozliščih potrebne vedno več moči. Proces klasifikacije je ključni dejavnik, ki vpliva na skupno prepustnost sistema. Uvodoma uvrščamo temo s stališča telekomunikacijskih potreb in trendov, v članku samem pa se omejimo na arhitekture komunikacijskih naprav in analizo gradnikov. V splošnem so sodobna stikala v omrežnih vozliščih zgrajena iz procesorja, hitrega pomnilnika in vezij z implementarno logiko. Zahteva po vedno hitrejših in inteligentnih napravah je povzročila hiter razvoj arhitektur stikal. V članku je podan hiter pregled razvoja do pete generacije, kjer analiziramo različne kombinacije gradnikov v sistemu. Temu sledi analiza komponent za implementacijo algoritmov klasifikacije, tehnike za izboljšanje zmogljivosti ter ilustracija omejitev obstoječih sistemov. Članek zaključujemo z zahtevami in predlogi za novo generacijo stikal, kjer bo posebej izpostavljena potreba po večji fleksibilnosti komponent v smislu programljivosti. V zaključku predstavljamo še vlogo funkcijskega programiranja v teh okoljihTEXTznanstveno časopisjejournalsSlovenian National E-content AggregatorNational and University Library of SloveniaStrokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale