{"?xml":{"@version":"1.0"},"edm:RDF":{"@xmlns:dc":"http://purl.org/dc/elements/1.1/","@xmlns:edm":"http://www.europeana.eu/schemas/edm/","@xmlns:wgs84_pos":"http://www.w3.org/2003/01/geo/wgs84_pos","@xmlns:foaf":"http://xmlns.com/foaf/0.1/","@xmlns:rdaGr2":"http://rdvocab.info/ElementsGr2","@xmlns:oai":"http://www.openarchives.org/OAI/2.0/","@xmlns:owl":"http://www.w3.org/2002/07/owl#","@xmlns:rdf":"http://www.w3.org/1999/02/22-rdf-syntax-ns#","@xmlns:ore":"http://www.openarchives.org/ore/terms/","@xmlns:skos":"http://www.w3.org/2004/02/skos/core#","@xmlns:dcterms":"http://purl.org/dc/terms/","edm:WebResource":[{"@rdf:about":"http://www.dlib.si/stream/URN:NBN:SI:doc-P5Y7P4O0/7e6b643a-8950-4849-b7e4-92f75be4ff9f/PDF","dcterms:extent":"606 KB"},{"@rdf:about":"http://www.dlib.si/stream/URN:NBN:SI:doc-P5Y7P4O0/f6611165-9864-419e-a509-1b2e3db37acd/TEXT","dcterms:extent":"27 KB"}],"edm:TimeSpan":{"@rdf:about":"1985-2025","edm:begin":{"@xml:lang":"en","#text":"1985"},"edm:end":{"@xml:lang":"en","#text":"2025"}},"edm:ProvidedCHO":{"@rdf:about":"URN:NBN:SI:doc-P5Y7P4O0","dcterms:isPartOf":[{"@rdf:resource":"https://www.dlib.si/details/URN:NBN:SI:spr-Z2J12Z6C"},{"@xml:lang":"sl","#text":"Informacije MIDEM"}],"dcterms:issued":"2005","dc:creator":["Babič, Rudolf","Kovačič, Kosta","Osebik, Davorin"],"dc:format":[{"@xml:lang":"sl","#text":"številka:3"},{"@xml:lang":"sl","#text":"letnik:35"},{"@xml:lang":"sl","#text":"str. 133-139"}],"dc:identifier":["ISSN:0352-9045","COBISSID:10162710","URN:URN:NBN:SI:doc-P5Y7P4O0"],"dc:language":"sl","dc:publisher":{"@xml:lang":"sl","#text":"Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale"},"dc:subject":[{"@xml:lang":"sl","#text":"aritmetično-logična enota"},{"@xml:lang":"sl","#text":"digitalna sita"},{"@xml:lang":"sl","#text":"obdelava signalov"},{"@xml:lang":"sl","#text":"programirna vezja"}],"dcterms:temporal":{"@rdf:resource":"1985-2025"},"dc:title":{"@xml:lang":"sl","#text":"Aritmetična-logična enota z zaporedno logiko za izračun utežne vsote s programirnimi vezji|"},"dc:description":[{"@xml:lang":"sl","#text":"In this article the design of the arithmetic logic unit with serial arithmetic procedure for weighted sum calculation and programmable logic cell array implementation is presented. This arithmetic logic unit is especially intended for adaptive FIR digital filter realization because all the coefficients of the digital filter can be changed simultaneously between two input samples. FIR digital filter with proposed arithmetic logic unit with serial arithmetic is shown in Fig. 3. It can be design ed in the modular structure (Fig. 5) that allows the whole system to be expanded to any number of coefficients with minimal effort. The previous realizations of digital filters in programmable circuits were focused on reduction of the complexity of the hardware realization /5/. The idea that stands behind the serial arithmetic structure is the reduction of hardware implementation complexity. It is shown that the hardware complexity increases linearly with the number of coefficients used (Table 1 and Fig. 8). The FIR digital filter in the modular structure consists of N celIs. One cell of the modular structure is elementary arithmetic block (Fig. 4) and consists of serial multiplier (Fig. 6), serial adder (Fig. 7) and FIFO register. The filter has been designed in the Xilinx ISE 6.1 environment. The basic units, serial multiplier, serial adder and FIFO register of digital filter structure is designed with VHDL. The Xilinx schematic editor was used for connections between basic units. The test application is made with FIR digital filter of 16 coefficients and a 16-bit quantization of input and output signal. The Xilinx FPGA circuit XC3S-400 is used for implementation of FIR digital filter structures with 8, 16,32 and 64 taps. The 64 taps FIR digital filter occupy only 72 % of input output blocks (lOB) and 78 % of slices of the whole XC3S-400 circuit used for this application. At 71 MHz clock frequency a sample frequency of input-outputsignal of 4.4 MHz has been obtained. The processing of one output signal sample needs 16 clock pulses"},{"@xml:lang":"sl","#text":"V članku je opisana izvedba aritmetično-Iogične enote z zaporedno logiko za sprotno določitev utežne vsote implementirane v programirna vezja (FPGA). Aritmetično logično enoto lahko uporabimo pri načrtovanju in izvedbi digitalnih FIR sit. Celotna struktura sita ima modularno zasnovo, ki podpira enostavno razširitev digitalnega FIR sita glede na poljubno število koeficientov. Zgradba modulov temelji na uporabi zaporedne logike za izvajanje aritmetičnih operacij. Pri načrtovanju smo se omejili na 16-bitni zapis vhodno-izhodnega signala digitalnega FIR sita. Načrtovanje digitalnega FIR sita z opisano aritmetično logično enoto za izračun utežne vsote koeficientov zagotavlja majhno aparaturno kompleksnost in linearno naraščanje aparaturne kompleksnosti sita glede na število koeficientov. FIR sito je zasnovano tako, da se lahko uporabi kot samostojno vezje. Opisana aritmetično logična enota v sistemu digitalnega FIR sita omogoča sproten vnos koeficientov v času med dvema vzorcema vhodnega signala, zato jo lahko uporabimo tudi kot FIR enoto v sistemu adaptivnega sita. Za načrtovanje aritmetično-logične enote in njene uporabe pri izvedbi digitalnih FIR sit smo uporabili programski paket Xilinx ISE 6.1 WebPack, ki podpira vnos, sintezo vezja in implementacijo v programirna vezja. Izbrali smo programirno vezje XC3S-400, družine Spartan, firme Xilinx. Vanj smo implementirali digitalna FIR sita z 8, 16, 32 in 64 koeficienti. Simulacijo digitalnega FIR sita smo opravili s programskim paketom ModelSim. Pri tem smo na osnovi rezultatov simulacije ugotovili, da lahko pri 16-bitnem zapisu vhodnega signala, dosežemo frekvenco vzorčenja 4.4MHz"}],"edm:type":"TEXT","dc:type":[{"@xml:lang":"sl","#text":"znanstveno časopisje"},{"@xml:lang":"en","#text":"journals"},{"@rdf:resource":"http://www.wikidata.org/entity/Q361785"}]},"ore:Aggregation":{"@rdf:about":"http://www.dlib.si/?URN=URN:NBN:SI:doc-P5Y7P4O0","edm:aggregatedCHO":{"@rdf:resource":"URN:NBN:SI:doc-P5Y7P4O0"},"edm:isShownBy":{"@rdf:resource":"http://www.dlib.si/stream/URN:NBN:SI:doc-P5Y7P4O0/7e6b643a-8950-4849-b7e4-92f75be4ff9f/PDF"},"edm:rights":{"@rdf:resource":"http://rightsstatements.org/vocab/InC/1.0/"},"edm:provider":"Slovenian National E-content Aggregator","edm:intermediateProvider":{"@xml:lang":"en","#text":"National and University Library of Slovenia"},"edm:dataProvider":{"@xml:lang":"sl","#text":"Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale"},"edm:object":{"@rdf:resource":"http://www.dlib.si/streamdb/URN:NBN:SI:doc-P5Y7P4O0/maxi/edm"},"edm:isShownAt":{"@rdf:resource":"http://www.dlib.si/details/URN:NBN:SI:doc-P5Y7P4O0"}}}}