<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:doc-NM7PUV7Q</identifier><date>2010</date><creator>Bürmen, Arpad</creator><creator>Puhan, Janez</creator><creator>Raič, Dušan</creator><creator>Tomažič, Sašo</creator><creator>Tuma, Tadej</creator><relation>documents/doc/N/URN_NBN_SI_doc-NM7PUV7Q_001.pdf</relation><relation>documents/doc/N/URN_NBN_SI_doc-NM7PUV7Q_001.txt</relation><format format_type="issue">3</format><format format_type="volume">40</format><format format_type="type">article</format><format format_type="extent">str. 167-173</format><identifier identifier_type="ISSN">0352-9045</identifier><identifier identifier_type="COBISSID">8150868</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-NM7PUV7Q</identifier><language>eng</language><publisher>Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale</publisher><source>Informacije MIDEM</source><rights>InC</rights><subject language_type_id="slv">integrirana vezja</subject><subject language_type_id="slv">načrtovanje</subject><subject language_type_id="slv">optimiranje</subject><subject language_type_id="slv">sinteza</subject><title>Optimising digital circuit cells</title><title>Optimizacija gradnikov digitalnih vezij</title></Record>