<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:doc-MDLTSSUE</identifier><date>2023</date><creator>Rojec, Žiga</creator><relation>documents/doc/M/URN_NBN_SI_doc-MDLTSSUE_001.pdf</relation><relation>documents/doc/M/URN_NBN_SI_doc-MDLTSSUE_001.txt</relation><format format_type="issue">2</format><format format_type="volume">53</format><format format_type="type">article</format><format format_type="extent">str. 103-117</format><identifier identifier_type="ISSN">0352-9045</identifier><identifier identifier_type="DOI">10.33180/InfMIDEM2023.205</identifier><identifier identifier_type="COBISSID">192963843</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-MDLTSSUE</identifier><language>eng</language><publisher publisher_location="Ljubljana">Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale</publisher><source>Informacije MIDEM</source><rights>BY</rights><subject language_type_id="slv">analogna vezja</subject><subject language_type_id="slv">odpornost na napake</subject><subject language_type_id="slv">optimizacija vezij</subject><subject language_type_id="slv">robustnost vezij</subject><subject language_type_id="slv">sinteza analognih vezij</subject><title>Towards smaller single-point failure-resilient analog circuits by use of a genetic algorithm</title><title>Manjšanje analognih vezij odpornih na odpoved poljubne komponente z uporabo genetskega algoritma</title></Record>