Modeling and simulation of high level leakage power reduction techniques for 7T SRAM cell design

URN:NBN:SI:doc-LVE5RU292012Akashe, ShyamBhushan, SushilSharma, Sanjaydocuments/doc/L/URN_NBN_SI_doc-LVE5RU29_001.pdfdocuments/doc/L/URN_NBN_SI_doc-LVE5RU29_001.txt242articlestr. 83-870352-90459955924URN:NBN:SI:doc-LVE5RU29engStrokovno društvo za mikroelektroniko, elektronske sestavne dele in materialeInformacije MIDEMInCizgubeSRAM celicašumtopologija vezjazakasnitveModeling and simulation of high level leakage power reduction techniques for 7T SRAM cell designModeliranje in simulacije tehnik znižanja visoke stopnje izgub v 7T SRAM celici