<?xml version="1.0"?><rdf:RDF xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:edm="http://www.europeana.eu/schemas/edm/" xmlns:wgs84_pos="http://www.w3.org/2003/01/geo/wgs84_pos" xmlns:foaf="http://xmlns.com/foaf/0.1/" xmlns:rdaGr2="http://rdvocab.info/ElementsGr2" xmlns:oai="http://www.openarchives.org/OAI/2.0/" xmlns:owl="http://www.w3.org/2002/07/owl#" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:ore="http://www.openarchives.org/ore/terms/" xmlns:skos="http://www.w3.org/2004/02/skos/core#" xmlns:dcterms="http://purl.org/dc/terms/"><edm:WebResource rdf:about="http://www.dlib.si/stream/URN:NBN:SI:doc-I441TNHH/ccc67075-7c25-4b07-9d35-e9a2d0322899/PDF"><dcterms:extent>933 KB</dcterms:extent></edm:WebResource><edm:WebResource rdf:about="http://www.dlib.si/stream/URN:NBN:SI:doc-I441TNHH/9db391fd-1ebe-4f44-b759-4c8dc82fdd43/TEXT"><dcterms:extent>0 KB</dcterms:extent></edm:WebResource><edm:TimeSpan rdf:about="1985-2025"><edm:begin xml:lang="en">1985</edm:begin><edm:end xml:lang="en">2025</edm:end></edm:TimeSpan><edm:ProvidedCHO rdf:about="URN:NBN:SI:doc-I441TNHH"><dcterms:isPartOf rdf:resource="https://www.dlib.si/details/URN:NBN:SI:spr-Z2J12Z6C" /><dcterms:issued>2024</dcterms:issued><dc:creator>Bürmen, Arpad</dc:creator><dc:creator>Fajfar, Iztok</dc:creator><dc:creator>Kunaver, Matevž</dc:creator><dc:creator>Puhan, Janez</dc:creator><dc:creator>Rojec, Žiga</dc:creator><dc:creator>Tomažič, Sašo</dc:creator><dc:creator>Tuma, Tadej</dc:creator><dc:format xml:lang="sl">številka:4</dc:format><dc:format xml:lang="sl">letnik:54</dc:format><dc:format xml:lang="sl">str. 271-281</dc:format><dc:identifier>DOI:10.33180/InfMIDEM2024.404</dc:identifier><dc:identifier>COBISSID_HOST:216529411</dc:identifier><dc:identifier>ISSN:2232-6979</dc:identifier><dc:identifier>URN:URN:NBN:SI:doc-I441TNHH</dc:identifier><dc:language>en</dc:language><dc:publisher xml:lang="sl">MIDEM</dc:publisher><dcterms:isPartOf xml:lang="sl">Informacije MIDEM</dcterms:isPartOf><dc:subject xml:lang="en">analog circuits</dc:subject><dc:subject xml:lang="sl">analogna vezja</dc:subject><dc:subject xml:lang="en">circuit simulation</dc:subject><dc:subject xml:lang="en">compact models</dc:subject><dc:subject xml:lang="en">hardware description langugage</dc:subject><dc:subject xml:lang="sl">jezik za opisovanje strojne opreme</dc:subject><dc:subject xml:lang="sl">kompaktni modeli</dc:subject><dc:subject xml:lang="sl">simulacija vezij</dc:subject><dc:subject xml:lang="sl">Verilog-A</dc:subject><dcterms:temporal rdf:resource="1985-2025" /><dc:title xml:lang="sl">Free software support for compact modelling with Verilog-A| Odprtokodna programska oprema za uporabo kompaktnih modelov v jeziku Verilog-A|</dc:title><dc:description xml:lang="sl">Verilog-A is the analog subset of Verilog-AMS - a hardware description language for analog and mixed-signal systems. Verilog-A is commonly used for the distribution of compact models of semiconductor devices. For such models to be usable a Verilog-A compiler is required. The compiler converts the model equations into a form that can be used by the simulator. Such compilers have been supplied with commercial simulators for many years now. Free software alternatives are much more scarce and limited in the features they offer. The paper gives an overview of Verilog-A, Free software Verilog-A compilers, and Free software/Open source simulators that can simulate compact models defined in Verilog-A. Advantages and disadvantages of individual compilers and simulators are highlighted</dc:description><dc:description xml:lang="sl">Verilog-AMS je opisni jezik za mešana analogno-digitalna vezja. Verilog-A je njegov podsklop, ki je namenjen opisu analognih vezij. Pogosto ga uporabljamo za distribucijo kompaktnih modelov polprevodniških elementov. Da bi take modele lahko uporabili v simulatorju vezij, potrebujemo prevajalnik za Verilog-A. Ta pretvori model v obliko, ki jo simulator lahko uporabi pri izračunu odziva vezja. Prevajalniki za Verilog-A so že dlje časa sestavni del tržnih programskih paketov za simulacijo vezij. Odprtokodnih alternativ je manj in podpirajo samo del specifikacije jezika. Članek poda pregled odprtokodnih prevajalnikov in simulatorjev s podporo za kompaktne medele opisane v jeziku Verilog-A s poudarkom na prednostih in slabostih posameznih prevajalnikov in simulatorjev</dc:description><edm:type>TEXT</edm:type><dc:type xml:lang="sl">znanstveno časopisje</dc:type><dc:type xml:lang="en">journals</dc:type><dc:type rdf:resource="http://www.wikidata.org/entity/Q361785" /></edm:ProvidedCHO><ore:Aggregation rdf:about="http://www.dlib.si/?URN=URN:NBN:SI:doc-I441TNHH"><edm:aggregatedCHO rdf:resource="URN:NBN:SI:doc-I441TNHH" /><edm:isShownBy rdf:resource="http://www.dlib.si/stream/URN:NBN:SI:doc-I441TNHH/ccc67075-7c25-4b07-9d35-e9a2d0322899/PDF" /><edm:rights rdf:resource="http://creativecommons.org/licenses/by/4.0/" /><edm:provider>Slovenian National E-content Aggregator</edm:provider><edm:intermediateProvider xml:lang="en">National and University Library of Slovenia</edm:intermediateProvider><edm:dataProvider xml:lang="sl">Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale</edm:dataProvider><edm:object rdf:resource="http://www.dlib.si/streamdb/URN:NBN:SI:doc-I441TNHH/maxi/edm" /><edm:isShownAt rdf:resource="http://www.dlib.si/details/URN:NBN:SI:doc-I441TNHH" /></ore:Aggregation></rdf:RDF>