<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:doc-H9AZJY04</identifier><date>2022</date><creator>Bulić, Patricio</creator><creator>Lotrič, Uroš</creator><creator>Pilipović, Ratko</creator><relation>documents/doc/H/URN_NBN_SI_doc-H9AZJY04_001.pdf</relation><relation>documents/doc/H/URN_NBN_SI_doc-H9AZJY04_001.txt</relation><format format_type="type">article</format><format format_type="extent">Str. 19-23</format><identifier identifier_type="COBISSID_HOST">122803459</identifier><identifier identifier_type="ISSN">2591-0442</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-H9AZJY04</identifier><language>slv</language><publisher publisher_location="Ljubljana">Fakulteta za elektrotehniko</publisher><publisher publisher_location="Ljubljana">Slovenska sekcija IEEE</publisher><source>Zbornik mednarodne Elektrotehniške in računalniške konference</source><rights>InC</rights><subject language_type_id="slv">ASIC</subject><subject language_type_id="slv">OpenLane</subject><subject language_type_id="slv">VLSI</subject><title>Načrtovanje in vrednotenje ASIC digitalnih vezij z orodjem OpenLANE</title></Record>