<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:doc-1N9C1236</identifier><date>2018</date><creator>Kamaraj, A.</creator><creator>Marichamay, P.</creator><relation>documents/doc/1/URN_NBN_SI_doc-1N9C1236_001.pdf</relation><relation>documents/doc/1/URN_NBN_SI_doc-1N9C1236_001.txt</relation><format format_type="issue">3</format><format format_type="volume">48</format><format format_type="type">article</format><format format_type="extent">str. 161-171</format><identifier identifier_type="ISSN">0352-9045</identifier><identifier identifier_type="COBISSID">305085696</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-1N9C1236</identifier><language>eng</language><publisher>Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale</publisher><source>Informacije MIDEM</source><rights>InC</rights><subject language_type_id="slv">polprevodniki</subject><subject language_type_id="slv">reverzibilna logika</subject><subject language_type_id="slv">strošek kvanta</subject><subject language_type_id="slv">tranzistorji</subject><subject language_type_id="slv">zakasnitev</subject><title>Design of fault-tolerant reversible floating point division</title><title>Načrtovanje proti napakam odpornega reverznega deljenja s plavajočo</title></Record>