<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:doc-0L0YESVA</identifier><date>1987</date><creator>Fajfar, Dušan</creator><creator>Lokar, Matija</creator><relation>documents/doc/0/URN_NBN_SI_doc-0L0YESVA_001.pdf</relation><relation>documents/doc/0/URN_NBN_SI_doc-0L0YESVA_001.txt</relation><format format_type="volume">11</format><format format_type="issue">4</format><format format_type="type">article</format><format format_type="extent">str. 3-7</format><identifier identifier_type="ISSN">0350-5596</identifier><identifier identifier_type="COBISSID_HOST">5119065</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-0L0YESVA</identifier><language>eng</language><publisher publisher_location="Ljubljana">Slovene Society Informatika</publisher><source>Informatica (Ljubljana)</source><rights>InC</rights><subject language_type_id="slv">matematika</subject><subject language_type_id="slv">porazdelitev zahtev v vmesniku končne velikosti</subject><subject language_type_id="slv">računalništvo</subject><subject language_type_id="slv">večnivojska povezovalna mreža</subject><subject language_type_id="slv">vzporedni procesorji</subject><title>Analysis of buffered multistage interconnection network for parrallel processors</title></Record>