<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:doc-04Y9ROOG</identifier><date>2021</date><creator>Boudour, Rachid</creator><creator>Youcef, Benabdallah Ahcene</creator><relation>documents/doc/0/URN_NBN_SI_doc-04Y9ROOG_001.pdf</relation><relation>documents/doc/0/URN_NBN_SI_doc-04Y9ROOG_001.txt</relation><format format_type="volume">45</format><format format_type="issue">6</format><format format_type="type">article</format><format format_type="extent">str. 143-150</format><identifier identifier_type="ISSN">0350-5596</identifier><identifier identifier_type="ISSN">1854-3871</identifier><identifier identifier_type="COBISSID_HOST">92140547</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-04Y9ROOG</identifier><language>eng</language><publisher>Slovensko društvo Informatika</publisher><source>Informatica (Ljubljana)</source><rights>BY</rights><subject language_type_id="slv">modeliranje jeder</subject><subject language_type_id="slv">programska oprema</subject><subject language_type_id="slv">računalništvo</subject><subject language_type_id="slv">strojna oprema</subject><title>A fast prototype for modeling IP cores using in SoC with UML Marte</title></Record>