Design of an asynchronous processor with bundled-data implementation on a commercial field programmable gate array

URN:NBN:SI:DOC-W60MA5802016Furushima, JukiyaNakajima, MasamitsuSaito, Hiroshidocuments/doc/W/URN_NBN_SI_doc-W60MA580_001.pdfdocuments/doc/W/URN_NBN_SI_doc-W60MA580_001.txt440articlestr. 399-4080350-559630253351URN:NBN:SI:doc-W60MA580engSlovensko društvo InformatikaInformatica (Ljubljana)InCcomputer scienceračunalništvoDesign of an asynchronous processor with bundled-data implementation on a commercial field programmable gate array